1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 #include <drm/drm_vblank.h> 27 #include <drm/drm_atomic_helper.h> 28 29 #include "dc.h" 30 #include "amdgpu.h" 31 #include "amdgpu_dm_psr.h" 32 #include "amdgpu_dm_replay.h" 33 #include "amdgpu_dm_crtc.h" 34 #include "amdgpu_dm_plane.h" 35 #include "amdgpu_dm_trace.h" 36 #include "amdgpu_dm_debugfs.h" 37 38 void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc) 39 { 40 struct drm_crtc *crtc = &acrtc->base; 41 struct drm_device *dev = crtc->dev; 42 unsigned long flags; 43 44 drm_crtc_handle_vblank(crtc); 45 46 spin_lock_irqsave(&dev->event_lock, flags); 47 48 /* Send completion event for cursor-only commits */ 49 if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 50 drm_crtc_send_vblank_event(crtc, acrtc->event); 51 drm_crtc_vblank_put(crtc); 52 acrtc->event = NULL; 53 } 54 55 spin_unlock_irqrestore(&dev->event_lock, flags); 56 } 57 58 bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state, 59 struct dc_stream_state *new_stream, 60 struct dc_stream_state *old_stream) 61 { 62 return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 63 } 64 65 bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc) 66 67 { 68 return acrtc->dm_irq_params.freesync_config.state == 69 VRR_STATE_ACTIVE_VARIABLE || 70 acrtc->dm_irq_params.freesync_config.state == 71 VRR_STATE_ACTIVE_FIXED; 72 } 73 74 int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable) 75 { 76 enum dc_irq_source irq_source; 77 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 78 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 79 int rc; 80 81 if (acrtc->otg_inst == -1) 82 return 0; 83 84 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst; 85 86 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 87 88 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n", 89 acrtc->crtc_id, enable ? "en" : "dis", rc); 90 return rc; 91 } 92 93 bool amdgpu_dm_crtc_vrr_active(struct dm_crtc_state *dm_state) 94 { 95 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE || 96 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 97 } 98 99 /** 100 * The DRM vblank counter enable/disable action is used as the trigger to enable 101 * or disable various panel self-refresh features: 102 * 103 * Panel Replay and PSR SU 104 * - Enable when: 105 * - vblank counter is disabled 106 * - entry is allowed: usermode demonstrates an adequate number of fast 107 * commits) 108 * - CRC capture window isn't active 109 * - Keep enabled even when vblank counter gets enabled 110 * 111 * PSR1 112 * - Enable condition same as above 113 * - Disable when vblank counter is enabled 114 */ 115 static void amdgpu_dm_crtc_set_panel_sr_feature( 116 struct vblank_control_work *vblank_work, 117 bool vblank_enabled, bool allow_sr_entry) 118 { 119 struct dc_link *link = vblank_work->stream->link; 120 bool is_sr_active = (link->replay_settings.replay_allow_active || 121 link->psr_settings.psr_allow_active); 122 bool is_crc_window_active = false; 123 124 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 125 is_crc_window_active = 126 amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base); 127 #endif 128 129 if (link->replay_settings.replay_feature_enabled && 130 allow_sr_entry && !is_sr_active && !is_crc_window_active) { 131 amdgpu_dm_replay_enable(vblank_work->stream, true); 132 } else if (vblank_enabled) { 133 if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && is_sr_active) 134 amdgpu_dm_psr_disable(vblank_work->stream); 135 } else if (link->psr_settings.psr_feature_enabled && 136 allow_sr_entry && !is_sr_active && !is_crc_window_active) { 137 amdgpu_dm_psr_enable(vblank_work->stream); 138 } 139 } 140 141 static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work) 142 { 143 struct vblank_control_work *vblank_work = 144 container_of(work, struct vblank_control_work, work); 145 struct amdgpu_display_manager *dm = vblank_work->dm; 146 147 mutex_lock(&dm->dc_lock); 148 149 if (vblank_work->enable) 150 dm->active_vblank_irq_count++; 151 else if (dm->active_vblank_irq_count) 152 dm->active_vblank_irq_count--; 153 154 dc_allow_idle_optimizations(dm->dc, dm->active_vblank_irq_count == 0); 155 156 DRM_DEBUG_KMS("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0); 157 158 /* 159 * Control PSR based on vblank requirements from OS 160 * 161 * If panel supports PSR SU, there's no need to disable PSR when OS is 162 * submitting fast atomic commits (we infer this by whether the OS 163 * requests vblank events). Fast atomic commits will simply trigger a 164 * full-frame-update (FFU); a specific case of selective-update (SU) 165 * where the SU region is the full hactive*vactive region. See 166 * fill_dc_dirty_rects(). 167 */ 168 if (vblank_work->stream && vblank_work->stream->link) { 169 amdgpu_dm_crtc_set_panel_sr_feature( 170 vblank_work, vblank_work->enable, 171 vblank_work->acrtc->dm_irq_params.allow_psr_entry || 172 vblank_work->stream->link->replay_settings.replay_feature_enabled); 173 } 174 175 mutex_unlock(&dm->dc_lock); 176 177 dc_stream_release(vblank_work->stream); 178 179 kfree(vblank_work); 180 } 181 182 static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable) 183 { 184 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 185 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 186 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); 187 struct amdgpu_display_manager *dm = &adev->dm; 188 struct vblank_control_work *work; 189 int rc = 0; 190 191 if (acrtc->otg_inst == -1) 192 goto skip; 193 194 if (enable) { 195 /* vblank irq on -> Only need vupdate irq in vrr mode */ 196 if (amdgpu_dm_crtc_vrr_active(acrtc_state)) 197 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true); 198 } else { 199 /* vblank irq off -> vupdate irq off */ 200 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false); 201 } 202 203 if (rc) 204 return rc; 205 206 rc = (enable) 207 ? amdgpu_irq_get(adev, &adev->crtc_irq, acrtc->crtc_id) 208 : amdgpu_irq_put(adev, &adev->crtc_irq, acrtc->crtc_id); 209 210 if (rc) 211 return rc; 212 213 skip: 214 if (amdgpu_in_reset(adev)) 215 return 0; 216 217 if (dm->vblank_control_workqueue) { 218 work = kzalloc(sizeof(*work), GFP_ATOMIC); 219 if (!work) 220 return -ENOMEM; 221 222 INIT_WORK(&work->work, amdgpu_dm_crtc_vblank_control_worker); 223 work->dm = dm; 224 work->acrtc = acrtc; 225 work->enable = enable; 226 227 if (acrtc_state->stream) { 228 dc_stream_retain(acrtc_state->stream); 229 work->stream = acrtc_state->stream; 230 } 231 232 queue_work(dm->vblank_control_workqueue, &work->work); 233 } 234 235 return 0; 236 } 237 238 int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc) 239 { 240 return amdgpu_dm_crtc_set_vblank(crtc, true); 241 } 242 243 void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc) 244 { 245 amdgpu_dm_crtc_set_vblank(crtc, false); 246 } 247 248 static void amdgpu_dm_crtc_destroy_state(struct drm_crtc *crtc, 249 struct drm_crtc_state *state) 250 { 251 struct dm_crtc_state *cur = to_dm_crtc_state(state); 252 253 /* TODO Destroy dc_stream objects are stream object is flattened */ 254 if (cur->stream) 255 dc_stream_release(cur->stream); 256 257 258 __drm_atomic_helper_crtc_destroy_state(state); 259 260 261 kfree(state); 262 } 263 264 static struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc *crtc) 265 { 266 struct dm_crtc_state *state, *cur; 267 268 cur = to_dm_crtc_state(crtc->state); 269 270 if (WARN_ON(!crtc->state)) 271 return NULL; 272 273 state = kzalloc(sizeof(*state), GFP_KERNEL); 274 if (!state) 275 return NULL; 276 277 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 278 279 if (cur->stream) { 280 state->stream = cur->stream; 281 dc_stream_retain(state->stream); 282 } 283 284 state->active_planes = cur->active_planes; 285 state->vrr_infopacket = cur->vrr_infopacket; 286 state->abm_level = cur->abm_level; 287 state->vrr_supported = cur->vrr_supported; 288 state->freesync_config = cur->freesync_config; 289 state->cm_has_degamma = cur->cm_has_degamma; 290 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; 291 state->regamma_tf = cur->regamma_tf; 292 state->crc_skip_count = cur->crc_skip_count; 293 state->mpo_requested = cur->mpo_requested; 294 /* TODO Duplicate dc_stream after objects are stream object is flattened */ 295 296 return &state->base; 297 } 298 299 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) 300 { 301 drm_crtc_cleanup(crtc); 302 kfree(crtc); 303 } 304 305 static void amdgpu_dm_crtc_reset_state(struct drm_crtc *crtc) 306 { 307 struct dm_crtc_state *state; 308 309 if (crtc->state) 310 amdgpu_dm_crtc_destroy_state(crtc, crtc->state); 311 312 state = kzalloc(sizeof(*state), GFP_KERNEL); 313 if (WARN_ON(!state)) 314 return; 315 316 __drm_atomic_helper_crtc_reset(crtc, &state->base); 317 } 318 319 #ifdef CONFIG_DEBUG_FS 320 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) 321 { 322 crtc_debugfs_init(crtc); 323 324 return 0; 325 } 326 #endif 327 328 #ifdef AMD_PRIVATE_COLOR 329 /** 330 * dm_crtc_additional_color_mgmt - enable additional color properties 331 * @crtc: DRM CRTC 332 * 333 * This function lets the driver enable post-blending CRTC regamma transfer 334 * function property in addition to DRM CRTC gamma LUT. Default value means 335 * linear transfer function, which is the default CRTC gamma LUT behaviour 336 * without this property. 337 */ 338 static void 339 dm_crtc_additional_color_mgmt(struct drm_crtc *crtc) 340 { 341 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 342 343 if (adev->dm.dc->caps.color.mpc.ogam_ram) 344 drm_object_attach_property(&crtc->base, 345 adev->mode_info.regamma_tf_property, 346 AMDGPU_TRANSFER_FUNCTION_DEFAULT); 347 } 348 349 static int 350 amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc, 351 struct drm_crtc_state *state, 352 struct drm_property *property, 353 uint64_t val) 354 { 355 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 356 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state); 357 358 if (property == adev->mode_info.regamma_tf_property) { 359 if (acrtc_state->regamma_tf != val) { 360 acrtc_state->regamma_tf = val; 361 acrtc_state->base.color_mgmt_changed |= 1; 362 } 363 } else { 364 drm_dbg_atomic(crtc->dev, 365 "[CRTC:%d:%s] unknown property [PROP:%d:%s]]\n", 366 crtc->base.id, crtc->name, 367 property->base.id, property->name); 368 return -EINVAL; 369 } 370 371 return 0; 372 } 373 374 static int 375 amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc, 376 const struct drm_crtc_state *state, 377 struct drm_property *property, 378 uint64_t *val) 379 { 380 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 381 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state); 382 383 if (property == adev->mode_info.regamma_tf_property) 384 *val = acrtc_state->regamma_tf; 385 else 386 return -EINVAL; 387 388 return 0; 389 } 390 #endif 391 392 /* Implemented only the options currently available for the driver */ 393 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { 394 .reset = amdgpu_dm_crtc_reset_state, 395 .destroy = amdgpu_dm_crtc_destroy, 396 .set_config = drm_atomic_helper_set_config, 397 .page_flip = drm_atomic_helper_page_flip, 398 .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state, 399 .atomic_destroy_state = amdgpu_dm_crtc_destroy_state, 400 .set_crc_source = amdgpu_dm_crtc_set_crc_source, 401 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, 402 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, 403 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 404 .enable_vblank = amdgpu_dm_crtc_enable_vblank, 405 .disable_vblank = amdgpu_dm_crtc_disable_vblank, 406 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 407 #if defined(CONFIG_DEBUG_FS) 408 .late_register = amdgpu_dm_crtc_late_register, 409 #endif 410 #ifdef AMD_PRIVATE_COLOR 411 .atomic_set_property = amdgpu_dm_atomic_crtc_set_property, 412 .atomic_get_property = amdgpu_dm_atomic_crtc_get_property, 413 #endif 414 }; 415 416 static void amdgpu_dm_crtc_helper_disable(struct drm_crtc *crtc) 417 { 418 } 419 420 static int amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state *new_crtc_state) 421 { 422 struct drm_atomic_state *state = new_crtc_state->state; 423 struct drm_plane *plane; 424 int num_active = 0; 425 426 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) { 427 struct drm_plane_state *new_plane_state; 428 429 /* Cursor planes are "fake". */ 430 if (plane->type == DRM_PLANE_TYPE_CURSOR) 431 continue; 432 433 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 434 435 if (!new_plane_state) { 436 /* 437 * The plane is enable on the CRTC and hasn't changed 438 * state. This means that it previously passed 439 * validation and is therefore enabled. 440 */ 441 num_active += 1; 442 continue; 443 } 444 445 /* We need a framebuffer to be considered enabled. */ 446 num_active += (new_plane_state->fb != NULL); 447 } 448 449 return num_active; 450 } 451 452 static void amdgpu_dm_crtc_update_crtc_active_planes(struct drm_crtc *crtc, 453 struct drm_crtc_state *new_crtc_state) 454 { 455 struct dm_crtc_state *dm_new_crtc_state = 456 to_dm_crtc_state(new_crtc_state); 457 458 dm_new_crtc_state->active_planes = 0; 459 460 if (!dm_new_crtc_state->stream) 461 return; 462 463 dm_new_crtc_state->active_planes = 464 amdgpu_dm_crtc_count_crtc_active_planes(new_crtc_state); 465 } 466 467 static bool amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, 468 const struct drm_display_mode *mode, 469 struct drm_display_mode *adjusted_mode) 470 { 471 return true; 472 } 473 474 static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, 475 struct drm_atomic_state *state) 476 { 477 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 478 crtc); 479 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 480 struct dc *dc = adev->dm.dc; 481 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 482 int ret = -EINVAL; 483 484 trace_amdgpu_dm_crtc_atomic_check(crtc_state); 485 486 amdgpu_dm_crtc_update_crtc_active_planes(crtc, crtc_state); 487 488 if (WARN_ON(unlikely(!dm_crtc_state->stream && 489 amdgpu_dm_crtc_modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) { 490 return ret; 491 } 492 493 /* 494 * We require the primary plane to be enabled whenever the CRTC is, otherwise 495 * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other 496 * planes are disabled, which is not supported by the hardware. And there is legacy 497 * userspace which stops using the HW cursor altogether in response to the resulting EINVAL. 498 */ 499 if (crtc_state->enable && 500 !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) { 501 DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n"); 502 return -EINVAL; 503 } 504 505 /* 506 * Only allow async flips for fast updates that don't change the FB 507 * pitch, the DCC state, rotation, etc. 508 */ 509 if (crtc_state->async_flip && 510 dm_crtc_state->update_type != UPDATE_TYPE_FAST) { 511 drm_dbg_atomic(crtc->dev, 512 "[CRTC:%d:%s] async flips are only supported for fast updates\n", 513 crtc->base.id, crtc->name); 514 return -EINVAL; 515 } 516 517 /* In some use cases, like reset, no stream is attached */ 518 if (!dm_crtc_state->stream) 519 return 0; 520 521 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK) 522 return 0; 523 524 DRM_DEBUG_ATOMIC("Failed DC stream validation\n"); 525 return ret; 526 } 527 528 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { 529 .disable = amdgpu_dm_crtc_helper_disable, 530 .atomic_check = amdgpu_dm_crtc_helper_atomic_check, 531 .mode_fixup = amdgpu_dm_crtc_helper_mode_fixup, 532 .get_scanout_position = amdgpu_crtc_get_scanout_position, 533 }; 534 535 int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 536 struct drm_plane *plane, 537 uint32_t crtc_index) 538 { 539 struct amdgpu_crtc *acrtc = NULL; 540 struct drm_plane *cursor_plane; 541 bool is_dcn; 542 int res = -ENOMEM; 543 544 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL); 545 if (!cursor_plane) 546 goto fail; 547 548 cursor_plane->type = DRM_PLANE_TYPE_CURSOR; 549 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL); 550 551 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); 552 if (!acrtc) 553 goto fail; 554 555 res = drm_crtc_init_with_planes( 556 dm->ddev, 557 &acrtc->base, 558 plane, 559 cursor_plane, 560 &amdgpu_dm_crtc_funcs, NULL); 561 562 if (res) 563 goto fail; 564 565 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); 566 567 /* Create (reset) the plane state */ 568 if (acrtc->base.funcs->reset) 569 acrtc->base.funcs->reset(&acrtc->base); 570 571 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; 572 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; 573 574 acrtc->crtc_id = crtc_index; 575 acrtc->base.enabled = false; 576 acrtc->otg_inst = -1; 577 578 dm->adev->mode_info.crtcs[crtc_index] = acrtc; 579 580 /* Don't enable DRM CRTC degamma property for DCE since it doesn't 581 * support programmable degamma anywhere. 582 */ 583 is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch; 584 drm_crtc_enable_color_mgmt(&acrtc->base, is_dcn ? MAX_COLOR_LUT_ENTRIES : 0, 585 true, MAX_COLOR_LUT_ENTRIES); 586 587 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); 588 589 #ifdef AMD_PRIVATE_COLOR 590 dm_crtc_additional_color_mgmt(&acrtc->base); 591 #endif 592 return 0; 593 594 fail: 595 kfree(acrtc); 596 kfree(cursor_plane); 597 return res; 598 } 599 600