1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
27 #define AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
28 
29 struct drm_crtc;
30 struct dm_crtc_state;
31 
32 enum amdgpu_dm_pipe_crc_source {
33 	AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0,
34 	AMDGPU_DM_PIPE_CRC_SOURCE_CRTC,
35 	AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER,
36 	AMDGPU_DM_PIPE_CRC_SOURCE_DPRX,
37 	AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER,
38 	AMDGPU_DM_PIPE_CRC_SOURCE_MAX,
39 	AMDGPU_DM_PIPE_CRC_SOURCE_INVALID = -1,
40 };
41 
42 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
43 #define MAX_CRTC 6
44 
45 struct phy_id_mapping {
46 	bool assigned;
47 	bool is_mst;
48 	uint8_t enc_hw_inst;
49 	u8 lct;
50 	u8 port_num;
51 	u8 rad[8];
52 };
53 
54 struct crc_data {
55 	uint32_t crc_R;
56 	uint32_t crc_G;
57 	uint32_t crc_B;
58 	uint32_t frame_count;
59 	bool crc_ready;
60 };
61 
62 struct crc_info {
63 	struct crc_data crc[MAX_CRC_WINDOW_NUM];
64 	struct completion completion;
65 	spinlock_t lock;
66 };
67 
68 struct crc_window_param {
69 	uint16_t x_start;
70 	uint16_t y_start;
71 	uint16_t x_end;
72 	uint16_t y_end;
73 	/* CRC window is activated or not*/
74 	bool enable;
75 	/* Update crc window during vertical blank or not */
76 	bool update_win;
77 	/* skip reading/writing for few frames */
78 	int skip_frame_cnt;
79 };
80 
81 struct secure_display_crtc_context {
82 	/* work to notify PSP TA*/
83 	struct work_struct notify_ta_work;
84 
85 	/* work to forward ROI to dmcu/dmub */
86 	struct work_struct forward_roi_work;
87 
88 	struct drm_crtc *crtc;
89 
90 	/* Region of Interest (ROI) */
91 	struct crc_window roi[MAX_CRC_WINDOW_NUM];
92 
93 	struct crc_info crc_info;
94 };
95 
96 struct secure_display_context {
97 
98 	struct secure_display_crtc_context *crtc_ctx;
99     /* Whether dmub support multiple ROI setting */
100 	bool support_mul_roi;
101 	bool phy_mapping_updated;
102 	int phy_id_mapping_cnt;
103 	struct phy_id_mapping phy_id_mapping[MAX_CRTC];
104 };
105 #endif
106 
107 static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source source)
108 {
109 	return (source > AMDGPU_DM_PIPE_CRC_SOURCE_NONE) &&
110 	       (source < AMDGPU_DM_PIPE_CRC_SOURCE_MAX);
111 }
112 
113 /* amdgpu_dm_crc.c */
114 #ifdef CONFIG_DEBUG_FS
115 int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
116 					struct dm_crtc_state *dm_crtc_state,
117 					enum amdgpu_dm_pipe_crc_source source);
118 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
119 int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
120 				     const char *src_name,
121 				     size_t *values_cnt);
122 const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
123 						  size_t *count);
124 void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
125 #else
126 #define amdgpu_dm_crtc_set_crc_source NULL
127 #define amdgpu_dm_crtc_verify_crc_source NULL
128 #define amdgpu_dm_crtc_get_crc_sources NULL
129 #define amdgpu_dm_crtc_handle_crc_irq(x)
130 #endif
131 
132 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
133 bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc);
134 void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc);
135 void amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev);
136 #else
137 #define amdgpu_dm_crc_window_is_activated(x)
138 #define amdgpu_dm_crtc_handle_crc_window_irq(x)
139 #define amdgpu_dm_crtc_secure_display_create_contexts(x)
140 #endif
141 
142 #endif /* AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ */
143