1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ 27 #define AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ 28 29 struct drm_crtc; 30 struct dm_crtc_state; 31 32 enum amdgpu_dm_pipe_crc_source { 33 AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0, 34 AMDGPU_DM_PIPE_CRC_SOURCE_CRTC, 35 AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER, 36 AMDGPU_DM_PIPE_CRC_SOURCE_DPRX, 37 AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER, 38 AMDGPU_DM_PIPE_CRC_SOURCE_MAX, 39 AMDGPU_DM_PIPE_CRC_SOURCE_INVALID = -1, 40 }; 41 42 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 43 struct crc_window_param { 44 struct crc_region roi; 45 /* CRC windwo is activated or not*/ 46 bool activated; 47 /* Update crc window during vertical blank or not */ 48 bool update_win; 49 /* skip reading/writing for few frames */ 50 int skip_frame_cnt; 51 }; 52 53 /* read_work for driver to call PSP to read */ 54 struct crc_rd_work { 55 struct work_struct notify_ta_work; 56 /* To protect crc_rd_work carried fields*/ 57 spinlock_t crc_rd_work_lock; 58 struct drm_crtc *crtc; 59 uint8_t phy_inst; 60 }; 61 62 /* forward_work for driver to forward ROI to dmu */ 63 struct crc_fw_work { 64 struct work_struct forward_roi_work; 65 struct amdgpu_display_manager *dm; 66 struct dc_stream_state *stream; 67 struct crc_region roi; 68 bool is_stop_cmd; 69 }; 70 #endif 71 72 static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source source) 73 { 74 return (source > AMDGPU_DM_PIPE_CRC_SOURCE_NONE) && 75 (source < AMDGPU_DM_PIPE_CRC_SOURCE_MAX); 76 } 77 78 /* amdgpu_dm_crc.c */ 79 #ifdef CONFIG_DEBUG_FS 80 int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, 81 struct dm_crtc_state *dm_crtc_state, 82 enum amdgpu_dm_pipe_crc_source source); 83 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name); 84 int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, 85 const char *src_name, 86 size_t *values_cnt); 87 const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, 88 size_t *count); 89 void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc); 90 #else 91 #define amdgpu_dm_crtc_set_crc_source NULL 92 #define amdgpu_dm_crtc_verify_crc_source NULL 93 #define amdgpu_dm_crtc_get_crc_sources NULL 94 #define amdgpu_dm_crtc_handle_crc_irq(x) 95 #endif 96 97 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 98 bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc); 99 void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc); 100 struct crc_rd_work *amdgpu_dm_crtc_secure_display_create_work(void); 101 #else 102 #define amdgpu_dm_crc_window_is_activated(x) 103 #define amdgpu_dm_crtc_handle_crc_window_irq(x) 104 #define amdgpu_dm_crtc_secure_display_create_work() 105 #endif 106 107 #endif /* AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ */ 108