1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ 27 #define AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ 28 29 struct drm_crtc; 30 struct dm_crtc_state; 31 32 enum amdgpu_dm_pipe_crc_source { 33 AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0, 34 AMDGPU_DM_PIPE_CRC_SOURCE_CRTC, 35 AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER, 36 AMDGPU_DM_PIPE_CRC_SOURCE_DPRX, 37 AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER, 38 AMDGPU_DM_PIPE_CRC_SOURCE_MAX, 39 AMDGPU_DM_PIPE_CRC_SOURCE_INVALID = -1, 40 }; 41 42 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 43 #define MAX_CRTC 6 44 45 struct phy_id_mapping { 46 bool assigned; 47 bool is_mst; 48 uint8_t enc_hw_inst; 49 u8 lct; 50 u8 port_num; 51 u8 rad[8]; 52 }; 53 54 struct crc_window_param { 55 uint16_t x_start; 56 uint16_t y_start; 57 uint16_t x_end; 58 uint16_t y_end; 59 /* CRC window is activated or not*/ 60 bool activated; 61 /* Update crc window during vertical blank or not */ 62 bool update_win; 63 /* skip reading/writing for few frames */ 64 int skip_frame_cnt; 65 }; 66 67 struct secure_display_crtc_context { 68 /* work to notify PSP TA*/ 69 struct work_struct notify_ta_work; 70 71 /* work to forward ROI to dmcu/dmub */ 72 struct work_struct forward_roi_work; 73 74 struct drm_crtc *crtc; 75 76 /* Region of Interest (ROI) */ 77 struct rect rect; 78 }; 79 80 struct secure_display_context { 81 82 struct secure_display_crtc_context *crtc_ctx; 83 84 bool phy_mapping_updated; 85 int phy_id_mapping_cnt; 86 struct phy_id_mapping phy_id_mapping[MAX_CRTC]; 87 }; 88 #endif 89 90 static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source source) 91 { 92 return (source > AMDGPU_DM_PIPE_CRC_SOURCE_NONE) && 93 (source < AMDGPU_DM_PIPE_CRC_SOURCE_MAX); 94 } 95 96 /* amdgpu_dm_crc.c */ 97 #ifdef CONFIG_DEBUG_FS 98 int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, 99 struct dm_crtc_state *dm_crtc_state, 100 enum amdgpu_dm_pipe_crc_source source); 101 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name); 102 int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, 103 const char *src_name, 104 size_t *values_cnt); 105 const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, 106 size_t *count); 107 void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc); 108 #else 109 #define amdgpu_dm_crtc_set_crc_source NULL 110 #define amdgpu_dm_crtc_verify_crc_source NULL 111 #define amdgpu_dm_crtc_get_crc_sources NULL 112 #define amdgpu_dm_crtc_handle_crc_irq(x) 113 #endif 114 115 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 116 bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc); 117 void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc); 118 void amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev); 119 #else 120 #define amdgpu_dm_crc_window_is_activated(x) 121 #define amdgpu_dm_crtc_handle_crc_window_irq(x) 122 #define amdgpu_dm_crtc_secure_display_create_contexts(x) 123 #endif 124 125 #endif /* AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ */ 126