1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <drm/drm_crtc.h> 27 #include <drm/drm_vblank.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_dm.h" 31 #include "dc.h" 32 33 static const char *const pipe_crc_sources[] = { 34 "none", 35 "crtc", 36 "crtc dither", 37 "dprx", 38 "dprx dither", 39 "auto", 40 }; 41 42 static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source) 43 { 44 if (!source || !strcmp(source, "none")) 45 return AMDGPU_DM_PIPE_CRC_SOURCE_NONE; 46 if (!strcmp(source, "auto") || !strcmp(source, "crtc")) 47 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC; 48 if (!strcmp(source, "dprx")) 49 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX; 50 if (!strcmp(source, "crtc dither")) 51 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER; 52 if (!strcmp(source, "dprx dither")) 53 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER; 54 55 return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID; 56 } 57 58 static bool dm_is_crc_source_crtc(enum amdgpu_dm_pipe_crc_source src) 59 { 60 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) || 61 (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER); 62 } 63 64 static bool dm_is_crc_source_dprx(enum amdgpu_dm_pipe_crc_source src) 65 { 66 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) || 67 (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER); 68 } 69 70 static bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src) 71 { 72 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER) || 73 (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER) || 74 (src == AMDGPU_DM_PIPE_CRC_SOURCE_NONE); 75 } 76 77 const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, 78 size_t *count) 79 { 80 *count = ARRAY_SIZE(pipe_crc_sources); 81 return pipe_crc_sources; 82 } 83 84 bool amdgpu_dm_crc_window_is_default(struct dm_crtc_state *dm_crtc_state) 85 { 86 bool ret = true; 87 88 if ((dm_crtc_state->crc_window.x_start != 0) || 89 (dm_crtc_state->crc_window.y_start != 0) || 90 (dm_crtc_state->crc_window.x_end != 0) || 91 (dm_crtc_state->crc_window.y_end != 0)) 92 ret = false; 93 94 return ret; 95 } 96 97 bool amdgpu_dm_crc_window_changed(struct dm_crtc_state *dm_new_crtc_state, 98 struct dm_crtc_state *dm_old_crtc_state) 99 { 100 bool ret = false; 101 102 if ((dm_new_crtc_state->crc_window.x_start != dm_old_crtc_state->crc_window.x_start) || 103 (dm_new_crtc_state->crc_window.y_start != dm_old_crtc_state->crc_window.y_start) || 104 (dm_new_crtc_state->crc_window.x_end != dm_old_crtc_state->crc_window.x_end) || 105 (dm_new_crtc_state->crc_window.y_end != dm_old_crtc_state->crc_window.y_end)) 106 ret = true; 107 108 return ret; 109 } 110 111 int 112 amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name, 113 size_t *values_cnt) 114 { 115 enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name); 116 117 if (source < 0) { 118 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n", 119 src_name, crtc->index); 120 return -EINVAL; 121 } 122 123 *values_cnt = 3; 124 return 0; 125 } 126 127 int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, 128 struct dm_crtc_state *dm_crtc_state, 129 enum amdgpu_dm_pipe_crc_source source) 130 { 131 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 132 struct dc_stream_state *stream_state = dm_crtc_state->stream; 133 bool enable = amdgpu_dm_is_valid_crc_source(source); 134 int ret = 0; 135 struct crc_params *crc_window = NULL, tmp_window; 136 137 /* Configuration will be deferred to stream enable. */ 138 if (!stream_state) 139 return 0; 140 141 mutex_lock(&adev->dm.dc_lock); 142 143 /* Enable CRTC CRC generation if necessary. */ 144 if (dm_is_crc_source_crtc(source)) { 145 if (!amdgpu_dm_crc_window_is_default(dm_crtc_state)) { 146 crc_window = &tmp_window; 147 148 tmp_window.windowa_x_start = dm_crtc_state->crc_window.x_start; 149 tmp_window.windowa_y_start = dm_crtc_state->crc_window.y_start; 150 tmp_window.windowa_x_end = dm_crtc_state->crc_window.x_end; 151 tmp_window.windowa_y_end = dm_crtc_state->crc_window.y_end; 152 tmp_window.windowb_x_start = dm_crtc_state->crc_window.x_start; 153 tmp_window.windowb_y_start = dm_crtc_state->crc_window.y_start; 154 tmp_window.windowb_x_end = dm_crtc_state->crc_window.x_end; 155 tmp_window.windowb_y_end = dm_crtc_state->crc_window.y_end; 156 } 157 158 if (!dc_stream_configure_crc(stream_state->ctx->dc, 159 stream_state, crc_window, enable, enable)) { 160 ret = -EINVAL; 161 goto unlock; 162 } 163 } 164 165 /* Configure dithering */ 166 if (!dm_need_crc_dither(source)) { 167 dc_stream_set_dither_option(stream_state, DITHER_OPTION_TRUN8); 168 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state, 169 DYN_EXPANSION_DISABLE); 170 } else { 171 dc_stream_set_dither_option(stream_state, 172 DITHER_OPTION_DEFAULT); 173 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state, 174 DYN_EXPANSION_AUTO); 175 } 176 177 unlock: 178 mutex_unlock(&adev->dm.dc_lock); 179 180 return ret; 181 } 182 183 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) 184 { 185 enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name); 186 struct drm_crtc_commit *commit; 187 struct dm_crtc_state *crtc_state; 188 struct drm_dp_aux *aux = NULL; 189 bool enable = false; 190 bool enabled = false; 191 int ret = 0; 192 193 if (source < 0) { 194 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n", 195 src_name, crtc->index); 196 return -EINVAL; 197 } 198 199 ret = drm_modeset_lock(&crtc->mutex, NULL); 200 if (ret) 201 return ret; 202 203 spin_lock(&crtc->commit_lock); 204 commit = list_first_entry_or_null(&crtc->commit_list, 205 struct drm_crtc_commit, commit_entry); 206 if (commit) 207 drm_crtc_commit_get(commit); 208 spin_unlock(&crtc->commit_lock); 209 210 if (commit) { 211 /* 212 * Need to wait for all outstanding programming to complete 213 * in commit tail since it can modify CRC related fields and 214 * hardware state. Since we're holding the CRTC lock we're 215 * guaranteed that no other commit work can be queued off 216 * before we modify the state below. 217 */ 218 ret = wait_for_completion_interruptible_timeout( 219 &commit->hw_done, 10 * HZ); 220 if (ret) 221 goto cleanup; 222 } 223 224 enable = amdgpu_dm_is_valid_crc_source(source); 225 crtc_state = to_dm_crtc_state(crtc->state); 226 227 /* 228 * USER REQ SRC | CURRENT SRC | BEHAVIOR 229 * ----------------------------- 230 * None | None | Do nothing 231 * None | CRTC | Disable CRTC CRC, set default to dither 232 * None | DPRX | Disable DPRX CRC, need 'aux', set default to dither 233 * None | CRTC DITHER | Disable CRTC CRC 234 * None | DPRX DITHER | Disable DPRX CRC, need 'aux' 235 * CRTC | XXXX | Enable CRTC CRC, no dither 236 * DPRX | XXXX | Enable DPRX CRC, need 'aux', no dither 237 * CRTC DITHER | XXXX | Enable CRTC CRC, set dither 238 * DPRX DITHER | XXXX | Enable DPRX CRC, need 'aux', set dither 239 */ 240 if (dm_is_crc_source_dprx(source) || 241 (source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE && 242 dm_is_crc_source_dprx(crtc_state->crc_src))) { 243 struct amdgpu_dm_connector *aconn = NULL; 244 struct drm_connector *connector; 245 struct drm_connector_list_iter conn_iter; 246 247 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 248 drm_for_each_connector_iter(connector, &conn_iter) { 249 if (!connector->state || connector->state->crtc != crtc) 250 continue; 251 252 aconn = to_amdgpu_dm_connector(connector); 253 break; 254 } 255 drm_connector_list_iter_end(&conn_iter); 256 257 if (!aconn) { 258 DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index); 259 ret = -EINVAL; 260 goto cleanup; 261 } 262 263 aux = &aconn->dm_dp_aux.aux; 264 265 if (!aux) { 266 DRM_DEBUG_DRIVER("No dp aux for amd connector\n"); 267 ret = -EINVAL; 268 goto cleanup; 269 } 270 } 271 272 if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) { 273 ret = -EINVAL; 274 goto cleanup; 275 } 276 277 /* 278 * Reading the CRC requires the vblank interrupt handler to be 279 * enabled. Keep a reference until CRC capture stops. 280 */ 281 enabled = amdgpu_dm_is_valid_crc_source(crtc_state->crc_src); 282 if (!enabled && enable) { 283 ret = drm_crtc_vblank_get(crtc); 284 if (ret) 285 goto cleanup; 286 287 if (dm_is_crc_source_dprx(source)) { 288 if (drm_dp_start_crc(aux, crtc)) { 289 DRM_DEBUG_DRIVER("dp start crc failed\n"); 290 ret = -EINVAL; 291 goto cleanup; 292 } 293 } 294 } else if (enabled && !enable) { 295 drm_crtc_vblank_put(crtc); 296 if (dm_is_crc_source_dprx(source)) { 297 if (drm_dp_stop_crc(aux)) { 298 DRM_DEBUG_DRIVER("dp stop crc failed\n"); 299 ret = -EINVAL; 300 goto cleanup; 301 } 302 } 303 } 304 305 crtc_state->crc_src = source; 306 307 /* Reset crc_skipped on dm state */ 308 crtc_state->crc_skip_count = 0; 309 310 cleanup: 311 if (commit) 312 drm_crtc_commit_put(commit); 313 314 drm_modeset_unlock(&crtc->mutex); 315 316 return ret; 317 } 318 319 /** 320 * amdgpu_dm_crtc_handle_crc_irq: Report to DRM the CRC on given CRTC. 321 * @crtc: DRM CRTC object. 322 * 323 * This function should be called at the end of a vblank, when the fb has been 324 * fully processed through the pipe. 325 */ 326 void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc) 327 { 328 struct dm_crtc_state *crtc_state; 329 struct dc_stream_state *stream_state; 330 uint32_t crcs[3]; 331 332 if (crtc == NULL) 333 return; 334 335 crtc_state = to_dm_crtc_state(crtc->state); 336 stream_state = crtc_state->stream; 337 338 /* Early return if CRC capture is not enabled. */ 339 if (!amdgpu_dm_is_valid_crc_source(crtc_state->crc_src)) 340 return; 341 342 /* 343 * Since flipping and crc enablement happen asynchronously, we - more 344 * often than not - will be returning an 'uncooked' crc on first frame. 345 * Probably because hw isn't ready yet. For added security, skip the 346 * first two CRC values. 347 */ 348 if (crtc_state->crc_skip_count < 2) { 349 crtc_state->crc_skip_count += 1; 350 return; 351 } 352 353 if (dm_is_crc_source_crtc(crtc_state->crc_src)) { 354 if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state, 355 &crcs[0], &crcs[1], &crcs[2])) 356 return; 357 358 drm_crtc_add_crc_entry(crtc, true, 359 drm_crtc_accurate_vblank_count(crtc), crcs); 360 } 361 } 362