1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <drm/drm_crtc.h> 27 #include <drm/drm_vblank.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_dm.h" 31 #include "dc.h" 32 #include "amdgpu_securedisplay.h" 33 34 static const char *const pipe_crc_sources[] = { 35 "none", 36 "crtc", 37 "crtc dither", 38 "dprx", 39 "dprx dither", 40 "auto", 41 }; 42 43 static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source) 44 { 45 if (!source || !strcmp(source, "none")) 46 return AMDGPU_DM_PIPE_CRC_SOURCE_NONE; 47 if (!strcmp(source, "auto") || !strcmp(source, "crtc")) 48 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC; 49 if (!strcmp(source, "dprx")) 50 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX; 51 if (!strcmp(source, "crtc dither")) 52 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER; 53 if (!strcmp(source, "dprx dither")) 54 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER; 55 56 return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID; 57 } 58 59 static bool dm_is_crc_source_crtc(enum amdgpu_dm_pipe_crc_source src) 60 { 61 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) || 62 (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER); 63 } 64 65 static bool dm_is_crc_source_dprx(enum amdgpu_dm_pipe_crc_source src) 66 { 67 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) || 68 (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER); 69 } 70 71 static bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src) 72 { 73 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER) || 74 (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER) || 75 (src == AMDGPU_DM_PIPE_CRC_SOURCE_NONE); 76 } 77 78 const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, 79 size_t *count) 80 { 81 *count = ARRAY_SIZE(pipe_crc_sources); 82 return pipe_crc_sources; 83 } 84 85 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 86 static void amdgpu_dm_set_crc_window_default(struct drm_crtc *crtc) 87 { 88 struct drm_device *drm_dev = crtc->dev; 89 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 90 91 spin_lock_irq(&drm_dev->event_lock); 92 acrtc->dm_irq_params.window_param.x_start = 0; 93 acrtc->dm_irq_params.window_param.y_start = 0; 94 acrtc->dm_irq_params.window_param.x_end = 0; 95 acrtc->dm_irq_params.window_param.y_end = 0; 96 acrtc->dm_irq_params.window_param.activated = false; 97 acrtc->dm_irq_params.window_param.update_win = false; 98 acrtc->dm_irq_params.window_param.skip_frame_cnt = 0; 99 spin_unlock_irq(&drm_dev->event_lock); 100 } 101 102 static void amdgpu_dm_crtc_notify_ta_to_read(struct work_struct *work) 103 { 104 struct secure_display_context *secure_display_ctx; 105 struct psp_context *psp; 106 struct securedisplay_cmd *securedisplay_cmd; 107 struct drm_crtc *crtc; 108 struct dc_stream_state *stream; 109 uint8_t phy_inst; 110 int ret; 111 112 secure_display_ctx = container_of(work, struct secure_display_context, notify_ta_work); 113 crtc = secure_display_ctx->crtc; 114 115 if (!crtc) { 116 return; 117 } 118 119 psp = &drm_to_adev(crtc->dev)->psp; 120 stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream; 121 phy_inst = stream->link->link_enc_hw_inst; 122 123 /* need lock for multiple crtcs to use the command buffer */ 124 mutex_lock(&psp->securedisplay_context.mutex); 125 126 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 127 TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC); 128 129 securedisplay_cmd->securedisplay_in_message.send_roi_crc.phy_id = phy_inst; 130 131 /* PSP TA is expected to finish data transmission over I2C within current frame, 132 * even there are up to 4 crtcs request to send in this frame. 133 */ 134 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC); 135 136 if (!ret) { 137 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 138 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 139 } 140 } 141 142 mutex_unlock(&psp->securedisplay_context.mutex); 143 } 144 145 static void 146 amdgpu_dm_forward_crc_window(struct work_struct *work) 147 { 148 struct secure_display_context *secure_display_ctx; 149 struct amdgpu_display_manager *dm; 150 struct drm_crtc *crtc; 151 struct dc_stream_state *stream; 152 153 secure_display_ctx = container_of(work, struct secure_display_context, forward_roi_work); 154 crtc = secure_display_ctx->crtc; 155 156 if (!crtc) 157 return; 158 159 dm = &drm_to_adev(crtc->dev)->dm; 160 stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream; 161 162 mutex_lock(&dm->dc_lock); 163 dc_stream_forward_crc_window(stream, &secure_display_ctx->rect, false); 164 mutex_unlock(&dm->dc_lock); 165 } 166 167 bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc) 168 { 169 struct drm_device *drm_dev = crtc->dev; 170 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 171 bool ret = false; 172 173 spin_lock_irq(&drm_dev->event_lock); 174 ret = acrtc->dm_irq_params.window_param.activated; 175 spin_unlock_irq(&drm_dev->event_lock); 176 177 return ret; 178 } 179 #endif 180 181 int 182 amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name, 183 size_t *values_cnt) 184 { 185 enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name); 186 187 if (source < 0) { 188 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n", 189 src_name, crtc->index); 190 return -EINVAL; 191 } 192 193 *values_cnt = 3; 194 return 0; 195 } 196 197 int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, 198 struct dm_crtc_state *dm_crtc_state, 199 enum amdgpu_dm_pipe_crc_source source) 200 { 201 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 202 int i; 203 #endif 204 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 205 struct dc_stream_state *stream_state = dm_crtc_state->stream; 206 bool enable = amdgpu_dm_is_valid_crc_source(source); 207 int ret = 0; 208 209 /* Configuration will be deferred to stream enable. */ 210 if (!stream_state) 211 return -EINVAL; 212 213 mutex_lock(&adev->dm.dc_lock); 214 215 /* Enable or disable CRTC CRC generation */ 216 if (dm_is_crc_source_crtc(source) || source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) { 217 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 218 /* Disable secure_display if it was enabled */ 219 if (!enable) { 220 for (i = 0; i < adev->dm.dc->caps.max_links; i++) { 221 if (adev->dm.secure_display_ctxs[i].crtc == crtc) { 222 /* stop ROI update on this crtc */ 223 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work); 224 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work); 225 dc_stream_forward_crc_window(stream_state, NULL, true); 226 } 227 } 228 } 229 #endif 230 if (!dc_stream_configure_crc(stream_state->ctx->dc, 231 stream_state, NULL, enable, enable)) { 232 ret = -EINVAL; 233 goto unlock; 234 } 235 } 236 237 /* Configure dithering */ 238 if (!dm_need_crc_dither(source)) { 239 dc_stream_set_dither_option(stream_state, DITHER_OPTION_TRUN8); 240 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state, 241 DYN_EXPANSION_DISABLE); 242 } else { 243 dc_stream_set_dither_option(stream_state, 244 DITHER_OPTION_DEFAULT); 245 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state, 246 DYN_EXPANSION_AUTO); 247 } 248 249 unlock: 250 mutex_unlock(&adev->dm.dc_lock); 251 252 return ret; 253 } 254 255 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) 256 { 257 enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name); 258 enum amdgpu_dm_pipe_crc_source cur_crc_src; 259 struct drm_crtc_commit *commit; 260 struct dm_crtc_state *crtc_state; 261 struct drm_device *drm_dev = crtc->dev; 262 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 263 struct drm_dp_aux *aux = NULL; 264 bool enable = false; 265 bool enabled = false; 266 int ret = 0; 267 268 if (source < 0) { 269 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n", 270 src_name, crtc->index); 271 return -EINVAL; 272 } 273 274 ret = drm_modeset_lock(&crtc->mutex, NULL); 275 if (ret) 276 return ret; 277 278 spin_lock(&crtc->commit_lock); 279 commit = list_first_entry_or_null(&crtc->commit_list, 280 struct drm_crtc_commit, commit_entry); 281 if (commit) 282 drm_crtc_commit_get(commit); 283 spin_unlock(&crtc->commit_lock); 284 285 if (commit) { 286 /* 287 * Need to wait for all outstanding programming to complete 288 * in commit tail since it can modify CRC related fields and 289 * hardware state. Since we're holding the CRTC lock we're 290 * guaranteed that no other commit work can be queued off 291 * before we modify the state below. 292 */ 293 ret = wait_for_completion_interruptible_timeout( 294 &commit->hw_done, 10 * HZ); 295 if (ret) 296 goto cleanup; 297 } 298 299 enable = amdgpu_dm_is_valid_crc_source(source); 300 crtc_state = to_dm_crtc_state(crtc->state); 301 spin_lock_irq(&drm_dev->event_lock); 302 cur_crc_src = acrtc->dm_irq_params.crc_src; 303 spin_unlock_irq(&drm_dev->event_lock); 304 305 /* 306 * USER REQ SRC | CURRENT SRC | BEHAVIOR 307 * ----------------------------- 308 * None | None | Do nothing 309 * None | CRTC | Disable CRTC CRC, set default to dither 310 * None | DPRX | Disable DPRX CRC, need 'aux', set default to dither 311 * None | CRTC DITHER | Disable CRTC CRC 312 * None | DPRX DITHER | Disable DPRX CRC, need 'aux' 313 * CRTC | XXXX | Enable CRTC CRC, no dither 314 * DPRX | XXXX | Enable DPRX CRC, need 'aux', no dither 315 * CRTC DITHER | XXXX | Enable CRTC CRC, set dither 316 * DPRX DITHER | XXXX | Enable DPRX CRC, need 'aux', set dither 317 */ 318 if (dm_is_crc_source_dprx(source) || 319 (source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE && 320 dm_is_crc_source_dprx(cur_crc_src))) { 321 struct amdgpu_dm_connector *aconn = NULL; 322 struct drm_connector *connector; 323 struct drm_connector_list_iter conn_iter; 324 325 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 326 drm_for_each_connector_iter(connector, &conn_iter) { 327 if (!connector->state || connector->state->crtc != crtc) 328 continue; 329 330 aconn = to_amdgpu_dm_connector(connector); 331 break; 332 } 333 drm_connector_list_iter_end(&conn_iter); 334 335 if (!aconn) { 336 DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index); 337 ret = -EINVAL; 338 goto cleanup; 339 } 340 341 aux = (aconn->port) ? &aconn->port->aux : &aconn->dm_dp_aux.aux; 342 343 if (!aux) { 344 DRM_DEBUG_DRIVER("No dp aux for amd connector\n"); 345 ret = -EINVAL; 346 goto cleanup; 347 } 348 349 if ((aconn->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) && 350 (aconn->base.connector_type != DRM_MODE_CONNECTOR_eDP)) { 351 DRM_DEBUG_DRIVER("No DP connector available for CRC source\n"); 352 ret = -EINVAL; 353 goto cleanup; 354 } 355 356 } 357 358 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 359 /* Reset secure_display when we change crc source from debugfs */ 360 amdgpu_dm_set_crc_window_default(crtc); 361 #endif 362 363 if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) { 364 ret = -EINVAL; 365 goto cleanup; 366 } 367 368 /* 369 * Reading the CRC requires the vblank interrupt handler to be 370 * enabled. Keep a reference until CRC capture stops. 371 */ 372 enabled = amdgpu_dm_is_valid_crc_source(cur_crc_src); 373 if (!enabled && enable) { 374 ret = drm_crtc_vblank_get(crtc); 375 if (ret) 376 goto cleanup; 377 378 if (dm_is_crc_source_dprx(source)) { 379 if (drm_dp_start_crc(aux, crtc)) { 380 DRM_DEBUG_DRIVER("dp start crc failed\n"); 381 ret = -EINVAL; 382 goto cleanup; 383 } 384 } 385 } else if (enabled && !enable) { 386 drm_crtc_vblank_put(crtc); 387 if (dm_is_crc_source_dprx(source)) { 388 if (drm_dp_stop_crc(aux)) { 389 DRM_DEBUG_DRIVER("dp stop crc failed\n"); 390 ret = -EINVAL; 391 goto cleanup; 392 } 393 } 394 } 395 396 spin_lock_irq(&drm_dev->event_lock); 397 acrtc->dm_irq_params.crc_src = source; 398 spin_unlock_irq(&drm_dev->event_lock); 399 400 /* Reset crc_skipped on dm state */ 401 crtc_state->crc_skip_count = 0; 402 403 cleanup: 404 if (commit) 405 drm_crtc_commit_put(commit); 406 407 drm_modeset_unlock(&crtc->mutex); 408 409 return ret; 410 } 411 412 /** 413 * amdgpu_dm_crtc_handle_crc_irq: Report to DRM the CRC on given CRTC. 414 * @crtc: DRM CRTC object. 415 * 416 * This function should be called at the end of a vblank, when the fb has been 417 * fully processed through the pipe. 418 */ 419 void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc) 420 { 421 struct dm_crtc_state *crtc_state; 422 struct dc_stream_state *stream_state; 423 struct drm_device *drm_dev = NULL; 424 enum amdgpu_dm_pipe_crc_source cur_crc_src; 425 struct amdgpu_crtc *acrtc = NULL; 426 uint32_t crcs[3]; 427 unsigned long flags; 428 429 if (crtc == NULL) 430 return; 431 432 crtc_state = to_dm_crtc_state(crtc->state); 433 stream_state = crtc_state->stream; 434 acrtc = to_amdgpu_crtc(crtc); 435 drm_dev = crtc->dev; 436 437 spin_lock_irqsave(&drm_dev->event_lock, flags); 438 cur_crc_src = acrtc->dm_irq_params.crc_src; 439 spin_unlock_irqrestore(&drm_dev->event_lock, flags); 440 441 /* Early return if CRC capture is not enabled. */ 442 if (!amdgpu_dm_is_valid_crc_source(cur_crc_src)) 443 return; 444 445 /* 446 * Since flipping and crc enablement happen asynchronously, we - more 447 * often than not - will be returning an 'uncooked' crc on first frame. 448 * Probably because hw isn't ready yet. For added security, skip the 449 * first two CRC values. 450 */ 451 if (crtc_state->crc_skip_count < 2) { 452 crtc_state->crc_skip_count += 1; 453 return; 454 } 455 456 if (dm_is_crc_source_crtc(cur_crc_src)) { 457 if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state, 458 &crcs[0], &crcs[1], &crcs[2])) 459 return; 460 461 drm_crtc_add_crc_entry(crtc, true, 462 drm_crtc_accurate_vblank_count(crtc), crcs); 463 } 464 } 465 466 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 467 void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) 468 { 469 struct drm_device *drm_dev = NULL; 470 enum amdgpu_dm_pipe_crc_source cur_crc_src; 471 struct amdgpu_crtc *acrtc = NULL; 472 struct amdgpu_device *adev = NULL; 473 struct secure_display_context *secure_display_ctx = NULL; 474 unsigned long flags1; 475 476 if (crtc == NULL) 477 return; 478 479 acrtc = to_amdgpu_crtc(crtc); 480 adev = drm_to_adev(crtc->dev); 481 drm_dev = crtc->dev; 482 483 spin_lock_irqsave(&drm_dev->event_lock, flags1); 484 cur_crc_src = acrtc->dm_irq_params.crc_src; 485 486 /* Early return if CRC capture is not enabled. */ 487 if (!amdgpu_dm_is_valid_crc_source(cur_crc_src) || 488 !dm_is_crc_source_crtc(cur_crc_src)) 489 goto cleanup; 490 491 if (!acrtc->dm_irq_params.window_param.activated) 492 goto cleanup; 493 494 if (acrtc->dm_irq_params.window_param.skip_frame_cnt) { 495 acrtc->dm_irq_params.window_param.skip_frame_cnt -= 1; 496 goto cleanup; 497 } 498 499 secure_display_ctx = &adev->dm.secure_display_ctxs[acrtc->crtc_id]; 500 if (WARN_ON(secure_display_ctx->crtc != crtc)) { 501 /* We have set the crtc when creating secure_display_context, 502 * don't expect it to be changed here. 503 */ 504 secure_display_ctx->crtc = crtc; 505 } 506 507 if (acrtc->dm_irq_params.window_param.update_win) { 508 /* prepare work for dmub to update ROI */ 509 secure_display_ctx->rect.x = acrtc->dm_irq_params.window_param.x_start; 510 secure_display_ctx->rect.y = acrtc->dm_irq_params.window_param.y_start; 511 secure_display_ctx->rect.width = acrtc->dm_irq_params.window_param.x_end - 512 acrtc->dm_irq_params.window_param.x_start; 513 secure_display_ctx->rect.height = acrtc->dm_irq_params.window_param.y_end - 514 acrtc->dm_irq_params.window_param.y_start; 515 schedule_work(&secure_display_ctx->forward_roi_work); 516 517 acrtc->dm_irq_params.window_param.update_win = false; 518 519 /* Statically skip 1 frame, because we may need to wait below things 520 * before sending ROI to dmub: 521 * 1. We defer the work by using system workqueue. 522 * 2. We may need to wait for dc_lock before accessing dmub. 523 */ 524 acrtc->dm_irq_params.window_param.skip_frame_cnt = 1; 525 526 } else { 527 /* prepare work for psp to read ROI/CRC and send to I2C */ 528 schedule_work(&secure_display_ctx->notify_ta_work); 529 } 530 531 cleanup: 532 spin_unlock_irqrestore(&drm_dev->event_lock, flags1); 533 } 534 535 struct secure_display_context * 536 amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev) 537 { 538 struct secure_display_context *secure_display_ctxs = NULL; 539 int i; 540 541 secure_display_ctxs = kcalloc(AMDGPU_MAX_CRTCS, sizeof(struct secure_display_context), GFP_KERNEL); 542 543 if (!secure_display_ctxs) 544 return NULL; 545 546 for (i = 0; i < adev->dm.dc->caps.max_links; i++) { 547 INIT_WORK(&secure_display_ctxs[i].forward_roi_work, amdgpu_dm_forward_crc_window); 548 INIT_WORK(&secure_display_ctxs[i].notify_ta_work, amdgpu_dm_crtc_notify_ta_to_read); 549 secure_display_ctxs[i].crtc = &adev->mode_info.crtcs[i]->base; 550 } 551 552 return secure_display_ctxs; 553 } 554 #endif 555