1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <drm/drm_crtc.h> 27 #include <drm/drm_vblank.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_dm.h" 31 #include "dc.h" 32 #include "amdgpu_securedisplay.h" 33 34 static const char *const pipe_crc_sources[] = { 35 "none", 36 "crtc", 37 "crtc dither", 38 "dprx", 39 "dprx dither", 40 "auto", 41 }; 42 43 static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source) 44 { 45 if (!source || !strcmp(source, "none")) 46 return AMDGPU_DM_PIPE_CRC_SOURCE_NONE; 47 if (!strcmp(source, "auto") || !strcmp(source, "crtc")) 48 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC; 49 if (!strcmp(source, "dprx")) 50 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX; 51 if (!strcmp(source, "crtc dither")) 52 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER; 53 if (!strcmp(source, "dprx dither")) 54 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER; 55 56 return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID; 57 } 58 59 static bool dm_is_crc_source_crtc(enum amdgpu_dm_pipe_crc_source src) 60 { 61 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) || 62 (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER); 63 } 64 65 static bool dm_is_crc_source_dprx(enum amdgpu_dm_pipe_crc_source src) 66 { 67 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) || 68 (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER); 69 } 70 71 static bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src) 72 { 73 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER) || 74 (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER) || 75 (src == AMDGPU_DM_PIPE_CRC_SOURCE_NONE); 76 } 77 78 const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, 79 size_t *count) 80 { 81 *count = ARRAY_SIZE(pipe_crc_sources); 82 return pipe_crc_sources; 83 } 84 85 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 86 static void amdgpu_dm_set_crc_window_default(struct drm_crtc *crtc) 87 { 88 struct drm_device *drm_dev = crtc->dev; 89 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 90 91 spin_lock_irq(&drm_dev->event_lock); 92 acrtc->dm_irq_params.window_param.x_start = 0; 93 acrtc->dm_irq_params.window_param.y_start = 0; 94 acrtc->dm_irq_params.window_param.x_end = 0; 95 acrtc->dm_irq_params.window_param.y_end = 0; 96 acrtc->dm_irq_params.window_param.activated = false; 97 acrtc->dm_irq_params.window_param.update_win = false; 98 acrtc->dm_irq_params.window_param.skip_frame_cnt = 0; 99 spin_unlock_irq(&drm_dev->event_lock); 100 } 101 102 static void amdgpu_dm_crtc_notify_ta_to_read(struct work_struct *work) 103 { 104 struct crc_rd_work *crc_rd_wrk; 105 struct amdgpu_device *adev; 106 struct psp_context *psp; 107 struct securedisplay_cmd *securedisplay_cmd; 108 struct drm_crtc *crtc; 109 uint8_t phy_id; 110 int ret; 111 112 crc_rd_wrk = container_of(work, struct crc_rd_work, notify_ta_work); 113 spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock); 114 crtc = crc_rd_wrk->crtc; 115 116 if (!crtc) { 117 spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock); 118 return; 119 } 120 121 adev = drm_to_adev(crtc->dev); 122 psp = &adev->psp; 123 phy_id = crc_rd_wrk->phy_inst; 124 spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock); 125 126 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 127 TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC); 128 securedisplay_cmd->securedisplay_in_message.send_roi_crc.phy_id = 129 phy_id; 130 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC); 131 if (!ret) { 132 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 133 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 134 } 135 } 136 } 137 138 static void 139 amdgpu_dm_forward_crc_window(struct work_struct *work) 140 { 141 struct crc_fw_work *crc_fw_wrk; 142 struct amdgpu_display_manager *dm; 143 144 crc_fw_wrk = container_of(work, struct crc_fw_work, forward_roi_work); 145 dm = crc_fw_wrk->dm; 146 147 mutex_lock(&dm->dc_lock); 148 dc_stream_forward_crc_window(dm->dc, &crc_fw_wrk->rect, crc_fw_wrk->stream, crc_fw_wrk->is_stop_cmd); 149 mutex_unlock(&dm->dc_lock); 150 151 kfree(crc_fw_wrk); 152 } 153 154 bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc) 155 { 156 struct drm_device *drm_dev = crtc->dev; 157 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 158 bool ret = false; 159 160 spin_lock_irq(&drm_dev->event_lock); 161 ret = acrtc->dm_irq_params.window_param.activated; 162 spin_unlock_irq(&drm_dev->event_lock); 163 164 return ret; 165 } 166 #endif 167 168 int 169 amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name, 170 size_t *values_cnt) 171 { 172 enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name); 173 174 if (source < 0) { 175 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n", 176 src_name, crtc->index); 177 return -EINVAL; 178 } 179 180 *values_cnt = 3; 181 return 0; 182 } 183 184 int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, 185 struct dm_crtc_state *dm_crtc_state, 186 enum amdgpu_dm_pipe_crc_source source) 187 { 188 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 189 struct dc_stream_state *stream_state = dm_crtc_state->stream; 190 bool enable = amdgpu_dm_is_valid_crc_source(source); 191 int ret = 0; 192 193 /* Configuration will be deferred to stream enable. */ 194 if (!stream_state) 195 return -EINVAL; 196 197 mutex_lock(&adev->dm.dc_lock); 198 199 /* Enable CRTC CRC generation if necessary. */ 200 if (dm_is_crc_source_crtc(source) || source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) { 201 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 202 if (!enable) { 203 if (adev->dm.crc_rd_wrk) { 204 flush_work(&adev->dm.crc_rd_wrk->notify_ta_work); 205 spin_lock_irq(&adev->dm.crc_rd_wrk->crc_rd_work_lock); 206 207 if (adev->dm.crc_rd_wrk->crtc == crtc) { 208 /* stop ROI update on this crtc */ 209 dc_stream_forward_crc_window(stream_state->ctx->dc, 210 NULL, stream_state, true); 211 adev->dm.crc_rd_wrk->crtc = NULL; 212 } 213 spin_unlock_irq(&adev->dm.crc_rd_wrk->crc_rd_work_lock); 214 } 215 } 216 #endif 217 if (!dc_stream_configure_crc(stream_state->ctx->dc, 218 stream_state, NULL, enable, enable)) { 219 ret = -EINVAL; 220 goto unlock; 221 } 222 } 223 224 /* Configure dithering */ 225 if (!dm_need_crc_dither(source)) { 226 dc_stream_set_dither_option(stream_state, DITHER_OPTION_TRUN8); 227 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state, 228 DYN_EXPANSION_DISABLE); 229 } else { 230 dc_stream_set_dither_option(stream_state, 231 DITHER_OPTION_DEFAULT); 232 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state, 233 DYN_EXPANSION_AUTO); 234 } 235 236 unlock: 237 mutex_unlock(&adev->dm.dc_lock); 238 239 return ret; 240 } 241 242 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) 243 { 244 enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name); 245 enum amdgpu_dm_pipe_crc_source cur_crc_src; 246 struct drm_crtc_commit *commit; 247 struct dm_crtc_state *crtc_state; 248 struct drm_device *drm_dev = crtc->dev; 249 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 250 struct drm_dp_aux *aux = NULL; 251 bool enable = false; 252 bool enabled = false; 253 int ret = 0; 254 255 if (source < 0) { 256 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n", 257 src_name, crtc->index); 258 return -EINVAL; 259 } 260 261 ret = drm_modeset_lock(&crtc->mutex, NULL); 262 if (ret) 263 return ret; 264 265 spin_lock(&crtc->commit_lock); 266 commit = list_first_entry_or_null(&crtc->commit_list, 267 struct drm_crtc_commit, commit_entry); 268 if (commit) 269 drm_crtc_commit_get(commit); 270 spin_unlock(&crtc->commit_lock); 271 272 if (commit) { 273 /* 274 * Need to wait for all outstanding programming to complete 275 * in commit tail since it can modify CRC related fields and 276 * hardware state. Since we're holding the CRTC lock we're 277 * guaranteed that no other commit work can be queued off 278 * before we modify the state below. 279 */ 280 ret = wait_for_completion_interruptible_timeout( 281 &commit->hw_done, 10 * HZ); 282 if (ret) 283 goto cleanup; 284 } 285 286 enable = amdgpu_dm_is_valid_crc_source(source); 287 crtc_state = to_dm_crtc_state(crtc->state); 288 spin_lock_irq(&drm_dev->event_lock); 289 cur_crc_src = acrtc->dm_irq_params.crc_src; 290 spin_unlock_irq(&drm_dev->event_lock); 291 292 /* 293 * USER REQ SRC | CURRENT SRC | BEHAVIOR 294 * ----------------------------- 295 * None | None | Do nothing 296 * None | CRTC | Disable CRTC CRC, set default to dither 297 * None | DPRX | Disable DPRX CRC, need 'aux', set default to dither 298 * None | CRTC DITHER | Disable CRTC CRC 299 * None | DPRX DITHER | Disable DPRX CRC, need 'aux' 300 * CRTC | XXXX | Enable CRTC CRC, no dither 301 * DPRX | XXXX | Enable DPRX CRC, need 'aux', no dither 302 * CRTC DITHER | XXXX | Enable CRTC CRC, set dither 303 * DPRX DITHER | XXXX | Enable DPRX CRC, need 'aux', set dither 304 */ 305 if (dm_is_crc_source_dprx(source) || 306 (source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE && 307 dm_is_crc_source_dprx(cur_crc_src))) { 308 struct amdgpu_dm_connector *aconn = NULL; 309 struct drm_connector *connector; 310 struct drm_connector_list_iter conn_iter; 311 312 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 313 drm_for_each_connector_iter(connector, &conn_iter) { 314 if (!connector->state || connector->state->crtc != crtc) 315 continue; 316 317 aconn = to_amdgpu_dm_connector(connector); 318 break; 319 } 320 drm_connector_list_iter_end(&conn_iter); 321 322 if (!aconn) { 323 DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index); 324 ret = -EINVAL; 325 goto cleanup; 326 } 327 328 aux = (aconn->port) ? &aconn->port->aux : &aconn->dm_dp_aux.aux; 329 330 if (!aux) { 331 DRM_DEBUG_DRIVER("No dp aux for amd connector\n"); 332 ret = -EINVAL; 333 goto cleanup; 334 } 335 336 if ((aconn->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) && 337 (aconn->base.connector_type != DRM_MODE_CONNECTOR_eDP)) { 338 DRM_DEBUG_DRIVER("No DP connector available for CRC source\n"); 339 ret = -EINVAL; 340 goto cleanup; 341 } 342 343 } 344 345 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 346 amdgpu_dm_set_crc_window_default(crtc); 347 #endif 348 349 if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) { 350 ret = -EINVAL; 351 goto cleanup; 352 } 353 354 /* 355 * Reading the CRC requires the vblank interrupt handler to be 356 * enabled. Keep a reference until CRC capture stops. 357 */ 358 enabled = amdgpu_dm_is_valid_crc_source(cur_crc_src); 359 if (!enabled && enable) { 360 ret = drm_crtc_vblank_get(crtc); 361 if (ret) 362 goto cleanup; 363 364 if (dm_is_crc_source_dprx(source)) { 365 if (drm_dp_start_crc(aux, crtc)) { 366 DRM_DEBUG_DRIVER("dp start crc failed\n"); 367 ret = -EINVAL; 368 goto cleanup; 369 } 370 } 371 } else if (enabled && !enable) { 372 drm_crtc_vblank_put(crtc); 373 if (dm_is_crc_source_dprx(source)) { 374 if (drm_dp_stop_crc(aux)) { 375 DRM_DEBUG_DRIVER("dp stop crc failed\n"); 376 ret = -EINVAL; 377 goto cleanup; 378 } 379 } 380 } 381 382 spin_lock_irq(&drm_dev->event_lock); 383 acrtc->dm_irq_params.crc_src = source; 384 spin_unlock_irq(&drm_dev->event_lock); 385 386 /* Reset crc_skipped on dm state */ 387 crtc_state->crc_skip_count = 0; 388 389 cleanup: 390 if (commit) 391 drm_crtc_commit_put(commit); 392 393 drm_modeset_unlock(&crtc->mutex); 394 395 return ret; 396 } 397 398 /** 399 * amdgpu_dm_crtc_handle_crc_irq: Report to DRM the CRC on given CRTC. 400 * @crtc: DRM CRTC object. 401 * 402 * This function should be called at the end of a vblank, when the fb has been 403 * fully processed through the pipe. 404 */ 405 void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc) 406 { 407 struct dm_crtc_state *crtc_state; 408 struct dc_stream_state *stream_state; 409 struct drm_device *drm_dev = NULL; 410 enum amdgpu_dm_pipe_crc_source cur_crc_src; 411 struct amdgpu_crtc *acrtc = NULL; 412 uint32_t crcs[3]; 413 unsigned long flags; 414 415 if (crtc == NULL) 416 return; 417 418 crtc_state = to_dm_crtc_state(crtc->state); 419 stream_state = crtc_state->stream; 420 acrtc = to_amdgpu_crtc(crtc); 421 drm_dev = crtc->dev; 422 423 spin_lock_irqsave(&drm_dev->event_lock, flags); 424 cur_crc_src = acrtc->dm_irq_params.crc_src; 425 spin_unlock_irqrestore(&drm_dev->event_lock, flags); 426 427 /* Early return if CRC capture is not enabled. */ 428 if (!amdgpu_dm_is_valid_crc_source(cur_crc_src)) 429 return; 430 431 /* 432 * Since flipping and crc enablement happen asynchronously, we - more 433 * often than not - will be returning an 'uncooked' crc on first frame. 434 * Probably because hw isn't ready yet. For added security, skip the 435 * first two CRC values. 436 */ 437 if (crtc_state->crc_skip_count < 2) { 438 crtc_state->crc_skip_count += 1; 439 return; 440 } 441 442 if (dm_is_crc_source_crtc(cur_crc_src)) { 443 if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state, 444 &crcs[0], &crcs[1], &crcs[2])) 445 return; 446 447 drm_crtc_add_crc_entry(crtc, true, 448 drm_crtc_accurate_vblank_count(crtc), crcs); 449 } 450 } 451 452 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 453 void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) 454 { 455 struct dc_stream_state *stream_state; 456 struct drm_device *drm_dev = NULL; 457 enum amdgpu_dm_pipe_crc_source cur_crc_src; 458 struct amdgpu_crtc *acrtc = NULL; 459 struct amdgpu_device *adev = NULL; 460 struct crc_rd_work *crc_rd_wrk; 461 struct crc_fw_work *crc_fw_wrk; 462 unsigned long flags1, flags2; 463 464 if (crtc == NULL) 465 return; 466 467 acrtc = to_amdgpu_crtc(crtc); 468 adev = drm_to_adev(crtc->dev); 469 drm_dev = crtc->dev; 470 471 spin_lock_irqsave(&drm_dev->event_lock, flags1); 472 stream_state = acrtc->dm_irq_params.stream; 473 cur_crc_src = acrtc->dm_irq_params.crc_src; 474 475 /* Early return if CRC capture is not enabled. */ 476 if (!amdgpu_dm_is_valid_crc_source(cur_crc_src)) 477 goto cleanup; 478 479 if (!dm_is_crc_source_crtc(cur_crc_src)) 480 goto cleanup; 481 482 if (!acrtc->dm_irq_params.window_param.activated) 483 goto cleanup; 484 485 if (acrtc->dm_irq_params.window_param.update_win) { 486 if (acrtc->dm_irq_params.window_param.skip_frame_cnt) { 487 acrtc->dm_irq_params.window_param.skip_frame_cnt -= 1; 488 goto cleanup; 489 } 490 491 /* prepare work for dmub to update ROI */ 492 crc_fw_wrk = kzalloc(sizeof(*crc_fw_wrk), GFP_ATOMIC); 493 if (!crc_fw_wrk) 494 goto cleanup; 495 496 INIT_WORK(&crc_fw_wrk->forward_roi_work, amdgpu_dm_forward_crc_window); 497 crc_fw_wrk->dm = &adev->dm; 498 crc_fw_wrk->stream = stream_state; 499 crc_fw_wrk->rect.x = acrtc->dm_irq_params.window_param.x_start; 500 crc_fw_wrk->rect.y = acrtc->dm_irq_params.window_param.y_start; 501 crc_fw_wrk->rect.width = acrtc->dm_irq_params.window_param.x_end - 502 acrtc->dm_irq_params.window_param.x_start; 503 crc_fw_wrk->rect.height = acrtc->dm_irq_params.window_param.y_end - 504 acrtc->dm_irq_params.window_param.y_start; 505 schedule_work(&crc_fw_wrk->forward_roi_work); 506 507 acrtc->dm_irq_params.window_param.update_win = false; 508 acrtc->dm_irq_params.window_param.skip_frame_cnt = 1; 509 510 } else { 511 if (acrtc->dm_irq_params.window_param.skip_frame_cnt) { 512 acrtc->dm_irq_params.window_param.skip_frame_cnt -= 1; 513 goto cleanup; 514 } 515 516 if (adev->dm.crc_rd_wrk) { 517 crc_rd_wrk = adev->dm.crc_rd_wrk; 518 spin_lock_irqsave(&crc_rd_wrk->crc_rd_work_lock, flags2); 519 crc_rd_wrk->phy_inst = stream_state->link->link_enc_hw_inst; 520 spin_unlock_irqrestore(&crc_rd_wrk->crc_rd_work_lock, flags2); 521 schedule_work(&crc_rd_wrk->notify_ta_work); 522 } 523 } 524 525 cleanup: 526 spin_unlock_irqrestore(&drm_dev->event_lock, flags1); 527 } 528 529 struct crc_rd_work *amdgpu_dm_crtc_secure_display_create_work(void) 530 { 531 struct crc_rd_work *crc_rd_wrk = NULL; 532 533 crc_rd_wrk = kzalloc(sizeof(*crc_rd_wrk), GFP_KERNEL); 534 535 if (!crc_rd_wrk) 536 return NULL; 537 538 spin_lock_init(&crc_rd_wrk->crc_rd_work_lock); 539 INIT_WORK(&crc_rd_wrk->notify_ta_work, amdgpu_dm_crtc_notify_ta_to_read); 540 541 return crc_rd_wrk; 542 } 543 #endif 544