1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <drm/drm_crtc.h> 27 #include <drm/drm_vblank.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_dm.h" 31 #include "dc.h" 32 #include "amdgpu_securedisplay.h" 33 34 static const char *const pipe_crc_sources[] = { 35 "none", 36 "crtc", 37 "crtc dither", 38 "dprx", 39 "dprx dither", 40 "auto", 41 }; 42 43 static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source) 44 { 45 if (!source || !strcmp(source, "none")) 46 return AMDGPU_DM_PIPE_CRC_SOURCE_NONE; 47 if (!strcmp(source, "auto") || !strcmp(source, "crtc")) 48 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC; 49 if (!strcmp(source, "dprx")) 50 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX; 51 if (!strcmp(source, "crtc dither")) 52 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER; 53 if (!strcmp(source, "dprx dither")) 54 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER; 55 56 return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID; 57 } 58 59 static bool dm_is_crc_source_crtc(enum amdgpu_dm_pipe_crc_source src) 60 { 61 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) || 62 (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER); 63 } 64 65 static bool dm_is_crc_source_dprx(enum amdgpu_dm_pipe_crc_source src) 66 { 67 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) || 68 (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER); 69 } 70 71 static bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src) 72 { 73 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER) || 74 (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER) || 75 (src == AMDGPU_DM_PIPE_CRC_SOURCE_NONE); 76 } 77 78 const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, 79 size_t *count) 80 { 81 *count = ARRAY_SIZE(pipe_crc_sources); 82 return pipe_crc_sources; 83 } 84 85 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 86 static void update_phy_id_mapping(struct amdgpu_device *adev) 87 { 88 struct drm_device *ddev = adev_to_drm(adev); 89 struct amdgpu_display_manager *dm = &adev->dm; 90 struct drm_connector *connector; 91 struct amdgpu_dm_connector *aconnector; 92 struct amdgpu_dm_connector *sort_connector[AMDGPU_DM_MAX_CRTC] = {NULL}; 93 struct drm_connector_list_iter iter; 94 uint8_t idx = 0, idx_2 = 0, connector_cnt = 0; 95 96 dm->secure_display_ctx.phy_mapping_updated = false; 97 98 mutex_lock(&ddev->mode_config.mutex); 99 drm_connector_list_iter_begin(ddev, &iter); 100 drm_for_each_connector_iter(connector, &iter) { 101 102 if (connector->status != connector_status_connected) 103 continue; 104 105 if (idx >= AMDGPU_DM_MAX_CRTC) { 106 DRM_WARN("%s connected connectors exceed max crtc\n", __func__); 107 mutex_unlock(&ddev->mode_config.mutex); 108 return; 109 } 110 111 aconnector = to_amdgpu_dm_connector(connector); 112 113 sort_connector[idx] = aconnector; 114 idx++; 115 connector_cnt++; 116 } 117 drm_connector_list_iter_end(&iter); 118 119 /* sort connectors by link_enc_hw_instance first */ 120 for (idx = connector_cnt; idx > 1 ; idx--) { 121 for (idx_2 = 0; idx_2 < (idx - 1); idx_2++) { 122 if (sort_connector[idx_2]->dc_link->link_enc_hw_inst > 123 sort_connector[idx_2 + 1]->dc_link->link_enc_hw_inst) { 124 aconnector = sort_connector[idx_2]; 125 sort_connector[idx_2] = sort_connector[idx_2 + 1]; 126 sort_connector[idx_2 + 1] = aconnector; 127 } 128 } 129 } 130 131 /* 132 * Sort mst connectors by RAD. mst connectors with the same enc_hw_instance are already 133 * sorted together above. 134 */ 135 for (idx = 0; idx < connector_cnt; /*Do nothing*/) { 136 if (sort_connector[idx]->mst_root) { 137 uint8_t i, j, k; 138 uint8_t mst_con_cnt = 1; 139 140 for (idx_2 = (idx + 1); idx_2 < connector_cnt; idx_2++) { 141 if (sort_connector[idx_2]->mst_root == sort_connector[idx]->mst_root) 142 mst_con_cnt++; 143 else 144 break; 145 } 146 147 for (i = mst_con_cnt; i > 1; i--) { 148 for (j = idx; j < (idx + i - 2); j++) { 149 int mstb_lct = sort_connector[j]->mst_output_port->parent->lct; 150 int next_mstb_lct = sort_connector[j + 1]->mst_output_port->parent->lct; 151 u8 *rad; 152 u8 *next_rad; 153 bool swap = false; 154 155 /* Sort by mst tree depth first. Then compare RAD if depth is the same*/ 156 if (mstb_lct > next_mstb_lct) { 157 swap = true; 158 } else if (mstb_lct == next_mstb_lct) { 159 if (mstb_lct == 1) { 160 if (sort_connector[j]->mst_output_port->port_num > sort_connector[j + 1]->mst_output_port->port_num) 161 swap = true; 162 } else if (mstb_lct > 1) { 163 rad = sort_connector[j]->mst_output_port->parent->rad; 164 next_rad = sort_connector[j + 1]->mst_output_port->parent->rad; 165 166 for (k = 0; k < mstb_lct - 1; k++) { 167 int shift = (k % 2) ? 0 : 4; 168 int port_num = (rad[k / 2] >> shift) & 0xf; 169 int next_port_num = (next_rad[k / 2] >> shift) & 0xf; 170 171 if (port_num > next_port_num) { 172 swap = true; 173 break; 174 } 175 } 176 } else { 177 DRM_ERROR("MST LCT shouldn't be set as < 1"); 178 mutex_unlock(&ddev->mode_config.mutex); 179 return; 180 } 181 } 182 183 if (swap) { 184 aconnector = sort_connector[j]; 185 sort_connector[j] = sort_connector[j + 1]; 186 sort_connector[j + 1] = aconnector; 187 } 188 } 189 } 190 191 idx += mst_con_cnt; 192 } else { 193 idx++; 194 } 195 } 196 197 /* Complete sorting. Assign relavant result to dm->secure_display_ctx.phy_id_mapping[]*/ 198 memset(dm->secure_display_ctx.phy_id_mapping, 0, sizeof(dm->secure_display_ctx.phy_id_mapping)); 199 for (idx = 0; idx < connector_cnt; idx++) { 200 aconnector = sort_connector[idx]; 201 202 dm->secure_display_ctx.phy_id_mapping[idx].assigned = true; 203 dm->secure_display_ctx.phy_id_mapping[idx].is_mst = false; 204 dm->secure_display_ctx.phy_id_mapping[idx].enc_hw_inst = aconnector->dc_link->link_enc_hw_inst; 205 206 if (sort_connector[idx]->mst_root) { 207 dm->secure_display_ctx.phy_id_mapping[idx].is_mst = true; 208 dm->secure_display_ctx.phy_id_mapping[idx].lct = aconnector->mst_output_port->parent->lct; 209 dm->secure_display_ctx.phy_id_mapping[idx].port_num = aconnector->mst_output_port->port_num; 210 memcpy(dm->secure_display_ctx.phy_id_mapping[idx].rad, 211 aconnector->mst_output_port->parent->rad, sizeof(aconnector->mst_output_port->parent->rad)); 212 } 213 } 214 mutex_unlock(&ddev->mode_config.mutex); 215 216 dm->secure_display_ctx.phy_id_mapping_cnt = connector_cnt; 217 dm->secure_display_ctx.phy_mapping_updated = true; 218 } 219 220 static bool get_phy_id(struct amdgpu_display_manager *dm, 221 struct amdgpu_dm_connector *aconnector, uint8_t *phy_id) 222 { 223 int idx, idx_2; 224 bool found = false; 225 226 /* 227 * Assume secure display start after all connectors are probed. The connection 228 * config is static as well 229 */ 230 if (!dm->secure_display_ctx.phy_mapping_updated) { 231 DRM_WARN("%s Should update the phy id table before get it's value", __func__); 232 return false; 233 } 234 235 for (idx = 0; idx < dm->secure_display_ctx.phy_id_mapping_cnt; idx++) { 236 if (!dm->secure_display_ctx.phy_id_mapping[idx].assigned) { 237 DRM_ERROR("phy_id_mapping[%d] should be assigned", idx); 238 return false; 239 } 240 241 if (aconnector->dc_link->link_enc_hw_inst == 242 dm->secure_display_ctx.phy_id_mapping[idx].enc_hw_inst) { 243 if (!dm->secure_display_ctx.phy_id_mapping[idx].is_mst) { 244 found = true; 245 goto out; 246 } else { 247 /* Could caused by wrongly pass mst root connector */ 248 if (!aconnector->mst_output_port) { 249 DRM_ERROR("%s Check mst case but connector without a port assigned", __func__); 250 return false; 251 } 252 253 if (aconnector->mst_root && 254 aconnector->mst_root->mst_mgr.mst_primary == NULL) { 255 DRM_WARN("%s pass in a stale mst connector", __func__); 256 } 257 258 if (aconnector->mst_output_port->parent->lct == dm->secure_display_ctx.phy_id_mapping[idx].lct && 259 aconnector->mst_output_port->port_num == dm->secure_display_ctx.phy_id_mapping[idx].port_num) { 260 if (aconnector->mst_output_port->parent->lct == 1) { 261 found = true; 262 goto out; 263 } else if (aconnector->mst_output_port->parent->lct > 1) { 264 /* Check RAD */ 265 for (idx_2 = 0; idx_2 < aconnector->mst_output_port->parent->lct - 1; idx_2++) { 266 int shift = (idx_2 % 2) ? 0 : 4; 267 int port_num = (aconnector->mst_output_port->parent->rad[idx_2 / 2] >> shift) & 0xf; 268 int port_num2 = (dm->secure_display_ctx.phy_id_mapping[idx].rad[idx_2 / 2] >> shift) & 0xf; 269 270 if (port_num != port_num2) 271 break; 272 } 273 274 if (idx_2 == aconnector->mst_output_port->parent->lct - 1) { 275 found = true; 276 goto out; 277 } 278 } else { 279 DRM_ERROR("lCT should be >= 1"); 280 return false; 281 } 282 } 283 } 284 } 285 } 286 287 out: 288 if (found) { 289 DRM_DEBUG_DRIVER("Associated secure display PHY ID as %d", idx); 290 *phy_id = idx; 291 } else { 292 DRM_WARN("Can't find associated phy ID"); 293 return false; 294 } 295 296 return true; 297 } 298 299 static void amdgpu_dm_set_crc_window_default(struct drm_crtc *crtc, struct dc_stream_state *stream) 300 { 301 struct drm_device *drm_dev = crtc->dev; 302 struct amdgpu_display_manager *dm = &drm_to_adev(drm_dev)->dm; 303 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 304 bool was_activated; 305 struct amdgpu_dm_connector *aconnector; 306 uint8_t phy_id; 307 308 spin_lock_irq(&drm_dev->event_lock); 309 was_activated = acrtc->dm_irq_params.window_param.activated; 310 acrtc->dm_irq_params.window_param.x_start = 0; 311 acrtc->dm_irq_params.window_param.y_start = 0; 312 acrtc->dm_irq_params.window_param.x_end = 0; 313 acrtc->dm_irq_params.window_param.y_end = 0; 314 acrtc->dm_irq_params.window_param.activated = false; 315 acrtc->dm_irq_params.window_param.update_win = false; 316 acrtc->dm_irq_params.window_param.skip_frame_cnt = 0; 317 spin_unlock_irq(&drm_dev->event_lock); 318 319 /* Disable secure_display if it was enabled */ 320 if (was_activated) { 321 /* stop ROI update on this crtc */ 322 flush_work(&dm->secure_display_ctx.crtc_ctx[crtc->index].notify_ta_work); 323 flush_work(&dm->secure_display_ctx.crtc_ctx[crtc->index].forward_roi_work); 324 325 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 326 327 if (aconnector && get_phy_id(dm, aconnector, &phy_id)) 328 dc_stream_forward_crc_window(stream, NULL, phy_id, true); 329 else 330 DRM_DEBUG_DRIVER("%s Can't find matching phy id", __func__); 331 } 332 } 333 334 static void amdgpu_dm_crtc_notify_ta_to_read(struct work_struct *work) 335 { 336 struct secure_display_crtc_context *crtc_ctx; 337 struct psp_context *psp; 338 struct ta_securedisplay_cmd *securedisplay_cmd; 339 struct drm_crtc *crtc; 340 struct dc_stream_state *stream; 341 struct amdgpu_dm_connector *aconnector; 342 uint8_t phy_inst; 343 struct amdgpu_display_manager *dm; 344 int ret; 345 346 crtc_ctx = container_of(work, struct secure_display_crtc_context, notify_ta_work); 347 crtc = crtc_ctx->crtc; 348 349 if (!crtc) 350 return; 351 352 psp = &drm_to_adev(crtc->dev)->psp; 353 354 if (!psp->securedisplay_context.context.initialized) { 355 DRM_DEBUG_DRIVER("Secure Display fails to notify PSP TA\n"); 356 return; 357 } 358 359 dm = &drm_to_adev(crtc->dev)->dm; 360 stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream; 361 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 362 if (!aconnector) 363 return; 364 365 mutex_lock(&crtc->dev->mode_config.mutex); 366 if (!get_phy_id(dm, aconnector, &phy_inst)) { 367 DRM_WARN("%s Can't find mapping phy id!", __func__); 368 mutex_unlock(&crtc->dev->mode_config.mutex); 369 return; 370 } 371 mutex_unlock(&crtc->dev->mode_config.mutex); 372 373 /* need lock for multiple crtcs to use the command buffer */ 374 mutex_lock(&psp->securedisplay_context.mutex); 375 376 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 377 TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC); 378 379 securedisplay_cmd->securedisplay_in_message.send_roi_crc.phy_id = phy_inst; 380 381 /* PSP TA is expected to finish data transmission over I2C within current frame, 382 * even there are up to 4 crtcs request to send in this frame. 383 */ 384 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC); 385 386 if (!ret) { 387 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) 388 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 389 } 390 391 mutex_unlock(&psp->securedisplay_context.mutex); 392 } 393 394 static void 395 amdgpu_dm_forward_crc_window(struct work_struct *work) 396 { 397 struct secure_display_crtc_context *crtc_ctx; 398 struct amdgpu_display_manager *dm; 399 struct drm_crtc *crtc; 400 struct dc_stream_state *stream; 401 struct amdgpu_dm_connector *aconnector; 402 uint8_t phy_id; 403 404 crtc_ctx = container_of(work, struct secure_display_crtc_context, forward_roi_work); 405 crtc = crtc_ctx->crtc; 406 407 if (!crtc) 408 return; 409 410 dm = &drm_to_adev(crtc->dev)->dm; 411 stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream; 412 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 413 414 if (!aconnector) 415 return; 416 417 mutex_lock(&crtc->dev->mode_config.mutex); 418 if (!get_phy_id(dm, aconnector, &phy_id)) { 419 DRM_WARN("%s Can't find mapping phy id!", __func__); 420 mutex_unlock(&crtc->dev->mode_config.mutex); 421 return; 422 } 423 mutex_unlock(&crtc->dev->mode_config.mutex); 424 425 mutex_lock(&dm->dc_lock); 426 dc_stream_forward_crc_window(stream, &crtc_ctx->rect, 427 phy_id, false); 428 mutex_unlock(&dm->dc_lock); 429 } 430 431 bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc) 432 { 433 struct drm_device *drm_dev = crtc->dev; 434 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 435 bool ret = false; 436 437 spin_lock_irq(&drm_dev->event_lock); 438 ret = acrtc->dm_irq_params.window_param.activated; 439 spin_unlock_irq(&drm_dev->event_lock); 440 441 return ret; 442 } 443 #endif 444 445 int 446 amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name, 447 size_t *values_cnt) 448 { 449 enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name); 450 451 if (source < 0) { 452 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n", 453 src_name, crtc->index); 454 return -EINVAL; 455 } 456 457 *values_cnt = 3; 458 return 0; 459 } 460 461 int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, 462 struct dm_crtc_state *dm_crtc_state, 463 enum amdgpu_dm_pipe_crc_source source) 464 { 465 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 466 struct dc_stream_state *stream_state = dm_crtc_state->stream; 467 bool enable = amdgpu_dm_is_valid_crc_source(source); 468 int ret = 0; 469 470 /* Configuration will be deferred to stream enable. */ 471 if (!stream_state) 472 return -EINVAL; 473 474 mutex_lock(&adev->dm.dc_lock); 475 476 /* Enable or disable CRTC CRC generation */ 477 if (dm_is_crc_source_crtc(source) || source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) { 478 if (!dc_stream_configure_crc(stream_state->ctx->dc, 479 stream_state, NULL, enable, enable)) { 480 ret = -EINVAL; 481 goto unlock; 482 } 483 } 484 485 /* Configure dithering */ 486 if (!dm_need_crc_dither(source)) { 487 dc_stream_set_dither_option(stream_state, DITHER_OPTION_TRUN8); 488 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state, 489 DYN_EXPANSION_DISABLE); 490 } else { 491 dc_stream_set_dither_option(stream_state, 492 DITHER_OPTION_DEFAULT); 493 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state, 494 DYN_EXPANSION_AUTO); 495 } 496 497 unlock: 498 mutex_unlock(&adev->dm.dc_lock); 499 500 return ret; 501 } 502 503 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) 504 { 505 enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name); 506 enum amdgpu_dm_pipe_crc_source cur_crc_src; 507 struct drm_crtc_commit *commit; 508 struct dm_crtc_state *crtc_state; 509 struct drm_device *drm_dev = crtc->dev; 510 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 511 struct amdgpu_device *adev = drm_to_adev(drm_dev); 512 struct amdgpu_display_manager *dm = &adev->dm; 513 #endif 514 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 515 struct drm_dp_aux *aux = NULL; 516 bool enable = false; 517 bool enabled = false; 518 int ret = 0; 519 520 if (source < 0) { 521 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n", 522 src_name, crtc->index); 523 return -EINVAL; 524 } 525 526 ret = drm_modeset_lock(&crtc->mutex, NULL); 527 if (ret) 528 return ret; 529 530 spin_lock(&crtc->commit_lock); 531 commit = list_first_entry_or_null(&crtc->commit_list, 532 struct drm_crtc_commit, commit_entry); 533 if (commit) 534 drm_crtc_commit_get(commit); 535 spin_unlock(&crtc->commit_lock); 536 537 if (commit) { 538 /* 539 * Need to wait for all outstanding programming to complete 540 * in commit tail since it can modify CRC related fields and 541 * hardware state. Since we're holding the CRTC lock we're 542 * guaranteed that no other commit work can be queued off 543 * before we modify the state below. 544 */ 545 ret = wait_for_completion_interruptible_timeout( 546 &commit->hw_done, 10 * HZ); 547 if (ret) 548 goto cleanup; 549 } 550 551 enable = amdgpu_dm_is_valid_crc_source(source); 552 crtc_state = to_dm_crtc_state(crtc->state); 553 spin_lock_irq(&drm_dev->event_lock); 554 cur_crc_src = acrtc->dm_irq_params.crc_src; 555 spin_unlock_irq(&drm_dev->event_lock); 556 557 /* 558 * USER REQ SRC | CURRENT SRC | BEHAVIOR 559 * ----------------------------- 560 * None | None | Do nothing 561 * None | CRTC | Disable CRTC CRC, set default to dither 562 * None | DPRX | Disable DPRX CRC, need 'aux', set default to dither 563 * None | CRTC DITHER | Disable CRTC CRC 564 * None | DPRX DITHER | Disable DPRX CRC, need 'aux' 565 * CRTC | XXXX | Enable CRTC CRC, no dither 566 * DPRX | XXXX | Enable DPRX CRC, need 'aux', no dither 567 * CRTC DITHER | XXXX | Enable CRTC CRC, set dither 568 * DPRX DITHER | XXXX | Enable DPRX CRC, need 'aux', set dither 569 */ 570 if (dm_is_crc_source_dprx(source) || 571 (source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE && 572 dm_is_crc_source_dprx(cur_crc_src))) { 573 struct amdgpu_dm_connector *aconn = NULL; 574 struct drm_connector *connector; 575 struct drm_connector_list_iter conn_iter; 576 577 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 578 drm_for_each_connector_iter(connector, &conn_iter) { 579 if (!connector->state || connector->state->crtc != crtc) 580 continue; 581 582 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 583 continue; 584 585 aconn = to_amdgpu_dm_connector(connector); 586 break; 587 } 588 drm_connector_list_iter_end(&conn_iter); 589 590 if (!aconn) { 591 DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index); 592 ret = -EINVAL; 593 goto cleanup; 594 } 595 596 aux = (aconn->mst_output_port) ? &aconn->mst_output_port->aux : &aconn->dm_dp_aux.aux; 597 598 if (!aux) { 599 DRM_DEBUG_DRIVER("No dp aux for amd connector\n"); 600 ret = -EINVAL; 601 goto cleanup; 602 } 603 604 if ((aconn->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) && 605 (aconn->base.connector_type != DRM_MODE_CONNECTOR_eDP)) { 606 DRM_DEBUG_DRIVER("No DP connector available for CRC source\n"); 607 ret = -EINVAL; 608 goto cleanup; 609 } 610 611 } 612 613 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 614 /* Reset secure_display when we change crc source from debugfs */ 615 amdgpu_dm_set_crc_window_default(crtc, crtc_state->stream); 616 #endif 617 618 if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) { 619 ret = -EINVAL; 620 goto cleanup; 621 } 622 623 /* 624 * Reading the CRC requires the vblank interrupt handler to be 625 * enabled. Keep a reference until CRC capture stops. 626 */ 627 enabled = amdgpu_dm_is_valid_crc_source(cur_crc_src); 628 if (!enabled && enable) { 629 ret = drm_crtc_vblank_get(crtc); 630 if (ret) 631 goto cleanup; 632 633 if (dm_is_crc_source_dprx(source)) { 634 if (drm_dp_start_crc(aux, crtc)) { 635 DRM_DEBUG_DRIVER("dp start crc failed\n"); 636 ret = -EINVAL; 637 goto cleanup; 638 } 639 } 640 } else if (enabled && !enable) { 641 drm_crtc_vblank_put(crtc); 642 if (dm_is_crc_source_dprx(source)) { 643 if (drm_dp_stop_crc(aux)) { 644 DRM_DEBUG_DRIVER("dp stop crc failed\n"); 645 ret = -EINVAL; 646 goto cleanup; 647 } 648 } 649 } 650 651 spin_lock_irq(&drm_dev->event_lock); 652 acrtc->dm_irq_params.crc_src = source; 653 spin_unlock_irq(&drm_dev->event_lock); 654 655 /* Reset crc_skipped on dm state */ 656 crtc_state->crc_skip_count = 0; 657 658 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 659 /* Initialize phy id mapping table for secure display*/ 660 if (!dm->secure_display_ctx.phy_mapping_updated) 661 update_phy_id_mapping(adev); 662 #endif 663 664 cleanup: 665 if (commit) 666 drm_crtc_commit_put(commit); 667 668 drm_modeset_unlock(&crtc->mutex); 669 670 return ret; 671 } 672 673 /** 674 * amdgpu_dm_crtc_handle_crc_irq: Report to DRM the CRC on given CRTC. 675 * @crtc: DRM CRTC object. 676 * 677 * This function should be called at the end of a vblank, when the fb has been 678 * fully processed through the pipe. 679 */ 680 void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc) 681 { 682 struct dm_crtc_state *crtc_state; 683 struct dc_stream_state *stream_state; 684 struct drm_device *drm_dev = NULL; 685 enum amdgpu_dm_pipe_crc_source cur_crc_src; 686 struct amdgpu_crtc *acrtc = NULL; 687 uint32_t crcs[3]; 688 unsigned long flags; 689 690 if (crtc == NULL) 691 return; 692 693 crtc_state = to_dm_crtc_state(crtc->state); 694 stream_state = crtc_state->stream; 695 acrtc = to_amdgpu_crtc(crtc); 696 drm_dev = crtc->dev; 697 698 spin_lock_irqsave(&drm_dev->event_lock, flags); 699 cur_crc_src = acrtc->dm_irq_params.crc_src; 700 spin_unlock_irqrestore(&drm_dev->event_lock, flags); 701 702 /* Early return if CRC capture is not enabled. */ 703 if (!amdgpu_dm_is_valid_crc_source(cur_crc_src)) 704 return; 705 706 /* 707 * Since flipping and crc enablement happen asynchronously, we - more 708 * often than not - will be returning an 'uncooked' crc on first frame. 709 * Probably because hw isn't ready yet. For added security, skip the 710 * first two CRC values. 711 */ 712 if (crtc_state->crc_skip_count < 2) { 713 crtc_state->crc_skip_count += 1; 714 return; 715 } 716 717 if (dm_is_crc_source_crtc(cur_crc_src)) { 718 if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state, 719 &crcs[0], &crcs[1], &crcs[2])) 720 return; 721 722 drm_crtc_add_crc_entry(crtc, true, 723 drm_crtc_accurate_vblank_count(crtc), crcs); 724 } 725 } 726 727 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 728 void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) 729 { 730 struct drm_device *drm_dev = NULL; 731 enum amdgpu_dm_pipe_crc_source cur_crc_src; 732 struct amdgpu_crtc *acrtc = NULL; 733 struct amdgpu_device *adev = NULL; 734 struct secure_display_crtc_context *crtc_ctx = NULL; 735 unsigned long flags1; 736 737 if (crtc == NULL) 738 return; 739 740 acrtc = to_amdgpu_crtc(crtc); 741 adev = drm_to_adev(crtc->dev); 742 drm_dev = crtc->dev; 743 744 spin_lock_irqsave(&drm_dev->event_lock, flags1); 745 cur_crc_src = acrtc->dm_irq_params.crc_src; 746 747 /* Early return if CRC capture is not enabled. */ 748 if (!amdgpu_dm_is_valid_crc_source(cur_crc_src) || 749 !dm_is_crc_source_crtc(cur_crc_src)) 750 goto cleanup; 751 752 if (!acrtc->dm_irq_params.window_param.activated) 753 goto cleanup; 754 755 if (acrtc->dm_irq_params.window_param.skip_frame_cnt) { 756 acrtc->dm_irq_params.window_param.skip_frame_cnt -= 1; 757 goto cleanup; 758 } 759 760 crtc_ctx = &adev->dm.secure_display_ctx.crtc_ctx[acrtc->crtc_id]; 761 if (WARN_ON(crtc_ctx->crtc != crtc)) { 762 /* We have set the crtc when creating secure_display_crtc_context, 763 * don't expect it to be changed here. 764 */ 765 crtc_ctx->crtc = crtc; 766 } 767 768 if (acrtc->dm_irq_params.window_param.update_win) { 769 /* prepare work for dmub to update ROI */ 770 crtc_ctx->rect.x = acrtc->dm_irq_params.window_param.x_start; 771 crtc_ctx->rect.y = acrtc->dm_irq_params.window_param.y_start; 772 crtc_ctx->rect.width = acrtc->dm_irq_params.window_param.x_end - 773 acrtc->dm_irq_params.window_param.x_start; 774 crtc_ctx->rect.height = acrtc->dm_irq_params.window_param.y_end - 775 acrtc->dm_irq_params.window_param.y_start; 776 schedule_work(&crtc_ctx->forward_roi_work); 777 778 acrtc->dm_irq_params.window_param.update_win = false; 779 780 /* Statically skip 1 frame, because we may need to wait below things 781 * before sending ROI to dmub: 782 * 1. We defer the work by using system workqueue. 783 * 2. We may need to wait for dc_lock before accessing dmub. 784 */ 785 acrtc->dm_irq_params.window_param.skip_frame_cnt = 1; 786 787 } else { 788 /* prepare work for psp to read ROI/CRC and send to I2C */ 789 schedule_work(&crtc_ctx->notify_ta_work); 790 } 791 792 cleanup: 793 spin_unlock_irqrestore(&drm_dev->event_lock, flags1); 794 } 795 796 void amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev) 797 { 798 struct secure_display_crtc_context *crtc_ctx = NULL; 799 int i; 800 801 crtc_ctx = kcalloc(adev->mode_info.num_crtc, 802 sizeof(struct secure_display_crtc_context), 803 GFP_KERNEL); 804 805 if (!crtc_ctx) { 806 adev->dm.secure_display_ctx.crtc_ctx = NULL; 807 return; 808 } 809 810 for (i = 0; i < adev->mode_info.num_crtc; i++) { 811 INIT_WORK(&crtc_ctx[i].forward_roi_work, amdgpu_dm_forward_crc_window); 812 INIT_WORK(&crtc_ctx[i].notify_ta_work, amdgpu_dm_crtc_notify_ta_to_read); 813 crtc_ctx[i].crtc = &adev->mode_info.crtcs[i]->base; 814 } 815 816 adev->dm.secure_display_ctx.crtc_ctx = crtc_ctx; 817 return; 818 } 819 #endif 820