1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <drm/drm_crtc.h> 27 #include <drm/drm_vblank.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_dm.h" 31 #include "dc.h" 32 #include "amdgpu_securedisplay.h" 33 34 static const char *const pipe_crc_sources[] = { 35 "none", 36 "crtc", 37 "crtc dither", 38 "dprx", 39 "dprx dither", 40 "auto", 41 }; 42 43 static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source) 44 { 45 if (!source || !strcmp(source, "none")) 46 return AMDGPU_DM_PIPE_CRC_SOURCE_NONE; 47 if (!strcmp(source, "auto") || !strcmp(source, "crtc")) 48 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC; 49 if (!strcmp(source, "dprx")) 50 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX; 51 if (!strcmp(source, "crtc dither")) 52 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER; 53 if (!strcmp(source, "dprx dither")) 54 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER; 55 56 return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID; 57 } 58 59 static bool dm_is_crc_source_crtc(enum amdgpu_dm_pipe_crc_source src) 60 { 61 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) || 62 (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER); 63 } 64 65 static bool dm_is_crc_source_dprx(enum amdgpu_dm_pipe_crc_source src) 66 { 67 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) || 68 (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER); 69 } 70 71 static bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src) 72 { 73 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER) || 74 (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER) || 75 (src == AMDGPU_DM_PIPE_CRC_SOURCE_NONE); 76 } 77 78 const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, 79 size_t *count) 80 { 81 *count = ARRAY_SIZE(pipe_crc_sources); 82 return pipe_crc_sources; 83 } 84 85 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 86 static void update_phy_id_mapping(struct amdgpu_device *adev) 87 { 88 struct drm_device *ddev = adev_to_drm(adev); 89 struct amdgpu_display_manager *dm = &adev->dm; 90 struct drm_connector *connector; 91 struct amdgpu_dm_connector *aconnector; 92 struct amdgpu_dm_connector *sort_connector[AMDGPU_DM_MAX_CRTC] = {NULL}; 93 struct drm_connector_list_iter iter; 94 uint8_t idx = 0, idx_2 = 0, connector_cnt = 0; 95 96 dm->secure_display_phy_mapping_updated = false; 97 98 mutex_lock(&ddev->mode_config.mutex); 99 drm_connector_list_iter_begin(ddev, &iter); 100 drm_for_each_connector_iter(connector, &iter) { 101 102 if (connector->status != connector_status_connected) 103 continue; 104 105 if (idx >= AMDGPU_DM_MAX_CRTC) { 106 DRM_WARN("%s connected connectors exceed max crtc\n", __func__); 107 mutex_unlock(&ddev->mode_config.mutex); 108 return; 109 } 110 111 aconnector = to_amdgpu_dm_connector(connector); 112 113 sort_connector[idx] = aconnector; 114 idx++; 115 connector_cnt++; 116 } 117 drm_connector_list_iter_end(&iter); 118 119 /* sort connectors by link_enc_hw_instance first */ 120 for (idx = connector_cnt; idx > 1 ; idx--) { 121 for (idx_2 = 0; idx_2 < (idx - 1); idx_2++) { 122 if (sort_connector[idx_2]->dc_link->link_enc_hw_inst > 123 sort_connector[idx_2 + 1]->dc_link->link_enc_hw_inst) { 124 aconnector = sort_connector[idx_2]; 125 sort_connector[idx_2] = sort_connector[idx_2 + 1]; 126 sort_connector[idx_2 + 1] = aconnector; 127 } 128 } 129 } 130 131 /* 132 * Sort mst connectors by RAD. mst connectors with the same enc_hw_instance are already 133 * sorted together above. 134 */ 135 for (idx = 0; idx < connector_cnt; /*Do nothing*/) { 136 if (sort_connector[idx]->mst_root) { 137 uint8_t i, j, k; 138 uint8_t mst_con_cnt = 1; 139 140 for (idx_2 = (idx + 1); idx_2 < connector_cnt; idx_2++) { 141 if (sort_connector[idx_2]->mst_root == sort_connector[idx]->mst_root) 142 mst_con_cnt++; 143 else 144 break; 145 } 146 147 for (i = mst_con_cnt; i > 1; i--) { 148 for (j = idx; j < (idx + i - 2); j++) { 149 int mstb_lct = sort_connector[j]->mst_output_port->parent->lct; 150 int next_mstb_lct = sort_connector[j + 1]->mst_output_port->parent->lct; 151 u8 *rad; 152 u8 *next_rad; 153 bool swap = false; 154 155 /* Sort by mst tree depth first. Then compare RAD if depth is the same*/ 156 if (mstb_lct > next_mstb_lct) { 157 swap = true; 158 } else if (mstb_lct == next_mstb_lct) { 159 if (mstb_lct == 1) { 160 if (sort_connector[j]->mst_output_port->port_num > sort_connector[j + 1]->mst_output_port->port_num) 161 swap = true; 162 } else if (mstb_lct > 1) { 163 rad = sort_connector[j]->mst_output_port->parent->rad; 164 next_rad = sort_connector[j + 1]->mst_output_port->parent->rad; 165 166 for (k = 0; k < mstb_lct - 1; k++) { 167 int shift = (k % 2) ? 0 : 4; 168 int port_num = (rad[k / 2] >> shift) & 0xf; 169 int next_port_num = (next_rad[k / 2] >> shift) & 0xf; 170 171 if (port_num > next_port_num) { 172 swap = true; 173 break; 174 } 175 } 176 } else { 177 DRM_ERROR("MST LCT shouldn't be set as < 1"); 178 mutex_unlock(&ddev->mode_config.mutex); 179 return; 180 } 181 } 182 183 if (swap) { 184 aconnector = sort_connector[j]; 185 sort_connector[j] = sort_connector[j + 1]; 186 sort_connector[j + 1] = aconnector; 187 } 188 } 189 } 190 191 idx += mst_con_cnt; 192 } else { 193 idx++; 194 } 195 } 196 197 /* Complete sorting. Assign relavant result to dm->phy_id_mapping[]*/ 198 memset(dm->phy_id_mapping, 0, sizeof(dm->phy_id_mapping)); 199 for (idx = 0; idx < connector_cnt; idx++) { 200 aconnector = sort_connector[idx]; 201 202 dm->phy_id_mapping[idx].assigned = true; 203 dm->phy_id_mapping[idx].is_mst = false; 204 dm->phy_id_mapping[idx].enc_hw_inst = aconnector->dc_link->link_enc_hw_inst; 205 206 if (sort_connector[idx]->mst_root) { 207 dm->phy_id_mapping[idx].is_mst = true; 208 dm->phy_id_mapping[idx].lct = aconnector->mst_output_port->parent->lct; 209 dm->phy_id_mapping[idx].port_num = aconnector->mst_output_port->port_num; 210 memcpy(dm->phy_id_mapping[idx].rad, aconnector->mst_output_port->parent->rad, 211 sizeof(aconnector->mst_output_port->parent->rad)); 212 } 213 } 214 mutex_unlock(&ddev->mode_config.mutex); 215 216 dm->phy_id_mapping_cnt = connector_cnt; 217 dm->secure_display_phy_mapping_updated = true; 218 } 219 220 static bool get_phy_id(struct amdgpu_display_manager *dm, 221 struct amdgpu_dm_connector *aconnector, uint8_t *phy_id) 222 { 223 int idx, idx_2; 224 bool found = false; 225 226 /* 227 * Assume secure display start after all connectors are probed. The connection 228 * config is static as well 229 */ 230 if (!dm->secure_display_phy_mapping_updated) { 231 DRM_WARN("%s Should update the phy id table before get it's value", __func__); 232 return false; 233 } 234 235 for (idx = 0; idx < dm->phy_id_mapping_cnt; idx++) { 236 if (!dm->phy_id_mapping[idx].assigned) { 237 DRM_ERROR("phy_id_mapping[%d] should be assigned", idx); 238 return false; 239 } 240 241 if (aconnector->dc_link->link_enc_hw_inst == dm->phy_id_mapping[idx].enc_hw_inst) { 242 if (!dm->phy_id_mapping[idx].is_mst) { 243 found = true; 244 goto out; 245 } else { 246 /* Could caused by wrongly pass mst root connector */ 247 if (!aconnector->mst_output_port) { 248 DRM_ERROR("%s Check mst case but connector without a port assigned", __func__); 249 return false; 250 } 251 252 if (aconnector->mst_root && 253 aconnector->mst_root->mst_mgr.mst_primary == NULL) { 254 DRM_WARN("%s pass in a stale mst connector", __func__); 255 } 256 257 if (aconnector->mst_output_port->parent->lct == dm->phy_id_mapping[idx].lct && 258 aconnector->mst_output_port->port_num == dm->phy_id_mapping[idx].port_num) { 259 if (aconnector->mst_output_port->parent->lct == 1) { 260 found = true; 261 goto out; 262 } else if (aconnector->mst_output_port->parent->lct > 1) { 263 /* Check RAD */ 264 for (idx_2 = 0; idx_2 < aconnector->mst_output_port->parent->lct - 1; idx_2++) { 265 int shift = (idx_2 % 2) ? 0 : 4; 266 int port_num = (aconnector->mst_output_port->parent->rad[idx_2 / 2] >> shift) & 0xf; 267 int port_num2 = (dm->phy_id_mapping[idx].rad[idx_2 / 2] >> shift) & 0xf; 268 269 if (port_num != port_num2) 270 break; 271 } 272 273 if (idx_2 == aconnector->mst_output_port->parent->lct - 1) { 274 found = true; 275 goto out; 276 } 277 } else { 278 DRM_ERROR("lCT should be >= 1"); 279 return false; 280 } 281 } 282 } 283 } 284 } 285 286 out: 287 if (found) { 288 DRM_DEBUG_DRIVER("Associated secure display PHY ID as %d", idx); 289 *phy_id = idx; 290 } else { 291 DRM_WARN("Can't find associated phy ID"); 292 return false; 293 } 294 295 return true; 296 } 297 298 static void amdgpu_dm_set_crc_window_default(struct drm_crtc *crtc, struct dc_stream_state *stream) 299 { 300 struct drm_device *drm_dev = crtc->dev; 301 struct amdgpu_display_manager *dm = &drm_to_adev(drm_dev)->dm; 302 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 303 bool was_activated; 304 struct amdgpu_dm_connector *aconnector; 305 uint8_t phy_id; 306 307 spin_lock_irq(&drm_dev->event_lock); 308 was_activated = acrtc->dm_irq_params.window_param.activated; 309 acrtc->dm_irq_params.window_param.x_start = 0; 310 acrtc->dm_irq_params.window_param.y_start = 0; 311 acrtc->dm_irq_params.window_param.x_end = 0; 312 acrtc->dm_irq_params.window_param.y_end = 0; 313 acrtc->dm_irq_params.window_param.activated = false; 314 acrtc->dm_irq_params.window_param.update_win = false; 315 acrtc->dm_irq_params.window_param.skip_frame_cnt = 0; 316 spin_unlock_irq(&drm_dev->event_lock); 317 318 /* Disable secure_display if it was enabled */ 319 if (was_activated) { 320 /* stop ROI update on this crtc */ 321 flush_work(&dm->secure_display_ctxs[crtc->index].notify_ta_work); 322 flush_work(&dm->secure_display_ctxs[crtc->index].forward_roi_work); 323 324 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 325 326 if (aconnector && get_phy_id(dm, aconnector, &phy_id)) 327 dc_stream_forward_crc_window(stream, NULL, phy_id, true); 328 else 329 DRM_DEBUG_DRIVER("%s Can't find matching phy id", __func__); 330 } 331 } 332 333 static void amdgpu_dm_crtc_notify_ta_to_read(struct work_struct *work) 334 { 335 struct secure_display_context *secure_display_ctx; 336 struct psp_context *psp; 337 struct ta_securedisplay_cmd *securedisplay_cmd; 338 struct drm_crtc *crtc; 339 struct dc_stream_state *stream; 340 struct amdgpu_dm_connector *aconnector; 341 uint8_t phy_inst; 342 struct amdgpu_display_manager *dm; 343 int ret; 344 345 secure_display_ctx = container_of(work, struct secure_display_context, notify_ta_work); 346 crtc = secure_display_ctx->crtc; 347 348 if (!crtc) 349 return; 350 351 psp = &drm_to_adev(crtc->dev)->psp; 352 353 if (!psp->securedisplay_context.context.initialized) { 354 DRM_DEBUG_DRIVER("Secure Display fails to notify PSP TA\n"); 355 return; 356 } 357 358 dm = &drm_to_adev(crtc->dev)->dm; 359 stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream; 360 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 361 if (!aconnector) 362 return; 363 364 mutex_lock(&crtc->dev->mode_config.mutex); 365 if (!get_phy_id(dm, aconnector, &phy_inst)) { 366 DRM_WARN("%s Can't find mapping phy id!", __func__); 367 mutex_unlock(&crtc->dev->mode_config.mutex); 368 return; 369 } 370 mutex_unlock(&crtc->dev->mode_config.mutex); 371 372 /* need lock for multiple crtcs to use the command buffer */ 373 mutex_lock(&psp->securedisplay_context.mutex); 374 375 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 376 TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC); 377 378 securedisplay_cmd->securedisplay_in_message.send_roi_crc.phy_id = phy_inst; 379 380 /* PSP TA is expected to finish data transmission over I2C within current frame, 381 * even there are up to 4 crtcs request to send in this frame. 382 */ 383 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC); 384 385 if (!ret) { 386 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) 387 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 388 } 389 390 mutex_unlock(&psp->securedisplay_context.mutex); 391 } 392 393 static void 394 amdgpu_dm_forward_crc_window(struct work_struct *work) 395 { 396 struct secure_display_context *secure_display_ctx; 397 struct amdgpu_display_manager *dm; 398 struct drm_crtc *crtc; 399 struct dc_stream_state *stream; 400 struct amdgpu_dm_connector *aconnector; 401 uint8_t phy_id; 402 403 secure_display_ctx = container_of(work, struct secure_display_context, forward_roi_work); 404 crtc = secure_display_ctx->crtc; 405 406 if (!crtc) 407 return; 408 409 dm = &drm_to_adev(crtc->dev)->dm; 410 stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream; 411 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 412 413 if (!aconnector) 414 return; 415 416 mutex_lock(&crtc->dev->mode_config.mutex); 417 if (!get_phy_id(dm, aconnector, &phy_id)) { 418 DRM_WARN("%s Can't find mapping phy id!", __func__); 419 mutex_unlock(&crtc->dev->mode_config.mutex); 420 return; 421 } 422 mutex_unlock(&crtc->dev->mode_config.mutex); 423 424 mutex_lock(&dm->dc_lock); 425 dc_stream_forward_crc_window(stream, &secure_display_ctx->rect, 426 phy_id, false); 427 mutex_unlock(&dm->dc_lock); 428 } 429 430 bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc) 431 { 432 struct drm_device *drm_dev = crtc->dev; 433 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 434 bool ret = false; 435 436 spin_lock_irq(&drm_dev->event_lock); 437 ret = acrtc->dm_irq_params.window_param.activated; 438 spin_unlock_irq(&drm_dev->event_lock); 439 440 return ret; 441 } 442 #endif 443 444 int 445 amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name, 446 size_t *values_cnt) 447 { 448 enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name); 449 450 if (source < 0) { 451 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n", 452 src_name, crtc->index); 453 return -EINVAL; 454 } 455 456 *values_cnt = 3; 457 return 0; 458 } 459 460 int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, 461 struct dm_crtc_state *dm_crtc_state, 462 enum amdgpu_dm_pipe_crc_source source) 463 { 464 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 465 struct dc_stream_state *stream_state = dm_crtc_state->stream; 466 bool enable = amdgpu_dm_is_valid_crc_source(source); 467 int ret = 0; 468 469 /* Configuration will be deferred to stream enable. */ 470 if (!stream_state) 471 return -EINVAL; 472 473 mutex_lock(&adev->dm.dc_lock); 474 475 /* Enable or disable CRTC CRC generation */ 476 if (dm_is_crc_source_crtc(source) || source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) { 477 if (!dc_stream_configure_crc(stream_state->ctx->dc, 478 stream_state, NULL, enable, enable)) { 479 ret = -EINVAL; 480 goto unlock; 481 } 482 } 483 484 /* Configure dithering */ 485 if (!dm_need_crc_dither(source)) { 486 dc_stream_set_dither_option(stream_state, DITHER_OPTION_TRUN8); 487 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state, 488 DYN_EXPANSION_DISABLE); 489 } else { 490 dc_stream_set_dither_option(stream_state, 491 DITHER_OPTION_DEFAULT); 492 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state, 493 DYN_EXPANSION_AUTO); 494 } 495 496 unlock: 497 mutex_unlock(&adev->dm.dc_lock); 498 499 return ret; 500 } 501 502 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) 503 { 504 enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name); 505 enum amdgpu_dm_pipe_crc_source cur_crc_src; 506 struct drm_crtc_commit *commit; 507 struct dm_crtc_state *crtc_state; 508 struct drm_device *drm_dev = crtc->dev; 509 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 510 struct amdgpu_device *adev = drm_to_adev(drm_dev); 511 struct amdgpu_display_manager *dm = &adev->dm; 512 #endif 513 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 514 struct drm_dp_aux *aux = NULL; 515 bool enable = false; 516 bool enabled = false; 517 int ret = 0; 518 519 if (source < 0) { 520 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n", 521 src_name, crtc->index); 522 return -EINVAL; 523 } 524 525 ret = drm_modeset_lock(&crtc->mutex, NULL); 526 if (ret) 527 return ret; 528 529 spin_lock(&crtc->commit_lock); 530 commit = list_first_entry_or_null(&crtc->commit_list, 531 struct drm_crtc_commit, commit_entry); 532 if (commit) 533 drm_crtc_commit_get(commit); 534 spin_unlock(&crtc->commit_lock); 535 536 if (commit) { 537 /* 538 * Need to wait for all outstanding programming to complete 539 * in commit tail since it can modify CRC related fields and 540 * hardware state. Since we're holding the CRTC lock we're 541 * guaranteed that no other commit work can be queued off 542 * before we modify the state below. 543 */ 544 ret = wait_for_completion_interruptible_timeout( 545 &commit->hw_done, 10 * HZ); 546 if (ret) 547 goto cleanup; 548 } 549 550 enable = amdgpu_dm_is_valid_crc_source(source); 551 crtc_state = to_dm_crtc_state(crtc->state); 552 spin_lock_irq(&drm_dev->event_lock); 553 cur_crc_src = acrtc->dm_irq_params.crc_src; 554 spin_unlock_irq(&drm_dev->event_lock); 555 556 /* 557 * USER REQ SRC | CURRENT SRC | BEHAVIOR 558 * ----------------------------- 559 * None | None | Do nothing 560 * None | CRTC | Disable CRTC CRC, set default to dither 561 * None | DPRX | Disable DPRX CRC, need 'aux', set default to dither 562 * None | CRTC DITHER | Disable CRTC CRC 563 * None | DPRX DITHER | Disable DPRX CRC, need 'aux' 564 * CRTC | XXXX | Enable CRTC CRC, no dither 565 * DPRX | XXXX | Enable DPRX CRC, need 'aux', no dither 566 * CRTC DITHER | XXXX | Enable CRTC CRC, set dither 567 * DPRX DITHER | XXXX | Enable DPRX CRC, need 'aux', set dither 568 */ 569 if (dm_is_crc_source_dprx(source) || 570 (source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE && 571 dm_is_crc_source_dprx(cur_crc_src))) { 572 struct amdgpu_dm_connector *aconn = NULL; 573 struct drm_connector *connector; 574 struct drm_connector_list_iter conn_iter; 575 576 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 577 drm_for_each_connector_iter(connector, &conn_iter) { 578 if (!connector->state || connector->state->crtc != crtc) 579 continue; 580 581 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 582 continue; 583 584 aconn = to_amdgpu_dm_connector(connector); 585 break; 586 } 587 drm_connector_list_iter_end(&conn_iter); 588 589 if (!aconn) { 590 DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index); 591 ret = -EINVAL; 592 goto cleanup; 593 } 594 595 aux = (aconn->mst_output_port) ? &aconn->mst_output_port->aux : &aconn->dm_dp_aux.aux; 596 597 if (!aux) { 598 DRM_DEBUG_DRIVER("No dp aux for amd connector\n"); 599 ret = -EINVAL; 600 goto cleanup; 601 } 602 603 if ((aconn->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) && 604 (aconn->base.connector_type != DRM_MODE_CONNECTOR_eDP)) { 605 DRM_DEBUG_DRIVER("No DP connector available for CRC source\n"); 606 ret = -EINVAL; 607 goto cleanup; 608 } 609 610 } 611 612 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 613 /* Reset secure_display when we change crc source from debugfs */ 614 amdgpu_dm_set_crc_window_default(crtc, crtc_state->stream); 615 #endif 616 617 if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) { 618 ret = -EINVAL; 619 goto cleanup; 620 } 621 622 /* 623 * Reading the CRC requires the vblank interrupt handler to be 624 * enabled. Keep a reference until CRC capture stops. 625 */ 626 enabled = amdgpu_dm_is_valid_crc_source(cur_crc_src); 627 if (!enabled && enable) { 628 ret = drm_crtc_vblank_get(crtc); 629 if (ret) 630 goto cleanup; 631 632 if (dm_is_crc_source_dprx(source)) { 633 if (drm_dp_start_crc(aux, crtc)) { 634 DRM_DEBUG_DRIVER("dp start crc failed\n"); 635 ret = -EINVAL; 636 goto cleanup; 637 } 638 } 639 } else if (enabled && !enable) { 640 drm_crtc_vblank_put(crtc); 641 if (dm_is_crc_source_dprx(source)) { 642 if (drm_dp_stop_crc(aux)) { 643 DRM_DEBUG_DRIVER("dp stop crc failed\n"); 644 ret = -EINVAL; 645 goto cleanup; 646 } 647 } 648 } 649 650 spin_lock_irq(&drm_dev->event_lock); 651 acrtc->dm_irq_params.crc_src = source; 652 spin_unlock_irq(&drm_dev->event_lock); 653 654 /* Reset crc_skipped on dm state */ 655 crtc_state->crc_skip_count = 0; 656 657 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 658 /* Initialize phy id mapping table for secure display*/ 659 if (!dm->secure_display_phy_mapping_updated) 660 update_phy_id_mapping(adev); 661 #endif 662 663 cleanup: 664 if (commit) 665 drm_crtc_commit_put(commit); 666 667 drm_modeset_unlock(&crtc->mutex); 668 669 return ret; 670 } 671 672 /** 673 * amdgpu_dm_crtc_handle_crc_irq: Report to DRM the CRC on given CRTC. 674 * @crtc: DRM CRTC object. 675 * 676 * This function should be called at the end of a vblank, when the fb has been 677 * fully processed through the pipe. 678 */ 679 void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc) 680 { 681 struct dm_crtc_state *crtc_state; 682 struct dc_stream_state *stream_state; 683 struct drm_device *drm_dev = NULL; 684 enum amdgpu_dm_pipe_crc_source cur_crc_src; 685 struct amdgpu_crtc *acrtc = NULL; 686 uint32_t crcs[3]; 687 unsigned long flags; 688 689 if (crtc == NULL) 690 return; 691 692 crtc_state = to_dm_crtc_state(crtc->state); 693 stream_state = crtc_state->stream; 694 acrtc = to_amdgpu_crtc(crtc); 695 drm_dev = crtc->dev; 696 697 spin_lock_irqsave(&drm_dev->event_lock, flags); 698 cur_crc_src = acrtc->dm_irq_params.crc_src; 699 spin_unlock_irqrestore(&drm_dev->event_lock, flags); 700 701 /* Early return if CRC capture is not enabled. */ 702 if (!amdgpu_dm_is_valid_crc_source(cur_crc_src)) 703 return; 704 705 /* 706 * Since flipping and crc enablement happen asynchronously, we - more 707 * often than not - will be returning an 'uncooked' crc on first frame. 708 * Probably because hw isn't ready yet. For added security, skip the 709 * first two CRC values. 710 */ 711 if (crtc_state->crc_skip_count < 2) { 712 crtc_state->crc_skip_count += 1; 713 return; 714 } 715 716 if (dm_is_crc_source_crtc(cur_crc_src)) { 717 if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state, 718 &crcs[0], &crcs[1], &crcs[2])) 719 return; 720 721 drm_crtc_add_crc_entry(crtc, true, 722 drm_crtc_accurate_vblank_count(crtc), crcs); 723 } 724 } 725 726 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 727 void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) 728 { 729 struct drm_device *drm_dev = NULL; 730 enum amdgpu_dm_pipe_crc_source cur_crc_src; 731 struct amdgpu_crtc *acrtc = NULL; 732 struct amdgpu_device *adev = NULL; 733 struct secure_display_context *secure_display_ctx = NULL; 734 unsigned long flags1; 735 736 if (crtc == NULL) 737 return; 738 739 acrtc = to_amdgpu_crtc(crtc); 740 adev = drm_to_adev(crtc->dev); 741 drm_dev = crtc->dev; 742 743 spin_lock_irqsave(&drm_dev->event_lock, flags1); 744 cur_crc_src = acrtc->dm_irq_params.crc_src; 745 746 /* Early return if CRC capture is not enabled. */ 747 if (!amdgpu_dm_is_valid_crc_source(cur_crc_src) || 748 !dm_is_crc_source_crtc(cur_crc_src)) 749 goto cleanup; 750 751 if (!acrtc->dm_irq_params.window_param.activated) 752 goto cleanup; 753 754 if (acrtc->dm_irq_params.window_param.skip_frame_cnt) { 755 acrtc->dm_irq_params.window_param.skip_frame_cnt -= 1; 756 goto cleanup; 757 } 758 759 secure_display_ctx = &adev->dm.secure_display_ctxs[acrtc->crtc_id]; 760 if (WARN_ON(secure_display_ctx->crtc != crtc)) { 761 /* We have set the crtc when creating secure_display_context, 762 * don't expect it to be changed here. 763 */ 764 secure_display_ctx->crtc = crtc; 765 } 766 767 if (acrtc->dm_irq_params.window_param.update_win) { 768 /* prepare work for dmub to update ROI */ 769 secure_display_ctx->rect.x = acrtc->dm_irq_params.window_param.x_start; 770 secure_display_ctx->rect.y = acrtc->dm_irq_params.window_param.y_start; 771 secure_display_ctx->rect.width = acrtc->dm_irq_params.window_param.x_end - 772 acrtc->dm_irq_params.window_param.x_start; 773 secure_display_ctx->rect.height = acrtc->dm_irq_params.window_param.y_end - 774 acrtc->dm_irq_params.window_param.y_start; 775 schedule_work(&secure_display_ctx->forward_roi_work); 776 777 acrtc->dm_irq_params.window_param.update_win = false; 778 779 /* Statically skip 1 frame, because we may need to wait below things 780 * before sending ROI to dmub: 781 * 1. We defer the work by using system workqueue. 782 * 2. We may need to wait for dc_lock before accessing dmub. 783 */ 784 acrtc->dm_irq_params.window_param.skip_frame_cnt = 1; 785 786 } else { 787 /* prepare work for psp to read ROI/CRC and send to I2C */ 788 schedule_work(&secure_display_ctx->notify_ta_work); 789 } 790 791 cleanup: 792 spin_unlock_irqrestore(&drm_dev->event_lock, flags1); 793 } 794 795 struct secure_display_context * 796 amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev) 797 { 798 struct secure_display_context *secure_display_ctxs = NULL; 799 int i; 800 801 secure_display_ctxs = kcalloc(adev->mode_info.num_crtc, 802 sizeof(struct secure_display_context), 803 GFP_KERNEL); 804 805 if (!secure_display_ctxs) 806 return NULL; 807 808 for (i = 0; i < adev->mode_info.num_crtc; i++) { 809 INIT_WORK(&secure_display_ctxs[i].forward_roi_work, amdgpu_dm_forward_crc_window); 810 INIT_WORK(&secure_display_ctxs[i].notify_ta_work, amdgpu_dm_crtc_notify_ta_to_read); 811 secure_display_ctxs[i].crtc = &adev->mode_info.crtcs[i]->base; 812 } 813 814 return secure_display_ctxs; 815 } 816 #endif 817