1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <drm/drm_crtc.h> 27 #include <drm/drm_vblank.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_dm.h" 31 #include "dc.h" 32 #include "amdgpu_securedisplay.h" 33 #include "amdgpu_dm_psr.h" 34 35 static const char *const pipe_crc_sources[] = { 36 "none", 37 "crtc", 38 "crtc dither", 39 "dprx", 40 "dprx dither", 41 "auto", 42 }; 43 44 static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source) 45 { 46 if (!source || !strcmp(source, "none")) 47 return AMDGPU_DM_PIPE_CRC_SOURCE_NONE; 48 if (!strcmp(source, "auto") || !strcmp(source, "crtc")) 49 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC; 50 if (!strcmp(source, "dprx")) 51 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX; 52 if (!strcmp(source, "crtc dither")) 53 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER; 54 if (!strcmp(source, "dprx dither")) 55 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER; 56 57 return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID; 58 } 59 60 static bool dm_is_crc_source_crtc(enum amdgpu_dm_pipe_crc_source src) 61 { 62 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) || 63 (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER); 64 } 65 66 static bool dm_is_crc_source_dprx(enum amdgpu_dm_pipe_crc_source src) 67 { 68 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) || 69 (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER); 70 } 71 72 static bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src) 73 { 74 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER) || 75 (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER) || 76 (src == AMDGPU_DM_PIPE_CRC_SOURCE_NONE); 77 } 78 79 const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, 80 size_t *count) 81 { 82 *count = ARRAY_SIZE(pipe_crc_sources); 83 return pipe_crc_sources; 84 } 85 86 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 87 static void amdgpu_dm_set_crc_window_default(struct drm_crtc *crtc, struct dc_stream_state *stream) 88 { 89 struct drm_device *drm_dev = crtc->dev; 90 struct amdgpu_display_manager *dm = &drm_to_adev(drm_dev)->dm; 91 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 92 bool was_activated; 93 94 spin_lock_irq(&drm_dev->event_lock); 95 was_activated = acrtc->dm_irq_params.window_param.activated; 96 acrtc->dm_irq_params.window_param.x_start = 0; 97 acrtc->dm_irq_params.window_param.y_start = 0; 98 acrtc->dm_irq_params.window_param.x_end = 0; 99 acrtc->dm_irq_params.window_param.y_end = 0; 100 acrtc->dm_irq_params.window_param.activated = false; 101 acrtc->dm_irq_params.window_param.update_win = false; 102 acrtc->dm_irq_params.window_param.skip_frame_cnt = 0; 103 spin_unlock_irq(&drm_dev->event_lock); 104 105 /* Disable secure_display if it was enabled */ 106 if (was_activated) { 107 /* stop ROI update on this crtc */ 108 flush_work(&dm->secure_display_ctxs[crtc->index].notify_ta_work); 109 flush_work(&dm->secure_display_ctxs[crtc->index].forward_roi_work); 110 dc_stream_forward_crc_window(stream, NULL, true); 111 } 112 } 113 114 static void amdgpu_dm_crtc_notify_ta_to_read(struct work_struct *work) 115 { 116 struct secure_display_context *secure_display_ctx; 117 struct psp_context *psp; 118 struct ta_securedisplay_cmd *securedisplay_cmd; 119 struct drm_crtc *crtc; 120 struct dc_stream_state *stream; 121 uint8_t phy_inst; 122 int ret; 123 124 secure_display_ctx = container_of(work, struct secure_display_context, notify_ta_work); 125 crtc = secure_display_ctx->crtc; 126 127 if (!crtc) 128 return; 129 130 psp = &drm_to_adev(crtc->dev)->psp; 131 132 if (!psp->securedisplay_context.context.initialized) { 133 DRM_DEBUG_DRIVER("Secure Display fails to notify PSP TA\n"); 134 return; 135 } 136 137 stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream; 138 phy_inst = stream->link->link_enc_hw_inst; 139 140 /* need lock for multiple crtcs to use the command buffer */ 141 mutex_lock(&psp->securedisplay_context.mutex); 142 143 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 144 TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC); 145 146 securedisplay_cmd->securedisplay_in_message.send_roi_crc.phy_id = phy_inst; 147 148 /* PSP TA is expected to finish data transmission over I2C within current frame, 149 * even there are up to 4 crtcs request to send in this frame. 150 */ 151 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC); 152 153 if (!ret) { 154 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) 155 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 156 } 157 158 mutex_unlock(&psp->securedisplay_context.mutex); 159 } 160 161 static void 162 amdgpu_dm_forward_crc_window(struct work_struct *work) 163 { 164 struct secure_display_context *secure_display_ctx; 165 struct amdgpu_display_manager *dm; 166 struct drm_crtc *crtc; 167 struct dc_stream_state *stream; 168 169 secure_display_ctx = container_of(work, struct secure_display_context, forward_roi_work); 170 crtc = secure_display_ctx->crtc; 171 172 if (!crtc) 173 return; 174 175 dm = &drm_to_adev(crtc->dev)->dm; 176 stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream; 177 178 mutex_lock(&dm->dc_lock); 179 dc_stream_forward_crc_window(stream, &secure_display_ctx->rect, false); 180 mutex_unlock(&dm->dc_lock); 181 } 182 183 bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc) 184 { 185 struct drm_device *drm_dev = crtc->dev; 186 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 187 bool ret = false; 188 189 spin_lock_irq(&drm_dev->event_lock); 190 ret = acrtc->dm_irq_params.window_param.activated; 191 spin_unlock_irq(&drm_dev->event_lock); 192 193 return ret; 194 } 195 #endif 196 197 int 198 amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name, 199 size_t *values_cnt) 200 { 201 enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name); 202 203 if (source < 0) { 204 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n", 205 src_name, crtc->index); 206 return -EINVAL; 207 } 208 209 *values_cnt = 3; 210 return 0; 211 } 212 213 int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, 214 struct dm_crtc_state *dm_crtc_state, 215 enum amdgpu_dm_pipe_crc_source source) 216 { 217 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 218 struct dc_stream_state *stream_state = dm_crtc_state->stream; 219 bool enable = amdgpu_dm_is_valid_crc_source(source); 220 int ret = 0; 221 222 /* Configuration will be deferred to stream enable. */ 223 if (!stream_state) 224 return -EINVAL; 225 226 mutex_lock(&adev->dm.dc_lock); 227 228 /* For PSR1, check that the panel has exited PSR */ 229 if (stream_state->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1) 230 amdgpu_dm_psr_wait_disable(stream_state); 231 232 /* Enable or disable CRTC CRC generation */ 233 if (dm_is_crc_source_crtc(source) || source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) { 234 if (!dc_stream_configure_crc(stream_state->ctx->dc, 235 stream_state, NULL, enable, enable)) { 236 ret = -EINVAL; 237 goto unlock; 238 } 239 } 240 241 /* Configure dithering */ 242 if (!dm_need_crc_dither(source)) { 243 dc_stream_set_dither_option(stream_state, DITHER_OPTION_TRUN8); 244 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state, 245 DYN_EXPANSION_DISABLE); 246 } else { 247 dc_stream_set_dither_option(stream_state, 248 DITHER_OPTION_DEFAULT); 249 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state, 250 DYN_EXPANSION_AUTO); 251 } 252 253 unlock: 254 mutex_unlock(&adev->dm.dc_lock); 255 256 return ret; 257 } 258 259 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) 260 { 261 enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name); 262 enum amdgpu_dm_pipe_crc_source cur_crc_src; 263 struct drm_crtc_commit *commit; 264 struct dm_crtc_state *crtc_state; 265 struct drm_device *drm_dev = crtc->dev; 266 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 267 struct drm_dp_aux *aux = NULL; 268 bool enable = false; 269 bool enabled = false; 270 int ret = 0; 271 272 if (source < 0) { 273 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n", 274 src_name, crtc->index); 275 return -EINVAL; 276 } 277 278 ret = drm_modeset_lock(&crtc->mutex, NULL); 279 if (ret) 280 return ret; 281 282 spin_lock(&crtc->commit_lock); 283 commit = list_first_entry_or_null(&crtc->commit_list, 284 struct drm_crtc_commit, commit_entry); 285 if (commit) 286 drm_crtc_commit_get(commit); 287 spin_unlock(&crtc->commit_lock); 288 289 if (commit) { 290 /* 291 * Need to wait for all outstanding programming to complete 292 * in commit tail since it can modify CRC related fields and 293 * hardware state. Since we're holding the CRTC lock we're 294 * guaranteed that no other commit work can be queued off 295 * before we modify the state below. 296 */ 297 ret = wait_for_completion_interruptible_timeout( 298 &commit->hw_done, 10 * HZ); 299 if (ret) 300 goto cleanup; 301 } 302 303 enable = amdgpu_dm_is_valid_crc_source(source); 304 crtc_state = to_dm_crtc_state(crtc->state); 305 spin_lock_irq(&drm_dev->event_lock); 306 cur_crc_src = acrtc->dm_irq_params.crc_src; 307 spin_unlock_irq(&drm_dev->event_lock); 308 309 /* 310 * USER REQ SRC | CURRENT SRC | BEHAVIOR 311 * ----------------------------- 312 * None | None | Do nothing 313 * None | CRTC | Disable CRTC CRC, set default to dither 314 * None | DPRX | Disable DPRX CRC, need 'aux', set default to dither 315 * None | CRTC DITHER | Disable CRTC CRC 316 * None | DPRX DITHER | Disable DPRX CRC, need 'aux' 317 * CRTC | XXXX | Enable CRTC CRC, no dither 318 * DPRX | XXXX | Enable DPRX CRC, need 'aux', no dither 319 * CRTC DITHER | XXXX | Enable CRTC CRC, set dither 320 * DPRX DITHER | XXXX | Enable DPRX CRC, need 'aux', set dither 321 */ 322 if (dm_is_crc_source_dprx(source) || 323 (source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE && 324 dm_is_crc_source_dprx(cur_crc_src))) { 325 struct amdgpu_dm_connector *aconn = NULL; 326 struct drm_connector *connector; 327 struct drm_connector_list_iter conn_iter; 328 329 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 330 drm_for_each_connector_iter(connector, &conn_iter) { 331 if (!connector->state || connector->state->crtc != crtc) 332 continue; 333 334 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 335 continue; 336 337 aconn = to_amdgpu_dm_connector(connector); 338 break; 339 } 340 drm_connector_list_iter_end(&conn_iter); 341 342 if (!aconn) { 343 DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index); 344 ret = -EINVAL; 345 goto cleanup; 346 } 347 348 aux = (aconn->mst_output_port) ? &aconn->mst_output_port->aux : &aconn->dm_dp_aux.aux; 349 350 if (!aux) { 351 DRM_DEBUG_DRIVER("No dp aux for amd connector\n"); 352 ret = -EINVAL; 353 goto cleanup; 354 } 355 356 if ((aconn->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) && 357 (aconn->base.connector_type != DRM_MODE_CONNECTOR_eDP)) { 358 DRM_DEBUG_DRIVER("No DP connector available for CRC source\n"); 359 ret = -EINVAL; 360 goto cleanup; 361 } 362 363 } 364 365 /* 366 * Reading the CRC requires the vblank interrupt handler to be 367 * enabled. Keep a reference until CRC capture stops. 368 */ 369 enabled = amdgpu_dm_is_valid_crc_source(cur_crc_src); 370 if (!enabled && enable) { 371 ret = drm_crtc_vblank_get(crtc); 372 if (ret) 373 goto cleanup; 374 } 375 376 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 377 /* Reset secure_display when we change crc source from debugfs */ 378 amdgpu_dm_set_crc_window_default(crtc, crtc_state->stream); 379 #endif 380 381 if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) { 382 ret = -EINVAL; 383 goto cleanup; 384 } 385 386 if (!enabled && enable) { 387 if (dm_is_crc_source_dprx(source)) { 388 if (drm_dp_start_crc(aux, crtc)) { 389 DRM_DEBUG_DRIVER("dp start crc failed\n"); 390 ret = -EINVAL; 391 goto cleanup; 392 } 393 } 394 } else if (enabled && !enable) { 395 drm_crtc_vblank_put(crtc); 396 if (dm_is_crc_source_dprx(source)) { 397 if (drm_dp_stop_crc(aux)) { 398 DRM_DEBUG_DRIVER("dp stop crc failed\n"); 399 ret = -EINVAL; 400 goto cleanup; 401 } 402 } 403 } 404 405 spin_lock_irq(&drm_dev->event_lock); 406 acrtc->dm_irq_params.crc_src = source; 407 spin_unlock_irq(&drm_dev->event_lock); 408 409 /* Reset crc_skipped on dm state */ 410 crtc_state->crc_skip_count = 0; 411 412 cleanup: 413 if (commit) 414 drm_crtc_commit_put(commit); 415 416 drm_modeset_unlock(&crtc->mutex); 417 418 return ret; 419 } 420 421 /** 422 * amdgpu_dm_crtc_handle_crc_irq: Report to DRM the CRC on given CRTC. 423 * @crtc: DRM CRTC object. 424 * 425 * This function should be called at the end of a vblank, when the fb has been 426 * fully processed through the pipe. 427 */ 428 void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc) 429 { 430 struct dm_crtc_state *crtc_state; 431 struct dc_stream_state *stream_state; 432 struct drm_device *drm_dev = NULL; 433 enum amdgpu_dm_pipe_crc_source cur_crc_src; 434 struct amdgpu_crtc *acrtc = NULL; 435 uint32_t crcs[3]; 436 unsigned long flags; 437 438 if (crtc == NULL) 439 return; 440 441 crtc_state = to_dm_crtc_state(crtc->state); 442 stream_state = crtc_state->stream; 443 acrtc = to_amdgpu_crtc(crtc); 444 drm_dev = crtc->dev; 445 446 spin_lock_irqsave(&drm_dev->event_lock, flags); 447 cur_crc_src = acrtc->dm_irq_params.crc_src; 448 spin_unlock_irqrestore(&drm_dev->event_lock, flags); 449 450 /* Early return if CRC capture is not enabled. */ 451 if (!amdgpu_dm_is_valid_crc_source(cur_crc_src)) 452 return; 453 454 /* 455 * Since flipping and crc enablement happen asynchronously, we - more 456 * often than not - will be returning an 'uncooked' crc on first frame. 457 * Probably because hw isn't ready yet. For added security, skip the 458 * first two CRC values. 459 */ 460 if (crtc_state->crc_skip_count < 2) { 461 crtc_state->crc_skip_count += 1; 462 return; 463 } 464 465 if (dm_is_crc_source_crtc(cur_crc_src)) { 466 if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state, 467 &crcs[0], &crcs[1], &crcs[2])) 468 return; 469 470 drm_crtc_add_crc_entry(crtc, true, 471 drm_crtc_accurate_vblank_count(crtc), crcs); 472 } 473 } 474 475 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 476 void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) 477 { 478 struct drm_device *drm_dev = NULL; 479 enum amdgpu_dm_pipe_crc_source cur_crc_src; 480 struct amdgpu_crtc *acrtc = NULL; 481 struct amdgpu_device *adev = NULL; 482 struct secure_display_context *secure_display_ctx = NULL; 483 unsigned long flags1; 484 485 if (crtc == NULL) 486 return; 487 488 acrtc = to_amdgpu_crtc(crtc); 489 adev = drm_to_adev(crtc->dev); 490 drm_dev = crtc->dev; 491 492 spin_lock_irqsave(&drm_dev->event_lock, flags1); 493 cur_crc_src = acrtc->dm_irq_params.crc_src; 494 495 /* Early return if CRC capture is not enabled. */ 496 if (!amdgpu_dm_is_valid_crc_source(cur_crc_src) || 497 !dm_is_crc_source_crtc(cur_crc_src)) 498 goto cleanup; 499 500 if (!acrtc->dm_irq_params.window_param.activated) 501 goto cleanup; 502 503 if (acrtc->dm_irq_params.window_param.skip_frame_cnt) { 504 acrtc->dm_irq_params.window_param.skip_frame_cnt -= 1; 505 goto cleanup; 506 } 507 508 secure_display_ctx = &adev->dm.secure_display_ctxs[acrtc->crtc_id]; 509 if (WARN_ON(secure_display_ctx->crtc != crtc)) { 510 /* We have set the crtc when creating secure_display_context, 511 * don't expect it to be changed here. 512 */ 513 secure_display_ctx->crtc = crtc; 514 } 515 516 if (acrtc->dm_irq_params.window_param.update_win) { 517 /* prepare work for dmub to update ROI */ 518 secure_display_ctx->rect.x = acrtc->dm_irq_params.window_param.x_start; 519 secure_display_ctx->rect.y = acrtc->dm_irq_params.window_param.y_start; 520 secure_display_ctx->rect.width = acrtc->dm_irq_params.window_param.x_end - 521 acrtc->dm_irq_params.window_param.x_start; 522 secure_display_ctx->rect.height = acrtc->dm_irq_params.window_param.y_end - 523 acrtc->dm_irq_params.window_param.y_start; 524 schedule_work(&secure_display_ctx->forward_roi_work); 525 526 acrtc->dm_irq_params.window_param.update_win = false; 527 528 /* Statically skip 1 frame, because we may need to wait below things 529 * before sending ROI to dmub: 530 * 1. We defer the work by using system workqueue. 531 * 2. We may need to wait for dc_lock before accessing dmub. 532 */ 533 acrtc->dm_irq_params.window_param.skip_frame_cnt = 1; 534 535 } else { 536 /* prepare work for psp to read ROI/CRC and send to I2C */ 537 schedule_work(&secure_display_ctx->notify_ta_work); 538 } 539 540 cleanup: 541 spin_unlock_irqrestore(&drm_dev->event_lock, flags1); 542 } 543 544 struct secure_display_context * 545 amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev) 546 { 547 struct secure_display_context *secure_display_ctxs = NULL; 548 int i; 549 550 secure_display_ctxs = kcalloc(adev->mode_info.num_crtc, 551 sizeof(struct secure_display_context), 552 GFP_KERNEL); 553 554 if (!secure_display_ctxs) 555 return NULL; 556 557 for (i = 0; i < adev->mode_info.num_crtc; i++) { 558 INIT_WORK(&secure_display_ctxs[i].forward_roi_work, amdgpu_dm_forward_crc_window); 559 INIT_WORK(&secure_display_ctxs[i].notify_ta_work, amdgpu_dm_crtc_notify_ta_to_read); 560 secure_display_ctxs[i].crtc = &adev->mode_info.crtcs[i]->base; 561 } 562 563 return secure_display_ctxs; 564 } 565 #endif 566