1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <drm/drm_crtc.h> 27 #include <drm/drm_vblank.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_dm.h" 31 #include "dc.h" 32 #include "amdgpu_securedisplay.h" 33 34 static const char *const pipe_crc_sources[] = { 35 "none", 36 "crtc", 37 "crtc dither", 38 "dprx", 39 "dprx dither", 40 "auto", 41 }; 42 43 static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source) 44 { 45 if (!source || !strcmp(source, "none")) 46 return AMDGPU_DM_PIPE_CRC_SOURCE_NONE; 47 if (!strcmp(source, "auto") || !strcmp(source, "crtc")) 48 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC; 49 if (!strcmp(source, "dprx")) 50 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX; 51 if (!strcmp(source, "crtc dither")) 52 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER; 53 if (!strcmp(source, "dprx dither")) 54 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER; 55 56 return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID; 57 } 58 59 static bool dm_is_crc_source_crtc(enum amdgpu_dm_pipe_crc_source src) 60 { 61 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) || 62 (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER); 63 } 64 65 static bool dm_is_crc_source_dprx(enum amdgpu_dm_pipe_crc_source src) 66 { 67 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) || 68 (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER); 69 } 70 71 static bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src) 72 { 73 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER) || 74 (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER) || 75 (src == AMDGPU_DM_PIPE_CRC_SOURCE_NONE); 76 } 77 78 const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, 79 size_t *count) 80 { 81 *count = ARRAY_SIZE(pipe_crc_sources); 82 return pipe_crc_sources; 83 } 84 85 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 86 static void amdgpu_dm_set_crc_window_default(struct drm_crtc *crtc) 87 { 88 struct drm_device *drm_dev = crtc->dev; 89 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 90 91 spin_lock_irq(&drm_dev->event_lock); 92 acrtc->dm_irq_params.window_param.x_start = 0; 93 acrtc->dm_irq_params.window_param.y_start = 0; 94 acrtc->dm_irq_params.window_param.x_end = 0; 95 acrtc->dm_irq_params.window_param.y_end = 0; 96 acrtc->dm_irq_params.window_param.activated = false; 97 acrtc->dm_irq_params.window_param.update_win = false; 98 acrtc->dm_irq_params.window_param.skip_frame_cnt = 0; 99 spin_unlock_irq(&drm_dev->event_lock); 100 } 101 102 static void amdgpu_dm_crtc_notify_ta_to_read(struct work_struct *work) 103 { 104 struct secure_display_context *secure_display_ctx; 105 struct psp_context *psp; 106 struct securedisplay_cmd *securedisplay_cmd; 107 struct drm_crtc *crtc; 108 struct dc_stream_state *stream; 109 uint8_t phy_inst; 110 int ret; 111 112 secure_display_ctx = container_of(work, struct secure_display_context, notify_ta_work); 113 crtc = secure_display_ctx->crtc; 114 115 if (!crtc) { 116 return; 117 } 118 119 psp = &drm_to_adev(crtc->dev)->psp; 120 stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream; 121 phy_inst = stream->link->link_enc_hw_inst; 122 123 /* need lock for multiple crtcs to use the command buffer */ 124 mutex_lock(&psp->securedisplay_context.mutex); 125 126 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 127 TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC); 128 129 securedisplay_cmd->securedisplay_in_message.send_roi_crc.phy_id = phy_inst; 130 131 /* PSP TA is expected to finish data transmission over I2C within current frame, 132 * even there are up to 4 crtcs request to send in this frame. 133 */ 134 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC); 135 136 if (!ret) { 137 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 138 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 139 } 140 } 141 142 mutex_unlock(&psp->securedisplay_context.mutex); 143 } 144 145 static void 146 amdgpu_dm_forward_crc_window(struct work_struct *work) 147 { 148 struct secure_display_context *secure_display_ctx; 149 struct amdgpu_display_manager *dm; 150 struct drm_crtc *crtc; 151 struct dc_stream_state *stream; 152 153 secure_display_ctx = container_of(work, struct secure_display_context, forward_roi_work); 154 crtc = secure_display_ctx->crtc; 155 156 if (!crtc) 157 return; 158 159 dm = &drm_to_adev(crtc->dev)->dm; 160 stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream; 161 162 mutex_lock(&dm->dc_lock); 163 dc_stream_forward_crc_window(stream, &secure_display_ctx->rect, false); 164 mutex_unlock(&dm->dc_lock); 165 } 166 167 bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc) 168 { 169 struct drm_device *drm_dev = crtc->dev; 170 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 171 bool ret = false; 172 173 spin_lock_irq(&drm_dev->event_lock); 174 ret = acrtc->dm_irq_params.window_param.activated; 175 spin_unlock_irq(&drm_dev->event_lock); 176 177 return ret; 178 } 179 #endif 180 181 int 182 amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name, 183 size_t *values_cnt) 184 { 185 enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name); 186 187 if (source < 0) { 188 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n", 189 src_name, crtc->index); 190 return -EINVAL; 191 } 192 193 *values_cnt = 3; 194 return 0; 195 } 196 197 int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, 198 struct dm_crtc_state *dm_crtc_state, 199 enum amdgpu_dm_pipe_crc_source source) 200 { 201 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 202 int i; 203 #endif 204 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 205 struct dc_stream_state *stream_state = dm_crtc_state->stream; 206 bool enable = amdgpu_dm_is_valid_crc_source(source); 207 int ret = 0; 208 209 /* Configuration will be deferred to stream enable. */ 210 if (!stream_state) 211 return -EINVAL; 212 213 mutex_lock(&adev->dm.dc_lock); 214 215 /* Enable or disable CRTC CRC generation */ 216 if (dm_is_crc_source_crtc(source) || source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) { 217 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 218 /* Disable secure_display if it was enabled */ 219 if (!enable) { 220 if (adev->dm.secure_display_ctxs) { 221 for (i = 0; i < adev->mode_info.num_crtc; i++) { 222 if (adev->dm.secure_display_ctxs[i].crtc == crtc) { 223 /* stop ROI update on this crtc */ 224 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work); 225 dc_stream_forward_crc_window(stream_state, NULL, true); 226 adev->dm.secure_display_ctxs[i].crtc = NULL; 227 } 228 } 229 } 230 } 231 #endif 232 if (!dc_stream_configure_crc(stream_state->ctx->dc, 233 stream_state, NULL, enable, enable)) { 234 ret = -EINVAL; 235 goto unlock; 236 } 237 } 238 239 /* Configure dithering */ 240 if (!dm_need_crc_dither(source)) { 241 dc_stream_set_dither_option(stream_state, DITHER_OPTION_TRUN8); 242 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state, 243 DYN_EXPANSION_DISABLE); 244 } else { 245 dc_stream_set_dither_option(stream_state, 246 DITHER_OPTION_DEFAULT); 247 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state, 248 DYN_EXPANSION_AUTO); 249 } 250 251 unlock: 252 mutex_unlock(&adev->dm.dc_lock); 253 254 return ret; 255 } 256 257 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) 258 { 259 enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name); 260 enum amdgpu_dm_pipe_crc_source cur_crc_src; 261 struct drm_crtc_commit *commit; 262 struct dm_crtc_state *crtc_state; 263 struct drm_device *drm_dev = crtc->dev; 264 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 265 struct drm_dp_aux *aux = NULL; 266 bool enable = false; 267 bool enabled = false; 268 int ret = 0; 269 270 if (source < 0) { 271 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n", 272 src_name, crtc->index); 273 return -EINVAL; 274 } 275 276 ret = drm_modeset_lock(&crtc->mutex, NULL); 277 if (ret) 278 return ret; 279 280 spin_lock(&crtc->commit_lock); 281 commit = list_first_entry_or_null(&crtc->commit_list, 282 struct drm_crtc_commit, commit_entry); 283 if (commit) 284 drm_crtc_commit_get(commit); 285 spin_unlock(&crtc->commit_lock); 286 287 if (commit) { 288 /* 289 * Need to wait for all outstanding programming to complete 290 * in commit tail since it can modify CRC related fields and 291 * hardware state. Since we're holding the CRTC lock we're 292 * guaranteed that no other commit work can be queued off 293 * before we modify the state below. 294 */ 295 ret = wait_for_completion_interruptible_timeout( 296 &commit->hw_done, 10 * HZ); 297 if (ret) 298 goto cleanup; 299 } 300 301 enable = amdgpu_dm_is_valid_crc_source(source); 302 crtc_state = to_dm_crtc_state(crtc->state); 303 spin_lock_irq(&drm_dev->event_lock); 304 cur_crc_src = acrtc->dm_irq_params.crc_src; 305 spin_unlock_irq(&drm_dev->event_lock); 306 307 /* 308 * USER REQ SRC | CURRENT SRC | BEHAVIOR 309 * ----------------------------- 310 * None | None | Do nothing 311 * None | CRTC | Disable CRTC CRC, set default to dither 312 * None | DPRX | Disable DPRX CRC, need 'aux', set default to dither 313 * None | CRTC DITHER | Disable CRTC CRC 314 * None | DPRX DITHER | Disable DPRX CRC, need 'aux' 315 * CRTC | XXXX | Enable CRTC CRC, no dither 316 * DPRX | XXXX | Enable DPRX CRC, need 'aux', no dither 317 * CRTC DITHER | XXXX | Enable CRTC CRC, set dither 318 * DPRX DITHER | XXXX | Enable DPRX CRC, need 'aux', set dither 319 */ 320 if (dm_is_crc_source_dprx(source) || 321 (source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE && 322 dm_is_crc_source_dprx(cur_crc_src))) { 323 struct amdgpu_dm_connector *aconn = NULL; 324 struct drm_connector *connector; 325 struct drm_connector_list_iter conn_iter; 326 327 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 328 drm_for_each_connector_iter(connector, &conn_iter) { 329 if (!connector->state || connector->state->crtc != crtc) 330 continue; 331 332 aconn = to_amdgpu_dm_connector(connector); 333 break; 334 } 335 drm_connector_list_iter_end(&conn_iter); 336 337 if (!aconn) { 338 DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index); 339 ret = -EINVAL; 340 goto cleanup; 341 } 342 343 aux = (aconn->port) ? &aconn->port->aux : &aconn->dm_dp_aux.aux; 344 345 if (!aux) { 346 DRM_DEBUG_DRIVER("No dp aux for amd connector\n"); 347 ret = -EINVAL; 348 goto cleanup; 349 } 350 351 if ((aconn->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) && 352 (aconn->base.connector_type != DRM_MODE_CONNECTOR_eDP)) { 353 DRM_DEBUG_DRIVER("No DP connector available for CRC source\n"); 354 ret = -EINVAL; 355 goto cleanup; 356 } 357 358 } 359 360 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 361 /* Reset secure_display when we change crc source from debugfs */ 362 amdgpu_dm_set_crc_window_default(crtc); 363 #endif 364 365 if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) { 366 ret = -EINVAL; 367 goto cleanup; 368 } 369 370 /* 371 * Reading the CRC requires the vblank interrupt handler to be 372 * enabled. Keep a reference until CRC capture stops. 373 */ 374 enabled = amdgpu_dm_is_valid_crc_source(cur_crc_src); 375 if (!enabled && enable) { 376 ret = drm_crtc_vblank_get(crtc); 377 if (ret) 378 goto cleanup; 379 380 if (dm_is_crc_source_dprx(source)) { 381 if (drm_dp_start_crc(aux, crtc)) { 382 DRM_DEBUG_DRIVER("dp start crc failed\n"); 383 ret = -EINVAL; 384 goto cleanup; 385 } 386 } 387 } else if (enabled && !enable) { 388 drm_crtc_vblank_put(crtc); 389 if (dm_is_crc_source_dprx(source)) { 390 if (drm_dp_stop_crc(aux)) { 391 DRM_DEBUG_DRIVER("dp stop crc failed\n"); 392 ret = -EINVAL; 393 goto cleanup; 394 } 395 } 396 } 397 398 spin_lock_irq(&drm_dev->event_lock); 399 acrtc->dm_irq_params.crc_src = source; 400 spin_unlock_irq(&drm_dev->event_lock); 401 402 /* Reset crc_skipped on dm state */ 403 crtc_state->crc_skip_count = 0; 404 405 cleanup: 406 if (commit) 407 drm_crtc_commit_put(commit); 408 409 drm_modeset_unlock(&crtc->mutex); 410 411 return ret; 412 } 413 414 /** 415 * amdgpu_dm_crtc_handle_crc_irq: Report to DRM the CRC on given CRTC. 416 * @crtc: DRM CRTC object. 417 * 418 * This function should be called at the end of a vblank, when the fb has been 419 * fully processed through the pipe. 420 */ 421 void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc) 422 { 423 struct dm_crtc_state *crtc_state; 424 struct dc_stream_state *stream_state; 425 struct drm_device *drm_dev = NULL; 426 enum amdgpu_dm_pipe_crc_source cur_crc_src; 427 struct amdgpu_crtc *acrtc = NULL; 428 uint32_t crcs[3]; 429 unsigned long flags; 430 431 if (crtc == NULL) 432 return; 433 434 crtc_state = to_dm_crtc_state(crtc->state); 435 stream_state = crtc_state->stream; 436 acrtc = to_amdgpu_crtc(crtc); 437 drm_dev = crtc->dev; 438 439 spin_lock_irqsave(&drm_dev->event_lock, flags); 440 cur_crc_src = acrtc->dm_irq_params.crc_src; 441 spin_unlock_irqrestore(&drm_dev->event_lock, flags); 442 443 /* Early return if CRC capture is not enabled. */ 444 if (!amdgpu_dm_is_valid_crc_source(cur_crc_src)) 445 return; 446 447 /* 448 * Since flipping and crc enablement happen asynchronously, we - more 449 * often than not - will be returning an 'uncooked' crc on first frame. 450 * Probably because hw isn't ready yet. For added security, skip the 451 * first two CRC values. 452 */ 453 if (crtc_state->crc_skip_count < 2) { 454 crtc_state->crc_skip_count += 1; 455 return; 456 } 457 458 if (dm_is_crc_source_crtc(cur_crc_src)) { 459 if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state, 460 &crcs[0], &crcs[1], &crcs[2])) 461 return; 462 463 drm_crtc_add_crc_entry(crtc, true, 464 drm_crtc_accurate_vblank_count(crtc), crcs); 465 } 466 } 467 468 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 469 void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) 470 { 471 struct drm_device *drm_dev = NULL; 472 enum amdgpu_dm_pipe_crc_source cur_crc_src; 473 struct amdgpu_crtc *acrtc = NULL; 474 struct amdgpu_device *adev = NULL; 475 struct secure_display_context *secure_display_ctx = NULL; 476 unsigned long flags1; 477 478 if (crtc == NULL) 479 return; 480 481 acrtc = to_amdgpu_crtc(crtc); 482 adev = drm_to_adev(crtc->dev); 483 drm_dev = crtc->dev; 484 485 spin_lock_irqsave(&drm_dev->event_lock, flags1); 486 cur_crc_src = acrtc->dm_irq_params.crc_src; 487 488 /* Early return if CRC capture is not enabled. */ 489 if (!amdgpu_dm_is_valid_crc_source(cur_crc_src) || 490 !dm_is_crc_source_crtc(cur_crc_src)) 491 goto cleanup; 492 493 if (!acrtc->dm_irq_params.window_param.activated) 494 goto cleanup; 495 496 if (acrtc->dm_irq_params.window_param.skip_frame_cnt) { 497 acrtc->dm_irq_params.window_param.skip_frame_cnt -= 1; 498 goto cleanup; 499 } 500 501 secure_display_ctx = &adev->dm.secure_display_ctxs[acrtc->crtc_id]; 502 secure_display_ctx->crtc = crtc; 503 504 if (acrtc->dm_irq_params.window_param.update_win) { 505 /* prepare work for dmub to update ROI */ 506 secure_display_ctx->rect.x = acrtc->dm_irq_params.window_param.x_start; 507 secure_display_ctx->rect.y = acrtc->dm_irq_params.window_param.y_start; 508 secure_display_ctx->rect.width = acrtc->dm_irq_params.window_param.x_end - 509 acrtc->dm_irq_params.window_param.x_start; 510 secure_display_ctx->rect.height = acrtc->dm_irq_params.window_param.y_end - 511 acrtc->dm_irq_params.window_param.y_start; 512 schedule_work(&secure_display_ctx->forward_roi_work); 513 514 acrtc->dm_irq_params.window_param.update_win = false; 515 516 /* Statically skip 1 frame, because we may need to wait below things 517 * before sending ROI to dmub: 518 * 1. We defer the work by using system workqueue. 519 * 2. We may need to wait for dc_lock before accessing dmub. 520 */ 521 acrtc->dm_irq_params.window_param.skip_frame_cnt = 1; 522 523 } else { 524 /* prepare work for psp to read ROI/CRC and send to I2C */ 525 schedule_work(&secure_display_ctx->notify_ta_work); 526 } 527 528 cleanup: 529 spin_unlock_irqrestore(&drm_dev->event_lock, flags1); 530 } 531 532 struct secure_display_context * 533 amdgpu_dm_crtc_secure_display_create_contexts(int num_crtc) 534 { 535 struct secure_display_context *secure_display_ctxs = NULL; 536 int i; 537 538 secure_display_ctxs = kcalloc(num_crtc, sizeof(struct secure_display_context), GFP_KERNEL); 539 540 if (!secure_display_ctxs) 541 return NULL; 542 543 for (i = 0; i < num_crtc; i++) { 544 INIT_WORK(&secure_display_ctxs[i].forward_roi_work, amdgpu_dm_forward_crc_window); 545 INIT_WORK(&secure_display_ctxs[i].notify_ta_work, amdgpu_dm_crtc_notify_ta_to_read); 546 } 547 548 return secure_display_ctxs; 549 } 550 #endif 551