1 /* 2 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/display/drm_dp_mst_helper.h> 30 #include <drm/drm_atomic.h> 31 #include <drm/drm_connector.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_plane.h> 34 #include "link_service_types.h" 35 #include <drm/drm_writeback.h> 36 37 /* 38 * This file contains the definition for amdgpu_display_manager 39 * and its API for amdgpu driver's use. 40 * This component provides all the display related functionality 41 * and this is the only component that calls DAL API. 42 * The API contained here intended for amdgpu driver use. 43 * The API that is called directly from KMS framework is located 44 * in amdgpu_dm_kms.h file 45 */ 46 47 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 48 49 #define AMDGPU_DM_MAX_CRTC 6 50 51 #define AMDGPU_DM_MAX_NUM_EDP 2 52 53 #define AMDGPU_DMUB_NOTIFICATION_MAX 6 54 55 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A 56 #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40 57 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3 0x3 58 59 #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL) 60 61 /* 62 #include "include/amdgpu_dal_power_if.h" 63 #include "amdgpu_dm_irq.h" 64 */ 65 66 #include "irq_types.h" 67 #include "signal_types.h" 68 #include "amdgpu_dm_crc.h" 69 #include "mod_info_packet.h" 70 struct aux_payload; 71 struct set_config_cmd_payload; 72 enum aux_return_code_type; 73 enum set_config_status; 74 75 /* Forward declarations */ 76 struct amdgpu_device; 77 struct amdgpu_crtc; 78 struct drm_device; 79 struct dc; 80 struct amdgpu_bo; 81 struct dmub_srv; 82 struct dc_plane_state; 83 struct dmub_notification; 84 85 struct amd_vsdb_block { 86 unsigned char ieee_id[3]; 87 unsigned char version; 88 unsigned char feature_caps; 89 }; 90 91 struct common_irq_params { 92 struct amdgpu_device *adev; 93 enum dc_irq_source irq_src; 94 atomic64_t previous_timestamp; 95 }; 96 97 /** 98 * struct dm_compressor_info - Buffer info used by frame buffer compression 99 * @cpu_addr: MMIO cpu addr 100 * @bo_ptr: Pointer to the buffer object 101 * @gpu_addr: MMIO gpu addr 102 */ 103 struct dm_compressor_info { 104 void *cpu_addr; 105 struct amdgpu_bo *bo_ptr; 106 uint64_t gpu_addr; 107 }; 108 109 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify); 110 111 /** 112 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ 113 * 114 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq 115 * @dmub_notify: notification for callback function 116 * @adev: amdgpu_device pointer 117 */ 118 struct dmub_hpd_work { 119 struct work_struct handle_hpd_work; 120 struct dmub_notification *dmub_notify; 121 struct amdgpu_device *adev; 122 }; 123 124 /** 125 * struct vblank_control_work - Work data for vblank control 126 * @work: Kernel work data for the work event 127 * @dm: amdgpu display manager device 128 * @acrtc: amdgpu CRTC instance for which the event has occurred 129 * @stream: DC stream for which the event has occurred 130 * @enable: true if enabling vblank 131 */ 132 struct vblank_control_work { 133 struct work_struct work; 134 struct amdgpu_display_manager *dm; 135 struct amdgpu_crtc *acrtc; 136 struct dc_stream_state *stream; 137 bool enable; 138 }; 139 140 struct idle_workqueue { 141 struct work_struct work; 142 struct amdgpu_display_manager *dm; 143 bool enable; 144 bool running; 145 }; 146 147 /** 148 * struct amdgpu_dm_backlight_caps - Information about backlight 149 * 150 * Describe the backlight support for ACPI or eDP AUX. 151 */ 152 struct amdgpu_dm_backlight_caps { 153 /** 154 * @ext_caps: Keep the data struct with all the information about the 155 * display support for HDR. 156 */ 157 union dpcd_sink_ext_caps *ext_caps; 158 /** 159 * @aux_min_input_signal: Min brightness value supported by the display 160 */ 161 u32 aux_min_input_signal; 162 /** 163 * @aux_max_input_signal: Max brightness value supported by the display 164 * in nits. 165 */ 166 u32 aux_max_input_signal; 167 /** 168 * @min_input_signal: minimum possible input in range 0-255. 169 */ 170 int min_input_signal; 171 /** 172 * @max_input_signal: maximum possible input in range 0-255. 173 */ 174 int max_input_signal; 175 /** 176 * @caps_valid: true if these values are from the ACPI interface. 177 */ 178 bool caps_valid; 179 /** 180 * @aux_support: Describes if the display supports AUX backlight. 181 */ 182 bool aux_support; 183 /** 184 * @ac_level: the default brightness if booted on AC 185 */ 186 u8 ac_level; 187 /** 188 * @dc_level: the default brightness if booted on DC 189 */ 190 u8 dc_level; 191 }; 192 193 /** 194 * struct dal_allocation - Tracks mapped FB memory for SMU communication 195 * @list: list of dal allocations 196 * @bo: GPU buffer object 197 * @cpu_ptr: CPU virtual address of the GPU buffer object 198 * @gpu_addr: GPU virtual address of the GPU buffer object 199 */ 200 struct dal_allocation { 201 struct list_head list; 202 struct amdgpu_bo *bo; 203 void *cpu_ptr; 204 u64 gpu_addr; 205 }; 206 207 /** 208 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq 209 * offload work 210 */ 211 struct hpd_rx_irq_offload_work_queue { 212 /** 213 * @wq: workqueue structure to queue offload work. 214 */ 215 struct workqueue_struct *wq; 216 /** 217 * @offload_lock: To protect fields of offload work queue. 218 */ 219 spinlock_t offload_lock; 220 /** 221 * @is_handling_link_loss: Used to prevent inserting link loss event when 222 * we're handling link loss 223 */ 224 bool is_handling_link_loss; 225 /** 226 * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message 227 * ready event when we're already handling mst message ready event 228 */ 229 bool is_handling_mst_msg_rdy_event; 230 /** 231 * @aconnector: The aconnector that this work queue is attached to 232 */ 233 struct amdgpu_dm_connector *aconnector; 234 }; 235 236 /** 237 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure 238 */ 239 struct hpd_rx_irq_offload_work { 240 /** 241 * @work: offload work 242 */ 243 struct work_struct work; 244 /** 245 * @data: reference irq data which is used while handling offload work 246 */ 247 union hpd_irq_data data; 248 /** 249 * @offload_wq: offload work queue that this work is queued to 250 */ 251 struct hpd_rx_irq_offload_work_queue *offload_wq; 252 }; 253 254 /** 255 * struct amdgpu_display_manager - Central amdgpu display manager device 256 * 257 * @dc: Display Core control structure 258 * @adev: AMDGPU base driver structure 259 * @ddev: DRM base driver structure 260 * @display_indexes_num: Max number of display streams supported 261 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 262 * @backlight_dev: Backlight control device 263 * @backlight_link: Link on which to control backlight 264 * @backlight_caps: Capabilities of the backlight device 265 * @freesync_module: Module handling freesync calculations 266 * @hdcp_workqueue: AMDGPU content protection queue 267 * @fw_dmcu: Reference to DMCU firmware 268 * @dmcu_fw_version: Version of the DMCU firmware 269 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 270 * @cached_state: Caches device atomic state for suspend/resume 271 * @cached_dc_state: Cached state of content streams 272 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 273 * @force_timing_sync: set via debugfs. When set, indicates that all connected 274 * displays will be forced to synchronize. 275 * @dmcub_trace_event_en: enable dmcub trace events 276 * @dmub_outbox_params: DMUB Outbox parameters 277 * @num_of_edps: number of backlight eDPs 278 * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the 279 * driver when true 280 * @dmub_aux_transfer_done: struct completion used to indicate when DMUB 281 * transfers are done 282 * @delayed_hpd_wq: work queue used to delay DMUB HPD work 283 */ 284 struct amdgpu_display_manager { 285 286 struct dc *dc; 287 288 /** 289 * @dmub_srv: 290 * 291 * DMUB service, used for controlling the DMUB on hardware 292 * that supports it. The pointer to the dmub_srv will be 293 * NULL on hardware that does not support it. 294 */ 295 struct dmub_srv *dmub_srv; 296 297 /** 298 * @dmub_notify: 299 * 300 * Notification from DMUB. 301 */ 302 303 struct dmub_notification *dmub_notify; 304 305 /** 306 * @dmub_callback: 307 * 308 * Callback functions to handle notification from DMUB. 309 */ 310 311 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; 312 313 /** 314 * @dmub_thread_offload: 315 * 316 * Flag to indicate if callback is offload. 317 */ 318 319 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; 320 321 /** 322 * @dmub_fb_info: 323 * 324 * Framebuffer regions for the DMUB. 325 */ 326 struct dmub_srv_fb_info *dmub_fb_info; 327 328 /** 329 * @dmub_fw: 330 * 331 * DMUB firmware, required on hardware that has DMUB support. 332 */ 333 const struct firmware *dmub_fw; 334 335 /** 336 * @dmub_bo: 337 * 338 * Buffer object for the DMUB. 339 */ 340 struct amdgpu_bo *dmub_bo; 341 342 /** 343 * @dmub_bo_gpu_addr: 344 * 345 * GPU virtual address for the DMUB buffer object. 346 */ 347 u64 dmub_bo_gpu_addr; 348 349 /** 350 * @dmub_bo_cpu_addr: 351 * 352 * CPU address for the DMUB buffer object. 353 */ 354 void *dmub_bo_cpu_addr; 355 356 /** 357 * @dmcub_fw_version: 358 * 359 * DMCUB firmware version. 360 */ 361 uint32_t dmcub_fw_version; 362 363 /** 364 * @cgs_device: 365 * 366 * The Common Graphics Services device. It provides an interface for 367 * accessing registers. 368 */ 369 struct cgs_device *cgs_device; 370 371 struct amdgpu_device *adev; 372 struct drm_device *ddev; 373 u16 display_indexes_num; 374 375 /** 376 * @atomic_obj: 377 * 378 * In combination with &dm_atomic_state it helps manage 379 * global atomic state that doesn't map cleanly into existing 380 * drm resources, like &dc_context. 381 */ 382 struct drm_private_obj atomic_obj; 383 384 /** 385 * @dc_lock: 386 * 387 * Guards access to DC functions that can issue register write 388 * sequences. 389 */ 390 struct mutex dc_lock; 391 392 /** 393 * @audio_lock: 394 * 395 * Guards access to audio instance changes. 396 */ 397 struct mutex audio_lock; 398 399 /** 400 * @audio_component: 401 * 402 * Used to notify ELD changes to sound driver. 403 */ 404 struct drm_audio_component *audio_component; 405 406 /** 407 * @audio_registered: 408 * 409 * True if the audio component has been registered 410 * successfully, false otherwise. 411 */ 412 bool audio_registered; 413 414 /** 415 * @irq_handler_list_low_tab: 416 * 417 * Low priority IRQ handler table. 418 * 419 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 420 * source. Low priority IRQ handlers are deferred to a workqueue to be 421 * processed. Hence, they can sleep. 422 * 423 * Note that handlers are called in the same order as they were 424 * registered (FIFO). 425 */ 426 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 427 428 /** 429 * @irq_handler_list_high_tab: 430 * 431 * High priority IRQ handler table. 432 * 433 * It is a n*m table, same as &irq_handler_list_low_tab. However, 434 * handlers in this table are not deferred and are called immediately. 435 */ 436 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 437 438 /** 439 * @pflip_params: 440 * 441 * Page flip IRQ parameters, passed to registered handlers when 442 * triggered. 443 */ 444 struct common_irq_params 445 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 446 447 /** 448 * @vblank_params: 449 * 450 * Vertical blanking IRQ parameters, passed to registered handlers when 451 * triggered. 452 */ 453 struct common_irq_params 454 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 455 456 /** 457 * @vline0_params: 458 * 459 * OTG vertical interrupt0 IRQ parameters, passed to registered 460 * handlers when triggered. 461 */ 462 struct common_irq_params 463 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 464 465 /** 466 * @vupdate_params: 467 * 468 * Vertical update IRQ parameters, passed to registered handlers when 469 * triggered. 470 */ 471 struct common_irq_params 472 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 473 474 /** 475 * @dmub_trace_params: 476 * 477 * DMUB trace event IRQ parameters, passed to registered handlers when 478 * triggered. 479 */ 480 struct common_irq_params 481 dmub_trace_params[1]; 482 483 struct common_irq_params 484 dmub_outbox_params[1]; 485 486 spinlock_t irq_handler_list_table_lock; 487 488 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; 489 490 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; 491 492 uint8_t num_of_edps; 493 494 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; 495 496 struct mod_freesync *freesync_module; 497 struct hdcp_workqueue *hdcp_workqueue; 498 499 /** 500 * @vblank_control_workqueue: 501 * 502 * Deferred work for vblank control events. 503 */ 504 struct workqueue_struct *vblank_control_workqueue; 505 struct idle_workqueue *idle_workqueue; 506 507 struct drm_atomic_state *cached_state; 508 struct dc_state *cached_dc_state; 509 510 struct dm_compressor_info compressor; 511 512 const struct firmware *fw_dmcu; 513 uint32_t dmcu_fw_version; 514 /** 515 * @soc_bounding_box: 516 * 517 * gpu_info FW provided soc bounding box struct or 0 if not 518 * available in FW 519 */ 520 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 521 522 /** 523 * @active_vblank_irq_count: 524 * 525 * number of currently active vblank irqs 526 */ 527 uint32_t active_vblank_irq_count; 528 529 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 530 /** 531 * @secure_display_ctxs: 532 * 533 * Store the ROI information and the work_struct to command dmub and psp for 534 * all crtcs. 535 */ 536 struct secure_display_context *secure_display_ctxs; 537 #endif 538 /** 539 * @hpd_rx_offload_wq: 540 * 541 * Work queue to offload works of hpd_rx_irq 542 */ 543 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; 544 /** 545 * @mst_encoders: 546 * 547 * fake encoders used for DP MST. 548 */ 549 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 550 bool force_timing_sync; 551 bool disable_hpd_irq; 552 bool dmcub_trace_event_en; 553 /** 554 * @da_list: 555 * 556 * DAL fb memory allocation list, for communication with SMU. 557 */ 558 struct list_head da_list; 559 struct completion dmub_aux_transfer_done; 560 struct workqueue_struct *delayed_hpd_wq; 561 562 /** 563 * @brightness: 564 * 565 * cached backlight values. 566 */ 567 u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; 568 /** 569 * @actual_brightness: 570 * 571 * last successfully applied backlight values. 572 */ 573 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; 574 575 /** 576 * @aux_hpd_discon_quirk: 577 * 578 * quirk for hpd discon while aux is on-going. 579 * occurred on certain intel platform 580 */ 581 bool aux_hpd_discon_quirk; 582 583 /** 584 * @dpia_aux_lock: 585 * 586 * Guards access to DPIA AUX 587 */ 588 struct mutex dpia_aux_lock; 589 590 /** 591 * @bb_from_dmub: 592 * 593 * Bounding box data read from dmub during early initialization for DCN4+ 594 */ 595 struct dml2_soc_bb *bb_from_dmub; 596 }; 597 598 enum dsc_clock_force_state { 599 DSC_CLK_FORCE_DEFAULT = 0, 600 DSC_CLK_FORCE_ENABLE, 601 DSC_CLK_FORCE_DISABLE, 602 }; 603 604 struct dsc_preferred_settings { 605 enum dsc_clock_force_state dsc_force_enable; 606 uint32_t dsc_num_slices_v; 607 uint32_t dsc_num_slices_h; 608 uint32_t dsc_bits_per_pixel; 609 bool dsc_force_disable_passthrough; 610 }; 611 612 enum mst_progress_status { 613 MST_STATUS_DEFAULT = 0, 614 MST_PROBE = BIT(0), 615 MST_REMOTE_EDID = BIT(1), 616 MST_ALLOCATE_NEW_PAYLOAD = BIT(2), 617 MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3), 618 }; 619 620 /** 621 * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info 622 * 623 * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this 624 * struct is useful to keep track of the display-specific information about 625 * FreeSync. 626 */ 627 struct amdgpu_hdmi_vsdb_info { 628 /** 629 * @amd_vsdb_version: Vendor Specific Data Block Version, should be 630 * used to determine which Vendor Specific InfoFrame (VSIF) to send. 631 */ 632 unsigned int amd_vsdb_version; 633 634 /** 635 * @freesync_supported: FreeSync Supported. 636 */ 637 bool freesync_supported; 638 639 /** 640 * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz. 641 */ 642 unsigned int min_refresh_rate_hz; 643 644 /** 645 * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz 646 */ 647 unsigned int max_refresh_rate_hz; 648 649 /** 650 * @replay_mode: Replay supported 651 */ 652 bool replay_mode; 653 }; 654 655 struct amdgpu_dm_connector { 656 657 struct drm_connector base; 658 uint32_t connector_id; 659 int bl_idx; 660 661 /* we need to mind the EDID between detect 662 and get modes due to analog/digital/tvencoder */ 663 struct edid *edid; 664 665 /* shared with amdgpu */ 666 struct amdgpu_hpd hpd; 667 668 /* number of modes generated from EDID at 'dc_sink' */ 669 int num_modes; 670 671 /* The 'old' sink - before an HPD. 672 * The 'current' sink is in dc_link->sink. */ 673 struct dc_sink *dc_sink; 674 struct dc_link *dc_link; 675 676 /** 677 * @dc_em_sink: Reference to the emulated (virtual) sink. 678 */ 679 struct dc_sink *dc_em_sink; 680 681 /* DM only */ 682 struct drm_dp_mst_topology_mgr mst_mgr; 683 struct amdgpu_dm_dp_aux dm_dp_aux; 684 struct drm_dp_mst_port *mst_output_port; 685 struct amdgpu_dm_connector *mst_root; 686 struct drm_dp_aux *dsc_aux; 687 struct mutex handle_mst_msg_ready; 688 689 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 690 struct amdgpu_i2c_adapter *i2c; 691 692 /* Monitor range limits */ 693 /** 694 * @min_vfreq: Minimal frequency supported by the display in Hz. This 695 * value is set to zero when there is no FreeSync support. 696 */ 697 int min_vfreq; 698 699 /** 700 * @max_vfreq: Maximum frequency supported by the display in Hz. This 701 * value is set to zero when there is no FreeSync support. 702 */ 703 int max_vfreq ; 704 705 /* Audio instance - protected by audio_lock. */ 706 int audio_inst; 707 708 struct mutex hpd_lock; 709 710 bool fake_enable; 711 bool force_yuv420_output; 712 struct dsc_preferred_settings dsc_settings; 713 union dp_downstream_port_present mst_downstream_port_present; 714 /* Cached display modes */ 715 struct drm_display_mode freesync_vid_base; 716 717 int psr_skip_count; 718 bool disallow_edp_enter_psr; 719 720 /* Record progress status of mst*/ 721 uint8_t mst_status; 722 723 /* Automated testing */ 724 bool timing_changed; 725 struct dc_crtc_timing *timing_requested; 726 727 /* Adaptive Sync */ 728 bool pack_sdp_v1_3; 729 enum adaptive_sync_type as_type; 730 struct amdgpu_hdmi_vsdb_info vsdb_info; 731 }; 732 733 static inline void amdgpu_dm_set_mst_status(uint8_t *status, 734 uint8_t flags, bool set) 735 { 736 if (set) 737 *status |= flags; 738 else 739 *status &= ~flags; 740 } 741 742 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 743 744 struct amdgpu_dm_wb_connector { 745 struct drm_writeback_connector base; 746 struct dc_link *link; 747 }; 748 749 #define to_amdgpu_dm_wb_connector(x) container_of(x, struct amdgpu_dm_wb_connector, base) 750 751 extern const struct amdgpu_ip_block_version dm_ip_block; 752 753 /* enum amdgpu_transfer_function: pre-defined transfer function supported by AMD. 754 * 755 * It includes standardized transfer functions and pure power functions. The 756 * transfer function coefficients are available at modules/color/color_gamma.c 757 */ 758 enum amdgpu_transfer_function { 759 AMDGPU_TRANSFER_FUNCTION_DEFAULT, 760 AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF, 761 AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF, 762 AMDGPU_TRANSFER_FUNCTION_PQ_EOTF, 763 AMDGPU_TRANSFER_FUNCTION_IDENTITY, 764 AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF, 765 AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF, 766 AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF, 767 AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF, 768 AMDGPU_TRANSFER_FUNCTION_BT709_OETF, 769 AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF, 770 AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF, 771 AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF, 772 AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF, 773 AMDGPU_TRANSFER_FUNCTION_COUNT 774 }; 775 776 struct dm_plane_state { 777 struct drm_plane_state base; 778 struct dc_plane_state *dc_state; 779 780 /* Plane color mgmt */ 781 /** 782 * @degamma_lut: 783 * 784 * 1D LUT for mapping framebuffer/plane pixel data before sampling or 785 * blending operations. It's usually applied to linearize input space. 786 * The blob (if not NULL) is an array of &struct drm_color_lut. 787 */ 788 struct drm_property_blob *degamma_lut; 789 /** 790 * @degamma_tf: 791 * 792 * Predefined transfer function to tell DC driver the input space to 793 * linearize. 794 */ 795 enum amdgpu_transfer_function degamma_tf; 796 /** 797 * @hdr_mult: 798 * 799 * Multiplier to 'gain' the plane. When PQ is decoded using the fixed 800 * func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on 801 * AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously. 802 * Therefore, 1.0 multiplier = 80 nits for SDR content. So if you 803 * want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is 804 * S31.32 sign-magnitude. 805 * 806 * HDR multiplier can wide range beyond [0.0, 1.0]. This means that PQ 807 * TF is needed for any subsequent linear-to-non-linear transforms. 808 */ 809 __u64 hdr_mult; 810 /** 811 * @ctm: 812 * 813 * Color transformation matrix. The blob (if not NULL) is a &struct 814 * drm_color_ctm_3x4. 815 */ 816 struct drm_property_blob *ctm; 817 /** 818 * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an 819 * array of &struct drm_color_lut. 820 */ 821 struct drm_property_blob *shaper_lut; 822 /** 823 * @shaper_tf: 824 * 825 * Predefined transfer function to delinearize color space. 826 */ 827 enum amdgpu_transfer_function shaper_tf; 828 /** 829 * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of 830 * &struct drm_color_lut. 831 */ 832 struct drm_property_blob *lut3d; 833 /** 834 * @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an 835 * array of &struct drm_color_lut. 836 */ 837 struct drm_property_blob *blend_lut; 838 /** 839 * @blend_tf: 840 * 841 * Pre-defined transfer function for converting plane pixel data before 842 * applying blend LUT. 843 */ 844 enum amdgpu_transfer_function blend_tf; 845 }; 846 847 enum amdgpu_dm_cursor_mode { 848 DM_CURSOR_NATIVE_MODE = 0, 849 DM_CURSOR_OVERLAY_MODE, 850 }; 851 852 struct dm_crtc_state { 853 struct drm_crtc_state base; 854 struct dc_stream_state *stream; 855 856 bool cm_has_degamma; 857 bool cm_is_degamma_srgb; 858 859 bool mpo_requested; 860 861 int update_type; 862 int active_planes; 863 864 int crc_skip_count; 865 866 bool freesync_vrr_info_changed; 867 868 bool dsc_force_changed; 869 bool vrr_supported; 870 struct mod_freesync_config freesync_config; 871 struct dc_info_packet vrr_infopacket; 872 873 int abm_level; 874 875 /** 876 * @regamma_tf: 877 * 878 * Pre-defined transfer function for converting internal FB -> wire 879 * encoding. 880 */ 881 enum amdgpu_transfer_function regamma_tf; 882 883 enum amdgpu_dm_cursor_mode cursor_mode; 884 }; 885 886 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 887 888 struct dm_atomic_state { 889 struct drm_private_state base; 890 891 struct dc_state *context; 892 }; 893 894 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 895 896 struct dm_connector_state { 897 struct drm_connector_state base; 898 899 enum amdgpu_rmx_type scaling; 900 uint8_t underscan_vborder; 901 uint8_t underscan_hborder; 902 bool underscan_enable; 903 bool freesync_capable; 904 bool update_hdcp; 905 uint8_t abm_level; 906 int vcpi_slots; 907 uint64_t pbn; 908 }; 909 910 #define to_dm_connector_state(x)\ 911 container_of((x), struct dm_connector_state, base) 912 913 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 914 struct drm_connector_state * 915 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 916 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 917 struct drm_connector_state *state, 918 struct drm_property *property, 919 uint64_t val); 920 921 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 922 const struct drm_connector_state *state, 923 struct drm_property *property, 924 uint64_t *val); 925 926 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 927 928 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 929 struct amdgpu_dm_connector *aconnector, 930 int connector_type, 931 struct dc_link *link, 932 int link_index); 933 934 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 935 struct drm_display_mode *mode); 936 937 void dm_restore_drm_connector_state(struct drm_device *dev, 938 struct drm_connector *connector); 939 940 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 941 struct edid *edid); 942 943 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 944 945 /* 3D LUT max size is 17x17x17 (4913 entries) */ 946 #define MAX_COLOR_3DLUT_SIZE 17 947 #define MAX_COLOR_3DLUT_BITDEPTH 12 948 int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, 949 struct drm_plane_state *plane_state); 950 /* 1D LUT size */ 951 #define MAX_COLOR_LUT_ENTRIES 4096 952 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 953 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 954 955 void amdgpu_dm_init_color_mod(void); 956 int amdgpu_dm_create_color_properties(struct amdgpu_device *adev); 957 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); 958 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 959 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 960 struct drm_plane_state *plane_state, 961 struct dc_plane_state *dc_plane_state); 962 963 void amdgpu_dm_update_connector_after_detect( 964 struct amdgpu_dm_connector *aconnector); 965 966 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 967 968 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index, 969 struct aux_payload *payload, enum aux_return_code_type *operation_result); 970 971 int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index, 972 struct set_config_cmd_payload *payload, enum set_config_status *operation_result); 973 974 struct dc_stream_state * 975 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, 976 const struct drm_display_mode *drm_mode, 977 const struct dm_connector_state *dm_state, 978 const struct dc_stream_state *old_stream); 979 980 int dm_atomic_get_state(struct drm_atomic_state *state, 981 struct dm_atomic_state **dm_state); 982 983 struct drm_connector * 984 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 985 struct drm_crtc *crtc); 986 987 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); 988 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev); 989 990 void *dm_allocate_gpu_mem(struct amdgpu_device *adev, 991 enum dc_gpu_mem_alloc_type type, 992 size_t size, 993 long long *addr); 994 995 bool amdgpu_dm_is_headless(struct amdgpu_device *adev); 996 997 #endif /* __AMDGPU_DM_H__ */ 998