1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* The caprices of the preprocessor require that this be declared right here */ 27 #define CREATE_TRACE_POINTS 28 29 #include "dm_services_types.h" 30 #include "dc.h" 31 #include "link_enc_cfg.h" 32 #include "dc/inc/core_types.h" 33 #include "dal_asic_id.h" 34 #include "dmub/dmub_srv.h" 35 #include "dc/inc/hw/dmcu.h" 36 #include "dc/inc/hw/abm.h" 37 #include "dc/dc_dmub_srv.h" 38 #include "dc/dc_edid_parser.h" 39 #include "dc/dc_stat.h" 40 #include "dc/dc_state.h" 41 #include "amdgpu_dm_trace.h" 42 #include "dpcd_defs.h" 43 #include "link/protocols/link_dpcd.h" 44 #include "link_service_types.h" 45 #include "link/protocols/link_dp_capability.h" 46 #include "link/protocols/link_ddc.h" 47 48 #include "vid.h" 49 #include "amdgpu.h" 50 #include "amdgpu_display.h" 51 #include "amdgpu_ucode.h" 52 #include "atom.h" 53 #include "amdgpu_dm.h" 54 #include "amdgpu_dm_plane.h" 55 #include "amdgpu_dm_crtc.h" 56 #include "amdgpu_dm_hdcp.h" 57 #include <drm/display/drm_hdcp_helper.h> 58 #include "amdgpu_dm_wb.h" 59 #include "amdgpu_pm.h" 60 #include "amdgpu_atombios.h" 61 62 #include "amd_shared.h" 63 #include "amdgpu_dm_irq.h" 64 #include "dm_helpers.h" 65 #include "amdgpu_dm_mst_types.h" 66 #if defined(CONFIG_DEBUG_FS) 67 #include "amdgpu_dm_debugfs.h" 68 #endif 69 #include "amdgpu_dm_psr.h" 70 #include "amdgpu_dm_replay.h" 71 72 #include "ivsrcid/ivsrcid_vislands30.h" 73 74 #include <linux/backlight.h> 75 #include <linux/module.h> 76 #include <linux/moduleparam.h> 77 #include <linux/types.h> 78 #include <linux/pm_runtime.h> 79 #include <linux/pci.h> 80 #include <linux/firmware.h> 81 #include <linux/component.h> 82 #include <linux/dmi.h> 83 84 #include <drm/display/drm_dp_mst_helper.h> 85 #include <drm/display/drm_hdmi_helper.h> 86 #include <drm/drm_atomic.h> 87 #include <drm/drm_atomic_uapi.h> 88 #include <drm/drm_atomic_helper.h> 89 #include <drm/drm_blend.h> 90 #include <drm/drm_fixed.h> 91 #include <drm/drm_fourcc.h> 92 #include <drm/drm_edid.h> 93 #include <drm/drm_eld.h> 94 #include <drm/drm_vblank.h> 95 #include <drm/drm_audio_component.h> 96 #include <drm/drm_gem_atomic_helper.h> 97 98 #include <acpi/video.h> 99 100 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 101 102 #include "dcn/dcn_1_0_offset.h" 103 #include "dcn/dcn_1_0_sh_mask.h" 104 #include "soc15_hw_ip.h" 105 #include "soc15_common.h" 106 #include "vega10_ip_offset.h" 107 108 #include "gc/gc_11_0_0_offset.h" 109 #include "gc/gc_11_0_0_sh_mask.h" 110 111 #include "modules/inc/mod_freesync.h" 112 #include "modules/power/power_helpers.h" 113 114 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin" 115 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB); 116 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin" 117 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB); 118 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin" 119 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB); 120 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin" 121 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB); 122 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin" 123 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB); 124 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin" 125 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB); 126 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin" 127 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB); 128 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin" 129 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB); 130 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin" 131 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB); 132 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin" 133 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB); 134 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin" 135 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB); 136 137 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin" 138 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB); 139 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin" 140 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB); 141 142 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" 143 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 144 145 #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin" 146 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); 147 148 #define FIRMWARE_DCN_35_DMUB "amdgpu/dcn_3_5_dmcub.bin" 149 MODULE_FIRMWARE(FIRMWARE_DCN_35_DMUB); 150 151 #define FIRMWARE_DCN_351_DMUB "amdgpu/dcn_3_5_1_dmcub.bin" 152 MODULE_FIRMWARE(FIRMWARE_DCN_351_DMUB); 153 154 #define FIRMWARE_DCN_401_DMUB "amdgpu/dcn_4_0_1_dmcub.bin" 155 MODULE_FIRMWARE(FIRMWARE_DCN_401_DMUB); 156 157 /* Number of bytes in PSP header for firmware. */ 158 #define PSP_HEADER_BYTES 0x100 159 160 /* Number of bytes in PSP footer for firmware. */ 161 #define PSP_FOOTER_BYTES 0x100 162 163 /** 164 * DOC: overview 165 * 166 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 167 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM 168 * requests into DC requests, and DC responses into DRM responses. 169 * 170 * The root control structure is &struct amdgpu_display_manager. 171 */ 172 173 /* basic init/fini API */ 174 static int amdgpu_dm_init(struct amdgpu_device *adev); 175 static void amdgpu_dm_fini(struct amdgpu_device *adev); 176 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector); 177 178 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link) 179 { 180 switch (link->dpcd_caps.dongle_type) { 181 case DISPLAY_DONGLE_NONE: 182 return DRM_MODE_SUBCONNECTOR_Native; 183 case DISPLAY_DONGLE_DP_VGA_CONVERTER: 184 return DRM_MODE_SUBCONNECTOR_VGA; 185 case DISPLAY_DONGLE_DP_DVI_CONVERTER: 186 case DISPLAY_DONGLE_DP_DVI_DONGLE: 187 return DRM_MODE_SUBCONNECTOR_DVID; 188 case DISPLAY_DONGLE_DP_HDMI_CONVERTER: 189 case DISPLAY_DONGLE_DP_HDMI_DONGLE: 190 return DRM_MODE_SUBCONNECTOR_HDMIA; 191 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: 192 default: 193 return DRM_MODE_SUBCONNECTOR_Unknown; 194 } 195 } 196 197 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector) 198 { 199 struct dc_link *link = aconnector->dc_link; 200 struct drm_connector *connector = &aconnector->base; 201 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 202 203 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 204 return; 205 206 if (aconnector->dc_sink) 207 subconnector = get_subconnector_type(link); 208 209 drm_object_property_set_value(&connector->base, 210 connector->dev->mode_config.dp_subconnector_property, 211 subconnector); 212 } 213 214 /* 215 * initializes drm_device display related structures, based on the information 216 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 217 * drm_encoder, drm_mode_config 218 * 219 * Returns 0 on success 220 */ 221 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 222 /* removes and deallocates the drm structures, created by the above function */ 223 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 224 225 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 226 struct amdgpu_dm_connector *amdgpu_dm_connector, 227 u32 link_index, 228 struct amdgpu_encoder *amdgpu_encoder); 229 static int amdgpu_dm_encoder_init(struct drm_device *dev, 230 struct amdgpu_encoder *aencoder, 231 uint32_t link_index); 232 233 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); 234 235 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); 236 237 static int amdgpu_dm_atomic_check(struct drm_device *dev, 238 struct drm_atomic_state *state); 239 240 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector); 241 static void handle_hpd_rx_irq(void *param); 242 243 static bool 244 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 245 struct drm_crtc_state *new_crtc_state); 246 /* 247 * dm_vblank_get_counter 248 * 249 * @brief 250 * Get counter for number of vertical blanks 251 * 252 * @param 253 * struct amdgpu_device *adev - [in] desired amdgpu device 254 * int disp_idx - [in] which CRTC to get the counter from 255 * 256 * @return 257 * Counter for vertical blanks 258 */ 259 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 260 { 261 struct amdgpu_crtc *acrtc = NULL; 262 263 if (crtc >= adev->mode_info.num_crtc) 264 return 0; 265 266 acrtc = adev->mode_info.crtcs[crtc]; 267 268 if (!acrtc->dm_irq_params.stream) { 269 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 270 crtc); 271 return 0; 272 } 273 274 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); 275 } 276 277 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 278 u32 *vbl, u32 *position) 279 { 280 u32 v_blank_start = 0, v_blank_end = 0, h_position = 0, v_position = 0; 281 struct amdgpu_crtc *acrtc = NULL; 282 struct dc *dc = adev->dm.dc; 283 284 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 285 return -EINVAL; 286 287 acrtc = adev->mode_info.crtcs[crtc]; 288 289 if (!acrtc->dm_irq_params.stream) { 290 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 291 crtc); 292 return 0; 293 } 294 295 if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed) 296 dc_allow_idle_optimizations(dc, false); 297 298 /* 299 * TODO rework base driver to use values directly. 300 * for now parse it back into reg-format 301 */ 302 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, 303 &v_blank_start, 304 &v_blank_end, 305 &h_position, 306 &v_position); 307 308 *position = v_position | (h_position << 16); 309 *vbl = v_blank_start | (v_blank_end << 16); 310 311 return 0; 312 } 313 314 static bool dm_is_idle(void *handle) 315 { 316 /* XXX todo */ 317 return true; 318 } 319 320 static int dm_wait_for_idle(void *handle) 321 { 322 /* XXX todo */ 323 return 0; 324 } 325 326 static bool dm_check_soft_reset(void *handle) 327 { 328 return false; 329 } 330 331 static int dm_soft_reset(void *handle) 332 { 333 /* XXX todo */ 334 return 0; 335 } 336 337 static struct amdgpu_crtc * 338 get_crtc_by_otg_inst(struct amdgpu_device *adev, 339 int otg_inst) 340 { 341 struct drm_device *dev = adev_to_drm(adev); 342 struct drm_crtc *crtc; 343 struct amdgpu_crtc *amdgpu_crtc; 344 345 if (WARN_ON(otg_inst == -1)) 346 return adev->mode_info.crtcs[0]; 347 348 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 349 amdgpu_crtc = to_amdgpu_crtc(crtc); 350 351 if (amdgpu_crtc->otg_inst == otg_inst) 352 return amdgpu_crtc; 353 } 354 355 return NULL; 356 } 357 358 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, 359 struct dm_crtc_state *new_state) 360 { 361 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) 362 return true; 363 else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state)) 364 return true; 365 else 366 return false; 367 } 368 369 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update, 370 int planes_count) 371 { 372 int i, j; 373 374 for (i = 0, j = planes_count - 1; i < j; i++, j--) 375 swap(array_of_surface_update[i], array_of_surface_update[j]); 376 } 377 378 /** 379 * update_planes_and_stream_adapter() - Send planes to be updated in DC 380 * 381 * DC has a generic way to update planes and stream via 382 * dc_update_planes_and_stream function; however, DM might need some 383 * adjustments and preparation before calling it. This function is a wrapper 384 * for the dc_update_planes_and_stream that does any required configuration 385 * before passing control to DC. 386 * 387 * @dc: Display Core control structure 388 * @update_type: specify whether it is FULL/MEDIUM/FAST update 389 * @planes_count: planes count to update 390 * @stream: stream state 391 * @stream_update: stream update 392 * @array_of_surface_update: dc surface update pointer 393 * 394 */ 395 static inline bool update_planes_and_stream_adapter(struct dc *dc, 396 int update_type, 397 int planes_count, 398 struct dc_stream_state *stream, 399 struct dc_stream_update *stream_update, 400 struct dc_surface_update *array_of_surface_update) 401 { 402 reverse_planes_order(array_of_surface_update, planes_count); 403 404 /* 405 * Previous frame finished and HW is ready for optimization. 406 */ 407 if (update_type == UPDATE_TYPE_FAST) 408 dc_post_update_surfaces_to_stream(dc); 409 410 return dc_update_planes_and_stream(dc, 411 array_of_surface_update, 412 planes_count, 413 stream, 414 stream_update); 415 } 416 417 /** 418 * dm_pflip_high_irq() - Handle pageflip interrupt 419 * @interrupt_params: ignored 420 * 421 * Handles the pageflip interrupt by notifying all interested parties 422 * that the pageflip has been completed. 423 */ 424 static void dm_pflip_high_irq(void *interrupt_params) 425 { 426 struct amdgpu_crtc *amdgpu_crtc; 427 struct common_irq_params *irq_params = interrupt_params; 428 struct amdgpu_device *adev = irq_params->adev; 429 struct drm_device *dev = adev_to_drm(adev); 430 unsigned long flags; 431 struct drm_pending_vblank_event *e; 432 u32 vpos, hpos, v_blank_start, v_blank_end; 433 bool vrr_active; 434 435 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); 436 437 /* IRQ could occur when in initial stage */ 438 /* TODO work and BO cleanup */ 439 if (amdgpu_crtc == NULL) { 440 drm_dbg_state(dev, "CRTC is null, returning.\n"); 441 return; 442 } 443 444 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 445 446 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 447 drm_dbg_state(dev, 448 "amdgpu_crtc->pflip_status = %d != AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n", 449 amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED, 450 amdgpu_crtc->crtc_id, amdgpu_crtc); 451 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 452 return; 453 } 454 455 /* page flip completed. */ 456 e = amdgpu_crtc->event; 457 amdgpu_crtc->event = NULL; 458 459 WARN_ON(!e); 460 461 vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc); 462 463 /* Fixed refresh rate, or VRR scanout position outside front-porch? */ 464 if (!vrr_active || 465 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start, 466 &v_blank_end, &hpos, &vpos) || 467 (vpos < v_blank_start)) { 468 /* Update to correct count and vblank timestamp if racing with 469 * vblank irq. This also updates to the correct vblank timestamp 470 * even in VRR mode, as scanout is past the front-porch atm. 471 */ 472 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); 473 474 /* Wake up userspace by sending the pageflip event with proper 475 * count and timestamp of vblank of flip completion. 476 */ 477 if (e) { 478 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); 479 480 /* Event sent, so done with vblank for this flip */ 481 drm_crtc_vblank_put(&amdgpu_crtc->base); 482 } 483 } else if (e) { 484 /* VRR active and inside front-porch: vblank count and 485 * timestamp for pageflip event will only be up to date after 486 * drm_crtc_handle_vblank() has been executed from late vblank 487 * irq handler after start of back-porch (vline 0). We queue the 488 * pageflip event for send-out by drm_crtc_handle_vblank() with 489 * updated timestamp and count, once it runs after us. 490 * 491 * We need to open-code this instead of using the helper 492 * drm_crtc_arm_vblank_event(), as that helper would 493 * call drm_crtc_accurate_vblank_count(), which we must 494 * not call in VRR mode while we are in front-porch! 495 */ 496 497 /* sequence will be replaced by real count during send-out. */ 498 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); 499 e->pipe = amdgpu_crtc->crtc_id; 500 501 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list); 502 e = NULL; 503 } 504 505 /* Keep track of vblank of this flip for flip throttling. We use the 506 * cooked hw counter, as that one incremented at start of this vblank 507 * of pageflip completion, so last_flip_vblank is the forbidden count 508 * for queueing new pageflips if vsync + VRR is enabled. 509 */ 510 amdgpu_crtc->dm_irq_params.last_flip_vblank = 511 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base); 512 513 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 514 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 515 516 drm_dbg_state(dev, 517 "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n", 518 amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int)!e); 519 } 520 521 static void dm_vupdate_high_irq(void *interrupt_params) 522 { 523 struct common_irq_params *irq_params = interrupt_params; 524 struct amdgpu_device *adev = irq_params->adev; 525 struct amdgpu_crtc *acrtc; 526 struct drm_device *drm_dev; 527 struct drm_vblank_crtc *vblank; 528 ktime_t frame_duration_ns, previous_timestamp; 529 unsigned long flags; 530 int vrr_active; 531 532 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); 533 534 if (acrtc) { 535 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); 536 drm_dev = acrtc->base.dev; 537 vblank = &drm_dev->vblank[acrtc->base.index]; 538 previous_timestamp = atomic64_read(&irq_params->previous_timestamp); 539 frame_duration_ns = vblank->time - previous_timestamp; 540 541 if (frame_duration_ns > 0) { 542 trace_amdgpu_refresh_rate_track(acrtc->base.index, 543 frame_duration_ns, 544 ktime_divns(NSEC_PER_SEC, frame_duration_ns)); 545 atomic64_set(&irq_params->previous_timestamp, vblank->time); 546 } 547 548 drm_dbg_vbl(drm_dev, 549 "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, 550 vrr_active); 551 552 /* Core vblank handling is done here after end of front-porch in 553 * vrr mode, as vblank timestamping will give valid results 554 * while now done after front-porch. This will also deliver 555 * page-flip completion events that have been queued to us 556 * if a pageflip happened inside front-porch. 557 */ 558 if (vrr_active) { 559 amdgpu_dm_crtc_handle_vblank(acrtc); 560 561 /* BTR processing for pre-DCE12 ASICs */ 562 if (acrtc->dm_irq_params.stream && 563 adev->family < AMDGPU_FAMILY_AI) { 564 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 565 mod_freesync_handle_v_update( 566 adev->dm.freesync_module, 567 acrtc->dm_irq_params.stream, 568 &acrtc->dm_irq_params.vrr_params); 569 570 dc_stream_adjust_vmin_vmax( 571 adev->dm.dc, 572 acrtc->dm_irq_params.stream, 573 &acrtc->dm_irq_params.vrr_params.adjust); 574 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 575 } 576 } 577 } 578 } 579 580 /** 581 * dm_crtc_high_irq() - Handles CRTC interrupt 582 * @interrupt_params: used for determining the CRTC instance 583 * 584 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK 585 * event handler. 586 */ 587 static void dm_crtc_high_irq(void *interrupt_params) 588 { 589 struct common_irq_params *irq_params = interrupt_params; 590 struct amdgpu_device *adev = irq_params->adev; 591 struct drm_writeback_job *job; 592 struct amdgpu_crtc *acrtc; 593 unsigned long flags; 594 int vrr_active; 595 596 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); 597 if (!acrtc) 598 return; 599 600 if (acrtc->wb_pending) { 601 if (acrtc->wb_conn) { 602 spin_lock_irqsave(&acrtc->wb_conn->job_lock, flags); 603 job = list_first_entry_or_null(&acrtc->wb_conn->job_queue, 604 struct drm_writeback_job, 605 list_entry); 606 spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags); 607 608 if (job) { 609 unsigned int v_total, refresh_hz; 610 struct dc_stream_state *stream = acrtc->dm_irq_params.stream; 611 612 v_total = stream->adjust.v_total_max ? 613 stream->adjust.v_total_max : stream->timing.v_total; 614 refresh_hz = div_u64((uint64_t) stream->timing.pix_clk_100hz * 615 100LL, (v_total * stream->timing.h_total)); 616 mdelay(1000 / refresh_hz); 617 618 drm_writeback_signal_completion(acrtc->wb_conn, 0); 619 dc_stream_fc_disable_writeback(adev->dm.dc, 620 acrtc->dm_irq_params.stream, 0); 621 } 622 } else 623 DRM_ERROR("%s: no amdgpu_crtc wb_conn\n", __func__); 624 acrtc->wb_pending = false; 625 } 626 627 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); 628 629 drm_dbg_vbl(adev_to_drm(adev), 630 "crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id, 631 vrr_active, acrtc->dm_irq_params.active_planes); 632 633 /** 634 * Core vblank handling at start of front-porch is only possible 635 * in non-vrr mode, as only there vblank timestamping will give 636 * valid results while done in front-porch. Otherwise defer it 637 * to dm_vupdate_high_irq after end of front-porch. 638 */ 639 if (!vrr_active) 640 amdgpu_dm_crtc_handle_vblank(acrtc); 641 642 /** 643 * Following stuff must happen at start of vblank, for crc 644 * computation and below-the-range btr support in vrr mode. 645 */ 646 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); 647 648 /* BTR updates need to happen before VUPDATE on Vega and above. */ 649 if (adev->family < AMDGPU_FAMILY_AI) 650 return; 651 652 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 653 654 if (acrtc->dm_irq_params.stream && 655 acrtc->dm_irq_params.vrr_params.supported && 656 acrtc->dm_irq_params.freesync_config.state == 657 VRR_STATE_ACTIVE_VARIABLE) { 658 mod_freesync_handle_v_update(adev->dm.freesync_module, 659 acrtc->dm_irq_params.stream, 660 &acrtc->dm_irq_params.vrr_params); 661 662 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream, 663 &acrtc->dm_irq_params.vrr_params.adjust); 664 } 665 666 /* 667 * If there aren't any active_planes then DCH HUBP may be clock-gated. 668 * In that case, pageflip completion interrupts won't fire and pageflip 669 * completion events won't get delivered. Prevent this by sending 670 * pending pageflip events from here if a flip is still pending. 671 * 672 * If any planes are enabled, use dm_pflip_high_irq() instead, to 673 * avoid race conditions between flip programming and completion, 674 * which could cause too early flip completion events. 675 */ 676 if (adev->family >= AMDGPU_FAMILY_RV && 677 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED && 678 acrtc->dm_irq_params.active_planes == 0) { 679 if (acrtc->event) { 680 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event); 681 acrtc->event = NULL; 682 drm_crtc_vblank_put(&acrtc->base); 683 } 684 acrtc->pflip_status = AMDGPU_FLIP_NONE; 685 } 686 687 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 688 } 689 690 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 691 /** 692 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for 693 * DCN generation ASICs 694 * @interrupt_params: interrupt parameters 695 * 696 * Used to set crc window/read out crc value at vertical line 0 position 697 */ 698 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params) 699 { 700 struct common_irq_params *irq_params = interrupt_params; 701 struct amdgpu_device *adev = irq_params->adev; 702 struct amdgpu_crtc *acrtc; 703 704 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0); 705 706 if (!acrtc) 707 return; 708 709 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base); 710 } 711 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */ 712 713 /** 714 * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command. 715 * @adev: amdgpu_device pointer 716 * @notify: dmub notification structure 717 * 718 * Dmub AUX or SET_CONFIG command completion processing callback 719 * Copies dmub notification to DM which is to be read by AUX command. 720 * issuing thread and also signals the event to wake up the thread. 721 */ 722 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev, 723 struct dmub_notification *notify) 724 { 725 if (adev->dm.dmub_notify) 726 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification)); 727 if (notify->type == DMUB_NOTIFICATION_AUX_REPLY) 728 complete(&adev->dm.dmub_aux_transfer_done); 729 } 730 731 /** 732 * dmub_hpd_callback - DMUB HPD interrupt processing callback. 733 * @adev: amdgpu_device pointer 734 * @notify: dmub notification structure 735 * 736 * Dmub Hpd interrupt processing callback. Gets displayindex through the 737 * ink index and calls helper to do the processing. 738 */ 739 static void dmub_hpd_callback(struct amdgpu_device *adev, 740 struct dmub_notification *notify) 741 { 742 struct amdgpu_dm_connector *aconnector; 743 struct amdgpu_dm_connector *hpd_aconnector = NULL; 744 struct drm_connector *connector; 745 struct drm_connector_list_iter iter; 746 struct dc_link *link; 747 u8 link_index = 0; 748 struct drm_device *dev; 749 750 if (adev == NULL) 751 return; 752 753 if (notify == NULL) { 754 DRM_ERROR("DMUB HPD callback notification was NULL"); 755 return; 756 } 757 758 if (notify->link_index > adev->dm.dc->link_count) { 759 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index); 760 return; 761 } 762 763 link_index = notify->link_index; 764 link = adev->dm.dc->links[link_index]; 765 dev = adev->dm.ddev; 766 767 drm_connector_list_iter_begin(dev, &iter); 768 drm_for_each_connector_iter(connector, &iter) { 769 770 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 771 continue; 772 773 aconnector = to_amdgpu_dm_connector(connector); 774 if (link && aconnector->dc_link == link) { 775 if (notify->type == DMUB_NOTIFICATION_HPD) 776 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index); 777 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) 778 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index); 779 else 780 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n", 781 notify->type, link_index); 782 783 hpd_aconnector = aconnector; 784 break; 785 } 786 } 787 drm_connector_list_iter_end(&iter); 788 789 if (hpd_aconnector) { 790 if (notify->type == DMUB_NOTIFICATION_HPD) 791 handle_hpd_irq_helper(hpd_aconnector); 792 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) 793 handle_hpd_rx_irq(hpd_aconnector); 794 } 795 } 796 797 /** 798 * register_dmub_notify_callback - Sets callback for DMUB notify 799 * @adev: amdgpu_device pointer 800 * @type: Type of dmub notification 801 * @callback: Dmub interrupt callback function 802 * @dmub_int_thread_offload: offload indicator 803 * 804 * API to register a dmub callback handler for a dmub notification 805 * Also sets indicator whether callback processing to be offloaded. 806 * to dmub interrupt handling thread 807 * Return: true if successfully registered, false if there is existing registration 808 */ 809 static bool register_dmub_notify_callback(struct amdgpu_device *adev, 810 enum dmub_notification_type type, 811 dmub_notify_interrupt_callback_t callback, 812 bool dmub_int_thread_offload) 813 { 814 if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) { 815 adev->dm.dmub_callback[type] = callback; 816 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload; 817 } else 818 return false; 819 820 return true; 821 } 822 823 static void dm_handle_hpd_work(struct work_struct *work) 824 { 825 struct dmub_hpd_work *dmub_hpd_wrk; 826 827 dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work); 828 829 if (!dmub_hpd_wrk->dmub_notify) { 830 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL"); 831 return; 832 } 833 834 if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) { 835 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev, 836 dmub_hpd_wrk->dmub_notify); 837 } 838 839 kfree(dmub_hpd_wrk->dmub_notify); 840 kfree(dmub_hpd_wrk); 841 842 } 843 844 #define DMUB_TRACE_MAX_READ 64 845 /** 846 * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt 847 * @interrupt_params: used for determining the Outbox instance 848 * 849 * Handles the Outbox Interrupt 850 * event handler. 851 */ 852 static void dm_dmub_outbox1_low_irq(void *interrupt_params) 853 { 854 struct dmub_notification notify = {0}; 855 struct common_irq_params *irq_params = interrupt_params; 856 struct amdgpu_device *adev = irq_params->adev; 857 struct amdgpu_display_manager *dm = &adev->dm; 858 struct dmcub_trace_buf_entry entry = { 0 }; 859 u32 count = 0; 860 struct dmub_hpd_work *dmub_hpd_wrk; 861 struct dc_link *plink = NULL; 862 863 if (dc_enable_dmub_notifications(adev->dm.dc) && 864 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) { 865 866 do { 867 dc_stat_get_dmub_notification(adev->dm.dc, ¬ify); 868 if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) { 869 DRM_ERROR("DM: notify type %d invalid!", notify.type); 870 continue; 871 } 872 if (!dm->dmub_callback[notify.type]) { 873 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type); 874 continue; 875 } 876 if (dm->dmub_thread_offload[notify.type] == true) { 877 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC); 878 if (!dmub_hpd_wrk) { 879 DRM_ERROR("Failed to allocate dmub_hpd_wrk"); 880 return; 881 } 882 dmub_hpd_wrk->dmub_notify = kmemdup(¬ify, sizeof(struct dmub_notification), 883 GFP_ATOMIC); 884 if (!dmub_hpd_wrk->dmub_notify) { 885 kfree(dmub_hpd_wrk); 886 DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify"); 887 return; 888 } 889 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work); 890 dmub_hpd_wrk->adev = adev; 891 if (notify.type == DMUB_NOTIFICATION_HPD) { 892 plink = adev->dm.dc->links[notify.link_index]; 893 if (plink) { 894 plink->hpd_status = 895 notify.hpd_status == DP_HPD_PLUG; 896 } 897 } 898 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work); 899 } else { 900 dm->dmub_callback[notify.type](adev, ¬ify); 901 } 902 } while (notify.pending_notification); 903 } 904 905 906 do { 907 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) { 908 trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count, 909 entry.param0, entry.param1); 910 911 DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n", 912 entry.trace_code, entry.tick_count, entry.param0, entry.param1); 913 } else 914 break; 915 916 count++; 917 918 } while (count <= DMUB_TRACE_MAX_READ); 919 920 if (count > DMUB_TRACE_MAX_READ) 921 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ"); 922 } 923 924 static int dm_set_clockgating_state(void *handle, 925 enum amd_clockgating_state state) 926 { 927 return 0; 928 } 929 930 static int dm_set_powergating_state(void *handle, 931 enum amd_powergating_state state) 932 { 933 return 0; 934 } 935 936 /* Prototypes of private functions */ 937 static int dm_early_init(void *handle); 938 939 /* Allocate memory for FBC compressed data */ 940 static void amdgpu_dm_fbc_init(struct drm_connector *connector) 941 { 942 struct amdgpu_device *adev = drm_to_adev(connector->dev); 943 struct dm_compressor_info *compressor = &adev->dm.compressor; 944 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); 945 struct drm_display_mode *mode; 946 unsigned long max_size = 0; 947 948 if (adev->dm.dc->fbc_compressor == NULL) 949 return; 950 951 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) 952 return; 953 954 if (compressor->bo_ptr) 955 return; 956 957 958 list_for_each_entry(mode, &connector->modes, head) { 959 if (max_size < mode->htotal * mode->vtotal) 960 max_size = mode->htotal * mode->vtotal; 961 } 962 963 if (max_size) { 964 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, 965 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, 966 &compressor->gpu_addr, &compressor->cpu_addr); 967 968 if (r) 969 DRM_ERROR("DM: Failed to initialize FBC\n"); 970 else { 971 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; 972 DRM_INFO("DM: FBC alloc %lu\n", max_size*4); 973 } 974 975 } 976 977 } 978 979 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, 980 int pipe, bool *enabled, 981 unsigned char *buf, int max_bytes) 982 { 983 struct drm_device *dev = dev_get_drvdata(kdev); 984 struct amdgpu_device *adev = drm_to_adev(dev); 985 struct drm_connector *connector; 986 struct drm_connector_list_iter conn_iter; 987 struct amdgpu_dm_connector *aconnector; 988 int ret = 0; 989 990 *enabled = false; 991 992 mutex_lock(&adev->dm.audio_lock); 993 994 drm_connector_list_iter_begin(dev, &conn_iter); 995 drm_for_each_connector_iter(connector, &conn_iter) { 996 997 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 998 continue; 999 1000 aconnector = to_amdgpu_dm_connector(connector); 1001 if (aconnector->audio_inst != port) 1002 continue; 1003 1004 *enabled = true; 1005 ret = drm_eld_size(connector->eld); 1006 memcpy(buf, connector->eld, min(max_bytes, ret)); 1007 1008 break; 1009 } 1010 drm_connector_list_iter_end(&conn_iter); 1011 1012 mutex_unlock(&adev->dm.audio_lock); 1013 1014 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); 1015 1016 return ret; 1017 } 1018 1019 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { 1020 .get_eld = amdgpu_dm_audio_component_get_eld, 1021 }; 1022 1023 static int amdgpu_dm_audio_component_bind(struct device *kdev, 1024 struct device *hda_kdev, void *data) 1025 { 1026 struct drm_device *dev = dev_get_drvdata(kdev); 1027 struct amdgpu_device *adev = drm_to_adev(dev); 1028 struct drm_audio_component *acomp = data; 1029 1030 acomp->ops = &amdgpu_dm_audio_component_ops; 1031 acomp->dev = kdev; 1032 adev->dm.audio_component = acomp; 1033 1034 return 0; 1035 } 1036 1037 static void amdgpu_dm_audio_component_unbind(struct device *kdev, 1038 struct device *hda_kdev, void *data) 1039 { 1040 struct amdgpu_device *adev = drm_to_adev(dev_get_drvdata(kdev)); 1041 struct drm_audio_component *acomp = data; 1042 1043 acomp->ops = NULL; 1044 acomp->dev = NULL; 1045 adev->dm.audio_component = NULL; 1046 } 1047 1048 static const struct component_ops amdgpu_dm_audio_component_bind_ops = { 1049 .bind = amdgpu_dm_audio_component_bind, 1050 .unbind = amdgpu_dm_audio_component_unbind, 1051 }; 1052 1053 static int amdgpu_dm_audio_init(struct amdgpu_device *adev) 1054 { 1055 int i, ret; 1056 1057 if (!amdgpu_audio) 1058 return 0; 1059 1060 adev->mode_info.audio.enabled = true; 1061 1062 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; 1063 1064 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1065 adev->mode_info.audio.pin[i].channels = -1; 1066 adev->mode_info.audio.pin[i].rate = -1; 1067 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1068 adev->mode_info.audio.pin[i].status_bits = 0; 1069 adev->mode_info.audio.pin[i].category_code = 0; 1070 adev->mode_info.audio.pin[i].connected = false; 1071 adev->mode_info.audio.pin[i].id = 1072 adev->dm.dc->res_pool->audios[i]->inst; 1073 adev->mode_info.audio.pin[i].offset = 0; 1074 } 1075 1076 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops); 1077 if (ret < 0) 1078 return ret; 1079 1080 adev->dm.audio_registered = true; 1081 1082 return 0; 1083 } 1084 1085 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) 1086 { 1087 if (!amdgpu_audio) 1088 return; 1089 1090 if (!adev->mode_info.audio.enabled) 1091 return; 1092 1093 if (adev->dm.audio_registered) { 1094 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); 1095 adev->dm.audio_registered = false; 1096 } 1097 1098 /* TODO: Disable audio? */ 1099 1100 adev->mode_info.audio.enabled = false; 1101 } 1102 1103 static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) 1104 { 1105 struct drm_audio_component *acomp = adev->dm.audio_component; 1106 1107 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { 1108 DRM_DEBUG_KMS("Notify ELD: %d\n", pin); 1109 1110 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 1111 pin, -1); 1112 } 1113 } 1114 1115 static int dm_dmub_hw_init(struct amdgpu_device *adev) 1116 { 1117 const struct dmcub_firmware_header_v1_0 *hdr; 1118 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 1119 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 1120 const struct firmware *dmub_fw = adev->dm.dmub_fw; 1121 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; 1122 struct abm *abm = adev->dm.dc->res_pool->abm; 1123 struct dc_context *ctx = adev->dm.dc->ctx; 1124 struct dmub_srv_hw_params hw_params; 1125 enum dmub_status status; 1126 const unsigned char *fw_inst_const, *fw_bss_data; 1127 u32 i, fw_inst_const_size, fw_bss_data_size; 1128 bool has_hw_support; 1129 1130 if (!dmub_srv) 1131 /* DMUB isn't supported on the ASIC. */ 1132 return 0; 1133 1134 if (!fb_info) { 1135 DRM_ERROR("No framebuffer info for DMUB service.\n"); 1136 return -EINVAL; 1137 } 1138 1139 if (!dmub_fw) { 1140 /* Firmware required for DMUB support. */ 1141 DRM_ERROR("No firmware provided for DMUB.\n"); 1142 return -EINVAL; 1143 } 1144 1145 /* initialize register offsets for ASICs with runtime initialization available */ 1146 if (dmub_srv->hw_funcs.init_reg_offsets) 1147 dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx); 1148 1149 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support); 1150 if (status != DMUB_STATUS_OK) { 1151 DRM_ERROR("Error checking HW support for DMUB: %d\n", status); 1152 return -EINVAL; 1153 } 1154 1155 if (!has_hw_support) { 1156 DRM_INFO("DMUB unsupported on ASIC\n"); 1157 return 0; 1158 } 1159 1160 /* Reset DMCUB if it was previously running - before we overwrite its memory. */ 1161 status = dmub_srv_hw_reset(dmub_srv); 1162 if (status != DMUB_STATUS_OK) 1163 DRM_WARN("Error resetting DMUB HW: %d\n", status); 1164 1165 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data; 1166 1167 fw_inst_const = dmub_fw->data + 1168 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1169 PSP_HEADER_BYTES; 1170 1171 fw_bss_data = dmub_fw->data + 1172 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1173 le32_to_cpu(hdr->inst_const_bytes); 1174 1175 /* Copy firmware and bios info into FB memory. */ 1176 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 1177 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 1178 1179 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 1180 1181 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP, 1182 * amdgpu_ucode_init_single_fw will load dmub firmware 1183 * fw_inst_const part to cw0; otherwise, the firmware back door load 1184 * will be done by dm_dmub_hw_init 1185 */ 1186 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1187 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const, 1188 fw_inst_const_size); 1189 } 1190 1191 if (fw_bss_data_size) 1192 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr, 1193 fw_bss_data, fw_bss_data_size); 1194 1195 /* Copy firmware bios info into FB memory. */ 1196 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios, 1197 adev->bios_size); 1198 1199 /* Reset regions that need to be reset. */ 1200 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0, 1201 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size); 1202 1203 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0, 1204 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size); 1205 1206 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0, 1207 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size); 1208 1209 /* Initialize hardware. */ 1210 memset(&hw_params, 0, sizeof(hw_params)); 1211 hw_params.fb_base = adev->gmc.fb_start; 1212 hw_params.fb_offset = adev->vm_manager.vram_base_offset; 1213 1214 /* backdoor load firmware and trigger dmub running */ 1215 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 1216 hw_params.load_inst_const = true; 1217 1218 if (dmcu) 1219 hw_params.psp_version = dmcu->psp_version; 1220 1221 for (i = 0; i < fb_info->num_fb; ++i) 1222 hw_params.fb[i] = &fb_info->fb[i]; 1223 1224 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1225 case IP_VERSION(3, 1, 3): 1226 case IP_VERSION(3, 1, 4): 1227 case IP_VERSION(3, 5, 0): 1228 case IP_VERSION(3, 5, 1): 1229 case IP_VERSION(4, 0, 1): 1230 hw_params.dpia_supported = true; 1231 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia; 1232 break; 1233 default: 1234 break; 1235 } 1236 1237 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1238 case IP_VERSION(3, 5, 0): 1239 case IP_VERSION(3, 5, 1): 1240 hw_params.ips_sequential_ono = adev->external_rev_id > 0x10; 1241 break; 1242 default: 1243 break; 1244 } 1245 1246 status = dmub_srv_hw_init(dmub_srv, &hw_params); 1247 if (status != DMUB_STATUS_OK) { 1248 DRM_ERROR("Error initializing DMUB HW: %d\n", status); 1249 return -EINVAL; 1250 } 1251 1252 /* Wait for firmware load to finish. */ 1253 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); 1254 if (status != DMUB_STATUS_OK) 1255 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); 1256 1257 /* Init DMCU and ABM if available. */ 1258 if (dmcu && abm) { 1259 dmcu->funcs->dmcu_init(dmcu); 1260 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 1261 } 1262 1263 if (!adev->dm.dc->ctx->dmub_srv) 1264 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv); 1265 if (!adev->dm.dc->ctx->dmub_srv) { 1266 DRM_ERROR("Couldn't allocate DC DMUB server!\n"); 1267 return -ENOMEM; 1268 } 1269 1270 DRM_INFO("DMUB hardware initialized: version=0x%08X\n", 1271 adev->dm.dmcub_fw_version); 1272 1273 return 0; 1274 } 1275 1276 static void dm_dmub_hw_resume(struct amdgpu_device *adev) 1277 { 1278 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 1279 enum dmub_status status; 1280 bool init; 1281 1282 if (!dmub_srv) { 1283 /* DMUB isn't supported on the ASIC. */ 1284 return; 1285 } 1286 1287 status = dmub_srv_is_hw_init(dmub_srv, &init); 1288 if (status != DMUB_STATUS_OK) 1289 DRM_WARN("DMUB hardware init check failed: %d\n", status); 1290 1291 if (status == DMUB_STATUS_OK && init) { 1292 /* Wait for firmware load to finish. */ 1293 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); 1294 if (status != DMUB_STATUS_OK) 1295 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); 1296 } else { 1297 /* Perform the full hardware initialization. */ 1298 dm_dmub_hw_init(adev); 1299 } 1300 } 1301 1302 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) 1303 { 1304 u64 pt_base; 1305 u32 logical_addr_low; 1306 u32 logical_addr_high; 1307 u32 agp_base, agp_bot, agp_top; 1308 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; 1309 1310 memset(pa_config, 0, sizeof(*pa_config)); 1311 1312 agp_base = 0; 1313 agp_bot = adev->gmc.agp_start >> 24; 1314 agp_top = adev->gmc.agp_end >> 24; 1315 1316 /* AGP aperture is disabled */ 1317 if (agp_bot > agp_top) { 1318 logical_addr_low = adev->gmc.fb_start >> 18; 1319 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 1320 AMD_APU_IS_RENOIR | 1321 AMD_APU_IS_GREEN_SARDINE)) 1322 /* 1323 * Raven2 has a HW issue that it is unable to use the vram which 1324 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 1325 * workaround that increase system aperture high address (add 1) 1326 * to get rid of the VM fault and hardware hang. 1327 */ 1328 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1; 1329 else 1330 logical_addr_high = adev->gmc.fb_end >> 18; 1331 } else { 1332 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; 1333 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 1334 AMD_APU_IS_RENOIR | 1335 AMD_APU_IS_GREEN_SARDINE)) 1336 /* 1337 * Raven2 has a HW issue that it is unable to use the vram which 1338 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 1339 * workaround that increase system aperture high address (add 1) 1340 * to get rid of the VM fault and hardware hang. 1341 */ 1342 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); 1343 else 1344 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; 1345 } 1346 1347 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 1348 1349 page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >> 1350 AMDGPU_GPU_PAGE_SHIFT); 1351 page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >> 1352 AMDGPU_GPU_PAGE_SHIFT); 1353 page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >> 1354 AMDGPU_GPU_PAGE_SHIFT); 1355 page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >> 1356 AMDGPU_GPU_PAGE_SHIFT); 1357 page_table_base.high_part = upper_32_bits(pt_base); 1358 page_table_base.low_part = lower_32_bits(pt_base); 1359 1360 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; 1361 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; 1362 1363 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24; 1364 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; 1365 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; 1366 1367 pa_config->system_aperture.fb_base = adev->gmc.fb_start; 1368 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset; 1369 pa_config->system_aperture.fb_top = adev->gmc.fb_end; 1370 1371 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; 1372 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; 1373 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; 1374 1375 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support; 1376 1377 } 1378 1379 static void force_connector_state( 1380 struct amdgpu_dm_connector *aconnector, 1381 enum drm_connector_force force_state) 1382 { 1383 struct drm_connector *connector = &aconnector->base; 1384 1385 mutex_lock(&connector->dev->mode_config.mutex); 1386 aconnector->base.force = force_state; 1387 mutex_unlock(&connector->dev->mode_config.mutex); 1388 1389 mutex_lock(&aconnector->hpd_lock); 1390 drm_kms_helper_connector_hotplug_event(connector); 1391 mutex_unlock(&aconnector->hpd_lock); 1392 } 1393 1394 static void dm_handle_hpd_rx_offload_work(struct work_struct *work) 1395 { 1396 struct hpd_rx_irq_offload_work *offload_work; 1397 struct amdgpu_dm_connector *aconnector; 1398 struct dc_link *dc_link; 1399 struct amdgpu_device *adev; 1400 enum dc_connection_type new_connection_type = dc_connection_none; 1401 unsigned long flags; 1402 union test_response test_response; 1403 1404 memset(&test_response, 0, sizeof(test_response)); 1405 1406 offload_work = container_of(work, struct hpd_rx_irq_offload_work, work); 1407 aconnector = offload_work->offload_wq->aconnector; 1408 1409 if (!aconnector) { 1410 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work"); 1411 goto skip; 1412 } 1413 1414 adev = drm_to_adev(aconnector->base.dev); 1415 dc_link = aconnector->dc_link; 1416 1417 mutex_lock(&aconnector->hpd_lock); 1418 if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) 1419 DRM_ERROR("KMS: Failed to detect connector\n"); 1420 mutex_unlock(&aconnector->hpd_lock); 1421 1422 if (new_connection_type == dc_connection_none) 1423 goto skip; 1424 1425 if (amdgpu_in_reset(adev)) 1426 goto skip; 1427 1428 if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || 1429 offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { 1430 dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT); 1431 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); 1432 offload_work->offload_wq->is_handling_mst_msg_rdy_event = false; 1433 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); 1434 goto skip; 1435 } 1436 1437 mutex_lock(&adev->dm.dc_lock); 1438 if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) { 1439 dc_link_dp_handle_automated_test(dc_link); 1440 1441 if (aconnector->timing_changed) { 1442 /* force connector disconnect and reconnect */ 1443 force_connector_state(aconnector, DRM_FORCE_OFF); 1444 msleep(100); 1445 force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED); 1446 } 1447 1448 test_response.bits.ACK = 1; 1449 1450 core_link_write_dpcd( 1451 dc_link, 1452 DP_TEST_RESPONSE, 1453 &test_response.raw, 1454 sizeof(test_response)); 1455 } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) && 1456 dc_link_check_link_loss_status(dc_link, &offload_work->data) && 1457 dc_link_dp_allow_hpd_rx_irq(dc_link)) { 1458 /* offload_work->data is from handle_hpd_rx_irq-> 1459 * schedule_hpd_rx_offload_work.this is defer handle 1460 * for hpd short pulse. upon here, link status may be 1461 * changed, need get latest link status from dpcd 1462 * registers. if link status is good, skip run link 1463 * training again. 1464 */ 1465 union hpd_irq_data irq_data; 1466 1467 memset(&irq_data, 0, sizeof(irq_data)); 1468 1469 /* before dc_link_dp_handle_link_loss, allow new link lost handle 1470 * request be added to work queue if link lost at end of dc_link_ 1471 * dp_handle_link_loss 1472 */ 1473 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); 1474 offload_work->offload_wq->is_handling_link_loss = false; 1475 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); 1476 1477 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) && 1478 dc_link_check_link_loss_status(dc_link, &irq_data)) 1479 dc_link_dp_handle_link_loss(dc_link); 1480 } 1481 mutex_unlock(&adev->dm.dc_lock); 1482 1483 skip: 1484 kfree(offload_work); 1485 1486 } 1487 1488 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc) 1489 { 1490 int max_caps = dc->caps.max_links; 1491 int i = 0; 1492 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL; 1493 1494 hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL); 1495 1496 if (!hpd_rx_offload_wq) 1497 return NULL; 1498 1499 1500 for (i = 0; i < max_caps; i++) { 1501 hpd_rx_offload_wq[i].wq = 1502 create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq"); 1503 1504 if (hpd_rx_offload_wq[i].wq == NULL) { 1505 DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!"); 1506 goto out_err; 1507 } 1508 1509 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock); 1510 } 1511 1512 return hpd_rx_offload_wq; 1513 1514 out_err: 1515 for (i = 0; i < max_caps; i++) { 1516 if (hpd_rx_offload_wq[i].wq) 1517 destroy_workqueue(hpd_rx_offload_wq[i].wq); 1518 } 1519 kfree(hpd_rx_offload_wq); 1520 return NULL; 1521 } 1522 1523 struct amdgpu_stutter_quirk { 1524 u16 chip_vendor; 1525 u16 chip_device; 1526 u16 subsys_vendor; 1527 u16 subsys_device; 1528 u8 revision; 1529 }; 1530 1531 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = { 1532 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */ 1533 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, 1534 { 0, 0, 0, 0, 0 }, 1535 }; 1536 1537 static bool dm_should_disable_stutter(struct pci_dev *pdev) 1538 { 1539 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list; 1540 1541 while (p && p->chip_device != 0) { 1542 if (pdev->vendor == p->chip_vendor && 1543 pdev->device == p->chip_device && 1544 pdev->subsystem_vendor == p->subsys_vendor && 1545 pdev->subsystem_device == p->subsys_device && 1546 pdev->revision == p->revision) { 1547 return true; 1548 } 1549 ++p; 1550 } 1551 return false; 1552 } 1553 1554 static const struct dmi_system_id hpd_disconnect_quirk_table[] = { 1555 { 1556 .matches = { 1557 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1558 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"), 1559 }, 1560 }, 1561 { 1562 .matches = { 1563 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1564 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"), 1565 }, 1566 }, 1567 { 1568 .matches = { 1569 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1570 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"), 1571 }, 1572 }, 1573 { 1574 .matches = { 1575 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1576 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"), 1577 }, 1578 }, 1579 { 1580 .matches = { 1581 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1582 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"), 1583 }, 1584 }, 1585 { 1586 .matches = { 1587 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1588 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"), 1589 }, 1590 }, 1591 { 1592 .matches = { 1593 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1594 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"), 1595 }, 1596 }, 1597 { 1598 .matches = { 1599 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1600 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"), 1601 }, 1602 }, 1603 { 1604 .matches = { 1605 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1606 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"), 1607 }, 1608 }, 1609 {} 1610 /* TODO: refactor this from a fixed table to a dynamic option */ 1611 }; 1612 1613 static void retrieve_dmi_info(struct amdgpu_display_manager *dm) 1614 { 1615 const struct dmi_system_id *dmi_id; 1616 1617 dm->aux_hpd_discon_quirk = false; 1618 1619 dmi_id = dmi_first_match(hpd_disconnect_quirk_table); 1620 if (dmi_id) { 1621 dm->aux_hpd_discon_quirk = true; 1622 DRM_INFO("aux_hpd_discon_quirk attached\n"); 1623 } 1624 } 1625 1626 static int amdgpu_dm_init(struct amdgpu_device *adev) 1627 { 1628 struct dc_init_data init_data; 1629 struct dc_callback_init init_params; 1630 int r; 1631 1632 adev->dm.ddev = adev_to_drm(adev); 1633 adev->dm.adev = adev; 1634 1635 /* Zero all the fields */ 1636 memset(&init_data, 0, sizeof(init_data)); 1637 memset(&init_params, 0, sizeof(init_params)); 1638 1639 mutex_init(&adev->dm.dpia_aux_lock); 1640 mutex_init(&adev->dm.dc_lock); 1641 mutex_init(&adev->dm.audio_lock); 1642 1643 if (amdgpu_dm_irq_init(adev)) { 1644 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); 1645 goto error; 1646 } 1647 1648 init_data.asic_id.chip_family = adev->family; 1649 1650 init_data.asic_id.pci_revision_id = adev->pdev->revision; 1651 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 1652 init_data.asic_id.chip_id = adev->pdev->device; 1653 1654 init_data.asic_id.vram_width = adev->gmc.vram_width; 1655 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 1656 init_data.asic_id.atombios_base_address = 1657 adev->mode_info.atom_context->bios; 1658 1659 init_data.driver = adev; 1660 1661 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 1662 1663 if (!adev->dm.cgs_device) { 1664 DRM_ERROR("amdgpu: failed to create cgs device.\n"); 1665 goto error; 1666 } 1667 1668 init_data.cgs_device = adev->dm.cgs_device; 1669 1670 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 1671 1672 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1673 case IP_VERSION(2, 1, 0): 1674 switch (adev->dm.dmcub_fw_version) { 1675 case 0: /* development */ 1676 case 0x1: /* linux-firmware.git hash 6d9f399 */ 1677 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */ 1678 init_data.flags.disable_dmcu = false; 1679 break; 1680 default: 1681 init_data.flags.disable_dmcu = true; 1682 } 1683 break; 1684 case IP_VERSION(2, 0, 3): 1685 init_data.flags.disable_dmcu = true; 1686 break; 1687 default: 1688 break; 1689 } 1690 1691 /* APU support S/G display by default except: 1692 * ASICs before Carrizo, 1693 * RAVEN1 (Users reported stability issue) 1694 */ 1695 1696 if (adev->asic_type < CHIP_CARRIZO) { 1697 init_data.flags.gpu_vm_support = false; 1698 } else if (adev->asic_type == CHIP_RAVEN) { 1699 if (adev->apu_flags & AMD_APU_IS_RAVEN) 1700 init_data.flags.gpu_vm_support = false; 1701 else 1702 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0); 1703 } else { 1704 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU); 1705 } 1706 1707 adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support; 1708 1709 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 1710 init_data.flags.fbc_support = true; 1711 1712 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) 1713 init_data.flags.multi_mon_pp_mclk_switch = true; 1714 1715 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) 1716 init_data.flags.disable_fractional_pwm = true; 1717 1718 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING) 1719 init_data.flags.edp_no_power_sequencing = true; 1720 1721 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A) 1722 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true; 1723 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0) 1724 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true; 1725 1726 init_data.flags.seamless_boot_edp_requested = false; 1727 1728 if (amdgpu_device_seamless_boot_supported(adev)) { 1729 init_data.flags.seamless_boot_edp_requested = true; 1730 init_data.flags.allow_seamless_boot_optimization = true; 1731 DRM_INFO("Seamless boot condition check passed\n"); 1732 } 1733 1734 init_data.flags.enable_mipi_converter_optimization = true; 1735 1736 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; 1737 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; 1738 init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0]; 1739 1740 if (amdgpu_dc_debug_mask & DC_DISABLE_IPS) 1741 init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL; 1742 else 1743 init_data.flags.disable_ips = DMUB_IPS_ENABLE; 1744 1745 init_data.flags.disable_ips_in_vpb = 0; 1746 1747 /* Enable DWB for tested platforms only */ 1748 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) 1749 init_data.num_virtual_links = 1; 1750 1751 INIT_LIST_HEAD(&adev->dm.da_list); 1752 1753 retrieve_dmi_info(&adev->dm); 1754 1755 /* Display Core create. */ 1756 adev->dm.dc = dc_create(&init_data); 1757 1758 if (adev->dm.dc) { 1759 DRM_INFO("Display Core v%s initialized on %s\n", DC_VER, 1760 dce_version_to_string(adev->dm.dc->ctx->dce_version)); 1761 } else { 1762 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); 1763 goto error; 1764 } 1765 1766 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { 1767 adev->dm.dc->debug.force_single_disp_pipe_split = false; 1768 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; 1769 } 1770 1771 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 1772 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 1773 if (dm_should_disable_stutter(adev->pdev)) 1774 adev->dm.dc->debug.disable_stutter = true; 1775 1776 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) 1777 adev->dm.dc->debug.disable_stutter = true; 1778 1779 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 1780 adev->dm.dc->debug.disable_dsc = true; 1781 1782 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) 1783 adev->dm.dc->debug.disable_clock_gate = true; 1784 1785 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH) 1786 adev->dm.dc->debug.force_subvp_mclk_switch = true; 1787 1788 if (amdgpu_dc_debug_mask & DC_ENABLE_DML2) { 1789 adev->dm.dc->debug.using_dml2 = true; 1790 adev->dm.dc->debug.using_dml21 = true; 1791 } 1792 1793 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm; 1794 1795 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ 1796 adev->dm.dc->debug.ignore_cable_id = true; 1797 1798 if (adev->dm.dc->caps.dp_hdmi21_pcon_support) 1799 DRM_INFO("DP-HDMI FRL PCON supported\n"); 1800 1801 r = dm_dmub_hw_init(adev); 1802 if (r) { 1803 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 1804 goto error; 1805 } 1806 1807 dc_hardware_init(adev->dm.dc); 1808 1809 adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc); 1810 if (!adev->dm.hpd_rx_offload_wq) { 1811 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n"); 1812 goto error; 1813 } 1814 1815 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) { 1816 struct dc_phy_addr_space_config pa_config; 1817 1818 mmhub_read_system_context(adev, &pa_config); 1819 1820 // Call the DC init_memory func 1821 dc_setup_system_context(adev->dm.dc, &pa_config); 1822 } 1823 1824 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 1825 if (!adev->dm.freesync_module) { 1826 DRM_ERROR( 1827 "amdgpu: failed to initialize freesync_module.\n"); 1828 } else 1829 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", 1830 adev->dm.freesync_module); 1831 1832 amdgpu_dm_init_color_mod(); 1833 1834 if (adev->dm.dc->caps.max_links > 0) { 1835 adev->dm.vblank_control_workqueue = 1836 create_singlethread_workqueue("dm_vblank_control_workqueue"); 1837 if (!adev->dm.vblank_control_workqueue) 1838 DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n"); 1839 } 1840 1841 if (adev->dm.dc->caps.ips_support && adev->dm.dc->config.disable_ips == DMUB_IPS_ENABLE) 1842 adev->dm.idle_workqueue = idle_create_workqueue(adev); 1843 1844 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) { 1845 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); 1846 1847 if (!adev->dm.hdcp_workqueue) 1848 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n"); 1849 else 1850 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue); 1851 1852 dc_init_callbacks(adev->dm.dc, &init_params); 1853 } 1854 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 1855 init_completion(&adev->dm.dmub_aux_transfer_done); 1856 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL); 1857 if (!adev->dm.dmub_notify) { 1858 DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify"); 1859 goto error; 1860 } 1861 1862 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq"); 1863 if (!adev->dm.delayed_hpd_wq) { 1864 DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n"); 1865 goto error; 1866 } 1867 1868 amdgpu_dm_outbox_init(adev); 1869 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY, 1870 dmub_aux_setconfig_callback, false)) { 1871 DRM_ERROR("amdgpu: fail to register dmub aux callback"); 1872 goto error; 1873 } 1874 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive. 1875 * It is expected that DMUB will resend any pending notifications at this point. Note 1876 * that hpd and hpd_irq handler registration are deferred to register_hpd_handlers() to 1877 * align legacy interface initialization sequence. Connection status will be proactivly 1878 * detected once in the amdgpu_dm_initialize_drm_device. 1879 */ 1880 dc_enable_dmub_outbox(adev->dm.dc); 1881 1882 /* DPIA trace goes to dmesg logs only if outbox is enabled */ 1883 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE) 1884 dc_dmub_srv_enable_dpia_trace(adev->dm.dc); 1885 } 1886 1887 if (amdgpu_dm_initialize_drm_device(adev)) { 1888 DRM_ERROR( 1889 "amdgpu: failed to initialize sw for display support.\n"); 1890 goto error; 1891 } 1892 1893 /* create fake encoders for MST */ 1894 dm_dp_create_fake_mst_encoders(adev); 1895 1896 /* TODO: Add_display_info? */ 1897 1898 /* TODO use dynamic cursor width */ 1899 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 1900 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 1901 1902 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { 1903 DRM_ERROR( 1904 "amdgpu: failed to initialize sw for display support.\n"); 1905 goto error; 1906 } 1907 1908 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 1909 adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev); 1910 if (!adev->dm.secure_display_ctxs) 1911 DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n"); 1912 #endif 1913 1914 DRM_DEBUG_DRIVER("KMS initialized.\n"); 1915 1916 return 0; 1917 error: 1918 amdgpu_dm_fini(adev); 1919 1920 return -EINVAL; 1921 } 1922 1923 static int amdgpu_dm_early_fini(void *handle) 1924 { 1925 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1926 1927 amdgpu_dm_audio_fini(adev); 1928 1929 return 0; 1930 } 1931 1932 static void amdgpu_dm_fini(struct amdgpu_device *adev) 1933 { 1934 int i; 1935 1936 if (adev->dm.vblank_control_workqueue) { 1937 destroy_workqueue(adev->dm.vblank_control_workqueue); 1938 adev->dm.vblank_control_workqueue = NULL; 1939 } 1940 1941 if (adev->dm.idle_workqueue) { 1942 if (adev->dm.idle_workqueue->running) { 1943 adev->dm.idle_workqueue->enable = false; 1944 flush_work(&adev->dm.idle_workqueue->work); 1945 } 1946 1947 kfree(adev->dm.idle_workqueue); 1948 adev->dm.idle_workqueue = NULL; 1949 } 1950 1951 amdgpu_dm_destroy_drm_device(&adev->dm); 1952 1953 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 1954 if (adev->dm.secure_display_ctxs) { 1955 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1956 if (adev->dm.secure_display_ctxs[i].crtc) { 1957 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work); 1958 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work); 1959 } 1960 } 1961 kfree(adev->dm.secure_display_ctxs); 1962 adev->dm.secure_display_ctxs = NULL; 1963 } 1964 #endif 1965 if (adev->dm.hdcp_workqueue) { 1966 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); 1967 adev->dm.hdcp_workqueue = NULL; 1968 } 1969 1970 if (adev->dm.dc) { 1971 dc_deinit_callbacks(adev->dm.dc); 1972 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); 1973 if (dc_enable_dmub_notifications(adev->dm.dc)) { 1974 kfree(adev->dm.dmub_notify); 1975 adev->dm.dmub_notify = NULL; 1976 destroy_workqueue(adev->dm.delayed_hpd_wq); 1977 adev->dm.delayed_hpd_wq = NULL; 1978 } 1979 } 1980 1981 if (adev->dm.dmub_bo) 1982 amdgpu_bo_free_kernel(&adev->dm.dmub_bo, 1983 &adev->dm.dmub_bo_gpu_addr, 1984 &adev->dm.dmub_bo_cpu_addr); 1985 1986 if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) { 1987 for (i = 0; i < adev->dm.dc->caps.max_links; i++) { 1988 if (adev->dm.hpd_rx_offload_wq[i].wq) { 1989 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq); 1990 adev->dm.hpd_rx_offload_wq[i].wq = NULL; 1991 } 1992 } 1993 1994 kfree(adev->dm.hpd_rx_offload_wq); 1995 adev->dm.hpd_rx_offload_wq = NULL; 1996 } 1997 1998 /* DC Destroy TODO: Replace destroy DAL */ 1999 if (adev->dm.dc) 2000 dc_destroy(&adev->dm.dc); 2001 /* 2002 * TODO: pageflip, vlank interrupt 2003 * 2004 * amdgpu_dm_irq_fini(adev); 2005 */ 2006 2007 if (adev->dm.cgs_device) { 2008 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 2009 adev->dm.cgs_device = NULL; 2010 } 2011 if (adev->dm.freesync_module) { 2012 mod_freesync_destroy(adev->dm.freesync_module); 2013 adev->dm.freesync_module = NULL; 2014 } 2015 2016 mutex_destroy(&adev->dm.audio_lock); 2017 mutex_destroy(&adev->dm.dc_lock); 2018 mutex_destroy(&adev->dm.dpia_aux_lock); 2019 } 2020 2021 static int load_dmcu_fw(struct amdgpu_device *adev) 2022 { 2023 const char *fw_name_dmcu = NULL; 2024 int r; 2025 const struct dmcu_firmware_header_v1_0 *hdr; 2026 2027 switch (adev->asic_type) { 2028 #if defined(CONFIG_DRM_AMD_DC_SI) 2029 case CHIP_TAHITI: 2030 case CHIP_PITCAIRN: 2031 case CHIP_VERDE: 2032 case CHIP_OLAND: 2033 #endif 2034 case CHIP_BONAIRE: 2035 case CHIP_HAWAII: 2036 case CHIP_KAVERI: 2037 case CHIP_KABINI: 2038 case CHIP_MULLINS: 2039 case CHIP_TONGA: 2040 case CHIP_FIJI: 2041 case CHIP_CARRIZO: 2042 case CHIP_STONEY: 2043 case CHIP_POLARIS11: 2044 case CHIP_POLARIS10: 2045 case CHIP_POLARIS12: 2046 case CHIP_VEGAM: 2047 case CHIP_VEGA10: 2048 case CHIP_VEGA12: 2049 case CHIP_VEGA20: 2050 return 0; 2051 case CHIP_NAVI12: 2052 fw_name_dmcu = FIRMWARE_NAVI12_DMCU; 2053 break; 2054 case CHIP_RAVEN: 2055 if (ASICREV_IS_PICASSO(adev->external_rev_id)) 2056 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 2057 else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) 2058 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 2059 else 2060 return 0; 2061 break; 2062 default: 2063 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2064 case IP_VERSION(2, 0, 2): 2065 case IP_VERSION(2, 0, 3): 2066 case IP_VERSION(2, 0, 0): 2067 case IP_VERSION(2, 1, 0): 2068 case IP_VERSION(3, 0, 0): 2069 case IP_VERSION(3, 0, 2): 2070 case IP_VERSION(3, 0, 3): 2071 case IP_VERSION(3, 0, 1): 2072 case IP_VERSION(3, 1, 2): 2073 case IP_VERSION(3, 1, 3): 2074 case IP_VERSION(3, 1, 4): 2075 case IP_VERSION(3, 1, 5): 2076 case IP_VERSION(3, 1, 6): 2077 case IP_VERSION(3, 2, 0): 2078 case IP_VERSION(3, 2, 1): 2079 case IP_VERSION(3, 5, 0): 2080 case IP_VERSION(3, 5, 1): 2081 case IP_VERSION(4, 0, 1): 2082 return 0; 2083 default: 2084 break; 2085 } 2086 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 2087 return -EINVAL; 2088 } 2089 2090 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2091 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); 2092 return 0; 2093 } 2094 2095 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu); 2096 if (r == -ENODEV) { 2097 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 2098 DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); 2099 adev->dm.fw_dmcu = NULL; 2100 return 0; 2101 } 2102 if (r) { 2103 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", 2104 fw_name_dmcu); 2105 amdgpu_ucode_release(&adev->dm.fw_dmcu); 2106 return r; 2107 } 2108 2109 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 2110 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 2111 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 2112 adev->firmware.fw_size += 2113 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 2114 2115 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 2116 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 2117 adev->firmware.fw_size += 2118 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 2119 2120 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 2121 2122 DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); 2123 2124 return 0; 2125 } 2126 2127 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address) 2128 { 2129 struct amdgpu_device *adev = ctx; 2130 2131 return dm_read_reg(adev->dm.dc->ctx, address); 2132 } 2133 2134 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address, 2135 uint32_t value) 2136 { 2137 struct amdgpu_device *adev = ctx; 2138 2139 return dm_write_reg(adev->dm.dc->ctx, address, value); 2140 } 2141 2142 static int dm_dmub_sw_init(struct amdgpu_device *adev) 2143 { 2144 struct dmub_srv_create_params create_params; 2145 struct dmub_srv_region_params region_params; 2146 struct dmub_srv_region_info region_info; 2147 struct dmub_srv_memory_params memory_params; 2148 struct dmub_srv_fb_info *fb_info; 2149 struct dmub_srv *dmub_srv; 2150 const struct dmcub_firmware_header_v1_0 *hdr; 2151 enum dmub_asic dmub_asic; 2152 enum dmub_status status; 2153 static enum dmub_window_memory_type window_memory_type[DMUB_WINDOW_TOTAL] = { 2154 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_0_INST_CONST 2155 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_1_STACK 2156 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_2_BSS_DATA 2157 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_3_VBIOS 2158 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_4_MAILBOX 2159 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_5_TRACEBUFF 2160 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_6_FW_STATE 2161 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_7_SCRATCH_MEM 2162 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_SHARED_STATE 2163 }; 2164 int r; 2165 2166 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2167 case IP_VERSION(2, 1, 0): 2168 dmub_asic = DMUB_ASIC_DCN21; 2169 break; 2170 case IP_VERSION(3, 0, 0): 2171 dmub_asic = DMUB_ASIC_DCN30; 2172 break; 2173 case IP_VERSION(3, 0, 1): 2174 dmub_asic = DMUB_ASIC_DCN301; 2175 break; 2176 case IP_VERSION(3, 0, 2): 2177 dmub_asic = DMUB_ASIC_DCN302; 2178 break; 2179 case IP_VERSION(3, 0, 3): 2180 dmub_asic = DMUB_ASIC_DCN303; 2181 break; 2182 case IP_VERSION(3, 1, 2): 2183 case IP_VERSION(3, 1, 3): 2184 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31; 2185 break; 2186 case IP_VERSION(3, 1, 4): 2187 dmub_asic = DMUB_ASIC_DCN314; 2188 break; 2189 case IP_VERSION(3, 1, 5): 2190 dmub_asic = DMUB_ASIC_DCN315; 2191 break; 2192 case IP_VERSION(3, 1, 6): 2193 dmub_asic = DMUB_ASIC_DCN316; 2194 break; 2195 case IP_VERSION(3, 2, 0): 2196 dmub_asic = DMUB_ASIC_DCN32; 2197 break; 2198 case IP_VERSION(3, 2, 1): 2199 dmub_asic = DMUB_ASIC_DCN321; 2200 break; 2201 case IP_VERSION(3, 5, 0): 2202 case IP_VERSION(3, 5, 1): 2203 dmub_asic = DMUB_ASIC_DCN35; 2204 break; 2205 case IP_VERSION(4, 0, 1): 2206 dmub_asic = DMUB_ASIC_DCN401; 2207 break; 2208 2209 default: 2210 /* ASIC doesn't support DMUB. */ 2211 return 0; 2212 } 2213 2214 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data; 2215 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version); 2216 2217 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2218 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id = 2219 AMDGPU_UCODE_ID_DMCUB; 2220 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = 2221 adev->dm.dmub_fw; 2222 adev->firmware.fw_size += 2223 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE); 2224 2225 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n", 2226 adev->dm.dmcub_fw_version); 2227 } 2228 2229 2230 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL); 2231 dmub_srv = adev->dm.dmub_srv; 2232 2233 if (!dmub_srv) { 2234 DRM_ERROR("Failed to allocate DMUB service!\n"); 2235 return -ENOMEM; 2236 } 2237 2238 memset(&create_params, 0, sizeof(create_params)); 2239 create_params.user_ctx = adev; 2240 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read; 2241 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write; 2242 create_params.asic = dmub_asic; 2243 2244 /* Create the DMUB service. */ 2245 status = dmub_srv_create(dmub_srv, &create_params); 2246 if (status != DMUB_STATUS_OK) { 2247 DRM_ERROR("Error creating DMUB service: %d\n", status); 2248 return -EINVAL; 2249 } 2250 2251 /* Calculate the size of all the regions for the DMUB service. */ 2252 memset(®ion_params, 0, sizeof(region_params)); 2253 2254 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 2255 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 2256 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 2257 region_params.vbios_size = adev->bios_size; 2258 region_params.fw_bss_data = region_params.bss_data_size ? 2259 adev->dm.dmub_fw->data + 2260 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 2261 le32_to_cpu(hdr->inst_const_bytes) : NULL; 2262 region_params.fw_inst_const = 2263 adev->dm.dmub_fw->data + 2264 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 2265 PSP_HEADER_BYTES; 2266 region_params.window_memory_type = window_memory_type; 2267 2268 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params, 2269 ®ion_info); 2270 2271 if (status != DMUB_STATUS_OK) { 2272 DRM_ERROR("Error calculating DMUB region info: %d\n", status); 2273 return -EINVAL; 2274 } 2275 2276 /* 2277 * Allocate a framebuffer based on the total size of all the regions. 2278 * TODO: Move this into GART. 2279 */ 2280 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE, 2281 AMDGPU_GEM_DOMAIN_VRAM | 2282 AMDGPU_GEM_DOMAIN_GTT, 2283 &adev->dm.dmub_bo, 2284 &adev->dm.dmub_bo_gpu_addr, 2285 &adev->dm.dmub_bo_cpu_addr); 2286 if (r) 2287 return r; 2288 2289 /* Rebase the regions on the framebuffer address. */ 2290 memset(&memory_params, 0, sizeof(memory_params)); 2291 memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr; 2292 memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr; 2293 memory_params.region_info = ®ion_info; 2294 memory_params.window_memory_type = window_memory_type; 2295 2296 adev->dm.dmub_fb_info = 2297 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL); 2298 fb_info = adev->dm.dmub_fb_info; 2299 2300 if (!fb_info) { 2301 DRM_ERROR( 2302 "Failed to allocate framebuffer info for DMUB service!\n"); 2303 return -ENOMEM; 2304 } 2305 2306 status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info); 2307 if (status != DMUB_STATUS_OK) { 2308 DRM_ERROR("Error calculating DMUB FB info: %d\n", status); 2309 return -EINVAL; 2310 } 2311 2312 return 0; 2313 } 2314 2315 static int dm_sw_init(void *handle) 2316 { 2317 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2318 int r; 2319 2320 r = dm_dmub_sw_init(adev); 2321 if (r) 2322 return r; 2323 2324 return load_dmcu_fw(adev); 2325 } 2326 2327 static int dm_sw_fini(void *handle) 2328 { 2329 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2330 2331 kfree(adev->dm.dmub_fb_info); 2332 adev->dm.dmub_fb_info = NULL; 2333 2334 if (adev->dm.dmub_srv) { 2335 dmub_srv_destroy(adev->dm.dmub_srv); 2336 kfree(adev->dm.dmub_srv); 2337 adev->dm.dmub_srv = NULL; 2338 } 2339 2340 amdgpu_ucode_release(&adev->dm.dmub_fw); 2341 amdgpu_ucode_release(&adev->dm.fw_dmcu); 2342 2343 return 0; 2344 } 2345 2346 static int detect_mst_link_for_all_connectors(struct drm_device *dev) 2347 { 2348 struct amdgpu_dm_connector *aconnector; 2349 struct drm_connector *connector; 2350 struct drm_connector_list_iter iter; 2351 int ret = 0; 2352 2353 drm_connector_list_iter_begin(dev, &iter); 2354 drm_for_each_connector_iter(connector, &iter) { 2355 2356 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 2357 continue; 2358 2359 aconnector = to_amdgpu_dm_connector(connector); 2360 if (aconnector->dc_link->type == dc_connection_mst_branch && 2361 aconnector->mst_mgr.aux) { 2362 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", 2363 aconnector, 2364 aconnector->base.base.id); 2365 2366 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 2367 if (ret < 0) { 2368 DRM_ERROR("DM_MST: Failed to start MST\n"); 2369 aconnector->dc_link->type = 2370 dc_connection_single; 2371 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, 2372 aconnector->dc_link); 2373 break; 2374 } 2375 } 2376 } 2377 drm_connector_list_iter_end(&iter); 2378 2379 return ret; 2380 } 2381 2382 static int dm_late_init(void *handle) 2383 { 2384 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2385 2386 struct dmcu_iram_parameters params; 2387 unsigned int linear_lut[16]; 2388 int i; 2389 struct dmcu *dmcu = NULL; 2390 2391 dmcu = adev->dm.dc->res_pool->dmcu; 2392 2393 for (i = 0; i < 16; i++) 2394 linear_lut[i] = 0xFFFF * i / 15; 2395 2396 params.set = 0; 2397 params.backlight_ramping_override = false; 2398 params.backlight_ramping_start = 0xCCCC; 2399 params.backlight_ramping_reduction = 0xCCCCCCCC; 2400 params.backlight_lut_array_size = 16; 2401 params.backlight_lut_array = linear_lut; 2402 2403 /* Min backlight level after ABM reduction, Don't allow below 1% 2404 * 0xFFFF x 0.01 = 0x28F 2405 */ 2406 params.min_abm_backlight = 0x28F; 2407 /* In the case where abm is implemented on dmcub, 2408 * dmcu object will be null. 2409 * ABM 2.4 and up are implemented on dmcub. 2410 */ 2411 if (dmcu) { 2412 if (!dmcu_load_iram(dmcu, params)) 2413 return -EINVAL; 2414 } else if (adev->dm.dc->ctx->dmub_srv) { 2415 struct dc_link *edp_links[MAX_NUM_EDP]; 2416 int edp_num; 2417 2418 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num); 2419 for (i = 0; i < edp_num; i++) { 2420 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) 2421 return -EINVAL; 2422 } 2423 } 2424 2425 return detect_mst_link_for_all_connectors(adev_to_drm(adev)); 2426 } 2427 2428 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) 2429 { 2430 int ret; 2431 u8 guid[16]; 2432 u64 tmp64; 2433 2434 mutex_lock(&mgr->lock); 2435 if (!mgr->mst_primary) 2436 goto out_fail; 2437 2438 if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) { 2439 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 2440 goto out_fail; 2441 } 2442 2443 ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 2444 DP_MST_EN | 2445 DP_UPSTREAM_IS_SRC); 2446 if (ret < 0) { 2447 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n"); 2448 goto out_fail; 2449 } 2450 2451 /* Some hubs forget their guids after they resume */ 2452 ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16); 2453 if (ret != 16) { 2454 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 2455 goto out_fail; 2456 } 2457 2458 if (memchr_inv(guid, 0, 16) == NULL) { 2459 tmp64 = get_jiffies_64(); 2460 memcpy(&guid[0], &tmp64, sizeof(u64)); 2461 memcpy(&guid[8], &tmp64, sizeof(u64)); 2462 2463 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16); 2464 2465 if (ret != 16) { 2466 drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n"); 2467 goto out_fail; 2468 } 2469 } 2470 2471 memcpy(mgr->mst_primary->guid, guid, 16); 2472 2473 out_fail: 2474 mutex_unlock(&mgr->lock); 2475 } 2476 2477 static void s3_handle_mst(struct drm_device *dev, bool suspend) 2478 { 2479 struct amdgpu_dm_connector *aconnector; 2480 struct drm_connector *connector; 2481 struct drm_connector_list_iter iter; 2482 struct drm_dp_mst_topology_mgr *mgr; 2483 2484 drm_connector_list_iter_begin(dev, &iter); 2485 drm_for_each_connector_iter(connector, &iter) { 2486 2487 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 2488 continue; 2489 2490 aconnector = to_amdgpu_dm_connector(connector); 2491 if (aconnector->dc_link->type != dc_connection_mst_branch || 2492 aconnector->mst_root) 2493 continue; 2494 2495 mgr = &aconnector->mst_mgr; 2496 2497 if (suspend) { 2498 drm_dp_mst_topology_mgr_suspend(mgr); 2499 } else { 2500 /* if extended timeout is supported in hardware, 2501 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer 2502 * CTS 4.2.1.1 regression introduced by CTS specs requirement update. 2503 */ 2504 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); 2505 if (!dp_is_lttpr_present(aconnector->dc_link)) 2506 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); 2507 2508 /* TODO: move resume_mst_branch_status() into drm mst resume again 2509 * once topology probing work is pulled out from mst resume into mst 2510 * resume 2nd step. mst resume 2nd step should be called after old 2511 * state getting restored (i.e. drm_atomic_helper_resume()). 2512 */ 2513 resume_mst_branch_status(mgr); 2514 } 2515 } 2516 drm_connector_list_iter_end(&iter); 2517 } 2518 2519 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) 2520 { 2521 int ret = 0; 2522 2523 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends 2524 * on window driver dc implementation. 2525 * For Navi1x, clock settings of dcn watermarks are fixed. the settings 2526 * should be passed to smu during boot up and resume from s3. 2527 * boot up: dc calculate dcn watermark clock settings within dc_create, 2528 * dcn20_resource_construct 2529 * then call pplib functions below to pass the settings to smu: 2530 * smu_set_watermarks_for_clock_ranges 2531 * smu_set_watermarks_table 2532 * navi10_set_watermarks_table 2533 * smu_write_watermarks_table 2534 * 2535 * For Renoir, clock settings of dcn watermark are also fixed values. 2536 * dc has implemented different flow for window driver: 2537 * dc_hardware_init / dc_set_power_state 2538 * dcn10_init_hw 2539 * notify_wm_ranges 2540 * set_wm_ranges 2541 * -- Linux 2542 * smu_set_watermarks_for_clock_ranges 2543 * renoir_set_watermarks_table 2544 * smu_write_watermarks_table 2545 * 2546 * For Linux, 2547 * dc_hardware_init -> amdgpu_dm_init 2548 * dc_set_power_state --> dm_resume 2549 * 2550 * therefore, this function apply to navi10/12/14 but not Renoir 2551 * * 2552 */ 2553 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2554 case IP_VERSION(2, 0, 2): 2555 case IP_VERSION(2, 0, 0): 2556 break; 2557 default: 2558 return 0; 2559 } 2560 2561 ret = amdgpu_dpm_write_watermarks_table(adev); 2562 if (ret) { 2563 DRM_ERROR("Failed to update WMTABLE!\n"); 2564 return ret; 2565 } 2566 2567 return 0; 2568 } 2569 2570 /** 2571 * dm_hw_init() - Initialize DC device 2572 * @handle: The base driver device containing the amdgpu_dm device. 2573 * 2574 * Initialize the &struct amdgpu_display_manager device. This involves calling 2575 * the initializers of each DM component, then populating the struct with them. 2576 * 2577 * Although the function implies hardware initialization, both hardware and 2578 * software are initialized here. Splitting them out to their relevant init 2579 * hooks is a future TODO item. 2580 * 2581 * Some notable things that are initialized here: 2582 * 2583 * - Display Core, both software and hardware 2584 * - DC modules that we need (freesync and color management) 2585 * - DRM software states 2586 * - Interrupt sources and handlers 2587 * - Vblank support 2588 * - Debug FS entries, if enabled 2589 */ 2590 static int dm_hw_init(void *handle) 2591 { 2592 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2593 /* Create DAL display manager */ 2594 amdgpu_dm_init(adev); 2595 amdgpu_dm_hpd_init(adev); 2596 2597 return 0; 2598 } 2599 2600 /** 2601 * dm_hw_fini() - Teardown DC device 2602 * @handle: The base driver device containing the amdgpu_dm device. 2603 * 2604 * Teardown components within &struct amdgpu_display_manager that require 2605 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 2606 * were loaded. Also flush IRQ workqueues and disable them. 2607 */ 2608 static int dm_hw_fini(void *handle) 2609 { 2610 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2611 2612 amdgpu_dm_hpd_fini(adev); 2613 2614 amdgpu_dm_irq_fini(adev); 2615 amdgpu_dm_fini(adev); 2616 return 0; 2617 } 2618 2619 2620 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, 2621 struct dc_state *state, bool enable) 2622 { 2623 enum dc_irq_source irq_source; 2624 struct amdgpu_crtc *acrtc; 2625 int rc = -EBUSY; 2626 int i = 0; 2627 2628 for (i = 0; i < state->stream_count; i++) { 2629 acrtc = get_crtc_by_otg_inst( 2630 adev, state->stream_status[i].primary_otg_inst); 2631 2632 if (acrtc && state->stream_status[i].plane_count != 0) { 2633 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; 2634 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 2635 if (rc) 2636 DRM_WARN("Failed to %s pflip interrupts\n", 2637 enable ? "enable" : "disable"); 2638 2639 if (enable) { 2640 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state))) 2641 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true); 2642 } else 2643 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false); 2644 2645 if (rc) 2646 DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis"); 2647 2648 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 2649 /* During gpu-reset we disable and then enable vblank irq, so 2650 * don't use amdgpu_irq_get/put() to avoid refcount change. 2651 */ 2652 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable)) 2653 DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis"); 2654 } 2655 } 2656 2657 } 2658 2659 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) 2660 { 2661 struct dc_state *context = NULL; 2662 enum dc_status res = DC_ERROR_UNEXPECTED; 2663 int i; 2664 struct dc_stream_state *del_streams[MAX_PIPES]; 2665 int del_streams_count = 0; 2666 struct dc_commit_streams_params params = {}; 2667 2668 memset(del_streams, 0, sizeof(del_streams)); 2669 2670 context = dc_state_create_current_copy(dc); 2671 if (context == NULL) 2672 goto context_alloc_fail; 2673 2674 /* First remove from context all streams */ 2675 for (i = 0; i < context->stream_count; i++) { 2676 struct dc_stream_state *stream = context->streams[i]; 2677 2678 del_streams[del_streams_count++] = stream; 2679 } 2680 2681 /* Remove all planes for removed streams and then remove the streams */ 2682 for (i = 0; i < del_streams_count; i++) { 2683 if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) { 2684 res = DC_FAIL_DETACH_SURFACES; 2685 goto fail; 2686 } 2687 2688 res = dc_state_remove_stream(dc, context, del_streams[i]); 2689 if (res != DC_OK) 2690 goto fail; 2691 } 2692 2693 params.streams = context->streams; 2694 params.stream_count = context->stream_count; 2695 res = dc_commit_streams(dc, ¶ms); 2696 2697 fail: 2698 dc_state_release(context); 2699 2700 context_alloc_fail: 2701 return res; 2702 } 2703 2704 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm) 2705 { 2706 int i; 2707 2708 if (dm->hpd_rx_offload_wq) { 2709 for (i = 0; i < dm->dc->caps.max_links; i++) 2710 flush_workqueue(dm->hpd_rx_offload_wq[i].wq); 2711 } 2712 } 2713 2714 static int dm_suspend(void *handle) 2715 { 2716 struct amdgpu_device *adev = handle; 2717 struct amdgpu_display_manager *dm = &adev->dm; 2718 int ret = 0; 2719 2720 if (amdgpu_in_reset(adev)) { 2721 mutex_lock(&dm->dc_lock); 2722 2723 dc_allow_idle_optimizations(adev->dm.dc, false); 2724 2725 dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state); 2726 2727 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); 2728 2729 amdgpu_dm_commit_zero_streams(dm->dc); 2730 2731 amdgpu_dm_irq_suspend(adev); 2732 2733 hpd_rx_irq_work_suspend(dm); 2734 2735 return ret; 2736 } 2737 2738 WARN_ON(adev->dm.cached_state); 2739 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); 2740 if (IS_ERR(adev->dm.cached_state)) 2741 return PTR_ERR(adev->dm.cached_state); 2742 2743 s3_handle_mst(adev_to_drm(adev), true); 2744 2745 amdgpu_dm_irq_suspend(adev); 2746 2747 hpd_rx_irq_work_suspend(dm); 2748 2749 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 2750 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3); 2751 2752 return 0; 2753 } 2754 2755 struct drm_connector * 2756 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 2757 struct drm_crtc *crtc) 2758 { 2759 u32 i; 2760 struct drm_connector_state *new_con_state; 2761 struct drm_connector *connector; 2762 struct drm_crtc *crtc_from_state; 2763 2764 for_each_new_connector_in_state(state, connector, new_con_state, i) { 2765 crtc_from_state = new_con_state->crtc; 2766 2767 if (crtc_from_state == crtc) 2768 return connector; 2769 } 2770 2771 return NULL; 2772 } 2773 2774 static void emulated_link_detect(struct dc_link *link) 2775 { 2776 struct dc_sink_init_data sink_init_data = { 0 }; 2777 struct display_sink_capability sink_caps = { 0 }; 2778 enum dc_edid_status edid_status; 2779 struct dc_context *dc_ctx = link->ctx; 2780 struct drm_device *dev = adev_to_drm(dc_ctx->driver_context); 2781 struct dc_sink *sink = NULL; 2782 struct dc_sink *prev_sink = NULL; 2783 2784 link->type = dc_connection_none; 2785 prev_sink = link->local_sink; 2786 2787 if (prev_sink) 2788 dc_sink_release(prev_sink); 2789 2790 switch (link->connector_signal) { 2791 case SIGNAL_TYPE_HDMI_TYPE_A: { 2792 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2793 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 2794 break; 2795 } 2796 2797 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 2798 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2799 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 2800 break; 2801 } 2802 2803 case SIGNAL_TYPE_DVI_DUAL_LINK: { 2804 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2805 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 2806 break; 2807 } 2808 2809 case SIGNAL_TYPE_LVDS: { 2810 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2811 sink_caps.signal = SIGNAL_TYPE_LVDS; 2812 break; 2813 } 2814 2815 case SIGNAL_TYPE_EDP: { 2816 sink_caps.transaction_type = 2817 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 2818 sink_caps.signal = SIGNAL_TYPE_EDP; 2819 break; 2820 } 2821 2822 case SIGNAL_TYPE_DISPLAY_PORT: { 2823 sink_caps.transaction_type = 2824 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 2825 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 2826 break; 2827 } 2828 2829 default: 2830 drm_err(dev, "Invalid connector type! signal:%d\n", 2831 link->connector_signal); 2832 return; 2833 } 2834 2835 sink_init_data.link = link; 2836 sink_init_data.sink_signal = sink_caps.signal; 2837 2838 sink = dc_sink_create(&sink_init_data); 2839 if (!sink) { 2840 drm_err(dev, "Failed to create sink!\n"); 2841 return; 2842 } 2843 2844 /* dc_sink_create returns a new reference */ 2845 link->local_sink = sink; 2846 2847 edid_status = dm_helpers_read_local_edid( 2848 link->ctx, 2849 link, 2850 sink); 2851 2852 if (edid_status != EDID_OK) 2853 drm_err(dev, "Failed to read EDID\n"); 2854 2855 } 2856 2857 static void dm_gpureset_commit_state(struct dc_state *dc_state, 2858 struct amdgpu_display_manager *dm) 2859 { 2860 struct { 2861 struct dc_surface_update surface_updates[MAX_SURFACES]; 2862 struct dc_plane_info plane_infos[MAX_SURFACES]; 2863 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 2864 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 2865 struct dc_stream_update stream_update; 2866 } *bundle; 2867 int k, m; 2868 2869 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 2870 2871 if (!bundle) { 2872 drm_err(dm->ddev, "Failed to allocate update bundle\n"); 2873 goto cleanup; 2874 } 2875 2876 for (k = 0; k < dc_state->stream_count; k++) { 2877 bundle->stream_update.stream = dc_state->streams[k]; 2878 2879 for (m = 0; m < dc_state->stream_status->plane_count; m++) { 2880 bundle->surface_updates[m].surface = 2881 dc_state->stream_status->plane_states[m]; 2882 bundle->surface_updates[m].surface->force_full_update = 2883 true; 2884 } 2885 2886 update_planes_and_stream_adapter(dm->dc, 2887 UPDATE_TYPE_FULL, 2888 dc_state->stream_status->plane_count, 2889 dc_state->streams[k], 2890 &bundle->stream_update, 2891 bundle->surface_updates); 2892 } 2893 2894 cleanup: 2895 kfree(bundle); 2896 } 2897 2898 static int dm_resume(void *handle) 2899 { 2900 struct amdgpu_device *adev = handle; 2901 struct drm_device *ddev = adev_to_drm(adev); 2902 struct amdgpu_display_manager *dm = &adev->dm; 2903 struct amdgpu_dm_connector *aconnector; 2904 struct drm_connector *connector; 2905 struct drm_connector_list_iter iter; 2906 struct drm_crtc *crtc; 2907 struct drm_crtc_state *new_crtc_state; 2908 struct dm_crtc_state *dm_new_crtc_state; 2909 struct drm_plane *plane; 2910 struct drm_plane_state *new_plane_state; 2911 struct dm_plane_state *dm_new_plane_state; 2912 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 2913 enum dc_connection_type new_connection_type = dc_connection_none; 2914 struct dc_state *dc_state; 2915 int i, r, j, ret; 2916 bool need_hotplug = false; 2917 struct dc_commit_streams_params commit_params = {}; 2918 2919 if (dm->dc->caps.ips_support) { 2920 dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false); 2921 } 2922 2923 if (amdgpu_in_reset(adev)) { 2924 dc_state = dm->cached_dc_state; 2925 2926 /* 2927 * The dc->current_state is backed up into dm->cached_dc_state 2928 * before we commit 0 streams. 2929 * 2930 * DC will clear link encoder assignments on the real state 2931 * but the changes won't propagate over to the copy we made 2932 * before the 0 streams commit. 2933 * 2934 * DC expects that link encoder assignments are *not* valid 2935 * when committing a state, so as a workaround we can copy 2936 * off of the current state. 2937 * 2938 * We lose the previous assignments, but we had already 2939 * commit 0 streams anyway. 2940 */ 2941 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state); 2942 2943 r = dm_dmub_hw_init(adev); 2944 if (r) 2945 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 2946 2947 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 2948 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2949 2950 dc_resume(dm->dc); 2951 2952 amdgpu_dm_irq_resume_early(adev); 2953 2954 for (i = 0; i < dc_state->stream_count; i++) { 2955 dc_state->streams[i]->mode_changed = true; 2956 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { 2957 dc_state->stream_status[i].plane_states[j]->update_flags.raw 2958 = 0xffffffff; 2959 } 2960 } 2961 2962 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 2963 amdgpu_dm_outbox_init(adev); 2964 dc_enable_dmub_outbox(adev->dm.dc); 2965 } 2966 2967 commit_params.streams = dc_state->streams; 2968 commit_params.stream_count = dc_state->stream_count; 2969 WARN_ON(!dc_commit_streams(dm->dc, &commit_params)); 2970 2971 dm_gpureset_commit_state(dm->cached_dc_state, dm); 2972 2973 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); 2974 2975 dc_state_release(dm->cached_dc_state); 2976 dm->cached_dc_state = NULL; 2977 2978 amdgpu_dm_irq_resume_late(adev); 2979 2980 mutex_unlock(&dm->dc_lock); 2981 2982 return 0; 2983 } 2984 /* Recreate dc_state - DC invalidates it when setting power state to S3. */ 2985 dc_state_release(dm_state->context); 2986 dm_state->context = dc_state_create(dm->dc, NULL); 2987 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ 2988 2989 /* Before powering on DC we need to re-initialize DMUB. */ 2990 dm_dmub_hw_resume(adev); 2991 2992 /* Re-enable outbox interrupts for DPIA. */ 2993 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 2994 amdgpu_dm_outbox_init(adev); 2995 dc_enable_dmub_outbox(adev->dm.dc); 2996 } 2997 2998 /* power on hardware */ 2999 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 3000 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 3001 3002 /* program HPD filter */ 3003 dc_resume(dm->dc); 3004 3005 /* 3006 * early enable HPD Rx IRQ, should be done before set mode as short 3007 * pulse interrupts are used for MST 3008 */ 3009 amdgpu_dm_irq_resume_early(adev); 3010 3011 /* On resume we need to rewrite the MSTM control bits to enable MST*/ 3012 s3_handle_mst(ddev, false); 3013 3014 /* Do detection*/ 3015 drm_connector_list_iter_begin(ddev, &iter); 3016 drm_for_each_connector_iter(connector, &iter) { 3017 3018 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 3019 continue; 3020 3021 aconnector = to_amdgpu_dm_connector(connector); 3022 3023 if (!aconnector->dc_link) 3024 continue; 3025 3026 /* 3027 * this is the case when traversing through already created end sink 3028 * MST connectors, should be skipped 3029 */ 3030 if (aconnector && aconnector->mst_root) 3031 continue; 3032 3033 mutex_lock(&aconnector->hpd_lock); 3034 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) 3035 DRM_ERROR("KMS: Failed to detect connector\n"); 3036 3037 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3038 emulated_link_detect(aconnector->dc_link); 3039 } else { 3040 mutex_lock(&dm->dc_lock); 3041 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3042 mutex_unlock(&dm->dc_lock); 3043 } 3044 3045 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 3046 aconnector->fake_enable = false; 3047 3048 if (aconnector->dc_sink) 3049 dc_sink_release(aconnector->dc_sink); 3050 aconnector->dc_sink = NULL; 3051 amdgpu_dm_update_connector_after_detect(aconnector); 3052 mutex_unlock(&aconnector->hpd_lock); 3053 } 3054 drm_connector_list_iter_end(&iter); 3055 3056 /* Force mode set in atomic commit */ 3057 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) 3058 new_crtc_state->active_changed = true; 3059 3060 /* 3061 * atomic_check is expected to create the dc states. We need to release 3062 * them here, since they were duplicated as part of the suspend 3063 * procedure. 3064 */ 3065 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 3066 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 3067 if (dm_new_crtc_state->stream) { 3068 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 3069 dc_stream_release(dm_new_crtc_state->stream); 3070 dm_new_crtc_state->stream = NULL; 3071 } 3072 dm_new_crtc_state->base.color_mgmt_changed = true; 3073 } 3074 3075 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 3076 dm_new_plane_state = to_dm_plane_state(new_plane_state); 3077 if (dm_new_plane_state->dc_state) { 3078 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 3079 dc_plane_state_release(dm_new_plane_state->dc_state); 3080 dm_new_plane_state->dc_state = NULL; 3081 } 3082 } 3083 3084 drm_atomic_helper_resume(ddev, dm->cached_state); 3085 3086 dm->cached_state = NULL; 3087 3088 /* Do mst topology probing after resuming cached state*/ 3089 drm_connector_list_iter_begin(ddev, &iter); 3090 drm_for_each_connector_iter(connector, &iter) { 3091 3092 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 3093 continue; 3094 3095 aconnector = to_amdgpu_dm_connector(connector); 3096 if (aconnector->dc_link->type != dc_connection_mst_branch || 3097 aconnector->mst_root) 3098 continue; 3099 3100 ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true); 3101 3102 if (ret < 0) { 3103 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, 3104 aconnector->dc_link); 3105 need_hotplug = true; 3106 } 3107 } 3108 drm_connector_list_iter_end(&iter); 3109 3110 if (need_hotplug) 3111 drm_kms_helper_hotplug_event(ddev); 3112 3113 amdgpu_dm_irq_resume_late(adev); 3114 3115 amdgpu_dm_smu_write_watermarks_table(adev); 3116 3117 return 0; 3118 } 3119 3120 /** 3121 * DOC: DM Lifecycle 3122 * 3123 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 3124 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 3125 * the base driver's device list to be initialized and torn down accordingly. 3126 * 3127 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 3128 */ 3129 3130 static const struct amd_ip_funcs amdgpu_dm_funcs = { 3131 .name = "dm", 3132 .early_init = dm_early_init, 3133 .late_init = dm_late_init, 3134 .sw_init = dm_sw_init, 3135 .sw_fini = dm_sw_fini, 3136 .early_fini = amdgpu_dm_early_fini, 3137 .hw_init = dm_hw_init, 3138 .hw_fini = dm_hw_fini, 3139 .suspend = dm_suspend, 3140 .resume = dm_resume, 3141 .is_idle = dm_is_idle, 3142 .wait_for_idle = dm_wait_for_idle, 3143 .check_soft_reset = dm_check_soft_reset, 3144 .soft_reset = dm_soft_reset, 3145 .set_clockgating_state = dm_set_clockgating_state, 3146 .set_powergating_state = dm_set_powergating_state, 3147 .dump_ip_state = NULL, 3148 .print_ip_state = NULL, 3149 }; 3150 3151 const struct amdgpu_ip_block_version dm_ip_block = { 3152 .type = AMD_IP_BLOCK_TYPE_DCE, 3153 .major = 1, 3154 .minor = 0, 3155 .rev = 0, 3156 .funcs = &amdgpu_dm_funcs, 3157 }; 3158 3159 3160 /** 3161 * DOC: atomic 3162 * 3163 * *WIP* 3164 */ 3165 3166 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 3167 .fb_create = amdgpu_display_user_framebuffer_create, 3168 .get_format_info = amdgpu_dm_plane_get_format_info, 3169 .atomic_check = amdgpu_dm_atomic_check, 3170 .atomic_commit = drm_atomic_helper_commit, 3171 }; 3172 3173 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 3174 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, 3175 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, 3176 }; 3177 3178 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) 3179 { 3180 struct amdgpu_dm_backlight_caps *caps; 3181 struct drm_connector *conn_base; 3182 struct amdgpu_device *adev; 3183 struct drm_luminance_range_info *luminance_range; 3184 3185 if (aconnector->bl_idx == -1 || 3186 aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP) 3187 return; 3188 3189 conn_base = &aconnector->base; 3190 adev = drm_to_adev(conn_base->dev); 3191 3192 caps = &adev->dm.backlight_caps[aconnector->bl_idx]; 3193 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; 3194 caps->aux_support = false; 3195 3196 if (caps->ext_caps->bits.oled == 1 3197 /* 3198 * || 3199 * caps->ext_caps->bits.sdr_aux_backlight_control == 1 || 3200 * caps->ext_caps->bits.hdr_aux_backlight_control == 1 3201 */) 3202 caps->aux_support = true; 3203 3204 if (amdgpu_backlight == 0) 3205 caps->aux_support = false; 3206 else if (amdgpu_backlight == 1) 3207 caps->aux_support = true; 3208 3209 luminance_range = &conn_base->display_info.luminance_range; 3210 3211 if (luminance_range->max_luminance) { 3212 caps->aux_min_input_signal = luminance_range->min_luminance; 3213 caps->aux_max_input_signal = luminance_range->max_luminance; 3214 } else { 3215 caps->aux_min_input_signal = 0; 3216 caps->aux_max_input_signal = 512; 3217 } 3218 } 3219 3220 void amdgpu_dm_update_connector_after_detect( 3221 struct amdgpu_dm_connector *aconnector) 3222 { 3223 struct drm_connector *connector = &aconnector->base; 3224 struct drm_device *dev = connector->dev; 3225 struct dc_sink *sink; 3226 3227 /* MST handled by drm_mst framework */ 3228 if (aconnector->mst_mgr.mst_state == true) 3229 return; 3230 3231 sink = aconnector->dc_link->local_sink; 3232 if (sink) 3233 dc_sink_retain(sink); 3234 3235 /* 3236 * Edid mgmt connector gets first update only in mode_valid hook and then 3237 * the connector sink is set to either fake or physical sink depends on link status. 3238 * Skip if already done during boot. 3239 */ 3240 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED 3241 && aconnector->dc_em_sink) { 3242 3243 /* 3244 * For S3 resume with headless use eml_sink to fake stream 3245 * because on resume connector->sink is set to NULL 3246 */ 3247 mutex_lock(&dev->mode_config.mutex); 3248 3249 if (sink) { 3250 if (aconnector->dc_sink) { 3251 amdgpu_dm_update_freesync_caps(connector, NULL); 3252 /* 3253 * retain and release below are used to 3254 * bump up refcount for sink because the link doesn't point 3255 * to it anymore after disconnect, so on next crtc to connector 3256 * reshuffle by UMD we will get into unwanted dc_sink release 3257 */ 3258 dc_sink_release(aconnector->dc_sink); 3259 } 3260 aconnector->dc_sink = sink; 3261 dc_sink_retain(aconnector->dc_sink); 3262 amdgpu_dm_update_freesync_caps(connector, 3263 aconnector->edid); 3264 } else { 3265 amdgpu_dm_update_freesync_caps(connector, NULL); 3266 if (!aconnector->dc_sink) { 3267 aconnector->dc_sink = aconnector->dc_em_sink; 3268 dc_sink_retain(aconnector->dc_sink); 3269 } 3270 } 3271 3272 mutex_unlock(&dev->mode_config.mutex); 3273 3274 if (sink) 3275 dc_sink_release(sink); 3276 return; 3277 } 3278 3279 /* 3280 * TODO: temporary guard to look for proper fix 3281 * if this sink is MST sink, we should not do anything 3282 */ 3283 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 3284 dc_sink_release(sink); 3285 return; 3286 } 3287 3288 if (aconnector->dc_sink == sink) { 3289 /* 3290 * We got a DP short pulse (Link Loss, DP CTS, etc...). 3291 * Do nothing!! 3292 */ 3293 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", 3294 aconnector->connector_id); 3295 if (sink) 3296 dc_sink_release(sink); 3297 return; 3298 } 3299 3300 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 3301 aconnector->connector_id, aconnector->dc_sink, sink); 3302 3303 mutex_lock(&dev->mode_config.mutex); 3304 3305 /* 3306 * 1. Update status of the drm connector 3307 * 2. Send an event and let userspace tell us what to do 3308 */ 3309 if (sink) { 3310 /* 3311 * TODO: check if we still need the S3 mode update workaround. 3312 * If yes, put it here. 3313 */ 3314 if (aconnector->dc_sink) { 3315 amdgpu_dm_update_freesync_caps(connector, NULL); 3316 dc_sink_release(aconnector->dc_sink); 3317 } 3318 3319 aconnector->dc_sink = sink; 3320 dc_sink_retain(aconnector->dc_sink); 3321 if (sink->dc_edid.length == 0) { 3322 aconnector->edid = NULL; 3323 if (aconnector->dc_link->aux_mode) { 3324 drm_dp_cec_unset_edid( 3325 &aconnector->dm_dp_aux.aux); 3326 } 3327 } else { 3328 aconnector->edid = 3329 (struct edid *)sink->dc_edid.raw_edid; 3330 3331 if (aconnector->dc_link->aux_mode) 3332 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, 3333 aconnector->edid); 3334 } 3335 3336 if (!aconnector->timing_requested) { 3337 aconnector->timing_requested = 3338 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL); 3339 if (!aconnector->timing_requested) 3340 drm_err(dev, 3341 "failed to create aconnector->requested_timing\n"); 3342 } 3343 3344 drm_connector_update_edid_property(connector, aconnector->edid); 3345 amdgpu_dm_update_freesync_caps(connector, aconnector->edid); 3346 update_connector_ext_caps(aconnector); 3347 } else { 3348 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 3349 amdgpu_dm_update_freesync_caps(connector, NULL); 3350 drm_connector_update_edid_property(connector, NULL); 3351 aconnector->num_modes = 0; 3352 dc_sink_release(aconnector->dc_sink); 3353 aconnector->dc_sink = NULL; 3354 aconnector->edid = NULL; 3355 kfree(aconnector->timing_requested); 3356 aconnector->timing_requested = NULL; 3357 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ 3358 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 3359 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3360 } 3361 3362 mutex_unlock(&dev->mode_config.mutex); 3363 3364 update_subconnector_property(aconnector); 3365 3366 if (sink) 3367 dc_sink_release(sink); 3368 } 3369 3370 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) 3371 { 3372 struct drm_connector *connector = &aconnector->base; 3373 struct drm_device *dev = connector->dev; 3374 enum dc_connection_type new_connection_type = dc_connection_none; 3375 struct amdgpu_device *adev = drm_to_adev(dev); 3376 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 3377 bool ret = false; 3378 3379 if (adev->dm.disable_hpd_irq) 3380 return; 3381 3382 /* 3383 * In case of failure or MST no need to update connector status or notify the OS 3384 * since (for MST case) MST does this in its own context. 3385 */ 3386 mutex_lock(&aconnector->hpd_lock); 3387 3388 if (adev->dm.hdcp_workqueue) { 3389 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 3390 dm_con_state->update_hdcp = true; 3391 } 3392 if (aconnector->fake_enable) 3393 aconnector->fake_enable = false; 3394 3395 aconnector->timing_changed = false; 3396 3397 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) 3398 DRM_ERROR("KMS: Failed to detect connector\n"); 3399 3400 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3401 emulated_link_detect(aconnector->dc_link); 3402 3403 drm_modeset_lock_all(dev); 3404 dm_restore_drm_connector_state(dev, connector); 3405 drm_modeset_unlock_all(dev); 3406 3407 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 3408 drm_kms_helper_connector_hotplug_event(connector); 3409 } else { 3410 mutex_lock(&adev->dm.dc_lock); 3411 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3412 mutex_unlock(&adev->dm.dc_lock); 3413 if (ret) { 3414 amdgpu_dm_update_connector_after_detect(aconnector); 3415 3416 drm_modeset_lock_all(dev); 3417 dm_restore_drm_connector_state(dev, connector); 3418 drm_modeset_unlock_all(dev); 3419 3420 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 3421 drm_kms_helper_connector_hotplug_event(connector); 3422 } 3423 } 3424 mutex_unlock(&aconnector->hpd_lock); 3425 3426 } 3427 3428 static void handle_hpd_irq(void *param) 3429 { 3430 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 3431 3432 handle_hpd_irq_helper(aconnector); 3433 3434 } 3435 3436 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq, 3437 union hpd_irq_data hpd_irq_data) 3438 { 3439 struct hpd_rx_irq_offload_work *offload_work = 3440 kzalloc(sizeof(*offload_work), GFP_KERNEL); 3441 3442 if (!offload_work) { 3443 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n"); 3444 return; 3445 } 3446 3447 INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work); 3448 offload_work->data = hpd_irq_data; 3449 offload_work->offload_wq = offload_wq; 3450 3451 queue_work(offload_wq->wq, &offload_work->work); 3452 DRM_DEBUG_KMS("queue work to handle hpd_rx offload work"); 3453 } 3454 3455 static void handle_hpd_rx_irq(void *param) 3456 { 3457 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 3458 struct drm_connector *connector = &aconnector->base; 3459 struct drm_device *dev = connector->dev; 3460 struct dc_link *dc_link = aconnector->dc_link; 3461 bool is_mst_root_connector = aconnector->mst_mgr.mst_state; 3462 bool result = false; 3463 enum dc_connection_type new_connection_type = dc_connection_none; 3464 struct amdgpu_device *adev = drm_to_adev(dev); 3465 union hpd_irq_data hpd_irq_data; 3466 bool link_loss = false; 3467 bool has_left_work = false; 3468 int idx = dc_link->link_index; 3469 struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx]; 3470 3471 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data)); 3472 3473 if (adev->dm.disable_hpd_irq) 3474 return; 3475 3476 /* 3477 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio 3478 * conflict, after implement i2c helper, this mutex should be 3479 * retired. 3480 */ 3481 mutex_lock(&aconnector->hpd_lock); 3482 3483 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, 3484 &link_loss, true, &has_left_work); 3485 3486 if (!has_left_work) 3487 goto out; 3488 3489 if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) { 3490 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3491 goto out; 3492 } 3493 3494 if (dc_link_dp_allow_hpd_rx_irq(dc_link)) { 3495 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || 3496 hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { 3497 bool skip = false; 3498 3499 /* 3500 * DOWN_REP_MSG_RDY is also handled by polling method 3501 * mgr->cbs->poll_hpd_irq() 3502 */ 3503 spin_lock(&offload_wq->offload_lock); 3504 skip = offload_wq->is_handling_mst_msg_rdy_event; 3505 3506 if (!skip) 3507 offload_wq->is_handling_mst_msg_rdy_event = true; 3508 3509 spin_unlock(&offload_wq->offload_lock); 3510 3511 if (!skip) 3512 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3513 3514 goto out; 3515 } 3516 3517 if (link_loss) { 3518 bool skip = false; 3519 3520 spin_lock(&offload_wq->offload_lock); 3521 skip = offload_wq->is_handling_link_loss; 3522 3523 if (!skip) 3524 offload_wq->is_handling_link_loss = true; 3525 3526 spin_unlock(&offload_wq->offload_lock); 3527 3528 if (!skip) 3529 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3530 3531 goto out; 3532 } 3533 } 3534 3535 out: 3536 if (result && !is_mst_root_connector) { 3537 /* Downstream Port status changed. */ 3538 if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) 3539 DRM_ERROR("KMS: Failed to detect connector\n"); 3540 3541 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3542 emulated_link_detect(dc_link); 3543 3544 if (aconnector->fake_enable) 3545 aconnector->fake_enable = false; 3546 3547 amdgpu_dm_update_connector_after_detect(aconnector); 3548 3549 3550 drm_modeset_lock_all(dev); 3551 dm_restore_drm_connector_state(dev, connector); 3552 drm_modeset_unlock_all(dev); 3553 3554 drm_kms_helper_connector_hotplug_event(connector); 3555 } else { 3556 bool ret = false; 3557 3558 mutex_lock(&adev->dm.dc_lock); 3559 ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX); 3560 mutex_unlock(&adev->dm.dc_lock); 3561 3562 if (ret) { 3563 if (aconnector->fake_enable) 3564 aconnector->fake_enable = false; 3565 3566 amdgpu_dm_update_connector_after_detect(aconnector); 3567 3568 drm_modeset_lock_all(dev); 3569 dm_restore_drm_connector_state(dev, connector); 3570 drm_modeset_unlock_all(dev); 3571 3572 drm_kms_helper_connector_hotplug_event(connector); 3573 } 3574 } 3575 } 3576 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) { 3577 if (adev->dm.hdcp_workqueue) 3578 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index); 3579 } 3580 3581 if (dc_link->type != dc_connection_mst_branch) 3582 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); 3583 3584 mutex_unlock(&aconnector->hpd_lock); 3585 } 3586 3587 static int register_hpd_handlers(struct amdgpu_device *adev) 3588 { 3589 struct drm_device *dev = adev_to_drm(adev); 3590 struct drm_connector *connector; 3591 struct amdgpu_dm_connector *aconnector; 3592 const struct dc_link *dc_link; 3593 struct dc_interrupt_params int_params = {0}; 3594 3595 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3596 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3597 3598 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 3599 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, 3600 dmub_hpd_callback, true)) { 3601 DRM_ERROR("amdgpu: fail to register dmub hpd callback"); 3602 return -EINVAL; 3603 } 3604 3605 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, 3606 dmub_hpd_callback, true)) { 3607 DRM_ERROR("amdgpu: fail to register dmub hpd callback"); 3608 return -EINVAL; 3609 } 3610 } 3611 3612 list_for_each_entry(connector, 3613 &dev->mode_config.connector_list, head) { 3614 3615 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 3616 continue; 3617 3618 aconnector = to_amdgpu_dm_connector(connector); 3619 dc_link = aconnector->dc_link; 3620 3621 if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) { 3622 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3623 int_params.irq_source = dc_link->irq_source_hpd; 3624 3625 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 3626 int_params.irq_source < DC_IRQ_SOURCE_HPD1 || 3627 int_params.irq_source > DC_IRQ_SOURCE_HPD6) { 3628 DRM_ERROR("Failed to register hpd irq!\n"); 3629 return -EINVAL; 3630 } 3631 3632 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 3633 handle_hpd_irq, (void *) aconnector)) 3634 return -ENOMEM; 3635 } 3636 3637 if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) { 3638 3639 /* Also register for DP short pulse (hpd_rx). */ 3640 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3641 int_params.irq_source = dc_link->irq_source_hpd_rx; 3642 3643 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 3644 int_params.irq_source < DC_IRQ_SOURCE_HPD1RX || 3645 int_params.irq_source > DC_IRQ_SOURCE_HPD6RX) { 3646 DRM_ERROR("Failed to register hpd rx irq!\n"); 3647 return -EINVAL; 3648 } 3649 3650 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 3651 handle_hpd_rx_irq, (void *) aconnector)) 3652 return -ENOMEM; 3653 } 3654 } 3655 return 0; 3656 } 3657 3658 #if defined(CONFIG_DRM_AMD_DC_SI) 3659 /* Register IRQ sources and initialize IRQ callbacks */ 3660 static int dce60_register_irq_handlers(struct amdgpu_device *adev) 3661 { 3662 struct dc *dc = adev->dm.dc; 3663 struct common_irq_params *c_irq_params; 3664 struct dc_interrupt_params int_params = {0}; 3665 int r; 3666 int i; 3667 unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3668 3669 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3670 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3671 3672 /* 3673 * Actions of amdgpu_irq_add_id(): 3674 * 1. Register a set() function with base driver. 3675 * Base driver will call set() function to enable/disable an 3676 * interrupt in DC hardware. 3677 * 2. Register amdgpu_dm_irq_handler(). 3678 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3679 * coming from DC hardware. 3680 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3681 * for acknowledging and handling. 3682 */ 3683 3684 /* Use VBLANK interrupt */ 3685 for (i = 0; i < adev->mode_info.num_crtc; i++) { 3686 r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq); 3687 if (r) { 3688 DRM_ERROR("Failed to add crtc irq id!\n"); 3689 return r; 3690 } 3691 3692 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3693 int_params.irq_source = 3694 dc_interrupt_to_irq_source(dc, i + 1, 0); 3695 3696 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 3697 int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 || 3698 int_params.irq_source > DC_IRQ_SOURCE_VBLANK6) { 3699 DRM_ERROR("Failed to register vblank irq!\n"); 3700 return -EINVAL; 3701 } 3702 3703 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3704 3705 c_irq_params->adev = adev; 3706 c_irq_params->irq_src = int_params.irq_source; 3707 3708 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 3709 dm_crtc_high_irq, c_irq_params)) 3710 return -ENOMEM; 3711 } 3712 3713 /* Use GRPH_PFLIP interrupt */ 3714 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 3715 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 3716 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 3717 if (r) { 3718 DRM_ERROR("Failed to add page flip irq id!\n"); 3719 return r; 3720 } 3721 3722 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3723 int_params.irq_source = 3724 dc_interrupt_to_irq_source(dc, i, 0); 3725 3726 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 3727 int_params.irq_source < DC_IRQ_SOURCE_PFLIP_FIRST || 3728 int_params.irq_source > DC_IRQ_SOURCE_PFLIP_LAST) { 3729 DRM_ERROR("Failed to register pflip irq!\n"); 3730 return -EINVAL; 3731 } 3732 3733 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 3734 3735 c_irq_params->adev = adev; 3736 c_irq_params->irq_src = int_params.irq_source; 3737 3738 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 3739 dm_pflip_high_irq, c_irq_params)) 3740 return -ENOMEM; 3741 } 3742 3743 /* HPD */ 3744 r = amdgpu_irq_add_id(adev, client_id, 3745 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 3746 if (r) { 3747 DRM_ERROR("Failed to add hpd irq id!\n"); 3748 return r; 3749 } 3750 3751 r = register_hpd_handlers(adev); 3752 3753 return r; 3754 } 3755 #endif 3756 3757 /* Register IRQ sources and initialize IRQ callbacks */ 3758 static int dce110_register_irq_handlers(struct amdgpu_device *adev) 3759 { 3760 struct dc *dc = adev->dm.dc; 3761 struct common_irq_params *c_irq_params; 3762 struct dc_interrupt_params int_params = {0}; 3763 int r; 3764 int i; 3765 unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3766 3767 if (adev->family >= AMDGPU_FAMILY_AI) 3768 client_id = SOC15_IH_CLIENTID_DCE; 3769 3770 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3771 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3772 3773 /* 3774 * Actions of amdgpu_irq_add_id(): 3775 * 1. Register a set() function with base driver. 3776 * Base driver will call set() function to enable/disable an 3777 * interrupt in DC hardware. 3778 * 2. Register amdgpu_dm_irq_handler(). 3779 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3780 * coming from DC hardware. 3781 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3782 * for acknowledging and handling. 3783 */ 3784 3785 /* Use VBLANK interrupt */ 3786 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { 3787 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); 3788 if (r) { 3789 DRM_ERROR("Failed to add crtc irq id!\n"); 3790 return r; 3791 } 3792 3793 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3794 int_params.irq_source = 3795 dc_interrupt_to_irq_source(dc, i, 0); 3796 3797 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 3798 int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 || 3799 int_params.irq_source > DC_IRQ_SOURCE_VBLANK6) { 3800 DRM_ERROR("Failed to register vblank irq!\n"); 3801 return -EINVAL; 3802 } 3803 3804 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3805 3806 c_irq_params->adev = adev; 3807 c_irq_params->irq_src = int_params.irq_source; 3808 3809 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 3810 dm_crtc_high_irq, c_irq_params)) 3811 return -ENOMEM; 3812 } 3813 3814 /* Use VUPDATE interrupt */ 3815 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { 3816 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); 3817 if (r) { 3818 DRM_ERROR("Failed to add vupdate irq id!\n"); 3819 return r; 3820 } 3821 3822 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3823 int_params.irq_source = 3824 dc_interrupt_to_irq_source(dc, i, 0); 3825 3826 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 3827 int_params.irq_source < DC_IRQ_SOURCE_VUPDATE1 || 3828 int_params.irq_source > DC_IRQ_SOURCE_VUPDATE6) { 3829 DRM_ERROR("Failed to register vupdate irq!\n"); 3830 return -EINVAL; 3831 } 3832 3833 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 3834 3835 c_irq_params->adev = adev; 3836 c_irq_params->irq_src = int_params.irq_source; 3837 3838 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 3839 dm_vupdate_high_irq, c_irq_params)) 3840 return -ENOMEM; 3841 } 3842 3843 /* Use GRPH_PFLIP interrupt */ 3844 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 3845 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 3846 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 3847 if (r) { 3848 DRM_ERROR("Failed to add page flip irq id!\n"); 3849 return r; 3850 } 3851 3852 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3853 int_params.irq_source = 3854 dc_interrupt_to_irq_source(dc, i, 0); 3855 3856 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 3857 int_params.irq_source < DC_IRQ_SOURCE_PFLIP_FIRST || 3858 int_params.irq_source > DC_IRQ_SOURCE_PFLIP_LAST) { 3859 DRM_ERROR("Failed to register pflip irq!\n"); 3860 return -EINVAL; 3861 } 3862 3863 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 3864 3865 c_irq_params->adev = adev; 3866 c_irq_params->irq_src = int_params.irq_source; 3867 3868 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 3869 dm_pflip_high_irq, c_irq_params)) 3870 return -ENOMEM; 3871 } 3872 3873 /* HPD */ 3874 r = amdgpu_irq_add_id(adev, client_id, 3875 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 3876 if (r) { 3877 DRM_ERROR("Failed to add hpd irq id!\n"); 3878 return r; 3879 } 3880 3881 r = register_hpd_handlers(adev); 3882 3883 return r; 3884 } 3885 3886 /* Register IRQ sources and initialize IRQ callbacks */ 3887 static int dcn10_register_irq_handlers(struct amdgpu_device *adev) 3888 { 3889 struct dc *dc = adev->dm.dc; 3890 struct common_irq_params *c_irq_params; 3891 struct dc_interrupt_params int_params = {0}; 3892 int r; 3893 int i; 3894 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3895 static const unsigned int vrtl_int_srcid[] = { 3896 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL, 3897 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL, 3898 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL, 3899 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL, 3900 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL, 3901 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL 3902 }; 3903 #endif 3904 3905 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3906 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3907 3908 /* 3909 * Actions of amdgpu_irq_add_id(): 3910 * 1. Register a set() function with base driver. 3911 * Base driver will call set() function to enable/disable an 3912 * interrupt in DC hardware. 3913 * 2. Register amdgpu_dm_irq_handler(). 3914 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3915 * coming from DC hardware. 3916 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3917 * for acknowledging and handling. 3918 */ 3919 3920 /* Use VSTARTUP interrupt */ 3921 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; 3922 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; 3923 i++) { 3924 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); 3925 3926 if (r) { 3927 DRM_ERROR("Failed to add crtc irq id!\n"); 3928 return r; 3929 } 3930 3931 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3932 int_params.irq_source = 3933 dc_interrupt_to_irq_source(dc, i, 0); 3934 3935 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 3936 int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 || 3937 int_params.irq_source > DC_IRQ_SOURCE_VBLANK6) { 3938 DRM_ERROR("Failed to register vblank irq!\n"); 3939 return -EINVAL; 3940 } 3941 3942 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3943 3944 c_irq_params->adev = adev; 3945 c_irq_params->irq_src = int_params.irq_source; 3946 3947 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 3948 dm_crtc_high_irq, c_irq_params)) 3949 return -ENOMEM; 3950 } 3951 3952 /* Use otg vertical line interrupt */ 3953 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3954 for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) { 3955 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, 3956 vrtl_int_srcid[i], &adev->vline0_irq); 3957 3958 if (r) { 3959 DRM_ERROR("Failed to add vline0 irq id!\n"); 3960 return r; 3961 } 3962 3963 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3964 int_params.irq_source = 3965 dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0); 3966 3967 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 3968 int_params.irq_source < DC_IRQ_SOURCE_DC1_VLINE0 || 3969 int_params.irq_source > DC_IRQ_SOURCE_DC6_VLINE0) { 3970 DRM_ERROR("Failed to register vline0 irq!\n"); 3971 return -EINVAL; 3972 } 3973 3974 c_irq_params = &adev->dm.vline0_params[int_params.irq_source 3975 - DC_IRQ_SOURCE_DC1_VLINE0]; 3976 3977 c_irq_params->adev = adev; 3978 c_irq_params->irq_src = int_params.irq_source; 3979 3980 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 3981 dm_dcn_vertical_interrupt0_high_irq, 3982 c_irq_params)) 3983 return -ENOMEM; 3984 } 3985 #endif 3986 3987 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to 3988 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx 3989 * to trigger at end of each vblank, regardless of state of the lock, 3990 * matching DCE behaviour. 3991 */ 3992 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT; 3993 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1; 3994 i++) { 3995 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq); 3996 3997 if (r) { 3998 DRM_ERROR("Failed to add vupdate irq id!\n"); 3999 return r; 4000 } 4001 4002 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 4003 int_params.irq_source = 4004 dc_interrupt_to_irq_source(dc, i, 0); 4005 4006 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 4007 int_params.irq_source < DC_IRQ_SOURCE_VUPDATE1 || 4008 int_params.irq_source > DC_IRQ_SOURCE_VUPDATE6) { 4009 DRM_ERROR("Failed to register vupdate irq!\n"); 4010 return -EINVAL; 4011 } 4012 4013 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 4014 4015 c_irq_params->adev = adev; 4016 c_irq_params->irq_src = int_params.irq_source; 4017 4018 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4019 dm_vupdate_high_irq, c_irq_params)) 4020 return -ENOMEM; 4021 } 4022 4023 /* Use GRPH_PFLIP interrupt */ 4024 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; 4025 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1; 4026 i++) { 4027 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); 4028 if (r) { 4029 DRM_ERROR("Failed to add page flip irq id!\n"); 4030 return r; 4031 } 4032 4033 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 4034 int_params.irq_source = 4035 dc_interrupt_to_irq_source(dc, i, 0); 4036 4037 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 4038 int_params.irq_source < DC_IRQ_SOURCE_PFLIP_FIRST || 4039 int_params.irq_source > DC_IRQ_SOURCE_PFLIP_LAST) { 4040 DRM_ERROR("Failed to register pflip irq!\n"); 4041 return -EINVAL; 4042 } 4043 4044 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 4045 4046 c_irq_params->adev = adev; 4047 c_irq_params->irq_src = int_params.irq_source; 4048 4049 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4050 dm_pflip_high_irq, c_irq_params)) 4051 return -ENOMEM; 4052 } 4053 4054 /* HPD */ 4055 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, 4056 &adev->hpd_irq); 4057 if (r) { 4058 DRM_ERROR("Failed to add hpd irq id!\n"); 4059 return r; 4060 } 4061 4062 r = register_hpd_handlers(adev); 4063 4064 return r; 4065 } 4066 /* Register Outbox IRQ sources and initialize IRQ callbacks */ 4067 static int register_outbox_irq_handlers(struct amdgpu_device *adev) 4068 { 4069 struct dc *dc = adev->dm.dc; 4070 struct common_irq_params *c_irq_params; 4071 struct dc_interrupt_params int_params = {0}; 4072 int r, i; 4073 4074 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 4075 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 4076 4077 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT, 4078 &adev->dmub_outbox_irq); 4079 if (r) { 4080 DRM_ERROR("Failed to add outbox irq id!\n"); 4081 return r; 4082 } 4083 4084 if (dc->ctx->dmub_srv) { 4085 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT; 4086 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 4087 int_params.irq_source = 4088 dc_interrupt_to_irq_source(dc, i, 0); 4089 4090 c_irq_params = &adev->dm.dmub_outbox_params[0]; 4091 4092 c_irq_params->adev = adev; 4093 c_irq_params->irq_src = int_params.irq_source; 4094 4095 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4096 dm_dmub_outbox1_low_irq, c_irq_params)) 4097 return -ENOMEM; 4098 } 4099 4100 return 0; 4101 } 4102 4103 /* 4104 * Acquires the lock for the atomic state object and returns 4105 * the new atomic state. 4106 * 4107 * This should only be called during atomic check. 4108 */ 4109 int dm_atomic_get_state(struct drm_atomic_state *state, 4110 struct dm_atomic_state **dm_state) 4111 { 4112 struct drm_device *dev = state->dev; 4113 struct amdgpu_device *adev = drm_to_adev(dev); 4114 struct amdgpu_display_manager *dm = &adev->dm; 4115 struct drm_private_state *priv_state; 4116 4117 if (*dm_state) 4118 return 0; 4119 4120 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 4121 if (IS_ERR(priv_state)) 4122 return PTR_ERR(priv_state); 4123 4124 *dm_state = to_dm_atomic_state(priv_state); 4125 4126 return 0; 4127 } 4128 4129 static struct dm_atomic_state * 4130 dm_atomic_get_new_state(struct drm_atomic_state *state) 4131 { 4132 struct drm_device *dev = state->dev; 4133 struct amdgpu_device *adev = drm_to_adev(dev); 4134 struct amdgpu_display_manager *dm = &adev->dm; 4135 struct drm_private_obj *obj; 4136 struct drm_private_state *new_obj_state; 4137 int i; 4138 4139 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 4140 if (obj->funcs == dm->atomic_obj.funcs) 4141 return to_dm_atomic_state(new_obj_state); 4142 } 4143 4144 return NULL; 4145 } 4146 4147 static struct drm_private_state * 4148 dm_atomic_duplicate_state(struct drm_private_obj *obj) 4149 { 4150 struct dm_atomic_state *old_state, *new_state; 4151 4152 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 4153 if (!new_state) 4154 return NULL; 4155 4156 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 4157 4158 old_state = to_dm_atomic_state(obj->state); 4159 4160 if (old_state && old_state->context) 4161 new_state->context = dc_state_create_copy(old_state->context); 4162 4163 if (!new_state->context) { 4164 kfree(new_state); 4165 return NULL; 4166 } 4167 4168 return &new_state->base; 4169 } 4170 4171 static void dm_atomic_destroy_state(struct drm_private_obj *obj, 4172 struct drm_private_state *state) 4173 { 4174 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 4175 4176 if (dm_state && dm_state->context) 4177 dc_state_release(dm_state->context); 4178 4179 kfree(dm_state); 4180 } 4181 4182 static struct drm_private_state_funcs dm_atomic_state_funcs = { 4183 .atomic_duplicate_state = dm_atomic_duplicate_state, 4184 .atomic_destroy_state = dm_atomic_destroy_state, 4185 }; 4186 4187 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 4188 { 4189 struct dm_atomic_state *state; 4190 int r; 4191 4192 adev->mode_info.mode_config_initialized = true; 4193 4194 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 4195 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 4196 4197 adev_to_drm(adev)->mode_config.max_width = 16384; 4198 adev_to_drm(adev)->mode_config.max_height = 16384; 4199 4200 adev_to_drm(adev)->mode_config.preferred_depth = 24; 4201 if (adev->asic_type == CHIP_HAWAII) 4202 /* disable prefer shadow for now due to hibernation issues */ 4203 adev_to_drm(adev)->mode_config.prefer_shadow = 0; 4204 else 4205 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 4206 /* indicates support for immediate flip */ 4207 adev_to_drm(adev)->mode_config.async_page_flip = true; 4208 4209 state = kzalloc(sizeof(*state), GFP_KERNEL); 4210 if (!state) 4211 return -ENOMEM; 4212 4213 state->context = dc_state_create_current_copy(adev->dm.dc); 4214 if (!state->context) { 4215 kfree(state); 4216 return -ENOMEM; 4217 } 4218 4219 drm_atomic_private_obj_init(adev_to_drm(adev), 4220 &adev->dm.atomic_obj, 4221 &state->base, 4222 &dm_atomic_state_funcs); 4223 4224 r = amdgpu_display_modeset_create_props(adev); 4225 if (r) { 4226 dc_state_release(state->context); 4227 kfree(state); 4228 return r; 4229 } 4230 4231 #ifdef AMD_PRIVATE_COLOR 4232 if (amdgpu_dm_create_color_properties(adev)) 4233 return -ENOMEM; 4234 #endif 4235 4236 r = amdgpu_dm_audio_init(adev); 4237 if (r) { 4238 dc_state_release(state->context); 4239 kfree(state); 4240 return r; 4241 } 4242 4243 return 0; 4244 } 4245 4246 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 4247 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 4248 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 4249 4250 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, 4251 int bl_idx) 4252 { 4253 #if defined(CONFIG_ACPI) 4254 struct amdgpu_dm_backlight_caps caps; 4255 4256 memset(&caps, 0, sizeof(caps)); 4257 4258 if (dm->backlight_caps[bl_idx].caps_valid) 4259 return; 4260 4261 amdgpu_acpi_get_backlight_caps(&caps); 4262 if (caps.caps_valid) { 4263 dm->backlight_caps[bl_idx].caps_valid = true; 4264 if (caps.aux_support) 4265 return; 4266 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal; 4267 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal; 4268 } else { 4269 dm->backlight_caps[bl_idx].min_input_signal = 4270 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 4271 dm->backlight_caps[bl_idx].max_input_signal = 4272 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 4273 } 4274 #else 4275 if (dm->backlight_caps[bl_idx].aux_support) 4276 return; 4277 4278 dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 4279 dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 4280 #endif 4281 } 4282 4283 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, 4284 unsigned int *min, unsigned int *max) 4285 { 4286 if (!caps) 4287 return 0; 4288 4289 if (caps->aux_support) { 4290 // Firmware limits are in nits, DC API wants millinits. 4291 *max = 1000 * caps->aux_max_input_signal; 4292 *min = 1000 * caps->aux_min_input_signal; 4293 } else { 4294 // Firmware limits are 8-bit, PWM control is 16-bit. 4295 *max = 0x101 * caps->max_input_signal; 4296 *min = 0x101 * caps->min_input_signal; 4297 } 4298 return 1; 4299 } 4300 4301 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps, 4302 uint32_t brightness) 4303 { 4304 unsigned int min, max; 4305 4306 if (!get_brightness_range(caps, &min, &max)) 4307 return brightness; 4308 4309 // Rescale 0..255 to min..max 4310 return min + DIV_ROUND_CLOSEST((max - min) * brightness, 4311 AMDGPU_MAX_BL_LEVEL); 4312 } 4313 4314 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps, 4315 uint32_t brightness) 4316 { 4317 unsigned int min, max; 4318 4319 if (!get_brightness_range(caps, &min, &max)) 4320 return brightness; 4321 4322 if (brightness < min) 4323 return 0; 4324 // Rescale min..max to 0..255 4325 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min), 4326 max - min); 4327 } 4328 4329 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, 4330 int bl_idx, 4331 u32 user_brightness) 4332 { 4333 struct amdgpu_dm_backlight_caps caps; 4334 struct dc_link *link; 4335 u32 brightness; 4336 bool rc; 4337 4338 amdgpu_dm_update_backlight_caps(dm, bl_idx); 4339 caps = dm->backlight_caps[bl_idx]; 4340 4341 dm->brightness[bl_idx] = user_brightness; 4342 /* update scratch register */ 4343 if (bl_idx == 0) 4344 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]); 4345 brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]); 4346 link = (struct dc_link *)dm->backlight_link[bl_idx]; 4347 4348 /* Change brightness based on AUX property */ 4349 if (caps.aux_support) { 4350 rc = dc_link_set_backlight_level_nits(link, true, brightness, 4351 AUX_BL_DEFAULT_TRANSITION_TIME_MS); 4352 if (!rc) 4353 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx); 4354 } else { 4355 rc = dc_link_set_backlight_level(link, brightness, 0); 4356 if (!rc) 4357 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx); 4358 } 4359 4360 if (rc) 4361 dm->actual_brightness[bl_idx] = user_brightness; 4362 } 4363 4364 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) 4365 { 4366 struct amdgpu_display_manager *dm = bl_get_data(bd); 4367 int i; 4368 4369 for (i = 0; i < dm->num_of_edps; i++) { 4370 if (bd == dm->backlight_dev[i]) 4371 break; 4372 } 4373 if (i >= AMDGPU_DM_MAX_NUM_EDP) 4374 i = 0; 4375 amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness); 4376 4377 return 0; 4378 } 4379 4380 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, 4381 int bl_idx) 4382 { 4383 int ret; 4384 struct amdgpu_dm_backlight_caps caps; 4385 struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx]; 4386 4387 amdgpu_dm_update_backlight_caps(dm, bl_idx); 4388 caps = dm->backlight_caps[bl_idx]; 4389 4390 if (caps.aux_support) { 4391 u32 avg, peak; 4392 bool rc; 4393 4394 rc = dc_link_get_backlight_level_nits(link, &avg, &peak); 4395 if (!rc) 4396 return dm->brightness[bl_idx]; 4397 return convert_brightness_to_user(&caps, avg); 4398 } 4399 4400 ret = dc_link_get_backlight_level(link); 4401 4402 if (ret == DC_ERROR_UNEXPECTED) 4403 return dm->brightness[bl_idx]; 4404 4405 return convert_brightness_to_user(&caps, ret); 4406 } 4407 4408 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) 4409 { 4410 struct amdgpu_display_manager *dm = bl_get_data(bd); 4411 int i; 4412 4413 for (i = 0; i < dm->num_of_edps; i++) { 4414 if (bd == dm->backlight_dev[i]) 4415 break; 4416 } 4417 if (i >= AMDGPU_DM_MAX_NUM_EDP) 4418 i = 0; 4419 return amdgpu_dm_backlight_get_level(dm, i); 4420 } 4421 4422 static const struct backlight_ops amdgpu_dm_backlight_ops = { 4423 .options = BL_CORE_SUSPENDRESUME, 4424 .get_brightness = amdgpu_dm_backlight_get_brightness, 4425 .update_status = amdgpu_dm_backlight_update_status, 4426 }; 4427 4428 static void 4429 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector) 4430 { 4431 struct drm_device *drm = aconnector->base.dev; 4432 struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm; 4433 struct backlight_properties props = { 0 }; 4434 char bl_name[16]; 4435 4436 if (aconnector->bl_idx == -1) 4437 return; 4438 4439 if (!acpi_video_backlight_use_native()) { 4440 drm_info(drm, "Skipping amdgpu DM backlight registration\n"); 4441 /* Try registering an ACPI video backlight device instead. */ 4442 acpi_video_register_backlight(); 4443 return; 4444 } 4445 4446 props.max_brightness = AMDGPU_MAX_BL_LEVEL; 4447 props.brightness = AMDGPU_MAX_BL_LEVEL; 4448 props.type = BACKLIGHT_RAW; 4449 4450 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", 4451 drm->primary->index + aconnector->bl_idx); 4452 4453 dm->backlight_dev[aconnector->bl_idx] = 4454 backlight_device_register(bl_name, aconnector->base.kdev, dm, 4455 &amdgpu_dm_backlight_ops, &props); 4456 4457 if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) { 4458 DRM_ERROR("DM: Backlight registration failed!\n"); 4459 dm->backlight_dev[aconnector->bl_idx] = NULL; 4460 } else 4461 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); 4462 } 4463 4464 static int initialize_plane(struct amdgpu_display_manager *dm, 4465 struct amdgpu_mode_info *mode_info, int plane_id, 4466 enum drm_plane_type plane_type, 4467 const struct dc_plane_cap *plane_cap) 4468 { 4469 struct drm_plane *plane; 4470 unsigned long possible_crtcs; 4471 int ret = 0; 4472 4473 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); 4474 if (!plane) { 4475 DRM_ERROR("KMS: Failed to allocate plane\n"); 4476 return -ENOMEM; 4477 } 4478 plane->type = plane_type; 4479 4480 /* 4481 * HACK: IGT tests expect that the primary plane for a CRTC 4482 * can only have one possible CRTC. Only expose support for 4483 * any CRTC if they're not going to be used as a primary plane 4484 * for a CRTC - like overlay or underlay planes. 4485 */ 4486 possible_crtcs = 1 << plane_id; 4487 if (plane_id >= dm->dc->caps.max_streams) 4488 possible_crtcs = 0xff; 4489 4490 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); 4491 4492 if (ret) { 4493 DRM_ERROR("KMS: Failed to initialize plane\n"); 4494 kfree(plane); 4495 return ret; 4496 } 4497 4498 if (mode_info) 4499 mode_info->planes[plane_id] = plane; 4500 4501 return ret; 4502 } 4503 4504 4505 static void setup_backlight_device(struct amdgpu_display_manager *dm, 4506 struct amdgpu_dm_connector *aconnector) 4507 { 4508 struct dc_link *link = aconnector->dc_link; 4509 int bl_idx = dm->num_of_edps; 4510 4511 if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) || 4512 link->type == dc_connection_none) 4513 return; 4514 4515 if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) { 4516 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n"); 4517 return; 4518 } 4519 4520 aconnector->bl_idx = bl_idx; 4521 4522 amdgpu_dm_update_backlight_caps(dm, bl_idx); 4523 dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL; 4524 dm->backlight_link[bl_idx] = link; 4525 dm->num_of_edps++; 4526 4527 update_connector_ext_caps(aconnector); 4528 } 4529 4530 static void amdgpu_set_panel_orientation(struct drm_connector *connector); 4531 4532 /* 4533 * In this architecture, the association 4534 * connector -> encoder -> crtc 4535 * id not really requried. The crtc and connector will hold the 4536 * display_index as an abstraction to use with DAL component 4537 * 4538 * Returns 0 on success 4539 */ 4540 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 4541 { 4542 struct amdgpu_display_manager *dm = &adev->dm; 4543 s32 i; 4544 struct amdgpu_dm_connector *aconnector = NULL; 4545 struct amdgpu_encoder *aencoder = NULL; 4546 struct amdgpu_mode_info *mode_info = &adev->mode_info; 4547 u32 link_cnt; 4548 s32 primary_planes; 4549 enum dc_connection_type new_connection_type = dc_connection_none; 4550 const struct dc_plane_cap *plane; 4551 bool psr_feature_enabled = false; 4552 bool replay_feature_enabled = false; 4553 int max_overlay = dm->dc->caps.max_slave_planes; 4554 4555 dm->display_indexes_num = dm->dc->caps.max_streams; 4556 /* Update the actual used number of crtc */ 4557 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 4558 4559 amdgpu_dm_set_irq_funcs(adev); 4560 4561 link_cnt = dm->dc->caps.max_links; 4562 if (amdgpu_dm_mode_config_init(dm->adev)) { 4563 DRM_ERROR("DM: Failed to initialize mode config\n"); 4564 return -EINVAL; 4565 } 4566 4567 /* There is one primary plane per CRTC */ 4568 primary_planes = dm->dc->caps.max_streams; 4569 if (primary_planes > AMDGPU_MAX_PLANES) { 4570 DRM_ERROR("DM: Plane nums out of 6 planes\n"); 4571 return -EINVAL; 4572 } 4573 4574 /* 4575 * Initialize primary planes, implicit planes for legacy IOCTLS. 4576 * Order is reversed to match iteration order in atomic check. 4577 */ 4578 for (i = (primary_planes - 1); i >= 0; i--) { 4579 plane = &dm->dc->caps.planes[i]; 4580 4581 if (initialize_plane(dm, mode_info, i, 4582 DRM_PLANE_TYPE_PRIMARY, plane)) { 4583 DRM_ERROR("KMS: Failed to initialize primary plane\n"); 4584 goto fail; 4585 } 4586 } 4587 4588 /* 4589 * Initialize overlay planes, index starting after primary planes. 4590 * These planes have a higher DRM index than the primary planes since 4591 * they should be considered as having a higher z-order. 4592 * Order is reversed to match iteration order in atomic check. 4593 * 4594 * Only support DCN for now, and only expose one so we don't encourage 4595 * userspace to use up all the pipes. 4596 */ 4597 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 4598 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 4599 4600 /* Do not create overlay if MPO disabled */ 4601 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO) 4602 break; 4603 4604 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) 4605 continue; 4606 4607 if (!plane->pixel_format_support.argb8888) 4608 continue; 4609 4610 if (max_overlay-- == 0) 4611 break; 4612 4613 if (initialize_plane(dm, NULL, primary_planes + i, 4614 DRM_PLANE_TYPE_OVERLAY, plane)) { 4615 DRM_ERROR("KMS: Failed to initialize overlay plane\n"); 4616 goto fail; 4617 } 4618 } 4619 4620 for (i = 0; i < dm->dc->caps.max_streams; i++) 4621 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 4622 DRM_ERROR("KMS: Failed to initialize crtc\n"); 4623 goto fail; 4624 } 4625 4626 /* Use Outbox interrupt */ 4627 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 4628 case IP_VERSION(3, 0, 0): 4629 case IP_VERSION(3, 1, 2): 4630 case IP_VERSION(3, 1, 3): 4631 case IP_VERSION(3, 1, 4): 4632 case IP_VERSION(3, 1, 5): 4633 case IP_VERSION(3, 1, 6): 4634 case IP_VERSION(3, 2, 0): 4635 case IP_VERSION(3, 2, 1): 4636 case IP_VERSION(2, 1, 0): 4637 case IP_VERSION(3, 5, 0): 4638 case IP_VERSION(3, 5, 1): 4639 case IP_VERSION(4, 0, 1): 4640 if (register_outbox_irq_handlers(dm->adev)) { 4641 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4642 goto fail; 4643 } 4644 break; 4645 default: 4646 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n", 4647 amdgpu_ip_version(adev, DCE_HWIP, 0)); 4648 } 4649 4650 /* Determine whether to enable PSR support by default. */ 4651 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) { 4652 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 4653 case IP_VERSION(3, 1, 2): 4654 case IP_VERSION(3, 1, 3): 4655 case IP_VERSION(3, 1, 4): 4656 case IP_VERSION(3, 1, 5): 4657 case IP_VERSION(3, 1, 6): 4658 case IP_VERSION(3, 2, 0): 4659 case IP_VERSION(3, 2, 1): 4660 case IP_VERSION(3, 5, 0): 4661 case IP_VERSION(3, 5, 1): 4662 case IP_VERSION(4, 0, 1): 4663 psr_feature_enabled = true; 4664 break; 4665 default: 4666 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK; 4667 break; 4668 } 4669 } 4670 4671 /* Determine whether to enable Replay support by default. */ 4672 if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) { 4673 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 4674 /* 4675 * Disabled by default due to https://gitlab.freedesktop.org/drm/amd/-/issues/3344 4676 * case IP_VERSION(3, 1, 4): 4677 * case IP_VERSION(3, 1, 5): 4678 * case IP_VERSION(3, 1, 6): 4679 * case IP_VERSION(3, 2, 0): 4680 * case IP_VERSION(3, 2, 1): 4681 * case IP_VERSION(3, 5, 0): 4682 * case IP_VERSION(3, 5, 1): 4683 * replay_feature_enabled = true; 4684 * break; 4685 */ 4686 default: 4687 replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK; 4688 break; 4689 } 4690 } 4691 4692 if (link_cnt > MAX_LINKS) { 4693 DRM_ERROR( 4694 "KMS: Cannot support more than %d display indexes\n", 4695 MAX_LINKS); 4696 goto fail; 4697 } 4698 4699 /* loops over all connectors on the board */ 4700 for (i = 0; i < link_cnt; i++) { 4701 struct dc_link *link = NULL; 4702 4703 link = dc_get_link_at_index(dm->dc, i); 4704 4705 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) { 4706 struct amdgpu_dm_wb_connector *wbcon = kzalloc(sizeof(*wbcon), GFP_KERNEL); 4707 4708 if (!wbcon) { 4709 DRM_ERROR("KMS: Failed to allocate writeback connector\n"); 4710 continue; 4711 } 4712 4713 if (amdgpu_dm_wb_connector_init(dm, wbcon, i)) { 4714 DRM_ERROR("KMS: Failed to initialize writeback connector\n"); 4715 kfree(wbcon); 4716 continue; 4717 } 4718 4719 link->psr_settings.psr_feature_enabled = false; 4720 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; 4721 4722 continue; 4723 } 4724 4725 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 4726 if (!aconnector) 4727 goto fail; 4728 4729 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); 4730 if (!aencoder) 4731 goto fail; 4732 4733 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 4734 DRM_ERROR("KMS: Failed to initialize encoder\n"); 4735 goto fail; 4736 } 4737 4738 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 4739 DRM_ERROR("KMS: Failed to initialize connector\n"); 4740 goto fail; 4741 } 4742 4743 if (dm->hpd_rx_offload_wq) 4744 dm->hpd_rx_offload_wq[aconnector->base.index].aconnector = 4745 aconnector; 4746 4747 if (!dc_link_detect_connection_type(link, &new_connection_type)) 4748 DRM_ERROR("KMS: Failed to detect connector\n"); 4749 4750 if (aconnector->base.force && new_connection_type == dc_connection_none) { 4751 emulated_link_detect(link); 4752 amdgpu_dm_update_connector_after_detect(aconnector); 4753 } else { 4754 bool ret = false; 4755 4756 mutex_lock(&dm->dc_lock); 4757 ret = dc_link_detect(link, DETECT_REASON_BOOT); 4758 mutex_unlock(&dm->dc_lock); 4759 4760 if (ret) { 4761 amdgpu_dm_update_connector_after_detect(aconnector); 4762 setup_backlight_device(dm, aconnector); 4763 4764 /* Disable PSR if Replay can be enabled */ 4765 if (replay_feature_enabled) 4766 if (amdgpu_dm_set_replay_caps(link, aconnector)) 4767 psr_feature_enabled = false; 4768 4769 if (psr_feature_enabled) 4770 amdgpu_dm_set_psr_caps(link); 4771 4772 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when 4773 * PSR is also supported. 4774 */ 4775 if (link->psr_settings.psr_feature_enabled) 4776 adev_to_drm(adev)->vblank_disable_immediate = false; 4777 } 4778 } 4779 amdgpu_set_panel_orientation(&aconnector->base); 4780 } 4781 4782 /* Software is initialized. Now we can register interrupt handlers. */ 4783 switch (adev->asic_type) { 4784 #if defined(CONFIG_DRM_AMD_DC_SI) 4785 case CHIP_TAHITI: 4786 case CHIP_PITCAIRN: 4787 case CHIP_VERDE: 4788 case CHIP_OLAND: 4789 if (dce60_register_irq_handlers(dm->adev)) { 4790 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4791 goto fail; 4792 } 4793 break; 4794 #endif 4795 case CHIP_BONAIRE: 4796 case CHIP_HAWAII: 4797 case CHIP_KAVERI: 4798 case CHIP_KABINI: 4799 case CHIP_MULLINS: 4800 case CHIP_TONGA: 4801 case CHIP_FIJI: 4802 case CHIP_CARRIZO: 4803 case CHIP_STONEY: 4804 case CHIP_POLARIS11: 4805 case CHIP_POLARIS10: 4806 case CHIP_POLARIS12: 4807 case CHIP_VEGAM: 4808 case CHIP_VEGA10: 4809 case CHIP_VEGA12: 4810 case CHIP_VEGA20: 4811 if (dce110_register_irq_handlers(dm->adev)) { 4812 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4813 goto fail; 4814 } 4815 break; 4816 default: 4817 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 4818 case IP_VERSION(1, 0, 0): 4819 case IP_VERSION(1, 0, 1): 4820 case IP_VERSION(2, 0, 2): 4821 case IP_VERSION(2, 0, 3): 4822 case IP_VERSION(2, 0, 0): 4823 case IP_VERSION(2, 1, 0): 4824 case IP_VERSION(3, 0, 0): 4825 case IP_VERSION(3, 0, 2): 4826 case IP_VERSION(3, 0, 3): 4827 case IP_VERSION(3, 0, 1): 4828 case IP_VERSION(3, 1, 2): 4829 case IP_VERSION(3, 1, 3): 4830 case IP_VERSION(3, 1, 4): 4831 case IP_VERSION(3, 1, 5): 4832 case IP_VERSION(3, 1, 6): 4833 case IP_VERSION(3, 2, 0): 4834 case IP_VERSION(3, 2, 1): 4835 case IP_VERSION(3, 5, 0): 4836 case IP_VERSION(3, 5, 1): 4837 case IP_VERSION(4, 0, 1): 4838 if (dcn10_register_irq_handlers(dm->adev)) { 4839 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4840 goto fail; 4841 } 4842 break; 4843 default: 4844 DRM_ERROR("Unsupported DCE IP versions: 0x%X\n", 4845 amdgpu_ip_version(adev, DCE_HWIP, 0)); 4846 goto fail; 4847 } 4848 break; 4849 } 4850 4851 return 0; 4852 fail: 4853 kfree(aencoder); 4854 kfree(aconnector); 4855 4856 return -EINVAL; 4857 } 4858 4859 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 4860 { 4861 drm_atomic_private_obj_fini(&dm->atomic_obj); 4862 } 4863 4864 /****************************************************************************** 4865 * amdgpu_display_funcs functions 4866 *****************************************************************************/ 4867 4868 /* 4869 * dm_bandwidth_update - program display watermarks 4870 * 4871 * @adev: amdgpu_device pointer 4872 * 4873 * Calculate and program the display watermarks and line buffer allocation. 4874 */ 4875 static void dm_bandwidth_update(struct amdgpu_device *adev) 4876 { 4877 /* TODO: implement later */ 4878 } 4879 4880 static const struct amdgpu_display_funcs dm_display_funcs = { 4881 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 4882 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 4883 .backlight_set_level = NULL, /* never called for DC */ 4884 .backlight_get_level = NULL, /* never called for DC */ 4885 .hpd_sense = NULL,/* called unconditionally */ 4886 .hpd_set_polarity = NULL, /* called unconditionally */ 4887 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 4888 .page_flip_get_scanoutpos = 4889 dm_crtc_get_scanoutpos,/* called unconditionally */ 4890 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 4891 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 4892 }; 4893 4894 #if defined(CONFIG_DEBUG_KERNEL_DC) 4895 4896 static ssize_t s3_debug_store(struct device *device, 4897 struct device_attribute *attr, 4898 const char *buf, 4899 size_t count) 4900 { 4901 int ret; 4902 int s3_state; 4903 struct drm_device *drm_dev = dev_get_drvdata(device); 4904 struct amdgpu_device *adev = drm_to_adev(drm_dev); 4905 4906 ret = kstrtoint(buf, 0, &s3_state); 4907 4908 if (ret == 0) { 4909 if (s3_state) { 4910 dm_resume(adev); 4911 drm_kms_helper_hotplug_event(adev_to_drm(adev)); 4912 } else 4913 dm_suspend(adev); 4914 } 4915 4916 return ret == 0 ? count : 0; 4917 } 4918 4919 DEVICE_ATTR_WO(s3_debug); 4920 4921 #endif 4922 4923 static int dm_init_microcode(struct amdgpu_device *adev) 4924 { 4925 char *fw_name_dmub; 4926 int r; 4927 4928 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 4929 case IP_VERSION(2, 1, 0): 4930 fw_name_dmub = FIRMWARE_RENOIR_DMUB; 4931 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) 4932 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB; 4933 break; 4934 case IP_VERSION(3, 0, 0): 4935 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0)) 4936 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB; 4937 else 4938 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB; 4939 break; 4940 case IP_VERSION(3, 0, 1): 4941 fw_name_dmub = FIRMWARE_VANGOGH_DMUB; 4942 break; 4943 case IP_VERSION(3, 0, 2): 4944 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB; 4945 break; 4946 case IP_VERSION(3, 0, 3): 4947 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB; 4948 break; 4949 case IP_VERSION(3, 1, 2): 4950 case IP_VERSION(3, 1, 3): 4951 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB; 4952 break; 4953 case IP_VERSION(3, 1, 4): 4954 fw_name_dmub = FIRMWARE_DCN_314_DMUB; 4955 break; 4956 case IP_VERSION(3, 1, 5): 4957 fw_name_dmub = FIRMWARE_DCN_315_DMUB; 4958 break; 4959 case IP_VERSION(3, 1, 6): 4960 fw_name_dmub = FIRMWARE_DCN316_DMUB; 4961 break; 4962 case IP_VERSION(3, 2, 0): 4963 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB; 4964 break; 4965 case IP_VERSION(3, 2, 1): 4966 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB; 4967 break; 4968 case IP_VERSION(3, 5, 0): 4969 fw_name_dmub = FIRMWARE_DCN_35_DMUB; 4970 break; 4971 case IP_VERSION(3, 5, 1): 4972 fw_name_dmub = FIRMWARE_DCN_351_DMUB; 4973 break; 4974 case IP_VERSION(4, 0, 1): 4975 fw_name_dmub = FIRMWARE_DCN_401_DMUB; 4976 break; 4977 default: 4978 /* ASIC doesn't support DMUB. */ 4979 return 0; 4980 } 4981 r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub); 4982 return r; 4983 } 4984 4985 static int dm_early_init(void *handle) 4986 { 4987 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4988 struct amdgpu_mode_info *mode_info = &adev->mode_info; 4989 struct atom_context *ctx = mode_info->atom_context; 4990 int index = GetIndexIntoMasterTable(DATA, Object_Header); 4991 u16 data_offset; 4992 4993 /* if there is no object header, skip DM */ 4994 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { 4995 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 4996 dev_info(adev->dev, "No object header, skipping DM\n"); 4997 return -ENOENT; 4998 } 4999 5000 switch (adev->asic_type) { 5001 #if defined(CONFIG_DRM_AMD_DC_SI) 5002 case CHIP_TAHITI: 5003 case CHIP_PITCAIRN: 5004 case CHIP_VERDE: 5005 adev->mode_info.num_crtc = 6; 5006 adev->mode_info.num_hpd = 6; 5007 adev->mode_info.num_dig = 6; 5008 break; 5009 case CHIP_OLAND: 5010 adev->mode_info.num_crtc = 2; 5011 adev->mode_info.num_hpd = 2; 5012 adev->mode_info.num_dig = 2; 5013 break; 5014 #endif 5015 case CHIP_BONAIRE: 5016 case CHIP_HAWAII: 5017 adev->mode_info.num_crtc = 6; 5018 adev->mode_info.num_hpd = 6; 5019 adev->mode_info.num_dig = 6; 5020 break; 5021 case CHIP_KAVERI: 5022 adev->mode_info.num_crtc = 4; 5023 adev->mode_info.num_hpd = 6; 5024 adev->mode_info.num_dig = 7; 5025 break; 5026 case CHIP_KABINI: 5027 case CHIP_MULLINS: 5028 adev->mode_info.num_crtc = 2; 5029 adev->mode_info.num_hpd = 6; 5030 adev->mode_info.num_dig = 6; 5031 break; 5032 case CHIP_FIJI: 5033 case CHIP_TONGA: 5034 adev->mode_info.num_crtc = 6; 5035 adev->mode_info.num_hpd = 6; 5036 adev->mode_info.num_dig = 7; 5037 break; 5038 case CHIP_CARRIZO: 5039 adev->mode_info.num_crtc = 3; 5040 adev->mode_info.num_hpd = 6; 5041 adev->mode_info.num_dig = 9; 5042 break; 5043 case CHIP_STONEY: 5044 adev->mode_info.num_crtc = 2; 5045 adev->mode_info.num_hpd = 6; 5046 adev->mode_info.num_dig = 9; 5047 break; 5048 case CHIP_POLARIS11: 5049 case CHIP_POLARIS12: 5050 adev->mode_info.num_crtc = 5; 5051 adev->mode_info.num_hpd = 5; 5052 adev->mode_info.num_dig = 5; 5053 break; 5054 case CHIP_POLARIS10: 5055 case CHIP_VEGAM: 5056 adev->mode_info.num_crtc = 6; 5057 adev->mode_info.num_hpd = 6; 5058 adev->mode_info.num_dig = 6; 5059 break; 5060 case CHIP_VEGA10: 5061 case CHIP_VEGA12: 5062 case CHIP_VEGA20: 5063 adev->mode_info.num_crtc = 6; 5064 adev->mode_info.num_hpd = 6; 5065 adev->mode_info.num_dig = 6; 5066 break; 5067 default: 5068 5069 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 5070 case IP_VERSION(2, 0, 2): 5071 case IP_VERSION(3, 0, 0): 5072 adev->mode_info.num_crtc = 6; 5073 adev->mode_info.num_hpd = 6; 5074 adev->mode_info.num_dig = 6; 5075 break; 5076 case IP_VERSION(2, 0, 0): 5077 case IP_VERSION(3, 0, 2): 5078 adev->mode_info.num_crtc = 5; 5079 adev->mode_info.num_hpd = 5; 5080 adev->mode_info.num_dig = 5; 5081 break; 5082 case IP_VERSION(2, 0, 3): 5083 case IP_VERSION(3, 0, 3): 5084 adev->mode_info.num_crtc = 2; 5085 adev->mode_info.num_hpd = 2; 5086 adev->mode_info.num_dig = 2; 5087 break; 5088 case IP_VERSION(1, 0, 0): 5089 case IP_VERSION(1, 0, 1): 5090 case IP_VERSION(3, 0, 1): 5091 case IP_VERSION(2, 1, 0): 5092 case IP_VERSION(3, 1, 2): 5093 case IP_VERSION(3, 1, 3): 5094 case IP_VERSION(3, 1, 4): 5095 case IP_VERSION(3, 1, 5): 5096 case IP_VERSION(3, 1, 6): 5097 case IP_VERSION(3, 2, 0): 5098 case IP_VERSION(3, 2, 1): 5099 case IP_VERSION(3, 5, 0): 5100 case IP_VERSION(3, 5, 1): 5101 case IP_VERSION(4, 0, 1): 5102 adev->mode_info.num_crtc = 4; 5103 adev->mode_info.num_hpd = 4; 5104 adev->mode_info.num_dig = 4; 5105 break; 5106 default: 5107 DRM_ERROR("Unsupported DCE IP versions: 0x%x\n", 5108 amdgpu_ip_version(adev, DCE_HWIP, 0)); 5109 return -EINVAL; 5110 } 5111 break; 5112 } 5113 5114 if (adev->mode_info.funcs == NULL) 5115 adev->mode_info.funcs = &dm_display_funcs; 5116 5117 /* 5118 * Note: Do NOT change adev->audio_endpt_rreg and 5119 * adev->audio_endpt_wreg because they are initialised in 5120 * amdgpu_device_init() 5121 */ 5122 #if defined(CONFIG_DEBUG_KERNEL_DC) 5123 device_create_file( 5124 adev_to_drm(adev)->dev, 5125 &dev_attr_s3_debug); 5126 #endif 5127 adev->dc_enabled = true; 5128 5129 return dm_init_microcode(adev); 5130 } 5131 5132 static bool modereset_required(struct drm_crtc_state *crtc_state) 5133 { 5134 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 5135 } 5136 5137 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 5138 { 5139 drm_encoder_cleanup(encoder); 5140 kfree(encoder); 5141 } 5142 5143 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 5144 .destroy = amdgpu_dm_encoder_destroy, 5145 }; 5146 5147 static int 5148 fill_plane_color_attributes(const struct drm_plane_state *plane_state, 5149 const enum surface_pixel_format format, 5150 enum dc_color_space *color_space) 5151 { 5152 bool full_range; 5153 5154 *color_space = COLOR_SPACE_SRGB; 5155 5156 /* DRM color properties only affect non-RGB formats. */ 5157 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 5158 return 0; 5159 5160 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); 5161 5162 switch (plane_state->color_encoding) { 5163 case DRM_COLOR_YCBCR_BT601: 5164 if (full_range) 5165 *color_space = COLOR_SPACE_YCBCR601; 5166 else 5167 *color_space = COLOR_SPACE_YCBCR601_LIMITED; 5168 break; 5169 5170 case DRM_COLOR_YCBCR_BT709: 5171 if (full_range) 5172 *color_space = COLOR_SPACE_YCBCR709; 5173 else 5174 *color_space = COLOR_SPACE_YCBCR709_LIMITED; 5175 break; 5176 5177 case DRM_COLOR_YCBCR_BT2020: 5178 if (full_range) 5179 *color_space = COLOR_SPACE_2020_YCBCR; 5180 else 5181 return -EINVAL; 5182 break; 5183 5184 default: 5185 return -EINVAL; 5186 } 5187 5188 return 0; 5189 } 5190 5191 static int 5192 fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 5193 const struct drm_plane_state *plane_state, 5194 const u64 tiling_flags, 5195 struct dc_plane_info *plane_info, 5196 struct dc_plane_address *address, 5197 bool tmz_surface, 5198 bool force_disable_dcc) 5199 { 5200 const struct drm_framebuffer *fb = plane_state->fb; 5201 const struct amdgpu_framebuffer *afb = 5202 to_amdgpu_framebuffer(plane_state->fb); 5203 int ret; 5204 5205 memset(plane_info, 0, sizeof(*plane_info)); 5206 5207 switch (fb->format->format) { 5208 case DRM_FORMAT_C8: 5209 plane_info->format = 5210 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 5211 break; 5212 case DRM_FORMAT_RGB565: 5213 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 5214 break; 5215 case DRM_FORMAT_XRGB8888: 5216 case DRM_FORMAT_ARGB8888: 5217 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 5218 break; 5219 case DRM_FORMAT_XRGB2101010: 5220 case DRM_FORMAT_ARGB2101010: 5221 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 5222 break; 5223 case DRM_FORMAT_XBGR2101010: 5224 case DRM_FORMAT_ABGR2101010: 5225 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 5226 break; 5227 case DRM_FORMAT_XBGR8888: 5228 case DRM_FORMAT_ABGR8888: 5229 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 5230 break; 5231 case DRM_FORMAT_NV21: 5232 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 5233 break; 5234 case DRM_FORMAT_NV12: 5235 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 5236 break; 5237 case DRM_FORMAT_P010: 5238 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; 5239 break; 5240 case DRM_FORMAT_XRGB16161616F: 5241 case DRM_FORMAT_ARGB16161616F: 5242 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; 5243 break; 5244 case DRM_FORMAT_XBGR16161616F: 5245 case DRM_FORMAT_ABGR16161616F: 5246 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; 5247 break; 5248 case DRM_FORMAT_XRGB16161616: 5249 case DRM_FORMAT_ARGB16161616: 5250 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; 5251 break; 5252 case DRM_FORMAT_XBGR16161616: 5253 case DRM_FORMAT_ABGR16161616: 5254 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; 5255 break; 5256 default: 5257 DRM_ERROR( 5258 "Unsupported screen format %p4cc\n", 5259 &fb->format->format); 5260 return -EINVAL; 5261 } 5262 5263 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 5264 case DRM_MODE_ROTATE_0: 5265 plane_info->rotation = ROTATION_ANGLE_0; 5266 break; 5267 case DRM_MODE_ROTATE_90: 5268 plane_info->rotation = ROTATION_ANGLE_90; 5269 break; 5270 case DRM_MODE_ROTATE_180: 5271 plane_info->rotation = ROTATION_ANGLE_180; 5272 break; 5273 case DRM_MODE_ROTATE_270: 5274 plane_info->rotation = ROTATION_ANGLE_270; 5275 break; 5276 default: 5277 plane_info->rotation = ROTATION_ANGLE_0; 5278 break; 5279 } 5280 5281 5282 plane_info->visible = true; 5283 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; 5284 5285 plane_info->layer_index = plane_state->normalized_zpos; 5286 5287 ret = fill_plane_color_attributes(plane_state, plane_info->format, 5288 &plane_info->color_space); 5289 if (ret) 5290 return ret; 5291 5292 ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format, 5293 plane_info->rotation, tiling_flags, 5294 &plane_info->tiling_info, 5295 &plane_info->plane_size, 5296 &plane_info->dcc, address, 5297 tmz_surface, force_disable_dcc); 5298 if (ret) 5299 return ret; 5300 5301 amdgpu_dm_plane_fill_blending_from_plane_state( 5302 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha, 5303 &plane_info->global_alpha, &plane_info->global_alpha_value); 5304 5305 return 0; 5306 } 5307 5308 static int fill_dc_plane_attributes(struct amdgpu_device *adev, 5309 struct dc_plane_state *dc_plane_state, 5310 struct drm_plane_state *plane_state, 5311 struct drm_crtc_state *crtc_state) 5312 { 5313 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 5314 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; 5315 struct dc_scaling_info scaling_info; 5316 struct dc_plane_info plane_info; 5317 int ret; 5318 bool force_disable_dcc = false; 5319 5320 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info); 5321 if (ret) 5322 return ret; 5323 5324 dc_plane_state->src_rect = scaling_info.src_rect; 5325 dc_plane_state->dst_rect = scaling_info.dst_rect; 5326 dc_plane_state->clip_rect = scaling_info.clip_rect; 5327 dc_plane_state->scaling_quality = scaling_info.scaling_quality; 5328 5329 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend; 5330 ret = fill_dc_plane_info_and_addr(adev, plane_state, 5331 afb->tiling_flags, 5332 &plane_info, 5333 &dc_plane_state->address, 5334 afb->tmz_surface, 5335 force_disable_dcc); 5336 if (ret) 5337 return ret; 5338 5339 dc_plane_state->format = plane_info.format; 5340 dc_plane_state->color_space = plane_info.color_space; 5341 dc_plane_state->format = plane_info.format; 5342 dc_plane_state->plane_size = plane_info.plane_size; 5343 dc_plane_state->rotation = plane_info.rotation; 5344 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; 5345 dc_plane_state->stereo_format = plane_info.stereo_format; 5346 dc_plane_state->tiling_info = plane_info.tiling_info; 5347 dc_plane_state->visible = plane_info.visible; 5348 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 5349 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha; 5350 dc_plane_state->global_alpha = plane_info.global_alpha; 5351 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 5352 dc_plane_state->dcc = plane_info.dcc; 5353 dc_plane_state->layer_index = plane_info.layer_index; 5354 dc_plane_state->flip_int_enabled = true; 5355 5356 /* 5357 * Always set input transfer function, since plane state is refreshed 5358 * every time. 5359 */ 5360 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, 5361 plane_state, 5362 dc_plane_state); 5363 if (ret) 5364 return ret; 5365 5366 return 0; 5367 } 5368 5369 static inline void fill_dc_dirty_rect(struct drm_plane *plane, 5370 struct rect *dirty_rect, int32_t x, 5371 s32 y, s32 width, s32 height, 5372 int *i, bool ffu) 5373 { 5374 WARN_ON(*i >= DC_MAX_DIRTY_RECTS); 5375 5376 dirty_rect->x = x; 5377 dirty_rect->y = y; 5378 dirty_rect->width = width; 5379 dirty_rect->height = height; 5380 5381 if (ffu) 5382 drm_dbg(plane->dev, 5383 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n", 5384 plane->base.id, width, height); 5385 else 5386 drm_dbg(plane->dev, 5387 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)", 5388 plane->base.id, x, y, width, height); 5389 5390 (*i)++; 5391 } 5392 5393 /** 5394 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates 5395 * 5396 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP 5397 * remote fb 5398 * @old_plane_state: Old state of @plane 5399 * @new_plane_state: New state of @plane 5400 * @crtc_state: New state of CRTC connected to the @plane 5401 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects 5402 * @is_psr_su: Flag indicating whether Panel Self Refresh Selective Update (PSR SU) is enabled. 5403 * If PSR SU is enabled and damage clips are available, only the regions of the screen 5404 * that have changed will be updated. If PSR SU is not enabled, 5405 * or if damage clips are not available, the entire screen will be updated. 5406 * @dirty_regions_changed: dirty regions changed 5407 * 5408 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions 5409 * (referred to as "damage clips" in DRM nomenclature) that require updating on 5410 * the eDP remote buffer. The responsibility of specifying the dirty regions is 5411 * amdgpu_dm's. 5412 * 5413 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the 5414 * plane with regions that require flushing to the eDP remote buffer. In 5415 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - 5416 * implicitly provide damage clips without any client support via the plane 5417 * bounds. 5418 */ 5419 static void fill_dc_dirty_rects(struct drm_plane *plane, 5420 struct drm_plane_state *old_plane_state, 5421 struct drm_plane_state *new_plane_state, 5422 struct drm_crtc_state *crtc_state, 5423 struct dc_flip_addrs *flip_addrs, 5424 bool is_psr_su, 5425 bool *dirty_regions_changed) 5426 { 5427 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 5428 struct rect *dirty_rects = flip_addrs->dirty_rects; 5429 u32 num_clips; 5430 struct drm_mode_rect *clips; 5431 bool bb_changed; 5432 bool fb_changed; 5433 u32 i = 0; 5434 *dirty_regions_changed = false; 5435 5436 /* 5437 * Cursor plane has it's own dirty rect update interface. See 5438 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data 5439 */ 5440 if (plane->type == DRM_PLANE_TYPE_CURSOR) 5441 return; 5442 5443 if (new_plane_state->rotation != DRM_MODE_ROTATE_0) 5444 goto ffu; 5445 5446 num_clips = drm_plane_get_damage_clips_count(new_plane_state); 5447 clips = drm_plane_get_damage_clips(new_plane_state); 5448 5449 if (num_clips && (!amdgpu_damage_clips || (amdgpu_damage_clips < 0 && 5450 is_psr_su))) 5451 goto ffu; 5452 5453 if (!dm_crtc_state->mpo_requested) { 5454 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS) 5455 goto ffu; 5456 5457 for (; flip_addrs->dirty_rect_count < num_clips; clips++) 5458 fill_dc_dirty_rect(new_plane_state->plane, 5459 &dirty_rects[flip_addrs->dirty_rect_count], 5460 clips->x1, clips->y1, 5461 clips->x2 - clips->x1, clips->y2 - clips->y1, 5462 &flip_addrs->dirty_rect_count, 5463 false); 5464 return; 5465 } 5466 5467 /* 5468 * MPO is requested. Add entire plane bounding box to dirty rects if 5469 * flipped to or damaged. 5470 * 5471 * If plane is moved or resized, also add old bounding box to dirty 5472 * rects. 5473 */ 5474 fb_changed = old_plane_state->fb->base.id != 5475 new_plane_state->fb->base.id; 5476 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x || 5477 old_plane_state->crtc_y != new_plane_state->crtc_y || 5478 old_plane_state->crtc_w != new_plane_state->crtc_w || 5479 old_plane_state->crtc_h != new_plane_state->crtc_h); 5480 5481 drm_dbg(plane->dev, 5482 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n", 5483 new_plane_state->plane->base.id, 5484 bb_changed, fb_changed, num_clips); 5485 5486 *dirty_regions_changed = bb_changed; 5487 5488 if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS) 5489 goto ffu; 5490 5491 if (bb_changed) { 5492 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 5493 new_plane_state->crtc_x, 5494 new_plane_state->crtc_y, 5495 new_plane_state->crtc_w, 5496 new_plane_state->crtc_h, &i, false); 5497 5498 /* Add old plane bounding-box if plane is moved or resized */ 5499 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 5500 old_plane_state->crtc_x, 5501 old_plane_state->crtc_y, 5502 old_plane_state->crtc_w, 5503 old_plane_state->crtc_h, &i, false); 5504 } 5505 5506 if (num_clips) { 5507 for (; i < num_clips; clips++) 5508 fill_dc_dirty_rect(new_plane_state->plane, 5509 &dirty_rects[i], clips->x1, 5510 clips->y1, clips->x2 - clips->x1, 5511 clips->y2 - clips->y1, &i, false); 5512 } else if (fb_changed && !bb_changed) { 5513 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 5514 new_plane_state->crtc_x, 5515 new_plane_state->crtc_y, 5516 new_plane_state->crtc_w, 5517 new_plane_state->crtc_h, &i, false); 5518 } 5519 5520 flip_addrs->dirty_rect_count = i; 5521 return; 5522 5523 ffu: 5524 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0, 5525 dm_crtc_state->base.mode.crtc_hdisplay, 5526 dm_crtc_state->base.mode.crtc_vdisplay, 5527 &flip_addrs->dirty_rect_count, true); 5528 } 5529 5530 static void update_stream_scaling_settings(const struct drm_display_mode *mode, 5531 const struct dm_connector_state *dm_state, 5532 struct dc_stream_state *stream) 5533 { 5534 enum amdgpu_rmx_type rmx_type; 5535 5536 struct rect src = { 0 }; /* viewport in composition space*/ 5537 struct rect dst = { 0 }; /* stream addressable area */ 5538 5539 /* no mode. nothing to be done */ 5540 if (!mode) 5541 return; 5542 5543 /* Full screen scaling by default */ 5544 src.width = mode->hdisplay; 5545 src.height = mode->vdisplay; 5546 dst.width = stream->timing.h_addressable; 5547 dst.height = stream->timing.v_addressable; 5548 5549 if (dm_state) { 5550 rmx_type = dm_state->scaling; 5551 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 5552 if (src.width * dst.height < 5553 src.height * dst.width) { 5554 /* height needs less upscaling/more downscaling */ 5555 dst.width = src.width * 5556 dst.height / src.height; 5557 } else { 5558 /* width needs less upscaling/more downscaling */ 5559 dst.height = src.height * 5560 dst.width / src.width; 5561 } 5562 } else if (rmx_type == RMX_CENTER) { 5563 dst = src; 5564 } 5565 5566 dst.x = (stream->timing.h_addressable - dst.width) / 2; 5567 dst.y = (stream->timing.v_addressable - dst.height) / 2; 5568 5569 if (dm_state->underscan_enable) { 5570 dst.x += dm_state->underscan_hborder / 2; 5571 dst.y += dm_state->underscan_vborder / 2; 5572 dst.width -= dm_state->underscan_hborder; 5573 dst.height -= dm_state->underscan_vborder; 5574 } 5575 } 5576 5577 stream->src = src; 5578 stream->dst = dst; 5579 5580 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n", 5581 dst.x, dst.y, dst.width, dst.height); 5582 5583 } 5584 5585 static enum dc_color_depth 5586 convert_color_depth_from_display_info(const struct drm_connector *connector, 5587 bool is_y420, int requested_bpc) 5588 { 5589 u8 bpc; 5590 5591 if (is_y420) { 5592 bpc = 8; 5593 5594 /* Cap display bpc based on HDMI 2.0 HF-VSDB */ 5595 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) 5596 bpc = 16; 5597 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) 5598 bpc = 12; 5599 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) 5600 bpc = 10; 5601 } else { 5602 bpc = (uint8_t)connector->display_info.bpc; 5603 /* Assume 8 bpc by default if no bpc is specified. */ 5604 bpc = bpc ? bpc : 8; 5605 } 5606 5607 if (requested_bpc > 0) { 5608 /* 5609 * Cap display bpc based on the user requested value. 5610 * 5611 * The value for state->max_bpc may not correctly updated 5612 * depending on when the connector gets added to the state 5613 * or if this was called outside of atomic check, so it 5614 * can't be used directly. 5615 */ 5616 bpc = min_t(u8, bpc, requested_bpc); 5617 5618 /* Round down to the nearest even number. */ 5619 bpc = bpc - (bpc & 1); 5620 } 5621 5622 switch (bpc) { 5623 case 0: 5624 /* 5625 * Temporary Work around, DRM doesn't parse color depth for 5626 * EDID revision before 1.4 5627 * TODO: Fix edid parsing 5628 */ 5629 return COLOR_DEPTH_888; 5630 case 6: 5631 return COLOR_DEPTH_666; 5632 case 8: 5633 return COLOR_DEPTH_888; 5634 case 10: 5635 return COLOR_DEPTH_101010; 5636 case 12: 5637 return COLOR_DEPTH_121212; 5638 case 14: 5639 return COLOR_DEPTH_141414; 5640 case 16: 5641 return COLOR_DEPTH_161616; 5642 default: 5643 return COLOR_DEPTH_UNDEFINED; 5644 } 5645 } 5646 5647 static enum dc_aspect_ratio 5648 get_aspect_ratio(const struct drm_display_mode *mode_in) 5649 { 5650 /* 1-1 mapping, since both enums follow the HDMI spec. */ 5651 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; 5652 } 5653 5654 static enum dc_color_space 5655 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, 5656 const struct drm_connector_state *connector_state) 5657 { 5658 enum dc_color_space color_space = COLOR_SPACE_SRGB; 5659 5660 switch (connector_state->colorspace) { 5661 case DRM_MODE_COLORIMETRY_BT601_YCC: 5662 if (dc_crtc_timing->flags.Y_ONLY) 5663 color_space = COLOR_SPACE_YCBCR601_LIMITED; 5664 else 5665 color_space = COLOR_SPACE_YCBCR601; 5666 break; 5667 case DRM_MODE_COLORIMETRY_BT709_YCC: 5668 if (dc_crtc_timing->flags.Y_ONLY) 5669 color_space = COLOR_SPACE_YCBCR709_LIMITED; 5670 else 5671 color_space = COLOR_SPACE_YCBCR709; 5672 break; 5673 case DRM_MODE_COLORIMETRY_OPRGB: 5674 color_space = COLOR_SPACE_ADOBERGB; 5675 break; 5676 case DRM_MODE_COLORIMETRY_BT2020_RGB: 5677 case DRM_MODE_COLORIMETRY_BT2020_YCC: 5678 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) 5679 color_space = COLOR_SPACE_2020_RGB_FULLRANGE; 5680 else 5681 color_space = COLOR_SPACE_2020_YCBCR; 5682 break; 5683 case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601 5684 default: 5685 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) { 5686 color_space = COLOR_SPACE_SRGB; 5687 /* 5688 * 27030khz is the separation point between HDTV and SDTV 5689 * according to HDMI spec, we use YCbCr709 and YCbCr601 5690 * respectively 5691 */ 5692 } else if (dc_crtc_timing->pix_clk_100hz > 270300) { 5693 if (dc_crtc_timing->flags.Y_ONLY) 5694 color_space = 5695 COLOR_SPACE_YCBCR709_LIMITED; 5696 else 5697 color_space = COLOR_SPACE_YCBCR709; 5698 } else { 5699 if (dc_crtc_timing->flags.Y_ONLY) 5700 color_space = 5701 COLOR_SPACE_YCBCR601_LIMITED; 5702 else 5703 color_space = COLOR_SPACE_YCBCR601; 5704 } 5705 break; 5706 } 5707 5708 return color_space; 5709 } 5710 5711 static enum display_content_type 5712 get_output_content_type(const struct drm_connector_state *connector_state) 5713 { 5714 switch (connector_state->content_type) { 5715 default: 5716 case DRM_MODE_CONTENT_TYPE_NO_DATA: 5717 return DISPLAY_CONTENT_TYPE_NO_DATA; 5718 case DRM_MODE_CONTENT_TYPE_GRAPHICS: 5719 return DISPLAY_CONTENT_TYPE_GRAPHICS; 5720 case DRM_MODE_CONTENT_TYPE_PHOTO: 5721 return DISPLAY_CONTENT_TYPE_PHOTO; 5722 case DRM_MODE_CONTENT_TYPE_CINEMA: 5723 return DISPLAY_CONTENT_TYPE_CINEMA; 5724 case DRM_MODE_CONTENT_TYPE_GAME: 5725 return DISPLAY_CONTENT_TYPE_GAME; 5726 } 5727 } 5728 5729 static bool adjust_colour_depth_from_display_info( 5730 struct dc_crtc_timing *timing_out, 5731 const struct drm_display_info *info) 5732 { 5733 enum dc_color_depth depth = timing_out->display_color_depth; 5734 int normalized_clk; 5735 5736 do { 5737 normalized_clk = timing_out->pix_clk_100hz / 10; 5738 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 5739 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 5740 normalized_clk /= 2; 5741 /* Adjusting pix clock following on HDMI spec based on colour depth */ 5742 switch (depth) { 5743 case COLOR_DEPTH_888: 5744 break; 5745 case COLOR_DEPTH_101010: 5746 normalized_clk = (normalized_clk * 30) / 24; 5747 break; 5748 case COLOR_DEPTH_121212: 5749 normalized_clk = (normalized_clk * 36) / 24; 5750 break; 5751 case COLOR_DEPTH_161616: 5752 normalized_clk = (normalized_clk * 48) / 24; 5753 break; 5754 default: 5755 /* The above depths are the only ones valid for HDMI. */ 5756 return false; 5757 } 5758 if (normalized_clk <= info->max_tmds_clock) { 5759 timing_out->display_color_depth = depth; 5760 return true; 5761 } 5762 } while (--depth > COLOR_DEPTH_666); 5763 return false; 5764 } 5765 5766 static void fill_stream_properties_from_drm_display_mode( 5767 struct dc_stream_state *stream, 5768 const struct drm_display_mode *mode_in, 5769 const struct drm_connector *connector, 5770 const struct drm_connector_state *connector_state, 5771 const struct dc_stream_state *old_stream, 5772 int requested_bpc) 5773 { 5774 struct dc_crtc_timing *timing_out = &stream->timing; 5775 const struct drm_display_info *info = &connector->display_info; 5776 struct amdgpu_dm_connector *aconnector = NULL; 5777 struct hdmi_vendor_infoframe hv_frame; 5778 struct hdmi_avi_infoframe avi_frame; 5779 5780 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 5781 aconnector = to_amdgpu_dm_connector(connector); 5782 5783 memset(&hv_frame, 0, sizeof(hv_frame)); 5784 memset(&avi_frame, 0, sizeof(avi_frame)); 5785 5786 timing_out->h_border_left = 0; 5787 timing_out->h_border_right = 0; 5788 timing_out->v_border_top = 0; 5789 timing_out->v_border_bottom = 0; 5790 /* TODO: un-hardcode */ 5791 if (drm_mode_is_420_only(info, mode_in) 5792 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 5793 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5794 else if (drm_mode_is_420_also(info, mode_in) 5795 && aconnector 5796 && aconnector->force_yuv420_output) 5797 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5798 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444) 5799 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 5800 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; 5801 else 5802 timing_out->pixel_encoding = PIXEL_ENCODING_RGB; 5803 5804 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; 5805 timing_out->display_color_depth = convert_color_depth_from_display_info( 5806 connector, 5807 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420), 5808 requested_bpc); 5809 timing_out->scan_type = SCANNING_TYPE_NODATA; 5810 timing_out->hdmi_vic = 0; 5811 5812 if (old_stream) { 5813 timing_out->vic = old_stream->timing.vic; 5814 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; 5815 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; 5816 } else { 5817 timing_out->vic = drm_match_cea_mode(mode_in); 5818 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) 5819 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; 5820 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) 5821 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; 5822 } 5823 5824 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 5825 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in); 5826 timing_out->vic = avi_frame.video_code; 5827 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in); 5828 timing_out->hdmi_vic = hv_frame.vic; 5829 } 5830 5831 if (aconnector && is_freesync_video_mode(mode_in, aconnector)) { 5832 timing_out->h_addressable = mode_in->hdisplay; 5833 timing_out->h_total = mode_in->htotal; 5834 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start; 5835 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay; 5836 timing_out->v_total = mode_in->vtotal; 5837 timing_out->v_addressable = mode_in->vdisplay; 5838 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay; 5839 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start; 5840 timing_out->pix_clk_100hz = mode_in->clock * 10; 5841 } else { 5842 timing_out->h_addressable = mode_in->crtc_hdisplay; 5843 timing_out->h_total = mode_in->crtc_htotal; 5844 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; 5845 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; 5846 timing_out->v_total = mode_in->crtc_vtotal; 5847 timing_out->v_addressable = mode_in->crtc_vdisplay; 5848 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; 5849 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; 5850 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; 5851 } 5852 5853 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 5854 5855 stream->out_transfer_func.type = TF_TYPE_PREDEFINED; 5856 stream->out_transfer_func.tf = TRANSFER_FUNCTION_SRGB; 5857 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 5858 if (!adjust_colour_depth_from_display_info(timing_out, info) && 5859 drm_mode_is_420_also(info, mode_in) && 5860 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) { 5861 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5862 adjust_colour_depth_from_display_info(timing_out, info); 5863 } 5864 } 5865 5866 stream->output_color_space = get_output_color_space(timing_out, connector_state); 5867 stream->content_type = get_output_content_type(connector_state); 5868 } 5869 5870 static void fill_audio_info(struct audio_info *audio_info, 5871 const struct drm_connector *drm_connector, 5872 const struct dc_sink *dc_sink) 5873 { 5874 int i = 0; 5875 int cea_revision = 0; 5876 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; 5877 5878 audio_info->manufacture_id = edid_caps->manufacturer_id; 5879 audio_info->product_id = edid_caps->product_id; 5880 5881 cea_revision = drm_connector->display_info.cea_rev; 5882 5883 strscpy(audio_info->display_name, 5884 edid_caps->display_name, 5885 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 5886 5887 if (cea_revision >= 3) { 5888 audio_info->mode_count = edid_caps->audio_mode_count; 5889 5890 for (i = 0; i < audio_info->mode_count; ++i) { 5891 audio_info->modes[i].format_code = 5892 (enum audio_format_code) 5893 (edid_caps->audio_modes[i].format_code); 5894 audio_info->modes[i].channel_count = 5895 edid_caps->audio_modes[i].channel_count; 5896 audio_info->modes[i].sample_rates.all = 5897 edid_caps->audio_modes[i].sample_rate; 5898 audio_info->modes[i].sample_size = 5899 edid_caps->audio_modes[i].sample_size; 5900 } 5901 } 5902 5903 audio_info->flags.all = edid_caps->speaker_flags; 5904 5905 /* TODO: We only check for the progressive mode, check for interlace mode too */ 5906 if (drm_connector->latency_present[0]) { 5907 audio_info->video_latency = drm_connector->video_latency[0]; 5908 audio_info->audio_latency = drm_connector->audio_latency[0]; 5909 } 5910 5911 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ 5912 5913 } 5914 5915 static void 5916 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 5917 struct drm_display_mode *dst_mode) 5918 { 5919 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; 5920 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; 5921 dst_mode->crtc_clock = src_mode->crtc_clock; 5922 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; 5923 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; 5924 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; 5925 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; 5926 dst_mode->crtc_htotal = src_mode->crtc_htotal; 5927 dst_mode->crtc_hskew = src_mode->crtc_hskew; 5928 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; 5929 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; 5930 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; 5931 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; 5932 dst_mode->crtc_vtotal = src_mode->crtc_vtotal; 5933 } 5934 5935 static void 5936 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 5937 const struct drm_display_mode *native_mode, 5938 bool scale_enabled) 5939 { 5940 if (scale_enabled) { 5941 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 5942 } else if (native_mode->clock == drm_mode->clock && 5943 native_mode->htotal == drm_mode->htotal && 5944 native_mode->vtotal == drm_mode->vtotal) { 5945 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 5946 } else { 5947 /* no scaling nor amdgpu inserted, no need to patch */ 5948 } 5949 } 5950 5951 static struct dc_sink * 5952 create_fake_sink(struct dc_link *link) 5953 { 5954 struct dc_sink_init_data sink_init_data = { 0 }; 5955 struct dc_sink *sink = NULL; 5956 5957 sink_init_data.link = link; 5958 sink_init_data.sink_signal = link->connector_signal; 5959 5960 sink = dc_sink_create(&sink_init_data); 5961 if (!sink) { 5962 DRM_ERROR("Failed to create sink!\n"); 5963 return NULL; 5964 } 5965 sink->sink_signal = SIGNAL_TYPE_VIRTUAL; 5966 5967 return sink; 5968 } 5969 5970 static void set_multisync_trigger_params( 5971 struct dc_stream_state *stream) 5972 { 5973 struct dc_stream_state *master = NULL; 5974 5975 if (stream->triggered_crtc_reset.enabled) { 5976 master = stream->triggered_crtc_reset.event_source; 5977 stream->triggered_crtc_reset.event = 5978 master->timing.flags.VSYNC_POSITIVE_POLARITY ? 5979 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING; 5980 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; 5981 } 5982 } 5983 5984 static void set_master_stream(struct dc_stream_state *stream_set[], 5985 int stream_count) 5986 { 5987 int j, highest_rfr = 0, master_stream = 0; 5988 5989 for (j = 0; j < stream_count; j++) { 5990 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 5991 int refresh_rate = 0; 5992 5993 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 5994 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 5995 if (refresh_rate > highest_rfr) { 5996 highest_rfr = refresh_rate; 5997 master_stream = j; 5998 } 5999 } 6000 } 6001 for (j = 0; j < stream_count; j++) { 6002 if (stream_set[j]) 6003 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 6004 } 6005 } 6006 6007 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 6008 { 6009 int i = 0; 6010 struct dc_stream_state *stream; 6011 6012 if (context->stream_count < 2) 6013 return; 6014 for (i = 0; i < context->stream_count ; i++) { 6015 if (!context->streams[i]) 6016 continue; 6017 /* 6018 * TODO: add a function to read AMD VSDB bits and set 6019 * crtc_sync_master.multi_sync_enabled flag 6020 * For now it's set to false 6021 */ 6022 } 6023 6024 set_master_stream(context->streams, context->stream_count); 6025 6026 for (i = 0; i < context->stream_count ; i++) { 6027 stream = context->streams[i]; 6028 6029 if (!stream) 6030 continue; 6031 6032 set_multisync_trigger_params(stream); 6033 } 6034 } 6035 6036 /** 6037 * DOC: FreeSync Video 6038 * 6039 * When a userspace application wants to play a video, the content follows a 6040 * standard format definition that usually specifies the FPS for that format. 6041 * The below list illustrates some video format and the expected FPS, 6042 * respectively: 6043 * 6044 * - TV/NTSC (23.976 FPS) 6045 * - Cinema (24 FPS) 6046 * - TV/PAL (25 FPS) 6047 * - TV/NTSC (29.97 FPS) 6048 * - TV/NTSC (30 FPS) 6049 * - Cinema HFR (48 FPS) 6050 * - TV/PAL (50 FPS) 6051 * - Commonly used (60 FPS) 6052 * - Multiples of 24 (48,72,96 FPS) 6053 * 6054 * The list of standards video format is not huge and can be added to the 6055 * connector modeset list beforehand. With that, userspace can leverage 6056 * FreeSync to extends the front porch in order to attain the target refresh 6057 * rate. Such a switch will happen seamlessly, without screen blanking or 6058 * reprogramming of the output in any other way. If the userspace requests a 6059 * modesetting change compatible with FreeSync modes that only differ in the 6060 * refresh rate, DC will skip the full update and avoid blink during the 6061 * transition. For example, the video player can change the modesetting from 6062 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without 6063 * causing any display blink. This same concept can be applied to a mode 6064 * setting change. 6065 */ 6066 static struct drm_display_mode * 6067 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, 6068 bool use_probed_modes) 6069 { 6070 struct drm_display_mode *m, *m_pref = NULL; 6071 u16 current_refresh, highest_refresh; 6072 struct list_head *list_head = use_probed_modes ? 6073 &aconnector->base.probed_modes : 6074 &aconnector->base.modes; 6075 6076 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 6077 return NULL; 6078 6079 if (aconnector->freesync_vid_base.clock != 0) 6080 return &aconnector->freesync_vid_base; 6081 6082 /* Find the preferred mode */ 6083 list_for_each_entry(m, list_head, head) { 6084 if (m->type & DRM_MODE_TYPE_PREFERRED) { 6085 m_pref = m; 6086 break; 6087 } 6088 } 6089 6090 if (!m_pref) { 6091 /* Probably an EDID with no preferred mode. Fallback to first entry */ 6092 m_pref = list_first_entry_or_null( 6093 &aconnector->base.modes, struct drm_display_mode, head); 6094 if (!m_pref) { 6095 DRM_DEBUG_DRIVER("No preferred mode found in EDID\n"); 6096 return NULL; 6097 } 6098 } 6099 6100 highest_refresh = drm_mode_vrefresh(m_pref); 6101 6102 /* 6103 * Find the mode with highest refresh rate with same resolution. 6104 * For some monitors, preferred mode is not the mode with highest 6105 * supported refresh rate. 6106 */ 6107 list_for_each_entry(m, list_head, head) { 6108 current_refresh = drm_mode_vrefresh(m); 6109 6110 if (m->hdisplay == m_pref->hdisplay && 6111 m->vdisplay == m_pref->vdisplay && 6112 highest_refresh < current_refresh) { 6113 highest_refresh = current_refresh; 6114 m_pref = m; 6115 } 6116 } 6117 6118 drm_mode_copy(&aconnector->freesync_vid_base, m_pref); 6119 return m_pref; 6120 } 6121 6122 static bool is_freesync_video_mode(const struct drm_display_mode *mode, 6123 struct amdgpu_dm_connector *aconnector) 6124 { 6125 struct drm_display_mode *high_mode; 6126 int timing_diff; 6127 6128 high_mode = get_highest_refresh_rate_mode(aconnector, false); 6129 if (!high_mode || !mode) 6130 return false; 6131 6132 timing_diff = high_mode->vtotal - mode->vtotal; 6133 6134 if (high_mode->clock == 0 || high_mode->clock != mode->clock || 6135 high_mode->hdisplay != mode->hdisplay || 6136 high_mode->vdisplay != mode->vdisplay || 6137 high_mode->hsync_start != mode->hsync_start || 6138 high_mode->hsync_end != mode->hsync_end || 6139 high_mode->htotal != mode->htotal || 6140 high_mode->hskew != mode->hskew || 6141 high_mode->vscan != mode->vscan || 6142 high_mode->vsync_start - mode->vsync_start != timing_diff || 6143 high_mode->vsync_end - mode->vsync_end != timing_diff) 6144 return false; 6145 else 6146 return true; 6147 } 6148 6149 #if defined(CONFIG_DRM_AMD_DC_FP) 6150 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector, 6151 struct dc_sink *sink, struct dc_stream_state *stream, 6152 struct dsc_dec_dpcd_caps *dsc_caps) 6153 { 6154 stream->timing.flags.DSC = 0; 6155 dsc_caps->is_dsc_supported = false; 6156 6157 if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || 6158 sink->sink_signal == SIGNAL_TYPE_EDP)) { 6159 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE || 6160 sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) 6161 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 6162 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, 6163 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, 6164 dsc_caps); 6165 } 6166 } 6167 6168 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector, 6169 struct dc_sink *sink, struct dc_stream_state *stream, 6170 struct dsc_dec_dpcd_caps *dsc_caps, 6171 uint32_t max_dsc_target_bpp_limit_override) 6172 { 6173 const struct dc_link_settings *verified_link_cap = NULL; 6174 u32 link_bw_in_kbps; 6175 u32 edp_min_bpp_x16, edp_max_bpp_x16; 6176 struct dc *dc = sink->ctx->dc; 6177 struct dc_dsc_bw_range bw_range = {0}; 6178 struct dc_dsc_config dsc_cfg = {0}; 6179 struct dc_dsc_config_options dsc_options = {0}; 6180 6181 dc_dsc_get_default_config_option(dc, &dsc_options); 6182 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; 6183 6184 verified_link_cap = dc_link_get_link_cap(stream->link); 6185 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap); 6186 edp_min_bpp_x16 = 8 * 16; 6187 edp_max_bpp_x16 = 8 * 16; 6188 6189 if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel) 6190 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel; 6191 6192 if (edp_max_bpp_x16 < edp_min_bpp_x16) 6193 edp_min_bpp_x16 = edp_max_bpp_x16; 6194 6195 if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0], 6196 dc->debug.dsc_min_slice_height_override, 6197 edp_min_bpp_x16, edp_max_bpp_x16, 6198 dsc_caps, 6199 &stream->timing, 6200 dc_link_get_highest_encoding_format(aconnector->dc_link), 6201 &bw_range)) { 6202 6203 if (bw_range.max_kbps < link_bw_in_kbps) { 6204 if (dc_dsc_compute_config(dc->res_pool->dscs[0], 6205 dsc_caps, 6206 &dsc_options, 6207 0, 6208 &stream->timing, 6209 dc_link_get_highest_encoding_format(aconnector->dc_link), 6210 &dsc_cfg)) { 6211 stream->timing.dsc_cfg = dsc_cfg; 6212 stream->timing.flags.DSC = 1; 6213 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16; 6214 } 6215 return; 6216 } 6217 } 6218 6219 if (dc_dsc_compute_config(dc->res_pool->dscs[0], 6220 dsc_caps, 6221 &dsc_options, 6222 link_bw_in_kbps, 6223 &stream->timing, 6224 dc_link_get_highest_encoding_format(aconnector->dc_link), 6225 &dsc_cfg)) { 6226 stream->timing.dsc_cfg = dsc_cfg; 6227 stream->timing.flags.DSC = 1; 6228 } 6229 } 6230 6231 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, 6232 struct dc_sink *sink, struct dc_stream_state *stream, 6233 struct dsc_dec_dpcd_caps *dsc_caps) 6234 { 6235 struct drm_connector *drm_connector = &aconnector->base; 6236 u32 link_bandwidth_kbps; 6237 struct dc *dc = sink->ctx->dc; 6238 u32 max_supported_bw_in_kbps, timing_bw_in_kbps; 6239 u32 dsc_max_supported_bw_in_kbps; 6240 u32 max_dsc_target_bpp_limit_override = 6241 drm_connector->display_info.max_dsc_bpp; 6242 struct dc_dsc_config_options dsc_options = {0}; 6243 6244 dc_dsc_get_default_config_option(dc, &dsc_options); 6245 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; 6246 6247 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, 6248 dc_link_get_link_cap(aconnector->dc_link)); 6249 6250 /* Set DSC policy according to dsc_clock_en */ 6251 dc_dsc_policy_set_enable_dsc_when_not_needed( 6252 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE); 6253 6254 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP && 6255 !aconnector->dc_link->panel_config.dsc.disable_dsc_edp && 6256 dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) { 6257 6258 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override); 6259 6260 } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { 6261 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { 6262 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 6263 dsc_caps, 6264 &dsc_options, 6265 link_bandwidth_kbps, 6266 &stream->timing, 6267 dc_link_get_highest_encoding_format(aconnector->dc_link), 6268 &stream->timing.dsc_cfg)) { 6269 stream->timing.flags.DSC = 1; 6270 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name); 6271 } 6272 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 6273 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing, 6274 dc_link_get_highest_encoding_format(aconnector->dc_link)); 6275 max_supported_bw_in_kbps = link_bandwidth_kbps; 6276 dsc_max_supported_bw_in_kbps = link_bandwidth_kbps; 6277 6278 if (timing_bw_in_kbps > max_supported_bw_in_kbps && 6279 max_supported_bw_in_kbps > 0 && 6280 dsc_max_supported_bw_in_kbps > 0) 6281 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 6282 dsc_caps, 6283 &dsc_options, 6284 dsc_max_supported_bw_in_kbps, 6285 &stream->timing, 6286 dc_link_get_highest_encoding_format(aconnector->dc_link), 6287 &stream->timing.dsc_cfg)) { 6288 stream->timing.flags.DSC = 1; 6289 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n", 6290 __func__, drm_connector->name); 6291 } 6292 } 6293 } 6294 6295 /* Overwrite the stream flag if DSC is enabled through debugfs */ 6296 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE) 6297 stream->timing.flags.DSC = 1; 6298 6299 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h) 6300 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; 6301 6302 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v) 6303 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; 6304 6305 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel) 6306 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel; 6307 } 6308 #endif 6309 6310 static struct dc_stream_state * 6311 create_stream_for_sink(struct drm_connector *connector, 6312 const struct drm_display_mode *drm_mode, 6313 const struct dm_connector_state *dm_state, 6314 const struct dc_stream_state *old_stream, 6315 int requested_bpc) 6316 { 6317 struct amdgpu_dm_connector *aconnector = NULL; 6318 struct drm_display_mode *preferred_mode = NULL; 6319 const struct drm_connector_state *con_state = &dm_state->base; 6320 struct dc_stream_state *stream = NULL; 6321 struct drm_display_mode mode; 6322 struct drm_display_mode saved_mode; 6323 struct drm_display_mode *freesync_mode = NULL; 6324 bool native_mode_found = false; 6325 bool recalculate_timing = false; 6326 bool scale = dm_state->scaling != RMX_OFF; 6327 int mode_refresh; 6328 int preferred_refresh = 0; 6329 enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN; 6330 #if defined(CONFIG_DRM_AMD_DC_FP) 6331 struct dsc_dec_dpcd_caps dsc_caps; 6332 #endif 6333 struct dc_link *link = NULL; 6334 struct dc_sink *sink = NULL; 6335 6336 drm_mode_init(&mode, drm_mode); 6337 memset(&saved_mode, 0, sizeof(saved_mode)); 6338 6339 if (connector == NULL) { 6340 DRM_ERROR("connector is NULL!\n"); 6341 return stream; 6342 } 6343 6344 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) { 6345 aconnector = NULL; 6346 aconnector = to_amdgpu_dm_connector(connector); 6347 link = aconnector->dc_link; 6348 } else { 6349 struct drm_writeback_connector *wbcon = NULL; 6350 struct amdgpu_dm_wb_connector *dm_wbcon = NULL; 6351 6352 wbcon = drm_connector_to_writeback(connector); 6353 dm_wbcon = to_amdgpu_dm_wb_connector(wbcon); 6354 link = dm_wbcon->link; 6355 } 6356 6357 if (!aconnector || !aconnector->dc_sink) { 6358 sink = create_fake_sink(link); 6359 if (!sink) 6360 return stream; 6361 6362 } else { 6363 sink = aconnector->dc_sink; 6364 dc_sink_retain(sink); 6365 } 6366 6367 stream = dc_create_stream_for_sink(sink); 6368 6369 if (stream == NULL) { 6370 DRM_ERROR("Failed to create stream for sink!\n"); 6371 goto finish; 6372 } 6373 6374 /* We leave this NULL for writeback connectors */ 6375 stream->dm_stream_context = aconnector; 6376 6377 stream->timing.flags.LTE_340MCSC_SCRAMBLE = 6378 connector->display_info.hdmi.scdc.scrambling.low_rates; 6379 6380 list_for_each_entry(preferred_mode, &connector->modes, head) { 6381 /* Search for preferred mode */ 6382 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { 6383 native_mode_found = true; 6384 break; 6385 } 6386 } 6387 if (!native_mode_found) 6388 preferred_mode = list_first_entry_or_null( 6389 &connector->modes, 6390 struct drm_display_mode, 6391 head); 6392 6393 mode_refresh = drm_mode_vrefresh(&mode); 6394 6395 if (preferred_mode == NULL) { 6396 /* 6397 * This may not be an error, the use case is when we have no 6398 * usermode calls to reset and set mode upon hotplug. In this 6399 * case, we call set mode ourselves to restore the previous mode 6400 * and the modelist may not be filled in time. 6401 */ 6402 DRM_DEBUG_DRIVER("No preferred mode found\n"); 6403 } else if (aconnector) { 6404 recalculate_timing = amdgpu_freesync_vid_mode && 6405 is_freesync_video_mode(&mode, aconnector); 6406 if (recalculate_timing) { 6407 freesync_mode = get_highest_refresh_rate_mode(aconnector, false); 6408 drm_mode_copy(&saved_mode, &mode); 6409 saved_mode.picture_aspect_ratio = mode.picture_aspect_ratio; 6410 drm_mode_copy(&mode, freesync_mode); 6411 mode.picture_aspect_ratio = saved_mode.picture_aspect_ratio; 6412 } else { 6413 decide_crtc_timing_for_drm_display_mode( 6414 &mode, preferred_mode, scale); 6415 6416 preferred_refresh = drm_mode_vrefresh(preferred_mode); 6417 } 6418 } 6419 6420 if (recalculate_timing) 6421 drm_mode_set_crtcinfo(&saved_mode, 0); 6422 6423 /* 6424 * If scaling is enabled and refresh rate didn't change 6425 * we copy the vic and polarities of the old timings 6426 */ 6427 if (!scale || mode_refresh != preferred_refresh) 6428 fill_stream_properties_from_drm_display_mode( 6429 stream, &mode, connector, con_state, NULL, 6430 requested_bpc); 6431 else 6432 fill_stream_properties_from_drm_display_mode( 6433 stream, &mode, connector, con_state, old_stream, 6434 requested_bpc); 6435 6436 /* The rest isn't needed for writeback connectors */ 6437 if (!aconnector) 6438 goto finish; 6439 6440 if (aconnector->timing_changed) { 6441 drm_dbg(aconnector->base.dev, 6442 "overriding timing for automated test, bpc %d, changing to %d\n", 6443 stream->timing.display_color_depth, 6444 aconnector->timing_requested->display_color_depth); 6445 stream->timing = *aconnector->timing_requested; 6446 } 6447 6448 #if defined(CONFIG_DRM_AMD_DC_FP) 6449 /* SST DSC determination policy */ 6450 update_dsc_caps(aconnector, sink, stream, &dsc_caps); 6451 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) 6452 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps); 6453 #endif 6454 6455 update_stream_scaling_settings(&mode, dm_state, stream); 6456 6457 fill_audio_info( 6458 &stream->audio_info, 6459 connector, 6460 sink); 6461 6462 update_stream_signal(stream, sink); 6463 6464 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 6465 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket); 6466 6467 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 6468 stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 6469 stream->signal == SIGNAL_TYPE_EDP) { 6470 // 6471 // should decide stream support vsc sdp colorimetry capability 6472 // before building vsc info packet 6473 // 6474 stream->use_vsc_sdp_for_colorimetry = stream->link->dpcd_caps.dpcd_rev.raw >= 0x14 && 6475 stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED; 6476 6477 if (stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) 6478 tf = TRANSFER_FUNC_GAMMA_22; 6479 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf); 6480 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY; 6481 6482 } 6483 finish: 6484 dc_sink_release(sink); 6485 6486 return stream; 6487 } 6488 6489 static enum drm_connector_status 6490 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 6491 { 6492 bool connected; 6493 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6494 6495 /* 6496 * Notes: 6497 * 1. This interface is NOT called in context of HPD irq. 6498 * 2. This interface *is called* in context of user-mode ioctl. Which 6499 * makes it a bad place for *any* MST-related activity. 6500 */ 6501 6502 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && 6503 !aconnector->fake_enable) 6504 connected = (aconnector->dc_sink != NULL); 6505 else 6506 connected = (aconnector->base.force == DRM_FORCE_ON || 6507 aconnector->base.force == DRM_FORCE_ON_DIGITAL); 6508 6509 update_subconnector_property(aconnector); 6510 6511 return (connected ? connector_status_connected : 6512 connector_status_disconnected); 6513 } 6514 6515 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 6516 struct drm_connector_state *connector_state, 6517 struct drm_property *property, 6518 uint64_t val) 6519 { 6520 struct drm_device *dev = connector->dev; 6521 struct amdgpu_device *adev = drm_to_adev(dev); 6522 struct dm_connector_state *dm_old_state = 6523 to_dm_connector_state(connector->state); 6524 struct dm_connector_state *dm_new_state = 6525 to_dm_connector_state(connector_state); 6526 6527 int ret = -EINVAL; 6528 6529 if (property == dev->mode_config.scaling_mode_property) { 6530 enum amdgpu_rmx_type rmx_type; 6531 6532 switch (val) { 6533 case DRM_MODE_SCALE_CENTER: 6534 rmx_type = RMX_CENTER; 6535 break; 6536 case DRM_MODE_SCALE_ASPECT: 6537 rmx_type = RMX_ASPECT; 6538 break; 6539 case DRM_MODE_SCALE_FULLSCREEN: 6540 rmx_type = RMX_FULL; 6541 break; 6542 case DRM_MODE_SCALE_NONE: 6543 default: 6544 rmx_type = RMX_OFF; 6545 break; 6546 } 6547 6548 if (dm_old_state->scaling == rmx_type) 6549 return 0; 6550 6551 dm_new_state->scaling = rmx_type; 6552 ret = 0; 6553 } else if (property == adev->mode_info.underscan_hborder_property) { 6554 dm_new_state->underscan_hborder = val; 6555 ret = 0; 6556 } else if (property == adev->mode_info.underscan_vborder_property) { 6557 dm_new_state->underscan_vborder = val; 6558 ret = 0; 6559 } else if (property == adev->mode_info.underscan_property) { 6560 dm_new_state->underscan_enable = val; 6561 ret = 0; 6562 } 6563 6564 return ret; 6565 } 6566 6567 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 6568 const struct drm_connector_state *state, 6569 struct drm_property *property, 6570 uint64_t *val) 6571 { 6572 struct drm_device *dev = connector->dev; 6573 struct amdgpu_device *adev = drm_to_adev(dev); 6574 struct dm_connector_state *dm_state = 6575 to_dm_connector_state(state); 6576 int ret = -EINVAL; 6577 6578 if (property == dev->mode_config.scaling_mode_property) { 6579 switch (dm_state->scaling) { 6580 case RMX_CENTER: 6581 *val = DRM_MODE_SCALE_CENTER; 6582 break; 6583 case RMX_ASPECT: 6584 *val = DRM_MODE_SCALE_ASPECT; 6585 break; 6586 case RMX_FULL: 6587 *val = DRM_MODE_SCALE_FULLSCREEN; 6588 break; 6589 case RMX_OFF: 6590 default: 6591 *val = DRM_MODE_SCALE_NONE; 6592 break; 6593 } 6594 ret = 0; 6595 } else if (property == adev->mode_info.underscan_hborder_property) { 6596 *val = dm_state->underscan_hborder; 6597 ret = 0; 6598 } else if (property == adev->mode_info.underscan_vborder_property) { 6599 *val = dm_state->underscan_vborder; 6600 ret = 0; 6601 } else if (property == adev->mode_info.underscan_property) { 6602 *val = dm_state->underscan_enable; 6603 ret = 0; 6604 } 6605 6606 return ret; 6607 } 6608 6609 /** 6610 * DOC: panel power savings 6611 * 6612 * The display manager allows you to set your desired **panel power savings** 6613 * level (between 0-4, with 0 representing off), e.g. using the following:: 6614 * 6615 * # echo 3 > /sys/class/drm/card0-eDP-1/amdgpu/panel_power_savings 6616 * 6617 * Modifying this value can have implications on color accuracy, so tread 6618 * carefully. 6619 */ 6620 6621 static ssize_t panel_power_savings_show(struct device *device, 6622 struct device_attribute *attr, 6623 char *buf) 6624 { 6625 struct drm_connector *connector = dev_get_drvdata(device); 6626 struct drm_device *dev = connector->dev; 6627 u8 val; 6628 6629 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 6630 val = to_dm_connector_state(connector->state)->abm_level == 6631 ABM_LEVEL_IMMEDIATE_DISABLE ? 0 : 6632 to_dm_connector_state(connector->state)->abm_level; 6633 drm_modeset_unlock(&dev->mode_config.connection_mutex); 6634 6635 return sysfs_emit(buf, "%u\n", val); 6636 } 6637 6638 static ssize_t panel_power_savings_store(struct device *device, 6639 struct device_attribute *attr, 6640 const char *buf, size_t count) 6641 { 6642 struct drm_connector *connector = dev_get_drvdata(device); 6643 struct drm_device *dev = connector->dev; 6644 long val; 6645 int ret; 6646 6647 ret = kstrtol(buf, 0, &val); 6648 6649 if (ret) 6650 return ret; 6651 6652 if (val < 0 || val > 4) 6653 return -EINVAL; 6654 6655 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 6656 to_dm_connector_state(connector->state)->abm_level = val ?: 6657 ABM_LEVEL_IMMEDIATE_DISABLE; 6658 drm_modeset_unlock(&dev->mode_config.connection_mutex); 6659 6660 drm_kms_helper_hotplug_event(dev); 6661 6662 return count; 6663 } 6664 6665 static DEVICE_ATTR_RW(panel_power_savings); 6666 6667 static struct attribute *amdgpu_attrs[] = { 6668 &dev_attr_panel_power_savings.attr, 6669 NULL 6670 }; 6671 6672 static const struct attribute_group amdgpu_group = { 6673 .name = "amdgpu", 6674 .attrs = amdgpu_attrs 6675 }; 6676 6677 static void amdgpu_dm_connector_unregister(struct drm_connector *connector) 6678 { 6679 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); 6680 6681 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP && 6682 amdgpu_dm_abm_level < 0) 6683 sysfs_remove_group(&connector->kdev->kobj, &amdgpu_group); 6684 6685 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); 6686 } 6687 6688 static void amdgpu_dm_connector_destroy(struct drm_connector *connector) 6689 { 6690 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6691 struct amdgpu_device *adev = drm_to_adev(connector->dev); 6692 struct amdgpu_display_manager *dm = &adev->dm; 6693 6694 /* 6695 * Call only if mst_mgr was initialized before since it's not done 6696 * for all connector types. 6697 */ 6698 if (aconnector->mst_mgr.dev) 6699 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr); 6700 6701 if (aconnector->bl_idx != -1) { 6702 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]); 6703 dm->backlight_dev[aconnector->bl_idx] = NULL; 6704 } 6705 6706 if (aconnector->dc_em_sink) 6707 dc_sink_release(aconnector->dc_em_sink); 6708 aconnector->dc_em_sink = NULL; 6709 if (aconnector->dc_sink) 6710 dc_sink_release(aconnector->dc_sink); 6711 aconnector->dc_sink = NULL; 6712 6713 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); 6714 drm_connector_unregister(connector); 6715 drm_connector_cleanup(connector); 6716 if (aconnector->i2c) { 6717 i2c_del_adapter(&aconnector->i2c->base); 6718 kfree(aconnector->i2c); 6719 } 6720 kfree(aconnector->dm_dp_aux.aux.name); 6721 6722 kfree(connector); 6723 } 6724 6725 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) 6726 { 6727 struct dm_connector_state *state = 6728 to_dm_connector_state(connector->state); 6729 6730 if (connector->state) 6731 __drm_atomic_helper_connector_destroy_state(connector->state); 6732 6733 kfree(state); 6734 6735 state = kzalloc(sizeof(*state), GFP_KERNEL); 6736 6737 if (state) { 6738 state->scaling = RMX_OFF; 6739 state->underscan_enable = false; 6740 state->underscan_hborder = 0; 6741 state->underscan_vborder = 0; 6742 state->base.max_requested_bpc = 8; 6743 state->vcpi_slots = 0; 6744 state->pbn = 0; 6745 6746 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 6747 if (amdgpu_dm_abm_level <= 0) 6748 state->abm_level = ABM_LEVEL_IMMEDIATE_DISABLE; 6749 else 6750 state->abm_level = amdgpu_dm_abm_level; 6751 } 6752 6753 __drm_atomic_helper_connector_reset(connector, &state->base); 6754 } 6755 } 6756 6757 struct drm_connector_state * 6758 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) 6759 { 6760 struct dm_connector_state *state = 6761 to_dm_connector_state(connector->state); 6762 6763 struct dm_connector_state *new_state = 6764 kmemdup(state, sizeof(*state), GFP_KERNEL); 6765 6766 if (!new_state) 6767 return NULL; 6768 6769 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 6770 6771 new_state->freesync_capable = state->freesync_capable; 6772 new_state->abm_level = state->abm_level; 6773 new_state->scaling = state->scaling; 6774 new_state->underscan_enable = state->underscan_enable; 6775 new_state->underscan_hborder = state->underscan_hborder; 6776 new_state->underscan_vborder = state->underscan_vborder; 6777 new_state->vcpi_slots = state->vcpi_slots; 6778 new_state->pbn = state->pbn; 6779 return &new_state->base; 6780 } 6781 6782 static int 6783 amdgpu_dm_connector_late_register(struct drm_connector *connector) 6784 { 6785 struct amdgpu_dm_connector *amdgpu_dm_connector = 6786 to_amdgpu_dm_connector(connector); 6787 int r; 6788 6789 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP && 6790 amdgpu_dm_abm_level < 0) { 6791 r = sysfs_create_group(&connector->kdev->kobj, 6792 &amdgpu_group); 6793 if (r) 6794 return r; 6795 } 6796 6797 amdgpu_dm_register_backlight_device(amdgpu_dm_connector); 6798 6799 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 6800 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 6801 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev; 6802 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux); 6803 if (r) 6804 return r; 6805 } 6806 6807 #if defined(CONFIG_DEBUG_FS) 6808 connector_debugfs_init(amdgpu_dm_connector); 6809 #endif 6810 6811 return 0; 6812 } 6813 6814 static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) 6815 { 6816 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6817 struct dc_link *dc_link = aconnector->dc_link; 6818 struct dc_sink *dc_em_sink = aconnector->dc_em_sink; 6819 struct edid *edid; 6820 struct i2c_adapter *ddc; 6821 6822 if (dc_link && dc_link->aux_mode) 6823 ddc = &aconnector->dm_dp_aux.aux.ddc; 6824 else 6825 ddc = &aconnector->i2c->base; 6826 6827 /* 6828 * Note: drm_get_edid gets edid in the following order: 6829 * 1) override EDID if set via edid_override debugfs, 6830 * 2) firmware EDID if set via edid_firmware module parameter 6831 * 3) regular DDC read. 6832 */ 6833 edid = drm_get_edid(connector, ddc); 6834 if (!edid) { 6835 DRM_ERROR("No EDID found on connector: %s.\n", connector->name); 6836 return; 6837 } 6838 6839 aconnector->edid = edid; 6840 6841 /* Update emulated (virtual) sink's EDID */ 6842 if (dc_em_sink && dc_link) { 6843 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps)); 6844 memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH); 6845 dm_helpers_parse_edid_caps( 6846 dc_link, 6847 &dc_em_sink->dc_edid, 6848 &dc_em_sink->edid_caps); 6849 } 6850 } 6851 6852 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 6853 .reset = amdgpu_dm_connector_funcs_reset, 6854 .detect = amdgpu_dm_connector_detect, 6855 .fill_modes = drm_helper_probe_single_connector_modes, 6856 .destroy = amdgpu_dm_connector_destroy, 6857 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 6858 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 6859 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 6860 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 6861 .late_register = amdgpu_dm_connector_late_register, 6862 .early_unregister = amdgpu_dm_connector_unregister, 6863 .force = amdgpu_dm_connector_funcs_force 6864 }; 6865 6866 static int get_modes(struct drm_connector *connector) 6867 { 6868 return amdgpu_dm_connector_get_modes(connector); 6869 } 6870 6871 static void create_eml_sink(struct amdgpu_dm_connector *aconnector) 6872 { 6873 struct drm_connector *connector = &aconnector->base; 6874 struct dc_link *dc_link = aconnector->dc_link; 6875 struct dc_sink_init_data init_params = { 6876 .link = aconnector->dc_link, 6877 .sink_signal = SIGNAL_TYPE_VIRTUAL 6878 }; 6879 struct edid *edid; 6880 struct i2c_adapter *ddc; 6881 6882 if (dc_link->aux_mode) 6883 ddc = &aconnector->dm_dp_aux.aux.ddc; 6884 else 6885 ddc = &aconnector->i2c->base; 6886 6887 /* 6888 * Note: drm_get_edid gets edid in the following order: 6889 * 1) override EDID if set via edid_override debugfs, 6890 * 2) firmware EDID if set via edid_firmware module parameter 6891 * 3) regular DDC read. 6892 */ 6893 edid = drm_get_edid(connector, ddc); 6894 if (!edid) { 6895 DRM_ERROR("No EDID found on connector: %s.\n", connector->name); 6896 return; 6897 } 6898 6899 if (drm_detect_hdmi_monitor(edid)) 6900 init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A; 6901 6902 aconnector->edid = edid; 6903 6904 aconnector->dc_em_sink = dc_link_add_remote_sink( 6905 aconnector->dc_link, 6906 (uint8_t *)edid, 6907 (edid->extensions + 1) * EDID_LENGTH, 6908 &init_params); 6909 6910 if (aconnector->base.force == DRM_FORCE_ON) { 6911 aconnector->dc_sink = aconnector->dc_link->local_sink ? 6912 aconnector->dc_link->local_sink : 6913 aconnector->dc_em_sink; 6914 dc_sink_retain(aconnector->dc_sink); 6915 } 6916 } 6917 6918 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) 6919 { 6920 struct dc_link *link = (struct dc_link *)aconnector->dc_link; 6921 6922 /* 6923 * In case of headless boot with force on for DP managed connector 6924 * Those settings have to be != 0 to get initial modeset 6925 */ 6926 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { 6927 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; 6928 link->verified_link_cap.link_rate = LINK_RATE_HIGH2; 6929 } 6930 6931 create_eml_sink(aconnector); 6932 } 6933 6934 static enum dc_status dm_validate_stream_and_context(struct dc *dc, 6935 struct dc_stream_state *stream) 6936 { 6937 enum dc_status dc_result = DC_ERROR_UNEXPECTED; 6938 struct dc_plane_state *dc_plane_state = NULL; 6939 struct dc_state *dc_state = NULL; 6940 6941 if (!stream) 6942 goto cleanup; 6943 6944 dc_plane_state = dc_create_plane_state(dc); 6945 if (!dc_plane_state) 6946 goto cleanup; 6947 6948 dc_state = dc_state_create(dc, NULL); 6949 if (!dc_state) 6950 goto cleanup; 6951 6952 /* populate stream to plane */ 6953 dc_plane_state->src_rect.height = stream->src.height; 6954 dc_plane_state->src_rect.width = stream->src.width; 6955 dc_plane_state->dst_rect.height = stream->src.height; 6956 dc_plane_state->dst_rect.width = stream->src.width; 6957 dc_plane_state->clip_rect.height = stream->src.height; 6958 dc_plane_state->clip_rect.width = stream->src.width; 6959 dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256; 6960 dc_plane_state->plane_size.surface_size.height = stream->src.height; 6961 dc_plane_state->plane_size.surface_size.width = stream->src.width; 6962 dc_plane_state->plane_size.chroma_size.height = stream->src.height; 6963 dc_plane_state->plane_size.chroma_size.width = stream->src.width; 6964 dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 6965 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; 6966 dc_plane_state->rotation = ROTATION_ANGLE_0; 6967 dc_plane_state->is_tiling_rotated = false; 6968 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL; 6969 6970 dc_result = dc_validate_stream(dc, stream); 6971 if (dc_result == DC_OK) 6972 dc_result = dc_validate_plane(dc, dc_plane_state); 6973 6974 if (dc_result == DC_OK) 6975 dc_result = dc_state_add_stream(dc, dc_state, stream); 6976 6977 if (dc_result == DC_OK && !dc_state_add_plane( 6978 dc, 6979 stream, 6980 dc_plane_state, 6981 dc_state)) 6982 dc_result = DC_FAIL_ATTACH_SURFACES; 6983 6984 if (dc_result == DC_OK) 6985 dc_result = dc_validate_global_state(dc, dc_state, true); 6986 6987 cleanup: 6988 if (dc_state) 6989 dc_state_release(dc_state); 6990 6991 if (dc_plane_state) 6992 dc_plane_state_release(dc_plane_state); 6993 6994 return dc_result; 6995 } 6996 6997 struct dc_stream_state * 6998 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, 6999 const struct drm_display_mode *drm_mode, 7000 const struct dm_connector_state *dm_state, 7001 const struct dc_stream_state *old_stream) 7002 { 7003 struct drm_connector *connector = &aconnector->base; 7004 struct amdgpu_device *adev = drm_to_adev(connector->dev); 7005 struct dc_stream_state *stream; 7006 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL; 7007 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8; 7008 enum dc_status dc_result = DC_OK; 7009 7010 do { 7011 stream = create_stream_for_sink(connector, drm_mode, 7012 dm_state, old_stream, 7013 requested_bpc); 7014 if (stream == NULL) { 7015 DRM_ERROR("Failed to create stream for sink!\n"); 7016 break; 7017 } 7018 7019 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 7020 return stream; 7021 7022 dc_result = dc_validate_stream(adev->dm.dc, stream); 7023 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 7024 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream); 7025 7026 if (dc_result == DC_OK) 7027 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream); 7028 7029 if (dc_result != DC_OK) { 7030 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n", 7031 drm_mode->hdisplay, 7032 drm_mode->vdisplay, 7033 drm_mode->clock, 7034 dc_result, 7035 dc_status_to_str(dc_result)); 7036 7037 dc_stream_release(stream); 7038 stream = NULL; 7039 requested_bpc -= 2; /* lower bpc to retry validation */ 7040 } 7041 7042 } while (stream == NULL && requested_bpc >= 6); 7043 7044 if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) { 7045 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n"); 7046 7047 aconnector->force_yuv420_output = true; 7048 stream = create_validate_stream_for_sink(aconnector, drm_mode, 7049 dm_state, old_stream); 7050 aconnector->force_yuv420_output = false; 7051 } 7052 7053 return stream; 7054 } 7055 7056 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 7057 struct drm_display_mode *mode) 7058 { 7059 int result = MODE_ERROR; 7060 struct dc_sink *dc_sink; 7061 /* TODO: Unhardcode stream count */ 7062 struct dc_stream_state *stream; 7063 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 7064 7065 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 7066 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) 7067 return result; 7068 7069 /* 7070 * Only run this the first time mode_valid is called to initilialize 7071 * EDID mgmt 7072 */ 7073 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && 7074 !aconnector->dc_em_sink) 7075 handle_edid_mgmt(aconnector); 7076 7077 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; 7078 7079 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL && 7080 aconnector->base.force != DRM_FORCE_ON) { 7081 DRM_ERROR("dc_sink is NULL!\n"); 7082 goto fail; 7083 } 7084 7085 drm_mode_set_crtcinfo(mode, 0); 7086 7087 stream = create_validate_stream_for_sink(aconnector, mode, 7088 to_dm_connector_state(connector->state), 7089 NULL); 7090 if (stream) { 7091 dc_stream_release(stream); 7092 result = MODE_OK; 7093 } 7094 7095 fail: 7096 /* TODO: error handling*/ 7097 return result; 7098 } 7099 7100 static int fill_hdr_info_packet(const struct drm_connector_state *state, 7101 struct dc_info_packet *out) 7102 { 7103 struct hdmi_drm_infoframe frame; 7104 unsigned char buf[30]; /* 26 + 4 */ 7105 ssize_t len; 7106 int ret, i; 7107 7108 memset(out, 0, sizeof(*out)); 7109 7110 if (!state->hdr_output_metadata) 7111 return 0; 7112 7113 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); 7114 if (ret) 7115 return ret; 7116 7117 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); 7118 if (len < 0) 7119 return (int)len; 7120 7121 /* Static metadata is a fixed 26 bytes + 4 byte header. */ 7122 if (len != 30) 7123 return -EINVAL; 7124 7125 /* Prepare the infopacket for DC. */ 7126 switch (state->connector->connector_type) { 7127 case DRM_MODE_CONNECTOR_HDMIA: 7128 out->hb0 = 0x87; /* type */ 7129 out->hb1 = 0x01; /* version */ 7130 out->hb2 = 0x1A; /* length */ 7131 out->sb[0] = buf[3]; /* checksum */ 7132 i = 1; 7133 break; 7134 7135 case DRM_MODE_CONNECTOR_DisplayPort: 7136 case DRM_MODE_CONNECTOR_eDP: 7137 out->hb0 = 0x00; /* sdp id, zero */ 7138 out->hb1 = 0x87; /* type */ 7139 out->hb2 = 0x1D; /* payload len - 1 */ 7140 out->hb3 = (0x13 << 2); /* sdp version */ 7141 out->sb[0] = 0x01; /* version */ 7142 out->sb[1] = 0x1A; /* length */ 7143 i = 2; 7144 break; 7145 7146 default: 7147 return -EINVAL; 7148 } 7149 7150 memcpy(&out->sb[i], &buf[4], 26); 7151 out->valid = true; 7152 7153 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, 7154 sizeof(out->sb), false); 7155 7156 return 0; 7157 } 7158 7159 static int 7160 amdgpu_dm_connector_atomic_check(struct drm_connector *conn, 7161 struct drm_atomic_state *state) 7162 { 7163 struct drm_connector_state *new_con_state = 7164 drm_atomic_get_new_connector_state(state, conn); 7165 struct drm_connector_state *old_con_state = 7166 drm_atomic_get_old_connector_state(state, conn); 7167 struct drm_crtc *crtc = new_con_state->crtc; 7168 struct drm_crtc_state *new_crtc_state; 7169 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn); 7170 int ret; 7171 7172 trace_amdgpu_dm_connector_atomic_check(new_con_state); 7173 7174 if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 7175 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr); 7176 if (ret < 0) 7177 return ret; 7178 } 7179 7180 if (!crtc) 7181 return 0; 7182 7183 if (new_con_state->colorspace != old_con_state->colorspace) { 7184 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 7185 if (IS_ERR(new_crtc_state)) 7186 return PTR_ERR(new_crtc_state); 7187 7188 new_crtc_state->mode_changed = true; 7189 } 7190 7191 if (new_con_state->content_type != old_con_state->content_type) { 7192 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 7193 if (IS_ERR(new_crtc_state)) 7194 return PTR_ERR(new_crtc_state); 7195 7196 new_crtc_state->mode_changed = true; 7197 } 7198 7199 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) { 7200 struct dc_info_packet hdr_infopacket; 7201 7202 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); 7203 if (ret) 7204 return ret; 7205 7206 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 7207 if (IS_ERR(new_crtc_state)) 7208 return PTR_ERR(new_crtc_state); 7209 7210 /* 7211 * DC considers the stream backends changed if the 7212 * static metadata changes. Forcing the modeset also 7213 * gives a simple way for userspace to switch from 7214 * 8bpc to 10bpc when setting the metadata to enter 7215 * or exit HDR. 7216 * 7217 * Changing the static metadata after it's been 7218 * set is permissible, however. So only force a 7219 * modeset if we're entering or exiting HDR. 7220 */ 7221 new_crtc_state->mode_changed = new_crtc_state->mode_changed || 7222 !old_con_state->hdr_output_metadata || 7223 !new_con_state->hdr_output_metadata; 7224 } 7225 7226 return 0; 7227 } 7228 7229 static const struct drm_connector_helper_funcs 7230 amdgpu_dm_connector_helper_funcs = { 7231 /* 7232 * If hotplugging a second bigger display in FB Con mode, bigger resolution 7233 * modes will be filtered by drm_mode_validate_size(), and those modes 7234 * are missing after user start lightdm. So we need to renew modes list. 7235 * in get_modes call back, not just return the modes count 7236 */ 7237 .get_modes = get_modes, 7238 .mode_valid = amdgpu_dm_connector_mode_valid, 7239 .atomic_check = amdgpu_dm_connector_atomic_check, 7240 }; 7241 7242 static void dm_encoder_helper_disable(struct drm_encoder *encoder) 7243 { 7244 7245 } 7246 7247 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) 7248 { 7249 switch (display_color_depth) { 7250 case COLOR_DEPTH_666: 7251 return 6; 7252 case COLOR_DEPTH_888: 7253 return 8; 7254 case COLOR_DEPTH_101010: 7255 return 10; 7256 case COLOR_DEPTH_121212: 7257 return 12; 7258 case COLOR_DEPTH_141414: 7259 return 14; 7260 case COLOR_DEPTH_161616: 7261 return 16; 7262 default: 7263 break; 7264 } 7265 return 0; 7266 } 7267 7268 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 7269 struct drm_crtc_state *crtc_state, 7270 struct drm_connector_state *conn_state) 7271 { 7272 struct drm_atomic_state *state = crtc_state->state; 7273 struct drm_connector *connector = conn_state->connector; 7274 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 7275 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state); 7276 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 7277 struct drm_dp_mst_topology_mgr *mst_mgr; 7278 struct drm_dp_mst_port *mst_port; 7279 struct drm_dp_mst_topology_state *mst_state; 7280 enum dc_color_depth color_depth; 7281 int clock, bpp = 0; 7282 bool is_y420 = false; 7283 7284 if (!aconnector->mst_output_port) 7285 return 0; 7286 7287 mst_port = aconnector->mst_output_port; 7288 mst_mgr = &aconnector->mst_root->mst_mgr; 7289 7290 if (!crtc_state->connectors_changed && !crtc_state->mode_changed) 7291 return 0; 7292 7293 mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr); 7294 if (IS_ERR(mst_state)) 7295 return PTR_ERR(mst_state); 7296 7297 mst_state->pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector->mst_root->dc_link)); 7298 7299 if (!state->duplicated) { 7300 int max_bpc = conn_state->max_requested_bpc; 7301 7302 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && 7303 aconnector->force_yuv420_output; 7304 color_depth = convert_color_depth_from_display_info(connector, 7305 is_y420, 7306 max_bpc); 7307 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; 7308 clock = adjusted_mode->clock; 7309 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4); 7310 } 7311 7312 dm_new_connector_state->vcpi_slots = 7313 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port, 7314 dm_new_connector_state->pbn); 7315 if (dm_new_connector_state->vcpi_slots < 0) { 7316 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); 7317 return dm_new_connector_state->vcpi_slots; 7318 } 7319 return 0; 7320 } 7321 7322 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 7323 .disable = dm_encoder_helper_disable, 7324 .atomic_check = dm_encoder_helper_atomic_check 7325 }; 7326 7327 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, 7328 struct dc_state *dc_state, 7329 struct dsc_mst_fairness_vars *vars) 7330 { 7331 struct dc_stream_state *stream = NULL; 7332 struct drm_connector *connector; 7333 struct drm_connector_state *new_con_state; 7334 struct amdgpu_dm_connector *aconnector; 7335 struct dm_connector_state *dm_conn_state; 7336 int i, j, ret; 7337 int vcpi, pbn_div, pbn = 0, slot_num = 0; 7338 7339 for_each_new_connector_in_state(state, connector, new_con_state, i) { 7340 7341 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 7342 continue; 7343 7344 aconnector = to_amdgpu_dm_connector(connector); 7345 7346 if (!aconnector->mst_output_port) 7347 continue; 7348 7349 if (!new_con_state || !new_con_state->crtc) 7350 continue; 7351 7352 dm_conn_state = to_dm_connector_state(new_con_state); 7353 7354 for (j = 0; j < dc_state->stream_count; j++) { 7355 stream = dc_state->streams[j]; 7356 if (!stream) 7357 continue; 7358 7359 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector) 7360 break; 7361 7362 stream = NULL; 7363 } 7364 7365 if (!stream) 7366 continue; 7367 7368 pbn_div = dm_mst_get_pbn_divider(stream->link); 7369 /* pbn is calculated by compute_mst_dsc_configs_for_state*/ 7370 for (j = 0; j < dc_state->stream_count; j++) { 7371 if (vars[j].aconnector == aconnector) { 7372 pbn = vars[j].pbn; 7373 break; 7374 } 7375 } 7376 7377 if (j == dc_state->stream_count) 7378 continue; 7379 7380 slot_num = DIV_ROUND_UP(pbn, pbn_div); 7381 7382 if (stream->timing.flags.DSC != 1) { 7383 dm_conn_state->pbn = pbn; 7384 dm_conn_state->vcpi_slots = slot_num; 7385 7386 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, 7387 dm_conn_state->pbn, false); 7388 if (ret < 0) 7389 return ret; 7390 7391 continue; 7392 } 7393 7394 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true); 7395 if (vcpi < 0) 7396 return vcpi; 7397 7398 dm_conn_state->pbn = pbn; 7399 dm_conn_state->vcpi_slots = vcpi; 7400 } 7401 return 0; 7402 } 7403 7404 static int to_drm_connector_type(enum signal_type st) 7405 { 7406 switch (st) { 7407 case SIGNAL_TYPE_HDMI_TYPE_A: 7408 return DRM_MODE_CONNECTOR_HDMIA; 7409 case SIGNAL_TYPE_EDP: 7410 return DRM_MODE_CONNECTOR_eDP; 7411 case SIGNAL_TYPE_LVDS: 7412 return DRM_MODE_CONNECTOR_LVDS; 7413 case SIGNAL_TYPE_RGB: 7414 return DRM_MODE_CONNECTOR_VGA; 7415 case SIGNAL_TYPE_DISPLAY_PORT: 7416 case SIGNAL_TYPE_DISPLAY_PORT_MST: 7417 return DRM_MODE_CONNECTOR_DisplayPort; 7418 case SIGNAL_TYPE_DVI_DUAL_LINK: 7419 case SIGNAL_TYPE_DVI_SINGLE_LINK: 7420 return DRM_MODE_CONNECTOR_DVID; 7421 case SIGNAL_TYPE_VIRTUAL: 7422 return DRM_MODE_CONNECTOR_VIRTUAL; 7423 7424 default: 7425 return DRM_MODE_CONNECTOR_Unknown; 7426 } 7427 } 7428 7429 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) 7430 { 7431 struct drm_encoder *encoder; 7432 7433 /* There is only one encoder per connector */ 7434 drm_connector_for_each_possible_encoder(connector, encoder) 7435 return encoder; 7436 7437 return NULL; 7438 } 7439 7440 static void amdgpu_dm_get_native_mode(struct drm_connector *connector) 7441 { 7442 struct drm_encoder *encoder; 7443 struct amdgpu_encoder *amdgpu_encoder; 7444 7445 encoder = amdgpu_dm_connector_to_encoder(connector); 7446 7447 if (encoder == NULL) 7448 return; 7449 7450 amdgpu_encoder = to_amdgpu_encoder(encoder); 7451 7452 amdgpu_encoder->native_mode.clock = 0; 7453 7454 if (!list_empty(&connector->probed_modes)) { 7455 struct drm_display_mode *preferred_mode = NULL; 7456 7457 list_for_each_entry(preferred_mode, 7458 &connector->probed_modes, 7459 head) { 7460 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) 7461 amdgpu_encoder->native_mode = *preferred_mode; 7462 7463 break; 7464 } 7465 7466 } 7467 } 7468 7469 static struct drm_display_mode * 7470 amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 7471 char *name, 7472 int hdisplay, int vdisplay) 7473 { 7474 struct drm_device *dev = encoder->dev; 7475 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 7476 struct drm_display_mode *mode = NULL; 7477 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 7478 7479 mode = drm_mode_duplicate(dev, native_mode); 7480 7481 if (mode == NULL) 7482 return NULL; 7483 7484 mode->hdisplay = hdisplay; 7485 mode->vdisplay = vdisplay; 7486 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 7487 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 7488 7489 return mode; 7490 7491 } 7492 7493 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 7494 struct drm_connector *connector) 7495 { 7496 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 7497 struct drm_display_mode *mode = NULL; 7498 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 7499 struct amdgpu_dm_connector *amdgpu_dm_connector = 7500 to_amdgpu_dm_connector(connector); 7501 int i; 7502 int n; 7503 struct mode_size { 7504 char name[DRM_DISPLAY_MODE_LEN]; 7505 int w; 7506 int h; 7507 } common_modes[] = { 7508 { "640x480", 640, 480}, 7509 { "800x600", 800, 600}, 7510 { "1024x768", 1024, 768}, 7511 { "1280x720", 1280, 720}, 7512 { "1280x800", 1280, 800}, 7513 {"1280x1024", 1280, 1024}, 7514 { "1440x900", 1440, 900}, 7515 {"1680x1050", 1680, 1050}, 7516 {"1600x1200", 1600, 1200}, 7517 {"1920x1080", 1920, 1080}, 7518 {"1920x1200", 1920, 1200} 7519 }; 7520 7521 n = ARRAY_SIZE(common_modes); 7522 7523 for (i = 0; i < n; i++) { 7524 struct drm_display_mode *curmode = NULL; 7525 bool mode_existed = false; 7526 7527 if (common_modes[i].w > native_mode->hdisplay || 7528 common_modes[i].h > native_mode->vdisplay || 7529 (common_modes[i].w == native_mode->hdisplay && 7530 common_modes[i].h == native_mode->vdisplay)) 7531 continue; 7532 7533 list_for_each_entry(curmode, &connector->probed_modes, head) { 7534 if (common_modes[i].w == curmode->hdisplay && 7535 common_modes[i].h == curmode->vdisplay) { 7536 mode_existed = true; 7537 break; 7538 } 7539 } 7540 7541 if (mode_existed) 7542 continue; 7543 7544 mode = amdgpu_dm_create_common_mode(encoder, 7545 common_modes[i].name, common_modes[i].w, 7546 common_modes[i].h); 7547 if (!mode) 7548 continue; 7549 7550 drm_mode_probed_add(connector, mode); 7551 amdgpu_dm_connector->num_modes++; 7552 } 7553 } 7554 7555 static void amdgpu_set_panel_orientation(struct drm_connector *connector) 7556 { 7557 struct drm_encoder *encoder; 7558 struct amdgpu_encoder *amdgpu_encoder; 7559 const struct drm_display_mode *native_mode; 7560 7561 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP && 7562 connector->connector_type != DRM_MODE_CONNECTOR_LVDS) 7563 return; 7564 7565 mutex_lock(&connector->dev->mode_config.mutex); 7566 amdgpu_dm_connector_get_modes(connector); 7567 mutex_unlock(&connector->dev->mode_config.mutex); 7568 7569 encoder = amdgpu_dm_connector_to_encoder(connector); 7570 if (!encoder) 7571 return; 7572 7573 amdgpu_encoder = to_amdgpu_encoder(encoder); 7574 7575 native_mode = &amdgpu_encoder->native_mode; 7576 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0) 7577 return; 7578 7579 drm_connector_set_panel_orientation_with_quirk(connector, 7580 DRM_MODE_PANEL_ORIENTATION_UNKNOWN, 7581 native_mode->hdisplay, 7582 native_mode->vdisplay); 7583 } 7584 7585 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 7586 struct edid *edid) 7587 { 7588 struct amdgpu_dm_connector *amdgpu_dm_connector = 7589 to_amdgpu_dm_connector(connector); 7590 7591 if (edid) { 7592 /* empty probed_modes */ 7593 INIT_LIST_HEAD(&connector->probed_modes); 7594 amdgpu_dm_connector->num_modes = 7595 drm_add_edid_modes(connector, edid); 7596 7597 /* sorting the probed modes before calling function 7598 * amdgpu_dm_get_native_mode() since EDID can have 7599 * more than one preferred mode. The modes that are 7600 * later in the probed mode list could be of higher 7601 * and preferred resolution. For example, 3840x2160 7602 * resolution in base EDID preferred timing and 4096x2160 7603 * preferred resolution in DID extension block later. 7604 */ 7605 drm_mode_sort(&connector->probed_modes); 7606 amdgpu_dm_get_native_mode(connector); 7607 7608 /* Freesync capabilities are reset by calling 7609 * drm_add_edid_modes() and need to be 7610 * restored here. 7611 */ 7612 amdgpu_dm_update_freesync_caps(connector, edid); 7613 } else { 7614 amdgpu_dm_connector->num_modes = 0; 7615 } 7616 } 7617 7618 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector, 7619 struct drm_display_mode *mode) 7620 { 7621 struct drm_display_mode *m; 7622 7623 list_for_each_entry(m, &aconnector->base.probed_modes, head) { 7624 if (drm_mode_equal(m, mode)) 7625 return true; 7626 } 7627 7628 return false; 7629 } 7630 7631 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) 7632 { 7633 const struct drm_display_mode *m; 7634 struct drm_display_mode *new_mode; 7635 uint i; 7636 u32 new_modes_count = 0; 7637 7638 /* Standard FPS values 7639 * 7640 * 23.976 - TV/NTSC 7641 * 24 - Cinema 7642 * 25 - TV/PAL 7643 * 29.97 - TV/NTSC 7644 * 30 - TV/NTSC 7645 * 48 - Cinema HFR 7646 * 50 - TV/PAL 7647 * 60 - Commonly used 7648 * 48,72,96,120 - Multiples of 24 7649 */ 7650 static const u32 common_rates[] = { 7651 23976, 24000, 25000, 29970, 30000, 7652 48000, 50000, 60000, 72000, 96000, 120000 7653 }; 7654 7655 /* 7656 * Find mode with highest refresh rate with the same resolution 7657 * as the preferred mode. Some monitors report a preferred mode 7658 * with lower resolution than the highest refresh rate supported. 7659 */ 7660 7661 m = get_highest_refresh_rate_mode(aconnector, true); 7662 if (!m) 7663 return 0; 7664 7665 for (i = 0; i < ARRAY_SIZE(common_rates); i++) { 7666 u64 target_vtotal, target_vtotal_diff; 7667 u64 num, den; 7668 7669 if (drm_mode_vrefresh(m) * 1000 < common_rates[i]) 7670 continue; 7671 7672 if (common_rates[i] < aconnector->min_vfreq * 1000 || 7673 common_rates[i] > aconnector->max_vfreq * 1000) 7674 continue; 7675 7676 num = (unsigned long long)m->clock * 1000 * 1000; 7677 den = common_rates[i] * (unsigned long long)m->htotal; 7678 target_vtotal = div_u64(num, den); 7679 target_vtotal_diff = target_vtotal - m->vtotal; 7680 7681 /* Check for illegal modes */ 7682 if (m->vsync_start + target_vtotal_diff < m->vdisplay || 7683 m->vsync_end + target_vtotal_diff < m->vsync_start || 7684 m->vtotal + target_vtotal_diff < m->vsync_end) 7685 continue; 7686 7687 new_mode = drm_mode_duplicate(aconnector->base.dev, m); 7688 if (!new_mode) 7689 goto out; 7690 7691 new_mode->vtotal += (u16)target_vtotal_diff; 7692 new_mode->vsync_start += (u16)target_vtotal_diff; 7693 new_mode->vsync_end += (u16)target_vtotal_diff; 7694 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 7695 new_mode->type |= DRM_MODE_TYPE_DRIVER; 7696 7697 if (!is_duplicate_mode(aconnector, new_mode)) { 7698 drm_mode_probed_add(&aconnector->base, new_mode); 7699 new_modes_count += 1; 7700 } else 7701 drm_mode_destroy(aconnector->base.dev, new_mode); 7702 } 7703 out: 7704 return new_modes_count; 7705 } 7706 7707 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, 7708 struct edid *edid) 7709 { 7710 struct amdgpu_dm_connector *amdgpu_dm_connector = 7711 to_amdgpu_dm_connector(connector); 7712 7713 if (!(amdgpu_freesync_vid_mode && edid)) 7714 return; 7715 7716 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 7717 amdgpu_dm_connector->num_modes += 7718 add_fs_modes(amdgpu_dm_connector); 7719 } 7720 7721 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) 7722 { 7723 struct amdgpu_dm_connector *amdgpu_dm_connector = 7724 to_amdgpu_dm_connector(connector); 7725 struct drm_encoder *encoder; 7726 struct edid *edid = amdgpu_dm_connector->edid; 7727 struct dc_link_settings *verified_link_cap = 7728 &amdgpu_dm_connector->dc_link->verified_link_cap; 7729 const struct dc *dc = amdgpu_dm_connector->dc_link->dc; 7730 7731 encoder = amdgpu_dm_connector_to_encoder(connector); 7732 7733 if (!drm_edid_is_valid(edid)) { 7734 amdgpu_dm_connector->num_modes = 7735 drm_add_modes_noedid(connector, 640, 480); 7736 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING) 7737 amdgpu_dm_connector->num_modes += 7738 drm_add_modes_noedid(connector, 1920, 1080); 7739 } else { 7740 amdgpu_dm_connector_ddc_get_modes(connector, edid); 7741 amdgpu_dm_connector_add_common_modes(encoder, connector); 7742 amdgpu_dm_connector_add_freesync_modes(connector, edid); 7743 } 7744 amdgpu_dm_fbc_init(connector); 7745 7746 return amdgpu_dm_connector->num_modes; 7747 } 7748 7749 static const u32 supported_colorspaces = 7750 BIT(DRM_MODE_COLORIMETRY_BT709_YCC) | 7751 BIT(DRM_MODE_COLORIMETRY_OPRGB) | 7752 BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) | 7753 BIT(DRM_MODE_COLORIMETRY_BT2020_YCC); 7754 7755 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 7756 struct amdgpu_dm_connector *aconnector, 7757 int connector_type, 7758 struct dc_link *link, 7759 int link_index) 7760 { 7761 struct amdgpu_device *adev = drm_to_adev(dm->ddev); 7762 7763 /* 7764 * Some of the properties below require access to state, like bpc. 7765 * Allocate some default initial connector state with our reset helper. 7766 */ 7767 if (aconnector->base.funcs->reset) 7768 aconnector->base.funcs->reset(&aconnector->base); 7769 7770 aconnector->connector_id = link_index; 7771 aconnector->bl_idx = -1; 7772 aconnector->dc_link = link; 7773 aconnector->base.interlace_allowed = false; 7774 aconnector->base.doublescan_allowed = false; 7775 aconnector->base.stereo_allowed = false; 7776 aconnector->base.dpms = DRM_MODE_DPMS_OFF; 7777 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ 7778 aconnector->audio_inst = -1; 7779 aconnector->pack_sdp_v1_3 = false; 7780 aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE; 7781 memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); 7782 mutex_init(&aconnector->hpd_lock); 7783 mutex_init(&aconnector->handle_mst_msg_ready); 7784 7785 /* 7786 * configure support HPD hot plug connector_>polled default value is 0 7787 * which means HPD hot plug not supported 7788 */ 7789 switch (connector_type) { 7790 case DRM_MODE_CONNECTOR_HDMIA: 7791 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7792 aconnector->base.ycbcr_420_allowed = 7793 link->link_enc->features.hdmi_ycbcr420_supported ? true : false; 7794 break; 7795 case DRM_MODE_CONNECTOR_DisplayPort: 7796 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7797 link->link_enc = link_enc_cfg_get_link_enc(link); 7798 ASSERT(link->link_enc); 7799 if (link->link_enc) 7800 aconnector->base.ycbcr_420_allowed = 7801 link->link_enc->features.dp_ycbcr420_supported ? true : false; 7802 break; 7803 case DRM_MODE_CONNECTOR_DVID: 7804 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7805 break; 7806 default: 7807 break; 7808 } 7809 7810 drm_object_attach_property(&aconnector->base.base, 7811 dm->ddev->mode_config.scaling_mode_property, 7812 DRM_MODE_SCALE_NONE); 7813 7814 drm_object_attach_property(&aconnector->base.base, 7815 adev->mode_info.underscan_property, 7816 UNDERSCAN_OFF); 7817 drm_object_attach_property(&aconnector->base.base, 7818 adev->mode_info.underscan_hborder_property, 7819 0); 7820 drm_object_attach_property(&aconnector->base.base, 7821 adev->mode_info.underscan_vborder_property, 7822 0); 7823 7824 if (!aconnector->mst_root) 7825 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); 7826 7827 aconnector->base.state->max_bpc = 16; 7828 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc; 7829 7830 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) { 7831 /* Content Type is currently only implemented for HDMI. */ 7832 drm_connector_attach_content_type_property(&aconnector->base); 7833 } 7834 7835 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) { 7836 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces)) 7837 drm_connector_attach_colorspace_property(&aconnector->base); 7838 } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) || 7839 connector_type == DRM_MODE_CONNECTOR_eDP) { 7840 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces)) 7841 drm_connector_attach_colorspace_property(&aconnector->base); 7842 } 7843 7844 if (connector_type == DRM_MODE_CONNECTOR_HDMIA || 7845 connector_type == DRM_MODE_CONNECTOR_DisplayPort || 7846 connector_type == DRM_MODE_CONNECTOR_eDP) { 7847 drm_connector_attach_hdr_output_metadata_property(&aconnector->base); 7848 7849 if (!aconnector->mst_root) 7850 drm_connector_attach_vrr_capable_property(&aconnector->base); 7851 7852 if (adev->dm.hdcp_workqueue) 7853 drm_connector_attach_content_protection_property(&aconnector->base, true); 7854 } 7855 } 7856 7857 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 7858 struct i2c_msg *msgs, int num) 7859 { 7860 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); 7861 struct ddc_service *ddc_service = i2c->ddc_service; 7862 struct i2c_command cmd; 7863 int i; 7864 int result = -EIO; 7865 7866 if (!ddc_service->ddc_pin || !ddc_service->ddc_pin->hw_info.hw_supported) 7867 return result; 7868 7869 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); 7870 7871 if (!cmd.payloads) 7872 return result; 7873 7874 cmd.number_of_payloads = num; 7875 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 7876 cmd.speed = 100; 7877 7878 for (i = 0; i < num; i++) { 7879 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); 7880 cmd.payloads[i].address = msgs[i].addr; 7881 cmd.payloads[i].length = msgs[i].len; 7882 cmd.payloads[i].data = msgs[i].buf; 7883 } 7884 7885 if (dc_submit_i2c( 7886 ddc_service->ctx->dc, 7887 ddc_service->link->link_index, 7888 &cmd)) 7889 result = num; 7890 7891 kfree(cmd.payloads); 7892 return result; 7893 } 7894 7895 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) 7896 { 7897 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 7898 } 7899 7900 static const struct i2c_algorithm amdgpu_dm_i2c_algo = { 7901 .master_xfer = amdgpu_dm_i2c_xfer, 7902 .functionality = amdgpu_dm_i2c_func, 7903 }; 7904 7905 static struct amdgpu_i2c_adapter * 7906 create_i2c(struct ddc_service *ddc_service, 7907 int link_index, 7908 int *res) 7909 { 7910 struct amdgpu_device *adev = ddc_service->ctx->driver_context; 7911 struct amdgpu_i2c_adapter *i2c; 7912 7913 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); 7914 if (!i2c) 7915 return NULL; 7916 i2c->base.owner = THIS_MODULE; 7917 i2c->base.dev.parent = &adev->pdev->dev; 7918 i2c->base.algo = &amdgpu_dm_i2c_algo; 7919 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); 7920 i2c_set_adapdata(&i2c->base, i2c); 7921 i2c->ddc_service = ddc_service; 7922 7923 return i2c; 7924 } 7925 7926 7927 /* 7928 * Note: this function assumes that dc_link_detect() was called for the 7929 * dc_link which will be represented by this aconnector. 7930 */ 7931 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 7932 struct amdgpu_dm_connector *aconnector, 7933 u32 link_index, 7934 struct amdgpu_encoder *aencoder) 7935 { 7936 int res = 0; 7937 int connector_type; 7938 struct dc *dc = dm->dc; 7939 struct dc_link *link = dc_get_link_at_index(dc, link_index); 7940 struct amdgpu_i2c_adapter *i2c; 7941 7942 /* Not needed for writeback connector */ 7943 link->priv = aconnector; 7944 7945 7946 i2c = create_i2c(link->ddc, link->link_index, &res); 7947 if (!i2c) { 7948 DRM_ERROR("Failed to create i2c adapter data\n"); 7949 return -ENOMEM; 7950 } 7951 7952 aconnector->i2c = i2c; 7953 res = i2c_add_adapter(&i2c->base); 7954 7955 if (res) { 7956 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); 7957 goto out_free; 7958 } 7959 7960 connector_type = to_drm_connector_type(link->connector_signal); 7961 7962 res = drm_connector_init_with_ddc( 7963 dm->ddev, 7964 &aconnector->base, 7965 &amdgpu_dm_connector_funcs, 7966 connector_type, 7967 &i2c->base); 7968 7969 if (res) { 7970 DRM_ERROR("connector_init failed\n"); 7971 aconnector->connector_id = -1; 7972 goto out_free; 7973 } 7974 7975 drm_connector_helper_add( 7976 &aconnector->base, 7977 &amdgpu_dm_connector_helper_funcs); 7978 7979 amdgpu_dm_connector_init_helper( 7980 dm, 7981 aconnector, 7982 connector_type, 7983 link, 7984 link_index); 7985 7986 drm_connector_attach_encoder( 7987 &aconnector->base, &aencoder->base); 7988 7989 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort 7990 || connector_type == DRM_MODE_CONNECTOR_eDP) 7991 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index); 7992 7993 out_free: 7994 if (res) { 7995 kfree(i2c); 7996 aconnector->i2c = NULL; 7997 } 7998 return res; 7999 } 8000 8001 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) 8002 { 8003 switch (adev->mode_info.num_crtc) { 8004 case 1: 8005 return 0x1; 8006 case 2: 8007 return 0x3; 8008 case 3: 8009 return 0x7; 8010 case 4: 8011 return 0xf; 8012 case 5: 8013 return 0x1f; 8014 case 6: 8015 default: 8016 return 0x3f; 8017 } 8018 } 8019 8020 static int amdgpu_dm_encoder_init(struct drm_device *dev, 8021 struct amdgpu_encoder *aencoder, 8022 uint32_t link_index) 8023 { 8024 struct amdgpu_device *adev = drm_to_adev(dev); 8025 8026 int res = drm_encoder_init(dev, 8027 &aencoder->base, 8028 &amdgpu_dm_encoder_funcs, 8029 DRM_MODE_ENCODER_TMDS, 8030 NULL); 8031 8032 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 8033 8034 if (!res) 8035 aencoder->encoder_id = link_index; 8036 else 8037 aencoder->encoder_id = -1; 8038 8039 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); 8040 8041 return res; 8042 } 8043 8044 static void manage_dm_interrupts(struct amdgpu_device *adev, 8045 struct amdgpu_crtc *acrtc, 8046 bool enable) 8047 { 8048 /* 8049 * We have no guarantee that the frontend index maps to the same 8050 * backend index - some even map to more than one. 8051 * 8052 * TODO: Use a different interrupt or check DC itself for the mapping. 8053 */ 8054 int irq_type = 8055 amdgpu_display_crtc_idx_to_irq_type( 8056 adev, 8057 acrtc->crtc_id); 8058 8059 if (enable) { 8060 drm_crtc_vblank_on(&acrtc->base); 8061 amdgpu_irq_get( 8062 adev, 8063 &adev->pageflip_irq, 8064 irq_type); 8065 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 8066 amdgpu_irq_get( 8067 adev, 8068 &adev->vline0_irq, 8069 irq_type); 8070 #endif 8071 } else { 8072 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 8073 amdgpu_irq_put( 8074 adev, 8075 &adev->vline0_irq, 8076 irq_type); 8077 #endif 8078 amdgpu_irq_put( 8079 adev, 8080 &adev->pageflip_irq, 8081 irq_type); 8082 drm_crtc_vblank_off(&acrtc->base); 8083 } 8084 } 8085 8086 static void dm_update_pflip_irq_state(struct amdgpu_device *adev, 8087 struct amdgpu_crtc *acrtc) 8088 { 8089 int irq_type = 8090 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); 8091 8092 /** 8093 * This reads the current state for the IRQ and force reapplies 8094 * the setting to hardware. 8095 */ 8096 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type); 8097 } 8098 8099 static bool 8100 is_scaling_state_different(const struct dm_connector_state *dm_state, 8101 const struct dm_connector_state *old_dm_state) 8102 { 8103 if (dm_state->scaling != old_dm_state->scaling) 8104 return true; 8105 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 8106 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 8107 return true; 8108 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 8109 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 8110 return true; 8111 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 8112 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 8113 return true; 8114 return false; 8115 } 8116 8117 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state, 8118 struct drm_crtc_state *old_crtc_state, 8119 struct drm_connector_state *new_conn_state, 8120 struct drm_connector_state *old_conn_state, 8121 const struct drm_connector *connector, 8122 struct hdcp_workqueue *hdcp_w) 8123 { 8124 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 8125 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 8126 8127 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 8128 connector->index, connector->status, connector->dpms); 8129 pr_debug("[HDCP_DM] state protection old: %x new: %x\n", 8130 old_conn_state->content_protection, new_conn_state->content_protection); 8131 8132 if (old_crtc_state) 8133 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 8134 old_crtc_state->enable, 8135 old_crtc_state->active, 8136 old_crtc_state->mode_changed, 8137 old_crtc_state->active_changed, 8138 old_crtc_state->connectors_changed); 8139 8140 if (new_crtc_state) 8141 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 8142 new_crtc_state->enable, 8143 new_crtc_state->active, 8144 new_crtc_state->mode_changed, 8145 new_crtc_state->active_changed, 8146 new_crtc_state->connectors_changed); 8147 8148 /* hdcp content type change */ 8149 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type && 8150 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 8151 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 8152 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__); 8153 return true; 8154 } 8155 8156 /* CP is being re enabled, ignore this */ 8157 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && 8158 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 8159 if (new_crtc_state && new_crtc_state->mode_changed) { 8160 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 8161 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__); 8162 return true; 8163 } 8164 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; 8165 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__); 8166 return false; 8167 } 8168 8169 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED 8170 * 8171 * Handles: UNDESIRED -> ENABLED 8172 */ 8173 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && 8174 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 8175 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 8176 8177 /* Stream removed and re-enabled 8178 * 8179 * Can sometimes overlap with the HPD case, 8180 * thus set update_hdcp to false to avoid 8181 * setting HDCP multiple times. 8182 * 8183 * Handles: DESIRED -> DESIRED (Special case) 8184 */ 8185 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) && 8186 new_conn_state->crtc && new_conn_state->crtc->enabled && 8187 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 8188 dm_con_state->update_hdcp = false; 8189 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n", 8190 __func__); 8191 return true; 8192 } 8193 8194 /* Hot-plug, headless s3, dpms 8195 * 8196 * Only start HDCP if the display is connected/enabled. 8197 * update_hdcp flag will be set to false until the next 8198 * HPD comes in. 8199 * 8200 * Handles: DESIRED -> DESIRED (Special case) 8201 */ 8202 if (dm_con_state->update_hdcp && 8203 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && 8204 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) { 8205 dm_con_state->update_hdcp = false; 8206 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n", 8207 __func__); 8208 return true; 8209 } 8210 8211 if (old_conn_state->content_protection == new_conn_state->content_protection) { 8212 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) { 8213 if (new_crtc_state && new_crtc_state->mode_changed) { 8214 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n", 8215 __func__); 8216 return true; 8217 } 8218 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n", 8219 __func__); 8220 return false; 8221 } 8222 8223 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__); 8224 return false; 8225 } 8226 8227 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 8228 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n", 8229 __func__); 8230 return true; 8231 } 8232 8233 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__); 8234 return false; 8235 } 8236 8237 static void remove_stream(struct amdgpu_device *adev, 8238 struct amdgpu_crtc *acrtc, 8239 struct dc_stream_state *stream) 8240 { 8241 /* this is the update mode case */ 8242 8243 acrtc->otg_inst = -1; 8244 acrtc->enabled = false; 8245 } 8246 8247 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 8248 { 8249 8250 assert_spin_locked(&acrtc->base.dev->event_lock); 8251 WARN_ON(acrtc->event); 8252 8253 acrtc->event = acrtc->base.state->event; 8254 8255 /* Set the flip status */ 8256 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 8257 8258 /* Mark this event as consumed */ 8259 acrtc->base.state->event = NULL; 8260 8261 drm_dbg_state(acrtc->base.dev, 8262 "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 8263 acrtc->crtc_id); 8264 } 8265 8266 static void update_freesync_state_on_stream( 8267 struct amdgpu_display_manager *dm, 8268 struct dm_crtc_state *new_crtc_state, 8269 struct dc_stream_state *new_stream, 8270 struct dc_plane_state *surface, 8271 u32 flip_timestamp_in_us) 8272 { 8273 struct mod_vrr_params vrr_params; 8274 struct dc_info_packet vrr_infopacket = {0}; 8275 struct amdgpu_device *adev = dm->adev; 8276 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 8277 unsigned long flags; 8278 bool pack_sdp_v1_3 = false; 8279 struct amdgpu_dm_connector *aconn; 8280 enum vrr_packet_type packet_type = PACKET_TYPE_VRR; 8281 8282 if (!new_stream) 8283 return; 8284 8285 /* 8286 * TODO: Determine why min/max totals and vrefresh can be 0 here. 8287 * For now it's sufficient to just guard against these conditions. 8288 */ 8289 8290 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 8291 return; 8292 8293 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 8294 vrr_params = acrtc->dm_irq_params.vrr_params; 8295 8296 if (surface) { 8297 mod_freesync_handle_preflip( 8298 dm->freesync_module, 8299 surface, 8300 new_stream, 8301 flip_timestamp_in_us, 8302 &vrr_params); 8303 8304 if (adev->family < AMDGPU_FAMILY_AI && 8305 amdgpu_dm_crtc_vrr_active(new_crtc_state)) { 8306 mod_freesync_handle_v_update(dm->freesync_module, 8307 new_stream, &vrr_params); 8308 8309 /* Need to call this before the frame ends. */ 8310 dc_stream_adjust_vmin_vmax(dm->dc, 8311 new_crtc_state->stream, 8312 &vrr_params.adjust); 8313 } 8314 } 8315 8316 aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context; 8317 8318 if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) { 8319 pack_sdp_v1_3 = aconn->pack_sdp_v1_3; 8320 8321 if (aconn->vsdb_info.amd_vsdb_version == 1) 8322 packet_type = PACKET_TYPE_FS_V1; 8323 else if (aconn->vsdb_info.amd_vsdb_version == 2) 8324 packet_type = PACKET_TYPE_FS_V2; 8325 else if (aconn->vsdb_info.amd_vsdb_version == 3) 8326 packet_type = PACKET_TYPE_FS_V3; 8327 8328 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL, 8329 &new_stream->adaptive_sync_infopacket); 8330 } 8331 8332 mod_freesync_build_vrr_infopacket( 8333 dm->freesync_module, 8334 new_stream, 8335 &vrr_params, 8336 packet_type, 8337 TRANSFER_FUNC_UNKNOWN, 8338 &vrr_infopacket, 8339 pack_sdp_v1_3); 8340 8341 new_crtc_state->freesync_vrr_info_changed |= 8342 (memcmp(&new_crtc_state->vrr_infopacket, 8343 &vrr_infopacket, 8344 sizeof(vrr_infopacket)) != 0); 8345 8346 acrtc->dm_irq_params.vrr_params = vrr_params; 8347 new_crtc_state->vrr_infopacket = vrr_infopacket; 8348 8349 new_stream->vrr_infopacket = vrr_infopacket; 8350 new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params); 8351 8352 if (new_crtc_state->freesync_vrr_info_changed) 8353 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", 8354 new_crtc_state->base.crtc->base.id, 8355 (int)new_crtc_state->base.vrr_enabled, 8356 (int)vrr_params.state); 8357 8358 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 8359 } 8360 8361 static void update_stream_irq_parameters( 8362 struct amdgpu_display_manager *dm, 8363 struct dm_crtc_state *new_crtc_state) 8364 { 8365 struct dc_stream_state *new_stream = new_crtc_state->stream; 8366 struct mod_vrr_params vrr_params; 8367 struct mod_freesync_config config = new_crtc_state->freesync_config; 8368 struct amdgpu_device *adev = dm->adev; 8369 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 8370 unsigned long flags; 8371 8372 if (!new_stream) 8373 return; 8374 8375 /* 8376 * TODO: Determine why min/max totals and vrefresh can be 0 here. 8377 * For now it's sufficient to just guard against these conditions. 8378 */ 8379 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 8380 return; 8381 8382 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 8383 vrr_params = acrtc->dm_irq_params.vrr_params; 8384 8385 if (new_crtc_state->vrr_supported && 8386 config.min_refresh_in_uhz && 8387 config.max_refresh_in_uhz) { 8388 /* 8389 * if freesync compatible mode was set, config.state will be set 8390 * in atomic check 8391 */ 8392 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz && 8393 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) || 8394 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) { 8395 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz; 8396 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz; 8397 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz; 8398 vrr_params.state = VRR_STATE_ACTIVE_FIXED; 8399 } else { 8400 config.state = new_crtc_state->base.vrr_enabled ? 8401 VRR_STATE_ACTIVE_VARIABLE : 8402 VRR_STATE_INACTIVE; 8403 } 8404 } else { 8405 config.state = VRR_STATE_UNSUPPORTED; 8406 } 8407 8408 mod_freesync_build_vrr_params(dm->freesync_module, 8409 new_stream, 8410 &config, &vrr_params); 8411 8412 new_crtc_state->freesync_config = config; 8413 /* Copy state for access from DM IRQ handler */ 8414 acrtc->dm_irq_params.freesync_config = config; 8415 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; 8416 acrtc->dm_irq_params.vrr_params = vrr_params; 8417 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 8418 } 8419 8420 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, 8421 struct dm_crtc_state *new_state) 8422 { 8423 bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state); 8424 bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state); 8425 8426 if (!old_vrr_active && new_vrr_active) { 8427 /* Transition VRR inactive -> active: 8428 * While VRR is active, we must not disable vblank irq, as a 8429 * reenable after disable would compute bogus vblank/pflip 8430 * timestamps if it likely happened inside display front-porch. 8431 * 8432 * We also need vupdate irq for the actual core vblank handling 8433 * at end of vblank. 8434 */ 8435 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0); 8436 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0); 8437 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n", 8438 __func__, new_state->base.crtc->base.id); 8439 } else if (old_vrr_active && !new_vrr_active) { 8440 /* Transition VRR active -> inactive: 8441 * Allow vblank irq disable again for fixed refresh rate. 8442 */ 8443 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0); 8444 drm_crtc_vblank_put(new_state->base.crtc); 8445 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n", 8446 __func__, new_state->base.crtc->base.id); 8447 } 8448 } 8449 8450 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) 8451 { 8452 struct drm_plane *plane; 8453 struct drm_plane_state *old_plane_state; 8454 int i; 8455 8456 /* 8457 * TODO: Make this per-stream so we don't issue redundant updates for 8458 * commits with multiple streams. 8459 */ 8460 for_each_old_plane_in_state(state, plane, old_plane_state, i) 8461 if (plane->type == DRM_PLANE_TYPE_CURSOR) 8462 amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); 8463 } 8464 8465 static inline uint32_t get_mem_type(struct drm_framebuffer *fb) 8466 { 8467 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); 8468 8469 return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; 8470 } 8471 8472 static void amdgpu_dm_update_cursor(struct drm_plane *plane, 8473 struct drm_plane_state *old_plane_state, 8474 struct dc_stream_update *update) 8475 { 8476 struct amdgpu_device *adev = drm_to_adev(plane->dev); 8477 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 8478 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 8479 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 8480 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 8481 uint64_t address = afb ? afb->address : 0; 8482 struct dc_cursor_position position = {0}; 8483 struct dc_cursor_attributes attributes; 8484 int ret; 8485 8486 if (!plane->state->fb && !old_plane_state->fb) 8487 return; 8488 8489 drm_dbg_atomic(plane->dev, "crtc_id=%d with size %d to %d\n", 8490 amdgpu_crtc->crtc_id, plane->state->crtc_w, 8491 plane->state->crtc_h); 8492 8493 ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position); 8494 if (ret) 8495 return; 8496 8497 if (!position.enable) { 8498 /* turn off cursor */ 8499 if (crtc_state && crtc_state->stream) { 8500 dc_stream_set_cursor_position(crtc_state->stream, 8501 &position); 8502 update->cursor_position = &crtc_state->stream->cursor_position; 8503 } 8504 return; 8505 } 8506 8507 amdgpu_crtc->cursor_width = plane->state->crtc_w; 8508 amdgpu_crtc->cursor_height = plane->state->crtc_h; 8509 8510 memset(&attributes, 0, sizeof(attributes)); 8511 attributes.address.high_part = upper_32_bits(address); 8512 attributes.address.low_part = lower_32_bits(address); 8513 attributes.width = plane->state->crtc_w; 8514 attributes.height = plane->state->crtc_h; 8515 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 8516 attributes.rotation_angle = 0; 8517 attributes.attribute_flags.value = 0; 8518 8519 /* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM 8520 * legacy gamma setup. 8521 */ 8522 if (crtc_state->cm_is_degamma_srgb && 8523 adev->dm.dc->caps.color.dpp.gamma_corr) 8524 attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1; 8525 8526 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0]; 8527 8528 if (crtc_state->stream) { 8529 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 8530 &attributes)) 8531 DRM_ERROR("DC failed to set cursor attributes\n"); 8532 8533 update->cursor_attributes = &crtc_state->stream->cursor_attributes; 8534 8535 if (!dc_stream_set_cursor_position(crtc_state->stream, 8536 &position)) 8537 DRM_ERROR("DC failed to set cursor position\n"); 8538 8539 update->cursor_position = &crtc_state->stream->cursor_position; 8540 } 8541 } 8542 8543 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 8544 struct drm_device *dev, 8545 struct amdgpu_display_manager *dm, 8546 struct drm_crtc *pcrtc, 8547 bool wait_for_vblank) 8548 { 8549 u32 i; 8550 u64 timestamp_ns = ktime_get_ns(); 8551 struct drm_plane *plane; 8552 struct drm_plane_state *old_plane_state, *new_plane_state; 8553 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 8554 struct drm_crtc_state *new_pcrtc_state = 8555 drm_atomic_get_new_crtc_state(state, pcrtc); 8556 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 8557 struct dm_crtc_state *dm_old_crtc_state = 8558 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 8559 int planes_count = 0, vpos, hpos; 8560 unsigned long flags; 8561 u32 target_vblank, last_flip_vblank; 8562 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); 8563 bool cursor_update = false; 8564 bool pflip_present = false; 8565 bool dirty_rects_changed = false; 8566 bool updated_planes_and_streams = false; 8567 struct { 8568 struct dc_surface_update surface_updates[MAX_SURFACES]; 8569 struct dc_plane_info plane_infos[MAX_SURFACES]; 8570 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 8571 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 8572 struct dc_stream_update stream_update; 8573 } *bundle; 8574 8575 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 8576 8577 if (!bundle) { 8578 drm_err(dev, "Failed to allocate update bundle\n"); 8579 goto cleanup; 8580 } 8581 8582 /* 8583 * Disable the cursor first if we're disabling all the planes. 8584 * It'll remain on the screen after the planes are re-enabled 8585 * if we don't. 8586 */ 8587 if (acrtc_state->active_planes == 0) 8588 amdgpu_dm_commit_cursors(state); 8589 8590 /* update planes when needed */ 8591 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 8592 struct drm_crtc *crtc = new_plane_state->crtc; 8593 struct drm_crtc_state *new_crtc_state; 8594 struct drm_framebuffer *fb = new_plane_state->fb; 8595 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb; 8596 bool plane_needs_flip; 8597 struct dc_plane_state *dc_plane; 8598 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 8599 8600 /* Cursor plane is handled after stream updates */ 8601 if (plane->type == DRM_PLANE_TYPE_CURSOR) { 8602 if ((fb && crtc == pcrtc) || 8603 (old_plane_state->fb && old_plane_state->crtc == pcrtc)) { 8604 cursor_update = true; 8605 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) != 0) 8606 amdgpu_dm_update_cursor(plane, old_plane_state, &bundle->stream_update); 8607 } 8608 8609 continue; 8610 } 8611 8612 if (!fb || !crtc || pcrtc != crtc) 8613 continue; 8614 8615 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 8616 if (!new_crtc_state->active) 8617 continue; 8618 8619 dc_plane = dm_new_plane_state->dc_state; 8620 if (!dc_plane) 8621 continue; 8622 8623 bundle->surface_updates[planes_count].surface = dc_plane; 8624 if (new_pcrtc_state->color_mgmt_changed) { 8625 bundle->surface_updates[planes_count].gamma = &dc_plane->gamma_correction; 8626 bundle->surface_updates[planes_count].in_transfer_func = &dc_plane->in_transfer_func; 8627 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; 8628 bundle->surface_updates[planes_count].hdr_mult = dc_plane->hdr_mult; 8629 bundle->surface_updates[planes_count].func_shaper = &dc_plane->in_shaper_func; 8630 bundle->surface_updates[planes_count].lut3d_func = &dc_plane->lut3d_func; 8631 bundle->surface_updates[planes_count].blend_tf = &dc_plane->blend_tf; 8632 } 8633 8634 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, 8635 &bundle->scaling_infos[planes_count]); 8636 8637 bundle->surface_updates[planes_count].scaling_info = 8638 &bundle->scaling_infos[planes_count]; 8639 8640 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 8641 8642 pflip_present = pflip_present || plane_needs_flip; 8643 8644 if (!plane_needs_flip) { 8645 planes_count += 1; 8646 continue; 8647 } 8648 8649 fill_dc_plane_info_and_addr( 8650 dm->adev, new_plane_state, 8651 afb->tiling_flags, 8652 &bundle->plane_infos[planes_count], 8653 &bundle->flip_addrs[planes_count].address, 8654 afb->tmz_surface, false); 8655 8656 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", 8657 new_plane_state->plane->index, 8658 bundle->plane_infos[planes_count].dcc.enable); 8659 8660 bundle->surface_updates[planes_count].plane_info = 8661 &bundle->plane_infos[planes_count]; 8662 8663 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled || 8664 acrtc_state->stream->link->replay_settings.replay_feature_enabled) { 8665 fill_dc_dirty_rects(plane, old_plane_state, 8666 new_plane_state, new_crtc_state, 8667 &bundle->flip_addrs[planes_count], 8668 acrtc_state->stream->link->psr_settings.psr_version == 8669 DC_PSR_VERSION_SU_1, 8670 &dirty_rects_changed); 8671 8672 /* 8673 * If the dirty regions changed, PSR-SU need to be disabled temporarily 8674 * and enabled it again after dirty regions are stable to avoid video glitch. 8675 * PSR-SU will be enabled in vblank_control_worker() if user pause the video 8676 * during the PSR-SU was disabled. 8677 */ 8678 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 8679 acrtc_attach->dm_irq_params.allow_psr_entry && 8680 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 8681 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && 8682 #endif 8683 dirty_rects_changed) { 8684 mutex_lock(&dm->dc_lock); 8685 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns = 8686 timestamp_ns; 8687 if (acrtc_state->stream->link->psr_settings.psr_allow_active) 8688 amdgpu_dm_psr_disable(acrtc_state->stream); 8689 mutex_unlock(&dm->dc_lock); 8690 } 8691 } 8692 8693 /* 8694 * Only allow immediate flips for fast updates that don't 8695 * change memory domain, FB pitch, DCC state, rotation or 8696 * mirroring. 8697 * 8698 * dm_crtc_helper_atomic_check() only accepts async flips with 8699 * fast updates. 8700 */ 8701 if (crtc->state->async_flip && 8702 (acrtc_state->update_type != UPDATE_TYPE_FAST || 8703 get_mem_type(old_plane_state->fb) != get_mem_type(fb))) 8704 drm_warn_once(state->dev, 8705 "[PLANE:%d:%s] async flip with non-fast update\n", 8706 plane->base.id, plane->name); 8707 8708 bundle->flip_addrs[planes_count].flip_immediate = 8709 crtc->state->async_flip && 8710 acrtc_state->update_type == UPDATE_TYPE_FAST && 8711 get_mem_type(old_plane_state->fb) == get_mem_type(fb); 8712 8713 timestamp_ns = ktime_get_ns(); 8714 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 8715 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 8716 bundle->surface_updates[planes_count].surface = dc_plane; 8717 8718 if (!bundle->surface_updates[planes_count].surface) { 8719 DRM_ERROR("No surface for CRTC: id=%d\n", 8720 acrtc_attach->crtc_id); 8721 continue; 8722 } 8723 8724 if (plane == pcrtc->primary) 8725 update_freesync_state_on_stream( 8726 dm, 8727 acrtc_state, 8728 acrtc_state->stream, 8729 dc_plane, 8730 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 8731 8732 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n", 8733 __func__, 8734 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 8735 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 8736 8737 planes_count += 1; 8738 8739 } 8740 8741 if (pflip_present) { 8742 if (!vrr_active) { 8743 /* Use old throttling in non-vrr fixed refresh rate mode 8744 * to keep flip scheduling based on target vblank counts 8745 * working in a backwards compatible way, e.g., for 8746 * clients using the GLX_OML_sync_control extension or 8747 * DRI3/Present extension with defined target_msc. 8748 */ 8749 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); 8750 } else { 8751 /* For variable refresh rate mode only: 8752 * Get vblank of last completed flip to avoid > 1 vrr 8753 * flips per video frame by use of throttling, but allow 8754 * flip programming anywhere in the possibly large 8755 * variable vrr vblank interval for fine-grained flip 8756 * timing control and more opportunity to avoid stutter 8757 * on late submission of flips. 8758 */ 8759 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8760 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank; 8761 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8762 } 8763 8764 target_vblank = last_flip_vblank + wait_for_vblank; 8765 8766 /* 8767 * Wait until we're out of the vertical blank period before the one 8768 * targeted by the flip 8769 */ 8770 while ((acrtc_attach->enabled && 8771 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 8772 0, &vpos, &hpos, NULL, 8773 NULL, &pcrtc->hwmode) 8774 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 8775 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 8776 (int)(target_vblank - 8777 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) { 8778 usleep_range(1000, 1100); 8779 } 8780 8781 /** 8782 * Prepare the flip event for the pageflip interrupt to handle. 8783 * 8784 * This only works in the case where we've already turned on the 8785 * appropriate hardware blocks (eg. HUBP) so in the transition case 8786 * from 0 -> n planes we have to skip a hardware generated event 8787 * and rely on sending it from software. 8788 */ 8789 if (acrtc_attach->base.state->event && 8790 acrtc_state->active_planes > 0) { 8791 drm_crtc_vblank_get(pcrtc); 8792 8793 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8794 8795 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); 8796 prepare_flip_isr(acrtc_attach); 8797 8798 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8799 } 8800 8801 if (acrtc_state->stream) { 8802 if (acrtc_state->freesync_vrr_info_changed) 8803 bundle->stream_update.vrr_infopacket = 8804 &acrtc_state->stream->vrr_infopacket; 8805 } 8806 } else if (cursor_update && acrtc_state->active_planes > 0 && 8807 acrtc_attach->base.state->event) { 8808 drm_crtc_vblank_get(pcrtc); 8809 8810 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8811 8812 acrtc_attach->event = acrtc_attach->base.state->event; 8813 acrtc_attach->base.state->event = NULL; 8814 8815 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8816 } 8817 8818 /* Update the planes if changed or disable if we don't have any. */ 8819 if ((planes_count || acrtc_state->active_planes == 0) && 8820 acrtc_state->stream) { 8821 /* 8822 * If PSR or idle optimizations are enabled then flush out 8823 * any pending work before hardware programming. 8824 */ 8825 if (dm->vblank_control_workqueue) 8826 flush_workqueue(dm->vblank_control_workqueue); 8827 8828 bundle->stream_update.stream = acrtc_state->stream; 8829 if (new_pcrtc_state->mode_changed) { 8830 bundle->stream_update.src = acrtc_state->stream->src; 8831 bundle->stream_update.dst = acrtc_state->stream->dst; 8832 } 8833 8834 if (new_pcrtc_state->color_mgmt_changed) { 8835 /* 8836 * TODO: This isn't fully correct since we've actually 8837 * already modified the stream in place. 8838 */ 8839 bundle->stream_update.gamut_remap = 8840 &acrtc_state->stream->gamut_remap_matrix; 8841 bundle->stream_update.output_csc_transform = 8842 &acrtc_state->stream->csc_color_matrix; 8843 bundle->stream_update.out_transfer_func = 8844 &acrtc_state->stream->out_transfer_func; 8845 bundle->stream_update.lut3d_func = 8846 (struct dc_3dlut *) acrtc_state->stream->lut3d_func; 8847 bundle->stream_update.func_shaper = 8848 (struct dc_transfer_func *) acrtc_state->stream->func_shaper; 8849 } 8850 8851 acrtc_state->stream->abm_level = acrtc_state->abm_level; 8852 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 8853 bundle->stream_update.abm_level = &acrtc_state->abm_level; 8854 8855 mutex_lock(&dm->dc_lock); 8856 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && 8857 acrtc_state->stream->link->psr_settings.psr_allow_active) 8858 amdgpu_dm_psr_disable(acrtc_state->stream); 8859 mutex_unlock(&dm->dc_lock); 8860 8861 /* 8862 * If FreeSync state on the stream has changed then we need to 8863 * re-adjust the min/max bounds now that DC doesn't handle this 8864 * as part of commit. 8865 */ 8866 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) { 8867 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8868 dc_stream_adjust_vmin_vmax( 8869 dm->dc, acrtc_state->stream, 8870 &acrtc_attach->dm_irq_params.vrr_params.adjust); 8871 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8872 } 8873 mutex_lock(&dm->dc_lock); 8874 update_planes_and_stream_adapter(dm->dc, 8875 acrtc_state->update_type, 8876 planes_count, 8877 acrtc_state->stream, 8878 &bundle->stream_update, 8879 bundle->surface_updates); 8880 updated_planes_and_streams = true; 8881 8882 /** 8883 * Enable or disable the interrupts on the backend. 8884 * 8885 * Most pipes are put into power gating when unused. 8886 * 8887 * When power gating is enabled on a pipe we lose the 8888 * interrupt enablement state when power gating is disabled. 8889 * 8890 * So we need to update the IRQ control state in hardware 8891 * whenever the pipe turns on (since it could be previously 8892 * power gated) or off (since some pipes can't be power gated 8893 * on some ASICs). 8894 */ 8895 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) 8896 dm_update_pflip_irq_state(drm_to_adev(dev), 8897 acrtc_attach); 8898 8899 if (acrtc_state->update_type > UPDATE_TYPE_FAST) { 8900 if (acrtc_state->stream->link->replay_settings.config.replay_supported && 8901 !acrtc_state->stream->link->replay_settings.replay_feature_enabled) { 8902 struct amdgpu_dm_connector *aconn = 8903 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; 8904 amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn); 8905 } else if (acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED && 8906 !acrtc_state->stream->link->psr_settings.psr_feature_enabled) { 8907 8908 struct amdgpu_dm_connector *aconn = (struct amdgpu_dm_connector *) 8909 acrtc_state->stream->dm_stream_context; 8910 8911 if (!aconn->disallow_edp_enter_psr) 8912 amdgpu_dm_link_setup_psr(acrtc_state->stream); 8913 } 8914 } 8915 8916 /* Decrement skip count when PSR is enabled and we're doing fast updates. */ 8917 if (acrtc_state->update_type == UPDATE_TYPE_FAST && 8918 acrtc_state->stream->link->psr_settings.psr_feature_enabled) { 8919 struct amdgpu_dm_connector *aconn = 8920 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; 8921 8922 if (aconn->psr_skip_count > 0) 8923 aconn->psr_skip_count--; 8924 8925 /* Allow PSR when skip count is 0. */ 8926 acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count; 8927 8928 /* 8929 * If sink supports PSR SU, there is no need to rely on 8930 * a vblank event disable request to enable PSR. PSR SU 8931 * can be enabled immediately once OS demonstrates an 8932 * adequate number of fast atomic commits to notify KMD 8933 * of update events. See `vblank_control_worker()`. 8934 */ 8935 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 8936 acrtc_attach->dm_irq_params.allow_psr_entry && 8937 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 8938 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && 8939 #endif 8940 !acrtc_state->stream->link->psr_settings.psr_allow_active && 8941 !aconn->disallow_edp_enter_psr && 8942 (timestamp_ns - 8943 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) > 8944 500000000) 8945 amdgpu_dm_psr_enable(acrtc_state->stream); 8946 } else { 8947 acrtc_attach->dm_irq_params.allow_psr_entry = false; 8948 } 8949 8950 mutex_unlock(&dm->dc_lock); 8951 } 8952 8953 /* 8954 * Update cursor state *after* programming all the planes. 8955 * This avoids redundant programming in the case where we're going 8956 * to be disabling a single plane - those pipes are being disabled. 8957 */ 8958 if (acrtc_state->active_planes && 8959 (!updated_planes_and_streams || amdgpu_ip_version(dm->adev, DCE_HWIP, 0) == 0)) 8960 amdgpu_dm_commit_cursors(state); 8961 8962 cleanup: 8963 kfree(bundle); 8964 } 8965 8966 static void amdgpu_dm_commit_audio(struct drm_device *dev, 8967 struct drm_atomic_state *state) 8968 { 8969 struct amdgpu_device *adev = drm_to_adev(dev); 8970 struct amdgpu_dm_connector *aconnector; 8971 struct drm_connector *connector; 8972 struct drm_connector_state *old_con_state, *new_con_state; 8973 struct drm_crtc_state *new_crtc_state; 8974 struct dm_crtc_state *new_dm_crtc_state; 8975 const struct dc_stream_status *status; 8976 int i, inst; 8977 8978 /* Notify device removals. */ 8979 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 8980 if (old_con_state->crtc != new_con_state->crtc) { 8981 /* CRTC changes require notification. */ 8982 goto notify; 8983 } 8984 8985 if (!new_con_state->crtc) 8986 continue; 8987 8988 new_crtc_state = drm_atomic_get_new_crtc_state( 8989 state, new_con_state->crtc); 8990 8991 if (!new_crtc_state) 8992 continue; 8993 8994 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 8995 continue; 8996 8997 notify: 8998 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 8999 continue; 9000 9001 aconnector = to_amdgpu_dm_connector(connector); 9002 9003 mutex_lock(&adev->dm.audio_lock); 9004 inst = aconnector->audio_inst; 9005 aconnector->audio_inst = -1; 9006 mutex_unlock(&adev->dm.audio_lock); 9007 9008 amdgpu_dm_audio_eld_notify(adev, inst); 9009 } 9010 9011 /* Notify audio device additions. */ 9012 for_each_new_connector_in_state(state, connector, new_con_state, i) { 9013 if (!new_con_state->crtc) 9014 continue; 9015 9016 new_crtc_state = drm_atomic_get_new_crtc_state( 9017 state, new_con_state->crtc); 9018 9019 if (!new_crtc_state) 9020 continue; 9021 9022 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 9023 continue; 9024 9025 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 9026 if (!new_dm_crtc_state->stream) 9027 continue; 9028 9029 status = dc_stream_get_status(new_dm_crtc_state->stream); 9030 if (!status) 9031 continue; 9032 9033 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 9034 continue; 9035 9036 aconnector = to_amdgpu_dm_connector(connector); 9037 9038 mutex_lock(&adev->dm.audio_lock); 9039 inst = status->audio_inst; 9040 aconnector->audio_inst = inst; 9041 mutex_unlock(&adev->dm.audio_lock); 9042 9043 amdgpu_dm_audio_eld_notify(adev, inst); 9044 } 9045 } 9046 9047 /* 9048 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 9049 * @crtc_state: the DRM CRTC state 9050 * @stream_state: the DC stream state. 9051 * 9052 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 9053 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 9054 */ 9055 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 9056 struct dc_stream_state *stream_state) 9057 { 9058 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 9059 } 9060 9061 static void dm_clear_writeback(struct amdgpu_display_manager *dm, 9062 struct dm_crtc_state *crtc_state) 9063 { 9064 dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0); 9065 } 9066 9067 static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, 9068 struct dc_state *dc_state) 9069 { 9070 struct drm_device *dev = state->dev; 9071 struct amdgpu_device *adev = drm_to_adev(dev); 9072 struct amdgpu_display_manager *dm = &adev->dm; 9073 struct drm_crtc *crtc; 9074 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 9075 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 9076 struct drm_connector_state *old_con_state; 9077 struct drm_connector *connector; 9078 bool mode_set_reset_required = false; 9079 u32 i; 9080 struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count}; 9081 9082 /* Disable writeback */ 9083 for_each_old_connector_in_state(state, connector, old_con_state, i) { 9084 struct dm_connector_state *dm_old_con_state; 9085 struct amdgpu_crtc *acrtc; 9086 9087 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 9088 continue; 9089 9090 old_crtc_state = NULL; 9091 9092 dm_old_con_state = to_dm_connector_state(old_con_state); 9093 if (!dm_old_con_state->base.crtc) 9094 continue; 9095 9096 acrtc = to_amdgpu_crtc(dm_old_con_state->base.crtc); 9097 if (acrtc) 9098 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 9099 9100 if (!acrtc->wb_enabled) 9101 continue; 9102 9103 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9104 9105 dm_clear_writeback(dm, dm_old_crtc_state); 9106 acrtc->wb_enabled = false; 9107 } 9108 9109 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 9110 new_crtc_state, i) { 9111 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 9112 9113 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9114 9115 if (old_crtc_state->active && 9116 (!new_crtc_state->active || 9117 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 9118 manage_dm_interrupts(adev, acrtc, false); 9119 dc_stream_release(dm_old_crtc_state->stream); 9120 } 9121 } 9122 9123 drm_atomic_helper_calc_timestamping_constants(state); 9124 9125 /* update changed items */ 9126 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 9127 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 9128 9129 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9130 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9131 9132 drm_dbg_state(state->dev, 9133 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 9134 acrtc->crtc_id, 9135 new_crtc_state->enable, 9136 new_crtc_state->active, 9137 new_crtc_state->planes_changed, 9138 new_crtc_state->mode_changed, 9139 new_crtc_state->active_changed, 9140 new_crtc_state->connectors_changed); 9141 9142 /* Disable cursor if disabling crtc */ 9143 if (old_crtc_state->active && !new_crtc_state->active) { 9144 struct dc_cursor_position position; 9145 9146 memset(&position, 0, sizeof(position)); 9147 mutex_lock(&dm->dc_lock); 9148 dc_stream_program_cursor_position(dm_old_crtc_state->stream, &position); 9149 mutex_unlock(&dm->dc_lock); 9150 } 9151 9152 /* Copy all transient state flags into dc state */ 9153 if (dm_new_crtc_state->stream) { 9154 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 9155 dm_new_crtc_state->stream); 9156 } 9157 9158 /* handles headless hotplug case, updating new_state and 9159 * aconnector as needed 9160 */ 9161 9162 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 9163 9164 DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); 9165 9166 if (!dm_new_crtc_state->stream) { 9167 /* 9168 * this could happen because of issues with 9169 * userspace notifications delivery. 9170 * In this case userspace tries to set mode on 9171 * display which is disconnected in fact. 9172 * dc_sink is NULL in this case on aconnector. 9173 * We expect reset mode will come soon. 9174 * 9175 * This can also happen when unplug is done 9176 * during resume sequence ended 9177 * 9178 * In this case, we want to pretend we still 9179 * have a sink to keep the pipe running so that 9180 * hw state is consistent with the sw state 9181 */ 9182 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 9183 __func__, acrtc->base.base.id); 9184 continue; 9185 } 9186 9187 if (dm_old_crtc_state->stream) 9188 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 9189 9190 pm_runtime_get_noresume(dev->dev); 9191 9192 acrtc->enabled = true; 9193 acrtc->hw_mode = new_crtc_state->mode; 9194 crtc->hwmode = new_crtc_state->mode; 9195 mode_set_reset_required = true; 9196 } else if (modereset_required(new_crtc_state)) { 9197 DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); 9198 /* i.e. reset mode */ 9199 if (dm_old_crtc_state->stream) 9200 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 9201 9202 mode_set_reset_required = true; 9203 } 9204 } /* for_each_crtc_in_state() */ 9205 9206 /* if there mode set or reset, disable eDP PSR, Replay */ 9207 if (mode_set_reset_required) { 9208 if (dm->vblank_control_workqueue) 9209 flush_workqueue(dm->vblank_control_workqueue); 9210 9211 amdgpu_dm_replay_disable_all(dm); 9212 amdgpu_dm_psr_disable_all(dm); 9213 } 9214 9215 dm_enable_per_frame_crtc_master_sync(dc_state); 9216 mutex_lock(&dm->dc_lock); 9217 WARN_ON(!dc_commit_streams(dm->dc, ¶ms)); 9218 9219 /* Allow idle optimization when vblank count is 0 for display off */ 9220 if (dm->active_vblank_irq_count == 0) 9221 dc_allow_idle_optimizations(dm->dc, true); 9222 mutex_unlock(&dm->dc_lock); 9223 9224 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 9225 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 9226 9227 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9228 9229 if (dm_new_crtc_state->stream != NULL) { 9230 const struct dc_stream_status *status = 9231 dc_stream_get_status(dm_new_crtc_state->stream); 9232 9233 if (!status) 9234 status = dc_state_get_stream_status(dc_state, 9235 dm_new_crtc_state->stream); 9236 if (!status) 9237 drm_err(dev, 9238 "got no status for stream %p on acrtc%p\n", 9239 dm_new_crtc_state->stream, acrtc); 9240 else 9241 acrtc->otg_inst = status->primary_otg_inst; 9242 } 9243 } 9244 } 9245 9246 static void dm_set_writeback(struct amdgpu_display_manager *dm, 9247 struct dm_crtc_state *crtc_state, 9248 struct drm_connector *connector, 9249 struct drm_connector_state *new_con_state) 9250 { 9251 struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector); 9252 struct amdgpu_device *adev = dm->adev; 9253 struct amdgpu_crtc *acrtc; 9254 struct dc_writeback_info *wb_info; 9255 struct pipe_ctx *pipe = NULL; 9256 struct amdgpu_framebuffer *afb; 9257 int i = 0; 9258 9259 wb_info = kzalloc(sizeof(*wb_info), GFP_KERNEL); 9260 if (!wb_info) { 9261 DRM_ERROR("Failed to allocate wb_info\n"); 9262 return; 9263 } 9264 9265 acrtc = to_amdgpu_crtc(wb_conn->encoder.crtc); 9266 if (!acrtc) { 9267 DRM_ERROR("no amdgpu_crtc found\n"); 9268 kfree(wb_info); 9269 return; 9270 } 9271 9272 afb = to_amdgpu_framebuffer(new_con_state->writeback_job->fb); 9273 if (!afb) { 9274 DRM_ERROR("No amdgpu_framebuffer found\n"); 9275 kfree(wb_info); 9276 return; 9277 } 9278 9279 for (i = 0; i < MAX_PIPES; i++) { 9280 if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) { 9281 pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i]; 9282 break; 9283 } 9284 } 9285 9286 /* fill in wb_info */ 9287 wb_info->wb_enabled = true; 9288 9289 wb_info->dwb_pipe_inst = 0; 9290 wb_info->dwb_params.dwbscl_black_color = 0; 9291 wb_info->dwb_params.hdr_mult = 0x1F000; 9292 wb_info->dwb_params.csc_params.gamut_adjust_type = CM_GAMUT_ADJUST_TYPE_BYPASS; 9293 wb_info->dwb_params.csc_params.gamut_coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13; 9294 wb_info->dwb_params.output_depth = DWB_OUTPUT_PIXEL_DEPTH_10BPC; 9295 wb_info->dwb_params.cnv_params.cnv_out_bpc = DWB_CNV_OUT_BPC_10BPC; 9296 9297 /* width & height from crtc */ 9298 wb_info->dwb_params.cnv_params.src_width = acrtc->base.mode.crtc_hdisplay; 9299 wb_info->dwb_params.cnv_params.src_height = acrtc->base.mode.crtc_vdisplay; 9300 wb_info->dwb_params.dest_width = acrtc->base.mode.crtc_hdisplay; 9301 wb_info->dwb_params.dest_height = acrtc->base.mode.crtc_vdisplay; 9302 9303 wb_info->dwb_params.cnv_params.crop_en = false; 9304 wb_info->dwb_params.stereo_params.stereo_enabled = false; 9305 9306 wb_info->dwb_params.cnv_params.out_max_pix_val = 0x3ff; // 10 bits 9307 wb_info->dwb_params.cnv_params.out_min_pix_val = 0; 9308 wb_info->dwb_params.cnv_params.fc_out_format = DWB_OUT_FORMAT_32BPP_ARGB; 9309 wb_info->dwb_params.cnv_params.out_denorm_mode = DWB_OUT_DENORM_BYPASS; 9310 9311 wb_info->dwb_params.out_format = dwb_scaler_mode_bypass444; 9312 9313 wb_info->dwb_params.capture_rate = dwb_capture_rate_0; 9314 9315 wb_info->dwb_params.scaler_taps.h_taps = 4; 9316 wb_info->dwb_params.scaler_taps.v_taps = 4; 9317 wb_info->dwb_params.scaler_taps.h_taps_c = 2; 9318 wb_info->dwb_params.scaler_taps.v_taps_c = 2; 9319 wb_info->dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING; 9320 9321 wb_info->mcif_buf_params.luma_pitch = afb->base.pitches[0]; 9322 wb_info->mcif_buf_params.chroma_pitch = afb->base.pitches[1]; 9323 9324 for (i = 0; i < DWB_MCIF_BUF_COUNT; i++) { 9325 wb_info->mcif_buf_params.luma_address[i] = afb->address; 9326 wb_info->mcif_buf_params.chroma_address[i] = 0; 9327 } 9328 9329 wb_info->mcif_buf_params.p_vmid = 1; 9330 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) { 9331 wb_info->mcif_warmup_params.start_address.quad_part = afb->address; 9332 wb_info->mcif_warmup_params.region_size = 9333 wb_info->mcif_buf_params.luma_pitch * wb_info->dwb_params.dest_height; 9334 } 9335 wb_info->mcif_warmup_params.p_vmid = 1; 9336 wb_info->writeback_source_plane = pipe->plane_state; 9337 9338 dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info); 9339 9340 acrtc->wb_pending = true; 9341 acrtc->wb_conn = wb_conn; 9342 drm_writeback_queue_job(wb_conn, new_con_state); 9343 } 9344 9345 /** 9346 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 9347 * @state: The atomic state to commit 9348 * 9349 * This will tell DC to commit the constructed DC state from atomic_check, 9350 * programming the hardware. Any failures here implies a hardware failure, since 9351 * atomic check should have filtered anything non-kosher. 9352 */ 9353 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) 9354 { 9355 struct drm_device *dev = state->dev; 9356 struct amdgpu_device *adev = drm_to_adev(dev); 9357 struct amdgpu_display_manager *dm = &adev->dm; 9358 struct dm_atomic_state *dm_state; 9359 struct dc_state *dc_state = NULL; 9360 u32 i, j; 9361 struct drm_crtc *crtc; 9362 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 9363 unsigned long flags; 9364 bool wait_for_vblank = true; 9365 struct drm_connector *connector; 9366 struct drm_connector_state *old_con_state, *new_con_state; 9367 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 9368 int crtc_disable_count = 0; 9369 9370 trace_amdgpu_dm_atomic_commit_tail_begin(state); 9371 9372 if (dm->dc->caps.ips_support && dm->dc->idle_optimizations_allowed) 9373 dc_allow_idle_optimizations(dm->dc, false); 9374 9375 drm_atomic_helper_update_legacy_modeset_state(dev, state); 9376 drm_dp_mst_atomic_wait_for_dependencies(state); 9377 9378 dm_state = dm_atomic_get_new_state(state); 9379 if (dm_state && dm_state->context) { 9380 dc_state = dm_state->context; 9381 amdgpu_dm_commit_streams(state, dc_state); 9382 } 9383 9384 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 9385 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9386 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 9387 struct amdgpu_dm_connector *aconnector; 9388 9389 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 9390 continue; 9391 9392 aconnector = to_amdgpu_dm_connector(connector); 9393 9394 if (!adev->dm.hdcp_workqueue) 9395 continue; 9396 9397 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i); 9398 9399 if (!connector) 9400 continue; 9401 9402 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 9403 connector->index, connector->status, connector->dpms); 9404 pr_debug("[HDCP_DM] state protection old: %x new: %x\n", 9405 old_con_state->content_protection, new_con_state->content_protection); 9406 9407 if (aconnector->dc_sink) { 9408 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 9409 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) { 9410 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n", 9411 aconnector->dc_sink->edid_caps.display_name); 9412 } 9413 } 9414 9415 new_crtc_state = NULL; 9416 old_crtc_state = NULL; 9417 9418 if (acrtc) { 9419 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 9420 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 9421 } 9422 9423 if (old_crtc_state) 9424 pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 9425 old_crtc_state->enable, 9426 old_crtc_state->active, 9427 old_crtc_state->mode_changed, 9428 old_crtc_state->active_changed, 9429 old_crtc_state->connectors_changed); 9430 9431 if (new_crtc_state) 9432 pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 9433 new_crtc_state->enable, 9434 new_crtc_state->active, 9435 new_crtc_state->mode_changed, 9436 new_crtc_state->active_changed, 9437 new_crtc_state->connectors_changed); 9438 } 9439 9440 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 9441 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9442 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 9443 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 9444 9445 if (!adev->dm.hdcp_workqueue) 9446 continue; 9447 9448 new_crtc_state = NULL; 9449 old_crtc_state = NULL; 9450 9451 if (acrtc) { 9452 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 9453 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 9454 } 9455 9456 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9457 9458 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && 9459 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 9460 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 9461 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 9462 dm_new_con_state->update_hdcp = true; 9463 continue; 9464 } 9465 9466 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state, 9467 old_con_state, connector, adev->dm.hdcp_workqueue)) { 9468 /* when display is unplugged from mst hub, connctor will 9469 * be destroyed within dm_dp_mst_connector_destroy. connector 9470 * hdcp perperties, like type, undesired, desired, enabled, 9471 * will be lost. So, save hdcp properties into hdcp_work within 9472 * amdgpu_dm_atomic_commit_tail. if the same display is 9473 * plugged back with same display index, its hdcp properties 9474 * will be retrieved from hdcp_work within dm_dp_mst_get_modes 9475 */ 9476 9477 bool enable_encryption = false; 9478 9479 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) 9480 enable_encryption = true; 9481 9482 if (aconnector->dc_link && aconnector->dc_sink && 9483 aconnector->dc_link->type == dc_connection_mst_branch) { 9484 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; 9485 struct hdcp_workqueue *hdcp_w = 9486 &hdcp_work[aconnector->dc_link->link_index]; 9487 9488 hdcp_w->hdcp_content_type[connector->index] = 9489 new_con_state->hdcp_content_type; 9490 hdcp_w->content_protection[connector->index] = 9491 new_con_state->content_protection; 9492 } 9493 9494 if (new_crtc_state && new_crtc_state->mode_changed && 9495 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) 9496 enable_encryption = true; 9497 9498 DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption); 9499 9500 hdcp_update_display( 9501 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, 9502 new_con_state->hdcp_content_type, enable_encryption); 9503 } 9504 } 9505 9506 /* Handle connector state changes */ 9507 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 9508 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9509 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 9510 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 9511 struct dc_surface_update *dummy_updates; 9512 struct dc_stream_update stream_update; 9513 struct dc_info_packet hdr_packet; 9514 struct dc_stream_status *status = NULL; 9515 bool abm_changed, hdr_changed, scaling_changed; 9516 9517 memset(&stream_update, 0, sizeof(stream_update)); 9518 9519 if (acrtc) { 9520 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 9521 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 9522 } 9523 9524 /* Skip any modesets/resets */ 9525 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 9526 continue; 9527 9528 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9529 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9530 9531 scaling_changed = is_scaling_state_different(dm_new_con_state, 9532 dm_old_con_state); 9533 9534 abm_changed = dm_new_crtc_state->abm_level != 9535 dm_old_crtc_state->abm_level; 9536 9537 hdr_changed = 9538 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); 9539 9540 if (!scaling_changed && !abm_changed && !hdr_changed) 9541 continue; 9542 9543 stream_update.stream = dm_new_crtc_state->stream; 9544 if (scaling_changed) { 9545 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, 9546 dm_new_con_state, dm_new_crtc_state->stream); 9547 9548 stream_update.src = dm_new_crtc_state->stream->src; 9549 stream_update.dst = dm_new_crtc_state->stream->dst; 9550 } 9551 9552 if (abm_changed) { 9553 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 9554 9555 stream_update.abm_level = &dm_new_crtc_state->abm_level; 9556 } 9557 9558 if (hdr_changed) { 9559 fill_hdr_info_packet(new_con_state, &hdr_packet); 9560 stream_update.hdr_static_metadata = &hdr_packet; 9561 } 9562 9563 status = dc_stream_get_status(dm_new_crtc_state->stream); 9564 9565 if (WARN_ON(!status)) 9566 continue; 9567 9568 WARN_ON(!status->plane_count); 9569 9570 /* 9571 * TODO: DC refuses to perform stream updates without a dc_surface_update. 9572 * Here we create an empty update on each plane. 9573 * To fix this, DC should permit updating only stream properties. 9574 */ 9575 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC); 9576 if (!dummy_updates) { 9577 DRM_ERROR("Failed to allocate memory for dummy_updates.\n"); 9578 continue; 9579 } 9580 for (j = 0; j < status->plane_count; j++) 9581 dummy_updates[j].surface = status->plane_states[0]; 9582 9583 9584 mutex_lock(&dm->dc_lock); 9585 dc_update_planes_and_stream(dm->dc, 9586 dummy_updates, 9587 status->plane_count, 9588 dm_new_crtc_state->stream, 9589 &stream_update); 9590 mutex_unlock(&dm->dc_lock); 9591 kfree(dummy_updates); 9592 } 9593 9594 /** 9595 * Enable interrupts for CRTCs that are newly enabled or went through 9596 * a modeset. It was intentionally deferred until after the front end 9597 * state was modified to wait until the OTG was on and so the IRQ 9598 * handlers didn't access stale or invalid state. 9599 */ 9600 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 9601 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 9602 #ifdef CONFIG_DEBUG_FS 9603 enum amdgpu_dm_pipe_crc_source cur_crc_src; 9604 #endif 9605 /* Count number of newly disabled CRTCs for dropping PM refs later. */ 9606 if (old_crtc_state->active && !new_crtc_state->active) 9607 crtc_disable_count++; 9608 9609 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9610 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9611 9612 /* For freesync config update on crtc state and params for irq */ 9613 update_stream_irq_parameters(dm, dm_new_crtc_state); 9614 9615 #ifdef CONFIG_DEBUG_FS 9616 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 9617 cur_crc_src = acrtc->dm_irq_params.crc_src; 9618 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 9619 #endif 9620 9621 if (new_crtc_state->active && 9622 (!old_crtc_state->active || 9623 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 9624 dc_stream_retain(dm_new_crtc_state->stream); 9625 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; 9626 manage_dm_interrupts(adev, acrtc, true); 9627 } 9628 /* Handle vrr on->off / off->on transitions */ 9629 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state); 9630 9631 #ifdef CONFIG_DEBUG_FS 9632 if (new_crtc_state->active && 9633 (!old_crtc_state->active || 9634 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 9635 /** 9636 * Frontend may have changed so reapply the CRC capture 9637 * settings for the stream. 9638 */ 9639 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { 9640 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 9641 if (amdgpu_dm_crc_window_is_activated(crtc)) { 9642 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 9643 acrtc->dm_irq_params.window_param.update_win = true; 9644 9645 /** 9646 * It takes 2 frames for HW to stably generate CRC when 9647 * resuming from suspend, so we set skip_frame_cnt 2. 9648 */ 9649 acrtc->dm_irq_params.window_param.skip_frame_cnt = 2; 9650 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 9651 } 9652 #endif 9653 if (amdgpu_dm_crtc_configure_crc_source( 9654 crtc, dm_new_crtc_state, cur_crc_src)) 9655 DRM_DEBUG_DRIVER("Failed to configure crc source"); 9656 } 9657 } 9658 #endif 9659 } 9660 9661 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 9662 if (new_crtc_state->async_flip) 9663 wait_for_vblank = false; 9664 9665 /* update planes when needed per crtc*/ 9666 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 9667 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9668 9669 if (dm_new_crtc_state->stream) 9670 amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank); 9671 } 9672 9673 /* Enable writeback */ 9674 for_each_new_connector_in_state(state, connector, new_con_state, i) { 9675 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9676 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 9677 9678 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 9679 continue; 9680 9681 if (!new_con_state->writeback_job) 9682 continue; 9683 9684 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 9685 9686 if (!new_crtc_state) 9687 continue; 9688 9689 if (acrtc->wb_enabled) 9690 continue; 9691 9692 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9693 9694 dm_set_writeback(dm, dm_new_crtc_state, connector, new_con_state); 9695 acrtc->wb_enabled = true; 9696 } 9697 9698 /* Update audio instances for each connector. */ 9699 amdgpu_dm_commit_audio(dev, state); 9700 9701 /* restore the backlight level */ 9702 for (i = 0; i < dm->num_of_edps; i++) { 9703 if (dm->backlight_dev[i] && 9704 (dm->actual_brightness[i] != dm->brightness[i])) 9705 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 9706 } 9707 9708 /* 9709 * send vblank event on all events not handled in flip and 9710 * mark consumed event for drm_atomic_helper_commit_hw_done 9711 */ 9712 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 9713 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 9714 9715 if (new_crtc_state->event) 9716 drm_send_event_locked(dev, &new_crtc_state->event->base); 9717 9718 new_crtc_state->event = NULL; 9719 } 9720 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 9721 9722 /* Signal HW programming completion */ 9723 drm_atomic_helper_commit_hw_done(state); 9724 9725 if (wait_for_vblank) 9726 drm_atomic_helper_wait_for_flip_done(dev, state); 9727 9728 drm_atomic_helper_cleanup_planes(dev, state); 9729 9730 /* Don't free the memory if we are hitting this as part of suspend. 9731 * This way we don't free any memory during suspend; see 9732 * amdgpu_bo_free_kernel(). The memory will be freed in the first 9733 * non-suspend modeset or when the driver is torn down. 9734 */ 9735 if (!adev->in_suspend) { 9736 /* return the stolen vga memory back to VRAM */ 9737 if (!adev->mman.keep_stolen_vga_memory) 9738 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 9739 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 9740 } 9741 9742 /* 9743 * Finally, drop a runtime PM reference for each newly disabled CRTC, 9744 * so we can put the GPU into runtime suspend if we're not driving any 9745 * displays anymore 9746 */ 9747 for (i = 0; i < crtc_disable_count; i++) 9748 pm_runtime_put_autosuspend(dev->dev); 9749 pm_runtime_mark_last_busy(dev->dev); 9750 } 9751 9752 static int dm_force_atomic_commit(struct drm_connector *connector) 9753 { 9754 int ret = 0; 9755 struct drm_device *ddev = connector->dev; 9756 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); 9757 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 9758 struct drm_plane *plane = disconnected_acrtc->base.primary; 9759 struct drm_connector_state *conn_state; 9760 struct drm_crtc_state *crtc_state; 9761 struct drm_plane_state *plane_state; 9762 9763 if (!state) 9764 return -ENOMEM; 9765 9766 state->acquire_ctx = ddev->mode_config.acquire_ctx; 9767 9768 /* Construct an atomic state to restore previous display setting */ 9769 9770 /* 9771 * Attach connectors to drm_atomic_state 9772 */ 9773 conn_state = drm_atomic_get_connector_state(state, connector); 9774 9775 ret = PTR_ERR_OR_ZERO(conn_state); 9776 if (ret) 9777 goto out; 9778 9779 /* Attach crtc to drm_atomic_state*/ 9780 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 9781 9782 ret = PTR_ERR_OR_ZERO(crtc_state); 9783 if (ret) 9784 goto out; 9785 9786 /* force a restore */ 9787 crtc_state->mode_changed = true; 9788 9789 /* Attach plane to drm_atomic_state */ 9790 plane_state = drm_atomic_get_plane_state(state, plane); 9791 9792 ret = PTR_ERR_OR_ZERO(plane_state); 9793 if (ret) 9794 goto out; 9795 9796 /* Call commit internally with the state we just constructed */ 9797 ret = drm_atomic_commit(state); 9798 9799 out: 9800 drm_atomic_state_put(state); 9801 if (ret) 9802 DRM_ERROR("Restoring old state failed with %i\n", ret); 9803 9804 return ret; 9805 } 9806 9807 /* 9808 * This function handles all cases when set mode does not come upon hotplug. 9809 * This includes when a display is unplugged then plugged back into the 9810 * same port and when running without usermode desktop manager supprot 9811 */ 9812 void dm_restore_drm_connector_state(struct drm_device *dev, 9813 struct drm_connector *connector) 9814 { 9815 struct amdgpu_dm_connector *aconnector; 9816 struct amdgpu_crtc *disconnected_acrtc; 9817 struct dm_crtc_state *acrtc_state; 9818 9819 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 9820 return; 9821 9822 aconnector = to_amdgpu_dm_connector(connector); 9823 9824 if (!aconnector->dc_sink || !connector->state || !connector->encoder) 9825 return; 9826 9827 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 9828 if (!disconnected_acrtc) 9829 return; 9830 9831 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); 9832 if (!acrtc_state->stream) 9833 return; 9834 9835 /* 9836 * If the previous sink is not released and different from the current, 9837 * we deduce we are in a state where we can not rely on usermode call 9838 * to turn on the display, so we do it here 9839 */ 9840 if (acrtc_state->stream->sink != aconnector->dc_sink) 9841 dm_force_atomic_commit(&aconnector->base); 9842 } 9843 9844 /* 9845 * Grabs all modesetting locks to serialize against any blocking commits, 9846 * Waits for completion of all non blocking commits. 9847 */ 9848 static int do_aquire_global_lock(struct drm_device *dev, 9849 struct drm_atomic_state *state) 9850 { 9851 struct drm_crtc *crtc; 9852 struct drm_crtc_commit *commit; 9853 long ret; 9854 9855 /* 9856 * Adding all modeset locks to aquire_ctx will 9857 * ensure that when the framework release it the 9858 * extra locks we are locking here will get released to 9859 */ 9860 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 9861 if (ret) 9862 return ret; 9863 9864 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 9865 spin_lock(&crtc->commit_lock); 9866 commit = list_first_entry_or_null(&crtc->commit_list, 9867 struct drm_crtc_commit, commit_entry); 9868 if (commit) 9869 drm_crtc_commit_get(commit); 9870 spin_unlock(&crtc->commit_lock); 9871 9872 if (!commit) 9873 continue; 9874 9875 /* 9876 * Make sure all pending HW programming completed and 9877 * page flips done 9878 */ 9879 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 9880 9881 if (ret > 0) 9882 ret = wait_for_completion_interruptible_timeout( 9883 &commit->flip_done, 10*HZ); 9884 9885 if (ret == 0) 9886 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n", 9887 crtc->base.id, crtc->name); 9888 9889 drm_crtc_commit_put(commit); 9890 } 9891 9892 return ret < 0 ? ret : 0; 9893 } 9894 9895 static void get_freesync_config_for_crtc( 9896 struct dm_crtc_state *new_crtc_state, 9897 struct dm_connector_state *new_con_state) 9898 { 9899 struct mod_freesync_config config = {0}; 9900 struct amdgpu_dm_connector *aconnector; 9901 struct drm_display_mode *mode = &new_crtc_state->base.mode; 9902 int vrefresh = drm_mode_vrefresh(mode); 9903 bool fs_vid_mode = false; 9904 9905 if (new_con_state->base.connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 9906 return; 9907 9908 aconnector = to_amdgpu_dm_connector(new_con_state->base.connector); 9909 9910 new_crtc_state->vrr_supported = new_con_state->freesync_capable && 9911 vrefresh >= aconnector->min_vfreq && 9912 vrefresh <= aconnector->max_vfreq; 9913 9914 if (new_crtc_state->vrr_supported) { 9915 new_crtc_state->stream->ignore_msa_timing_param = true; 9916 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 9917 9918 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000; 9919 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000; 9920 config.vsif_supported = true; 9921 config.btr = true; 9922 9923 if (fs_vid_mode) { 9924 config.state = VRR_STATE_ACTIVE_FIXED; 9925 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz; 9926 goto out; 9927 } else if (new_crtc_state->base.vrr_enabled) { 9928 config.state = VRR_STATE_ACTIVE_VARIABLE; 9929 } else { 9930 config.state = VRR_STATE_INACTIVE; 9931 } 9932 } 9933 out: 9934 new_crtc_state->freesync_config = config; 9935 } 9936 9937 static void reset_freesync_config_for_crtc( 9938 struct dm_crtc_state *new_crtc_state) 9939 { 9940 new_crtc_state->vrr_supported = false; 9941 9942 memset(&new_crtc_state->vrr_infopacket, 0, 9943 sizeof(new_crtc_state->vrr_infopacket)); 9944 } 9945 9946 static bool 9947 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 9948 struct drm_crtc_state *new_crtc_state) 9949 { 9950 const struct drm_display_mode *old_mode, *new_mode; 9951 9952 if (!old_crtc_state || !new_crtc_state) 9953 return false; 9954 9955 old_mode = &old_crtc_state->mode; 9956 new_mode = &new_crtc_state->mode; 9957 9958 if (old_mode->clock == new_mode->clock && 9959 old_mode->hdisplay == new_mode->hdisplay && 9960 old_mode->vdisplay == new_mode->vdisplay && 9961 old_mode->htotal == new_mode->htotal && 9962 old_mode->vtotal != new_mode->vtotal && 9963 old_mode->hsync_start == new_mode->hsync_start && 9964 old_mode->vsync_start != new_mode->vsync_start && 9965 old_mode->hsync_end == new_mode->hsync_end && 9966 old_mode->vsync_end != new_mode->vsync_end && 9967 old_mode->hskew == new_mode->hskew && 9968 old_mode->vscan == new_mode->vscan && 9969 (old_mode->vsync_end - old_mode->vsync_start) == 9970 (new_mode->vsync_end - new_mode->vsync_start)) 9971 return true; 9972 9973 return false; 9974 } 9975 9976 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) 9977 { 9978 u64 num, den, res; 9979 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base; 9980 9981 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED; 9982 9983 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000; 9984 den = (unsigned long long)new_crtc_state->mode.htotal * 9985 (unsigned long long)new_crtc_state->mode.vtotal; 9986 9987 res = div_u64(num, den); 9988 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res; 9989 } 9990 9991 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 9992 struct drm_atomic_state *state, 9993 struct drm_crtc *crtc, 9994 struct drm_crtc_state *old_crtc_state, 9995 struct drm_crtc_state *new_crtc_state, 9996 bool enable, 9997 bool *lock_and_validation_needed) 9998 { 9999 struct dm_atomic_state *dm_state = NULL; 10000 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 10001 struct dc_stream_state *new_stream; 10002 int ret = 0; 10003 10004 /* 10005 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 10006 * update changed items 10007 */ 10008 struct amdgpu_crtc *acrtc = NULL; 10009 struct drm_connector *connector = NULL; 10010 struct amdgpu_dm_connector *aconnector = NULL; 10011 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 10012 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 10013 10014 new_stream = NULL; 10015 10016 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 10017 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 10018 acrtc = to_amdgpu_crtc(crtc); 10019 connector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 10020 if (connector) 10021 aconnector = to_amdgpu_dm_connector(connector); 10022 10023 /* TODO This hack should go away */ 10024 if (connector && enable) { 10025 /* Make sure fake sink is created in plug-in scenario */ 10026 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 10027 connector); 10028 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 10029 connector); 10030 10031 if (IS_ERR(drm_new_conn_state)) { 10032 ret = PTR_ERR_OR_ZERO(drm_new_conn_state); 10033 goto fail; 10034 } 10035 10036 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 10037 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 10038 10039 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 10040 goto skip_modeset; 10041 10042 new_stream = create_validate_stream_for_sink(aconnector, 10043 &new_crtc_state->mode, 10044 dm_new_conn_state, 10045 dm_old_crtc_state->stream); 10046 10047 /* 10048 * we can have no stream on ACTION_SET if a display 10049 * was disconnected during S3, in this case it is not an 10050 * error, the OS will be updated after detection, and 10051 * will do the right thing on next atomic commit 10052 */ 10053 10054 if (!new_stream) { 10055 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 10056 __func__, acrtc->base.base.id); 10057 ret = -ENOMEM; 10058 goto fail; 10059 } 10060 10061 /* 10062 * TODO: Check VSDB bits to decide whether this should 10063 * be enabled or not. 10064 */ 10065 new_stream->triggered_crtc_reset.enabled = 10066 dm->force_timing_sync; 10067 10068 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 10069 10070 ret = fill_hdr_info_packet(drm_new_conn_state, 10071 &new_stream->hdr_static_metadata); 10072 if (ret) 10073 goto fail; 10074 10075 /* 10076 * If we already removed the old stream from the context 10077 * (and set the new stream to NULL) then we can't reuse 10078 * the old stream even if the stream and scaling are unchanged. 10079 * We'll hit the BUG_ON and black screen. 10080 * 10081 * TODO: Refactor this function to allow this check to work 10082 * in all conditions. 10083 */ 10084 if (amdgpu_freesync_vid_mode && 10085 dm_new_crtc_state->stream && 10086 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state)) 10087 goto skip_modeset; 10088 10089 if (dm_new_crtc_state->stream && 10090 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 10091 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 10092 new_crtc_state->mode_changed = false; 10093 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", 10094 new_crtc_state->mode_changed); 10095 } 10096 } 10097 10098 /* mode_changed flag may get updated above, need to check again */ 10099 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 10100 goto skip_modeset; 10101 10102 drm_dbg_state(state->dev, 10103 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 10104 acrtc->crtc_id, 10105 new_crtc_state->enable, 10106 new_crtc_state->active, 10107 new_crtc_state->planes_changed, 10108 new_crtc_state->mode_changed, 10109 new_crtc_state->active_changed, 10110 new_crtc_state->connectors_changed); 10111 10112 /* Remove stream for any changed/disabled CRTC */ 10113 if (!enable) { 10114 10115 if (!dm_old_crtc_state->stream) 10116 goto skip_modeset; 10117 10118 /* Unset freesync video if it was active before */ 10119 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) { 10120 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE; 10121 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0; 10122 } 10123 10124 /* Now check if we should set freesync video mode */ 10125 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream && 10126 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 10127 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) && 10128 is_timing_unchanged_for_freesync(new_crtc_state, 10129 old_crtc_state)) { 10130 new_crtc_state->mode_changed = false; 10131 DRM_DEBUG_DRIVER( 10132 "Mode change not required for front porch change, setting mode_changed to %d", 10133 new_crtc_state->mode_changed); 10134 10135 set_freesync_fixed_config(dm_new_crtc_state); 10136 10137 goto skip_modeset; 10138 } else if (amdgpu_freesync_vid_mode && aconnector && 10139 is_freesync_video_mode(&new_crtc_state->mode, 10140 aconnector)) { 10141 struct drm_display_mode *high_mode; 10142 10143 high_mode = get_highest_refresh_rate_mode(aconnector, false); 10144 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) 10145 set_freesync_fixed_config(dm_new_crtc_state); 10146 } 10147 10148 ret = dm_atomic_get_state(state, &dm_state); 10149 if (ret) 10150 goto fail; 10151 10152 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", 10153 crtc->base.id); 10154 10155 /* i.e. reset mode */ 10156 if (dc_state_remove_stream( 10157 dm->dc, 10158 dm_state->context, 10159 dm_old_crtc_state->stream) != DC_OK) { 10160 ret = -EINVAL; 10161 goto fail; 10162 } 10163 10164 dc_stream_release(dm_old_crtc_state->stream); 10165 dm_new_crtc_state->stream = NULL; 10166 10167 reset_freesync_config_for_crtc(dm_new_crtc_state); 10168 10169 *lock_and_validation_needed = true; 10170 10171 } else {/* Add stream for any updated/enabled CRTC */ 10172 /* 10173 * Quick fix to prevent NULL pointer on new_stream when 10174 * added MST connectors not found in existing crtc_state in the chained mode 10175 * TODO: need to dig out the root cause of that 10176 */ 10177 if (!connector) 10178 goto skip_modeset; 10179 10180 if (modereset_required(new_crtc_state)) 10181 goto skip_modeset; 10182 10183 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream, 10184 dm_old_crtc_state->stream)) { 10185 10186 WARN_ON(dm_new_crtc_state->stream); 10187 10188 ret = dm_atomic_get_state(state, &dm_state); 10189 if (ret) 10190 goto fail; 10191 10192 dm_new_crtc_state->stream = new_stream; 10193 10194 dc_stream_retain(new_stream); 10195 10196 DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n", 10197 crtc->base.id); 10198 10199 if (dc_state_add_stream( 10200 dm->dc, 10201 dm_state->context, 10202 dm_new_crtc_state->stream) != DC_OK) { 10203 ret = -EINVAL; 10204 goto fail; 10205 } 10206 10207 *lock_and_validation_needed = true; 10208 } 10209 } 10210 10211 skip_modeset: 10212 /* Release extra reference */ 10213 if (new_stream) 10214 dc_stream_release(new_stream); 10215 10216 /* 10217 * We want to do dc stream updates that do not require a 10218 * full modeset below. 10219 */ 10220 if (!(enable && connector && new_crtc_state->active)) 10221 return 0; 10222 /* 10223 * Given above conditions, the dc state cannot be NULL because: 10224 * 1. We're in the process of enabling CRTCs (just been added 10225 * to the dc context, or already is on the context) 10226 * 2. Has a valid connector attached, and 10227 * 3. Is currently active and enabled. 10228 * => The dc stream state currently exists. 10229 */ 10230 BUG_ON(dm_new_crtc_state->stream == NULL); 10231 10232 /* Scaling or underscan settings */ 10233 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || 10234 drm_atomic_crtc_needs_modeset(new_crtc_state)) 10235 update_stream_scaling_settings( 10236 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 10237 10238 /* ABM settings */ 10239 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 10240 10241 /* 10242 * Color management settings. We also update color properties 10243 * when a modeset is needed, to ensure it gets reprogrammed. 10244 */ 10245 if (dm_new_crtc_state->base.color_mgmt_changed || 10246 dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf || 10247 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 10248 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); 10249 if (ret) 10250 goto fail; 10251 } 10252 10253 /* Update Freesync settings. */ 10254 get_freesync_config_for_crtc(dm_new_crtc_state, 10255 dm_new_conn_state); 10256 10257 return ret; 10258 10259 fail: 10260 if (new_stream) 10261 dc_stream_release(new_stream); 10262 return ret; 10263 } 10264 10265 static bool should_reset_plane(struct drm_atomic_state *state, 10266 struct drm_plane *plane, 10267 struct drm_plane_state *old_plane_state, 10268 struct drm_plane_state *new_plane_state) 10269 { 10270 struct drm_plane *other; 10271 struct drm_plane_state *old_other_state, *new_other_state; 10272 struct drm_crtc_state *new_crtc_state; 10273 struct amdgpu_device *adev = drm_to_adev(plane->dev); 10274 int i; 10275 10276 /* 10277 * TODO: Remove this hack for all asics once it proves that the 10278 * fast updates works fine on DCN3.2+. 10279 */ 10280 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 2, 0) && 10281 state->allow_modeset) 10282 return true; 10283 10284 /* Exit early if we know that we're adding or removing the plane. */ 10285 if (old_plane_state->crtc != new_plane_state->crtc) 10286 return true; 10287 10288 /* old crtc == new_crtc == NULL, plane not in context. */ 10289 if (!new_plane_state->crtc) 10290 return false; 10291 10292 new_crtc_state = 10293 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 10294 10295 if (!new_crtc_state) 10296 return true; 10297 10298 /* CRTC Degamma changes currently require us to recreate planes. */ 10299 if (new_crtc_state->color_mgmt_changed) 10300 return true; 10301 10302 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) 10303 return true; 10304 10305 /* 10306 * If there are any new primary or overlay planes being added or 10307 * removed then the z-order can potentially change. To ensure 10308 * correct z-order and pipe acquisition the current DC architecture 10309 * requires us to remove and recreate all existing planes. 10310 * 10311 * TODO: Come up with a more elegant solution for this. 10312 */ 10313 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 10314 struct amdgpu_framebuffer *old_afb, *new_afb; 10315 struct dm_plane_state *dm_new_other_state, *dm_old_other_state; 10316 10317 dm_new_other_state = to_dm_plane_state(new_other_state); 10318 dm_old_other_state = to_dm_plane_state(old_other_state); 10319 10320 if (other->type == DRM_PLANE_TYPE_CURSOR) 10321 continue; 10322 10323 if (old_other_state->crtc != new_plane_state->crtc && 10324 new_other_state->crtc != new_plane_state->crtc) 10325 continue; 10326 10327 if (old_other_state->crtc != new_other_state->crtc) 10328 return true; 10329 10330 /* Src/dst size and scaling updates. */ 10331 if (old_other_state->src_w != new_other_state->src_w || 10332 old_other_state->src_h != new_other_state->src_h || 10333 old_other_state->crtc_w != new_other_state->crtc_w || 10334 old_other_state->crtc_h != new_other_state->crtc_h) 10335 return true; 10336 10337 /* Rotation / mirroring updates. */ 10338 if (old_other_state->rotation != new_other_state->rotation) 10339 return true; 10340 10341 /* Blending updates. */ 10342 if (old_other_state->pixel_blend_mode != 10343 new_other_state->pixel_blend_mode) 10344 return true; 10345 10346 /* Alpha updates. */ 10347 if (old_other_state->alpha != new_other_state->alpha) 10348 return true; 10349 10350 /* Colorspace changes. */ 10351 if (old_other_state->color_range != new_other_state->color_range || 10352 old_other_state->color_encoding != new_other_state->color_encoding) 10353 return true; 10354 10355 /* HDR/Transfer Function changes. */ 10356 if (dm_old_other_state->degamma_tf != dm_new_other_state->degamma_tf || 10357 dm_old_other_state->degamma_lut != dm_new_other_state->degamma_lut || 10358 dm_old_other_state->hdr_mult != dm_new_other_state->hdr_mult || 10359 dm_old_other_state->ctm != dm_new_other_state->ctm || 10360 dm_old_other_state->shaper_lut != dm_new_other_state->shaper_lut || 10361 dm_old_other_state->shaper_tf != dm_new_other_state->shaper_tf || 10362 dm_old_other_state->lut3d != dm_new_other_state->lut3d || 10363 dm_old_other_state->blend_lut != dm_new_other_state->blend_lut || 10364 dm_old_other_state->blend_tf != dm_new_other_state->blend_tf) 10365 return true; 10366 10367 /* Framebuffer checks fall at the end. */ 10368 if (!old_other_state->fb || !new_other_state->fb) 10369 continue; 10370 10371 /* Pixel format changes can require bandwidth updates. */ 10372 if (old_other_state->fb->format != new_other_state->fb->format) 10373 return true; 10374 10375 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; 10376 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb; 10377 10378 /* Tiling and DCC changes also require bandwidth updates. */ 10379 if (old_afb->tiling_flags != new_afb->tiling_flags || 10380 old_afb->base.modifier != new_afb->base.modifier) 10381 return true; 10382 } 10383 10384 return false; 10385 } 10386 10387 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, 10388 struct drm_plane_state *new_plane_state, 10389 struct drm_framebuffer *fb) 10390 { 10391 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev); 10392 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); 10393 unsigned int pitch; 10394 bool linear; 10395 10396 if (fb->width > new_acrtc->max_cursor_width || 10397 fb->height > new_acrtc->max_cursor_height) { 10398 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n", 10399 new_plane_state->fb->width, 10400 new_plane_state->fb->height); 10401 return -EINVAL; 10402 } 10403 if (new_plane_state->src_w != fb->width << 16 || 10404 new_plane_state->src_h != fb->height << 16) { 10405 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 10406 return -EINVAL; 10407 } 10408 10409 /* Pitch in pixels */ 10410 pitch = fb->pitches[0] / fb->format->cpp[0]; 10411 10412 if (fb->width != pitch) { 10413 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d", 10414 fb->width, pitch); 10415 return -EINVAL; 10416 } 10417 10418 switch (pitch) { 10419 case 64: 10420 case 128: 10421 case 256: 10422 /* FB pitch is supported by cursor plane */ 10423 break; 10424 default: 10425 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch); 10426 return -EINVAL; 10427 } 10428 10429 /* Core DRM takes care of checking FB modifiers, so we only need to 10430 * check tiling flags when the FB doesn't have a modifier. 10431 */ 10432 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { 10433 if (adev->family < AMDGPU_FAMILY_AI) { 10434 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && 10435 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && 10436 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; 10437 } else { 10438 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; 10439 } 10440 if (!linear) { 10441 DRM_DEBUG_ATOMIC("Cursor FB not linear"); 10442 return -EINVAL; 10443 } 10444 } 10445 10446 return 0; 10447 } 10448 10449 static int dm_update_plane_state(struct dc *dc, 10450 struct drm_atomic_state *state, 10451 struct drm_plane *plane, 10452 struct drm_plane_state *old_plane_state, 10453 struct drm_plane_state *new_plane_state, 10454 bool enable, 10455 bool *lock_and_validation_needed, 10456 bool *is_top_most_overlay) 10457 { 10458 10459 struct dm_atomic_state *dm_state = NULL; 10460 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 10461 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 10462 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 10463 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 10464 struct amdgpu_crtc *new_acrtc; 10465 bool needs_reset; 10466 int ret = 0; 10467 10468 10469 new_plane_crtc = new_plane_state->crtc; 10470 old_plane_crtc = old_plane_state->crtc; 10471 dm_new_plane_state = to_dm_plane_state(new_plane_state); 10472 dm_old_plane_state = to_dm_plane_state(old_plane_state); 10473 10474 if (plane->type == DRM_PLANE_TYPE_CURSOR) { 10475 if (!enable || !new_plane_crtc || 10476 drm_atomic_plane_disabling(plane->state, new_plane_state)) 10477 return 0; 10478 10479 new_acrtc = to_amdgpu_crtc(new_plane_crtc); 10480 10481 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) { 10482 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 10483 return -EINVAL; 10484 } 10485 10486 if (new_plane_state->fb) { 10487 ret = dm_check_cursor_fb(new_acrtc, new_plane_state, 10488 new_plane_state->fb); 10489 if (ret) 10490 return ret; 10491 } 10492 10493 return 0; 10494 } 10495 10496 needs_reset = should_reset_plane(state, plane, old_plane_state, 10497 new_plane_state); 10498 10499 /* Remove any changed/removed planes */ 10500 if (!enable) { 10501 if (!needs_reset) 10502 return 0; 10503 10504 if (!old_plane_crtc) 10505 return 0; 10506 10507 old_crtc_state = drm_atomic_get_old_crtc_state( 10508 state, old_plane_crtc); 10509 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 10510 10511 if (!dm_old_crtc_state->stream) 10512 return 0; 10513 10514 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", 10515 plane->base.id, old_plane_crtc->base.id); 10516 10517 ret = dm_atomic_get_state(state, &dm_state); 10518 if (ret) 10519 return ret; 10520 10521 if (!dc_state_remove_plane( 10522 dc, 10523 dm_old_crtc_state->stream, 10524 dm_old_plane_state->dc_state, 10525 dm_state->context)) { 10526 10527 return -EINVAL; 10528 } 10529 10530 if (dm_old_plane_state->dc_state) 10531 dc_plane_state_release(dm_old_plane_state->dc_state); 10532 10533 dm_new_plane_state->dc_state = NULL; 10534 10535 *lock_and_validation_needed = true; 10536 10537 } else { /* Add new planes */ 10538 struct dc_plane_state *dc_new_plane_state; 10539 10540 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 10541 return 0; 10542 10543 if (!new_plane_crtc) 10544 return 0; 10545 10546 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 10547 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 10548 10549 if (!dm_new_crtc_state->stream) 10550 return 0; 10551 10552 if (!needs_reset) 10553 return 0; 10554 10555 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); 10556 if (ret) 10557 return ret; 10558 10559 WARN_ON(dm_new_plane_state->dc_state); 10560 10561 dc_new_plane_state = dc_create_plane_state(dc); 10562 if (!dc_new_plane_state) 10563 return -ENOMEM; 10564 10565 /* Block top most plane from being a video plane */ 10566 if (plane->type == DRM_PLANE_TYPE_OVERLAY) { 10567 if (amdgpu_dm_plane_is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay) 10568 return -EINVAL; 10569 10570 *is_top_most_overlay = false; 10571 } 10572 10573 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n", 10574 plane->base.id, new_plane_crtc->base.id); 10575 10576 ret = fill_dc_plane_attributes( 10577 drm_to_adev(new_plane_crtc->dev), 10578 dc_new_plane_state, 10579 new_plane_state, 10580 new_crtc_state); 10581 if (ret) { 10582 dc_plane_state_release(dc_new_plane_state); 10583 return ret; 10584 } 10585 10586 ret = dm_atomic_get_state(state, &dm_state); 10587 if (ret) { 10588 dc_plane_state_release(dc_new_plane_state); 10589 return ret; 10590 } 10591 10592 /* 10593 * Any atomic check errors that occur after this will 10594 * not need a release. The plane state will be attached 10595 * to the stream, and therefore part of the atomic 10596 * state. It'll be released when the atomic state is 10597 * cleaned. 10598 */ 10599 if (!dc_state_add_plane( 10600 dc, 10601 dm_new_crtc_state->stream, 10602 dc_new_plane_state, 10603 dm_state->context)) { 10604 10605 dc_plane_state_release(dc_new_plane_state); 10606 return -EINVAL; 10607 } 10608 10609 dm_new_plane_state->dc_state = dc_new_plane_state; 10610 10611 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY); 10612 10613 /* Tell DC to do a full surface update every time there 10614 * is a plane change. Inefficient, but works for now. 10615 */ 10616 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; 10617 10618 *lock_and_validation_needed = true; 10619 } 10620 10621 10622 return ret; 10623 } 10624 10625 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state, 10626 int *src_w, int *src_h) 10627 { 10628 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 10629 case DRM_MODE_ROTATE_90: 10630 case DRM_MODE_ROTATE_270: 10631 *src_w = plane_state->src_h >> 16; 10632 *src_h = plane_state->src_w >> 16; 10633 break; 10634 case DRM_MODE_ROTATE_0: 10635 case DRM_MODE_ROTATE_180: 10636 default: 10637 *src_w = plane_state->src_w >> 16; 10638 *src_h = plane_state->src_h >> 16; 10639 break; 10640 } 10641 } 10642 10643 static void 10644 dm_get_plane_scale(struct drm_plane_state *plane_state, 10645 int *out_plane_scale_w, int *out_plane_scale_h) 10646 { 10647 int plane_src_w, plane_src_h; 10648 10649 dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h); 10650 *out_plane_scale_w = plane_state->crtc_w * 1000 / plane_src_w; 10651 *out_plane_scale_h = plane_state->crtc_h * 1000 / plane_src_h; 10652 } 10653 10654 static int dm_check_crtc_cursor(struct drm_atomic_state *state, 10655 struct drm_crtc *crtc, 10656 struct drm_crtc_state *new_crtc_state) 10657 { 10658 struct drm_plane *cursor = crtc->cursor, *plane, *underlying; 10659 struct drm_plane_state *old_plane_state, *new_plane_state; 10660 struct drm_plane_state *new_cursor_state, *new_underlying_state; 10661 int i; 10662 int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h; 10663 bool any_relevant_change = false; 10664 10665 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a 10666 * cursor per pipe but it's going to inherit the scaling and 10667 * positioning from the underlying pipe. Check the cursor plane's 10668 * blending properties match the underlying planes'. 10669 */ 10670 10671 /* If no plane was enabled or changed scaling, no need to check again */ 10672 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 10673 int new_scale_w, new_scale_h, old_scale_w, old_scale_h; 10674 10675 if (!new_plane_state || !new_plane_state->fb || new_plane_state->crtc != crtc) 10676 continue; 10677 10678 if (!old_plane_state || !old_plane_state->fb || old_plane_state->crtc != crtc) { 10679 any_relevant_change = true; 10680 break; 10681 } 10682 10683 if (new_plane_state->fb == old_plane_state->fb && 10684 new_plane_state->crtc_w == old_plane_state->crtc_w && 10685 new_plane_state->crtc_h == old_plane_state->crtc_h) 10686 continue; 10687 10688 dm_get_plane_scale(new_plane_state, &new_scale_w, &new_scale_h); 10689 dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h); 10690 10691 if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) { 10692 any_relevant_change = true; 10693 break; 10694 } 10695 } 10696 10697 if (!any_relevant_change) 10698 return 0; 10699 10700 new_cursor_state = drm_atomic_get_plane_state(state, cursor); 10701 if (IS_ERR(new_cursor_state)) 10702 return PTR_ERR(new_cursor_state); 10703 10704 if (!new_cursor_state->fb) 10705 return 0; 10706 10707 dm_get_plane_scale(new_cursor_state, &cursor_scale_w, &cursor_scale_h); 10708 10709 /* Need to check all enabled planes, even if this commit doesn't change 10710 * their state 10711 */ 10712 i = drm_atomic_add_affected_planes(state, crtc); 10713 if (i) 10714 return i; 10715 10716 for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) { 10717 /* Narrow down to non-cursor planes on the same CRTC as the cursor */ 10718 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor) 10719 continue; 10720 10721 /* Ignore disabled planes */ 10722 if (!new_underlying_state->fb) 10723 continue; 10724 10725 dm_get_plane_scale(new_underlying_state, 10726 &underlying_scale_w, &underlying_scale_h); 10727 10728 if (cursor_scale_w != underlying_scale_w || 10729 cursor_scale_h != underlying_scale_h) { 10730 drm_dbg_atomic(crtc->dev, 10731 "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n", 10732 cursor->base.id, cursor->name, underlying->base.id, underlying->name); 10733 return -EINVAL; 10734 } 10735 10736 /* If this plane covers the whole CRTC, no need to check planes underneath */ 10737 if (new_underlying_state->crtc_x <= 0 && 10738 new_underlying_state->crtc_y <= 0 && 10739 new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay && 10740 new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay) 10741 break; 10742 } 10743 10744 return 0; 10745 } 10746 10747 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) 10748 { 10749 struct drm_connector *connector; 10750 struct drm_connector_state *conn_state, *old_conn_state; 10751 struct amdgpu_dm_connector *aconnector = NULL; 10752 int i; 10753 10754 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) { 10755 if (!conn_state->crtc) 10756 conn_state = old_conn_state; 10757 10758 if (conn_state->crtc != crtc) 10759 continue; 10760 10761 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 10762 continue; 10763 10764 aconnector = to_amdgpu_dm_connector(connector); 10765 if (!aconnector->mst_output_port || !aconnector->mst_root) 10766 aconnector = NULL; 10767 else 10768 break; 10769 } 10770 10771 if (!aconnector) 10772 return 0; 10773 10774 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr); 10775 } 10776 10777 /** 10778 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 10779 * 10780 * @dev: The DRM device 10781 * @state: The atomic state to commit 10782 * 10783 * Validate that the given atomic state is programmable by DC into hardware. 10784 * This involves constructing a &struct dc_state reflecting the new hardware 10785 * state we wish to commit, then querying DC to see if it is programmable. It's 10786 * important not to modify the existing DC state. Otherwise, atomic_check 10787 * may unexpectedly commit hardware changes. 10788 * 10789 * When validating the DC state, it's important that the right locks are 10790 * acquired. For full updates case which removes/adds/updates streams on one 10791 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 10792 * that any such full update commit will wait for completion of any outstanding 10793 * flip using DRMs synchronization events. 10794 * 10795 * Note that DM adds the affected connectors for all CRTCs in state, when that 10796 * might not seem necessary. This is because DC stream creation requires the 10797 * DC sink, which is tied to the DRM connector state. Cleaning this up should 10798 * be possible but non-trivial - a possible TODO item. 10799 * 10800 * Return: -Error code if validation failed. 10801 */ 10802 static int amdgpu_dm_atomic_check(struct drm_device *dev, 10803 struct drm_atomic_state *state) 10804 { 10805 struct amdgpu_device *adev = drm_to_adev(dev); 10806 struct dm_atomic_state *dm_state = NULL; 10807 struct dc *dc = adev->dm.dc; 10808 struct drm_connector *connector; 10809 struct drm_connector_state *old_con_state, *new_con_state; 10810 struct drm_crtc *crtc; 10811 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 10812 struct drm_plane *plane; 10813 struct drm_plane_state *old_plane_state, *new_plane_state; 10814 enum dc_status status; 10815 int ret, i; 10816 bool lock_and_validation_needed = false; 10817 bool is_top_most_overlay = true; 10818 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 10819 struct drm_dp_mst_topology_mgr *mgr; 10820 struct drm_dp_mst_topology_state *mst_state; 10821 struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; 10822 10823 trace_amdgpu_dm_atomic_check_begin(state); 10824 10825 ret = drm_atomic_helper_check_modeset(dev, state); 10826 if (ret) { 10827 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n"); 10828 goto fail; 10829 } 10830 10831 /* Check connector changes */ 10832 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 10833 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 10834 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 10835 10836 /* Skip connectors that are disabled or part of modeset already. */ 10837 if (!new_con_state->crtc) 10838 continue; 10839 10840 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc); 10841 if (IS_ERR(new_crtc_state)) { 10842 DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n"); 10843 ret = PTR_ERR(new_crtc_state); 10844 goto fail; 10845 } 10846 10847 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level || 10848 dm_old_con_state->scaling != dm_new_con_state->scaling) 10849 new_crtc_state->connectors_changed = true; 10850 } 10851 10852 if (dc_resource_is_dsc_encoding_supported(dc)) { 10853 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10854 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { 10855 ret = add_affected_mst_dsc_crtcs(state, crtc); 10856 if (ret) { 10857 DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n"); 10858 goto fail; 10859 } 10860 } 10861 } 10862 } 10863 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10864 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 10865 10866 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 10867 !new_crtc_state->color_mgmt_changed && 10868 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && 10869 dm_old_crtc_state->dsc_force_changed == false) 10870 continue; 10871 10872 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state); 10873 if (ret) { 10874 DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n"); 10875 goto fail; 10876 } 10877 10878 if (!new_crtc_state->enable) 10879 continue; 10880 10881 ret = drm_atomic_add_affected_connectors(state, crtc); 10882 if (ret) { 10883 DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n"); 10884 goto fail; 10885 } 10886 10887 ret = drm_atomic_add_affected_planes(state, crtc); 10888 if (ret) { 10889 DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n"); 10890 goto fail; 10891 } 10892 10893 if (dm_old_crtc_state->dsc_force_changed) 10894 new_crtc_state->mode_changed = true; 10895 } 10896 10897 /* 10898 * Add all primary and overlay planes on the CRTC to the state 10899 * whenever a plane is enabled to maintain correct z-ordering 10900 * and to enable fast surface updates. 10901 */ 10902 drm_for_each_crtc(crtc, dev) { 10903 bool modified = false; 10904 10905 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 10906 if (plane->type == DRM_PLANE_TYPE_CURSOR) 10907 continue; 10908 10909 if (new_plane_state->crtc == crtc || 10910 old_plane_state->crtc == crtc) { 10911 modified = true; 10912 break; 10913 } 10914 } 10915 10916 if (!modified) 10917 continue; 10918 10919 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 10920 if (plane->type == DRM_PLANE_TYPE_CURSOR) 10921 continue; 10922 10923 new_plane_state = 10924 drm_atomic_get_plane_state(state, plane); 10925 10926 if (IS_ERR(new_plane_state)) { 10927 ret = PTR_ERR(new_plane_state); 10928 DRM_DEBUG_DRIVER("new_plane_state is BAD\n"); 10929 goto fail; 10930 } 10931 } 10932 } 10933 10934 /* 10935 * DC consults the zpos (layer_index in DC terminology) to determine the 10936 * hw plane on which to enable the hw cursor (see 10937 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in 10938 * atomic state, so call drm helper to normalize zpos. 10939 */ 10940 ret = drm_atomic_normalize_zpos(dev, state); 10941 if (ret) { 10942 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n"); 10943 goto fail; 10944 } 10945 10946 /* Remove exiting planes if they are modified */ 10947 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 10948 if (old_plane_state->fb && new_plane_state->fb && 10949 get_mem_type(old_plane_state->fb) != 10950 get_mem_type(new_plane_state->fb)) 10951 lock_and_validation_needed = true; 10952 10953 ret = dm_update_plane_state(dc, state, plane, 10954 old_plane_state, 10955 new_plane_state, 10956 false, 10957 &lock_and_validation_needed, 10958 &is_top_most_overlay); 10959 if (ret) { 10960 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n"); 10961 goto fail; 10962 } 10963 } 10964 10965 /* Disable all crtcs which require disable */ 10966 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10967 ret = dm_update_crtc_state(&adev->dm, state, crtc, 10968 old_crtc_state, 10969 new_crtc_state, 10970 false, 10971 &lock_and_validation_needed); 10972 if (ret) { 10973 DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n"); 10974 goto fail; 10975 } 10976 } 10977 10978 /* Enable all crtcs which require enable */ 10979 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10980 ret = dm_update_crtc_state(&adev->dm, state, crtc, 10981 old_crtc_state, 10982 new_crtc_state, 10983 true, 10984 &lock_and_validation_needed); 10985 if (ret) { 10986 DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n"); 10987 goto fail; 10988 } 10989 } 10990 10991 /* Add new/modified planes */ 10992 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 10993 ret = dm_update_plane_state(dc, state, plane, 10994 old_plane_state, 10995 new_plane_state, 10996 true, 10997 &lock_and_validation_needed, 10998 &is_top_most_overlay); 10999 if (ret) { 11000 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n"); 11001 goto fail; 11002 } 11003 } 11004 11005 #if defined(CONFIG_DRM_AMD_DC_FP) 11006 if (dc_resource_is_dsc_encoding_supported(dc)) { 11007 ret = pre_validate_dsc(state, &dm_state, vars); 11008 if (ret != 0) 11009 goto fail; 11010 } 11011 #endif 11012 11013 /* Run this here since we want to validate the streams we created */ 11014 ret = drm_atomic_helper_check_planes(dev, state); 11015 if (ret) { 11016 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n"); 11017 goto fail; 11018 } 11019 11020 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 11021 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 11022 if (dm_new_crtc_state->mpo_requested) 11023 DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc); 11024 } 11025 11026 /* Check cursor planes scaling */ 11027 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 11028 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state); 11029 if (ret) { 11030 DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n"); 11031 goto fail; 11032 } 11033 } 11034 11035 if (state->legacy_cursor_update) { 11036 /* 11037 * This is a fast cursor update coming from the plane update 11038 * helper, check if it can be done asynchronously for better 11039 * performance. 11040 */ 11041 state->async_update = 11042 !drm_atomic_helper_async_check(dev, state); 11043 11044 /* 11045 * Skip the remaining global validation if this is an async 11046 * update. Cursor updates can be done without affecting 11047 * state or bandwidth calcs and this avoids the performance 11048 * penalty of locking the private state object and 11049 * allocating a new dc_state. 11050 */ 11051 if (state->async_update) 11052 return 0; 11053 } 11054 11055 /* Check scaling and underscan changes*/ 11056 /* TODO Removed scaling changes validation due to inability to commit 11057 * new stream into context w\o causing full reset. Need to 11058 * decide how to handle. 11059 */ 11060 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 11061 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 11062 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 11063 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 11064 11065 /* Skip any modesets/resets */ 11066 if (!acrtc || drm_atomic_crtc_needs_modeset( 11067 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 11068 continue; 11069 11070 /* Skip any thing not scale or underscan changes */ 11071 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 11072 continue; 11073 11074 lock_and_validation_needed = true; 11075 } 11076 11077 /* set the slot info for each mst_state based on the link encoding format */ 11078 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { 11079 struct amdgpu_dm_connector *aconnector; 11080 struct drm_connector *connector; 11081 struct drm_connector_list_iter iter; 11082 u8 link_coding_cap; 11083 11084 drm_connector_list_iter_begin(dev, &iter); 11085 drm_for_each_connector_iter(connector, &iter) { 11086 if (connector->index == mst_state->mgr->conn_base_id) { 11087 aconnector = to_amdgpu_dm_connector(connector); 11088 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); 11089 drm_dp_mst_update_slots(mst_state, link_coding_cap); 11090 11091 break; 11092 } 11093 } 11094 drm_connector_list_iter_end(&iter); 11095 } 11096 11097 /** 11098 * Streams and planes are reset when there are changes that affect 11099 * bandwidth. Anything that affects bandwidth needs to go through 11100 * DC global validation to ensure that the configuration can be applied 11101 * to hardware. 11102 * 11103 * We have to currently stall out here in atomic_check for outstanding 11104 * commits to finish in this case because our IRQ handlers reference 11105 * DRM state directly - we can end up disabling interrupts too early 11106 * if we don't. 11107 * 11108 * TODO: Remove this stall and drop DM state private objects. 11109 */ 11110 if (lock_and_validation_needed) { 11111 ret = dm_atomic_get_state(state, &dm_state); 11112 if (ret) { 11113 DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n"); 11114 goto fail; 11115 } 11116 11117 ret = do_aquire_global_lock(dev, state); 11118 if (ret) { 11119 DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n"); 11120 goto fail; 11121 } 11122 11123 #if defined(CONFIG_DRM_AMD_DC_FP) 11124 if (dc_resource_is_dsc_encoding_supported(dc)) { 11125 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); 11126 if (ret) { 11127 DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n"); 11128 ret = -EINVAL; 11129 goto fail; 11130 } 11131 } 11132 #endif 11133 11134 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); 11135 if (ret) { 11136 DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n"); 11137 goto fail; 11138 } 11139 11140 /* 11141 * Perform validation of MST topology in the state: 11142 * We need to perform MST atomic check before calling 11143 * dc_validate_global_state(), or there is a chance 11144 * to get stuck in an infinite loop and hang eventually. 11145 */ 11146 ret = drm_dp_mst_atomic_check(state); 11147 if (ret) { 11148 DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n"); 11149 goto fail; 11150 } 11151 status = dc_validate_global_state(dc, dm_state->context, true); 11152 if (status != DC_OK) { 11153 DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)", 11154 dc_status_to_str(status), status); 11155 ret = -EINVAL; 11156 goto fail; 11157 } 11158 } else { 11159 /* 11160 * The commit is a fast update. Fast updates shouldn't change 11161 * the DC context, affect global validation, and can have their 11162 * commit work done in parallel with other commits not touching 11163 * the same resource. If we have a new DC context as part of 11164 * the DM atomic state from validation we need to free it and 11165 * retain the existing one instead. 11166 * 11167 * Furthermore, since the DM atomic state only contains the DC 11168 * context and can safely be annulled, we can free the state 11169 * and clear the associated private object now to free 11170 * some memory and avoid a possible use-after-free later. 11171 */ 11172 11173 for (i = 0; i < state->num_private_objs; i++) { 11174 struct drm_private_obj *obj = state->private_objs[i].ptr; 11175 11176 if (obj->funcs == adev->dm.atomic_obj.funcs) { 11177 int j = state->num_private_objs-1; 11178 11179 dm_atomic_destroy_state(obj, 11180 state->private_objs[i].state); 11181 11182 /* If i is not at the end of the array then the 11183 * last element needs to be moved to where i was 11184 * before the array can safely be truncated. 11185 */ 11186 if (i != j) 11187 state->private_objs[i] = 11188 state->private_objs[j]; 11189 11190 state->private_objs[j].ptr = NULL; 11191 state->private_objs[j].state = NULL; 11192 state->private_objs[j].old_state = NULL; 11193 state->private_objs[j].new_state = NULL; 11194 11195 state->num_private_objs = j; 11196 break; 11197 } 11198 } 11199 } 11200 11201 /* Store the overall update type for use later in atomic check. */ 11202 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 11203 struct dm_crtc_state *dm_new_crtc_state = 11204 to_dm_crtc_state(new_crtc_state); 11205 11206 /* 11207 * Only allow async flips for fast updates that don't change 11208 * the FB pitch, the DCC state, rotation, etc. 11209 */ 11210 if (new_crtc_state->async_flip && lock_and_validation_needed) { 11211 drm_dbg_atomic(crtc->dev, 11212 "[CRTC:%d:%s] async flips are only supported for fast updates\n", 11213 crtc->base.id, crtc->name); 11214 ret = -EINVAL; 11215 goto fail; 11216 } 11217 11218 dm_new_crtc_state->update_type = lock_and_validation_needed ? 11219 UPDATE_TYPE_FULL : UPDATE_TYPE_FAST; 11220 } 11221 11222 /* Must be success */ 11223 WARN_ON(ret); 11224 11225 trace_amdgpu_dm_atomic_check_finish(state, ret); 11226 11227 return ret; 11228 11229 fail: 11230 if (ret == -EDEADLK) 11231 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); 11232 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 11233 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); 11234 else 11235 DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret); 11236 11237 trace_amdgpu_dm_atomic_check_finish(state, ret); 11238 11239 return ret; 11240 } 11241 11242 static bool is_dp_capable_without_timing_msa(struct dc *dc, 11243 struct amdgpu_dm_connector *amdgpu_dm_connector) 11244 { 11245 u8 dpcd_data; 11246 bool capable = false; 11247 11248 if (amdgpu_dm_connector->dc_link && 11249 dm_helpers_dp_read_dpcd( 11250 NULL, 11251 amdgpu_dm_connector->dc_link, 11252 DP_DOWN_STREAM_PORT_COUNT, 11253 &dpcd_data, 11254 sizeof(dpcd_data))) { 11255 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; 11256 } 11257 11258 return capable; 11259 } 11260 11261 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm, 11262 unsigned int offset, 11263 unsigned int total_length, 11264 u8 *data, 11265 unsigned int length, 11266 struct amdgpu_hdmi_vsdb_info *vsdb) 11267 { 11268 bool res; 11269 union dmub_rb_cmd cmd; 11270 struct dmub_cmd_send_edid_cea *input; 11271 struct dmub_cmd_edid_cea_output *output; 11272 11273 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES) 11274 return false; 11275 11276 memset(&cmd, 0, sizeof(cmd)); 11277 11278 input = &cmd.edid_cea.data.input; 11279 11280 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA; 11281 cmd.edid_cea.header.sub_type = 0; 11282 cmd.edid_cea.header.payload_bytes = 11283 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header); 11284 input->offset = offset; 11285 input->length = length; 11286 input->cea_total_length = total_length; 11287 memcpy(input->payload, data, length); 11288 11289 res = dc_wake_and_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY); 11290 if (!res) { 11291 DRM_ERROR("EDID CEA parser failed\n"); 11292 return false; 11293 } 11294 11295 output = &cmd.edid_cea.data.output; 11296 11297 if (output->type == DMUB_CMD__EDID_CEA_ACK) { 11298 if (!output->ack.success) { 11299 DRM_ERROR("EDID CEA ack failed at offset %d\n", 11300 output->ack.offset); 11301 } 11302 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) { 11303 if (!output->amd_vsdb.vsdb_found) 11304 return false; 11305 11306 vsdb->freesync_supported = output->amd_vsdb.freesync_supported; 11307 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version; 11308 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate; 11309 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate; 11310 } else { 11311 DRM_WARN("Unknown EDID CEA parser results\n"); 11312 return false; 11313 } 11314 11315 return true; 11316 } 11317 11318 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm, 11319 u8 *edid_ext, int len, 11320 struct amdgpu_hdmi_vsdb_info *vsdb_info) 11321 { 11322 int i; 11323 11324 /* send extension block to DMCU for parsing */ 11325 for (i = 0; i < len; i += 8) { 11326 bool res; 11327 int offset; 11328 11329 /* send 8 bytes a time */ 11330 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8)) 11331 return false; 11332 11333 if (i+8 == len) { 11334 /* EDID block sent completed, expect result */ 11335 int version, min_rate, max_rate; 11336 11337 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate); 11338 if (res) { 11339 /* amd vsdb found */ 11340 vsdb_info->freesync_supported = 1; 11341 vsdb_info->amd_vsdb_version = version; 11342 vsdb_info->min_refresh_rate_hz = min_rate; 11343 vsdb_info->max_refresh_rate_hz = max_rate; 11344 return true; 11345 } 11346 /* not amd vsdb */ 11347 return false; 11348 } 11349 11350 /* check for ack*/ 11351 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset); 11352 if (!res) 11353 return false; 11354 } 11355 11356 return false; 11357 } 11358 11359 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm, 11360 u8 *edid_ext, int len, 11361 struct amdgpu_hdmi_vsdb_info *vsdb_info) 11362 { 11363 int i; 11364 11365 /* send extension block to DMCU for parsing */ 11366 for (i = 0; i < len; i += 8) { 11367 /* send 8 bytes a time */ 11368 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info)) 11369 return false; 11370 } 11371 11372 return vsdb_info->freesync_supported; 11373 } 11374 11375 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, 11376 u8 *edid_ext, int len, 11377 struct amdgpu_hdmi_vsdb_info *vsdb_info) 11378 { 11379 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); 11380 bool ret; 11381 11382 mutex_lock(&adev->dm.dc_lock); 11383 if (adev->dm.dmub_srv) 11384 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info); 11385 else 11386 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info); 11387 mutex_unlock(&adev->dm.dc_lock); 11388 return ret; 11389 } 11390 11391 static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector, 11392 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) 11393 { 11394 u8 *edid_ext = NULL; 11395 int i; 11396 int j = 0; 11397 11398 if (edid == NULL || edid->extensions == 0) 11399 return -ENODEV; 11400 11401 /* Find DisplayID extension */ 11402 for (i = 0; i < edid->extensions; i++) { 11403 edid_ext = (void *)(edid + (i + 1)); 11404 if (edid_ext[0] == DISPLAYID_EXT) 11405 break; 11406 } 11407 11408 while (j < EDID_LENGTH) { 11409 struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j]; 11410 unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]); 11411 11412 if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID && 11413 amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) { 11414 vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false; 11415 vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3; 11416 DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode); 11417 11418 return true; 11419 } 11420 j++; 11421 } 11422 11423 return false; 11424 } 11425 11426 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, 11427 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) 11428 { 11429 u8 *edid_ext = NULL; 11430 int i; 11431 bool valid_vsdb_found = false; 11432 11433 /*----- drm_find_cea_extension() -----*/ 11434 /* No EDID or EDID extensions */ 11435 if (edid == NULL || edid->extensions == 0) 11436 return -ENODEV; 11437 11438 /* Find CEA extension */ 11439 for (i = 0; i < edid->extensions; i++) { 11440 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1); 11441 if (edid_ext[0] == CEA_EXT) 11442 break; 11443 } 11444 11445 if (i == edid->extensions) 11446 return -ENODEV; 11447 11448 /*----- cea_db_offsets() -----*/ 11449 if (edid_ext[0] != CEA_EXT) 11450 return -ENODEV; 11451 11452 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info); 11453 11454 return valid_vsdb_found ? i : -ENODEV; 11455 } 11456 11457 /** 11458 * amdgpu_dm_update_freesync_caps - Update Freesync capabilities 11459 * 11460 * @connector: Connector to query. 11461 * @edid: EDID from monitor 11462 * 11463 * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep 11464 * track of some of the display information in the internal data struct used by 11465 * amdgpu_dm. This function checks which type of connector we need to set the 11466 * FreeSync parameters. 11467 */ 11468 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 11469 struct edid *edid) 11470 { 11471 int i = 0; 11472 struct detailed_timing *timing; 11473 struct detailed_non_pixel *data; 11474 struct detailed_data_monitor_range *range; 11475 struct amdgpu_dm_connector *amdgpu_dm_connector = 11476 to_amdgpu_dm_connector(connector); 11477 struct dm_connector_state *dm_con_state = NULL; 11478 struct dc_sink *sink; 11479 11480 struct amdgpu_device *adev = drm_to_adev(connector->dev); 11481 struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; 11482 bool freesync_capable = false; 11483 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; 11484 11485 if (!connector->state) { 11486 DRM_ERROR("%s - Connector has no state", __func__); 11487 goto update; 11488 } 11489 11490 sink = amdgpu_dm_connector->dc_sink ? 11491 amdgpu_dm_connector->dc_sink : 11492 amdgpu_dm_connector->dc_em_sink; 11493 11494 if (!edid || !sink) { 11495 dm_con_state = to_dm_connector_state(connector->state); 11496 11497 amdgpu_dm_connector->min_vfreq = 0; 11498 amdgpu_dm_connector->max_vfreq = 0; 11499 amdgpu_dm_connector->pixel_clock_mhz = 0; 11500 connector->display_info.monitor_range.min_vfreq = 0; 11501 connector->display_info.monitor_range.max_vfreq = 0; 11502 freesync_capable = false; 11503 11504 goto update; 11505 } 11506 11507 dm_con_state = to_dm_connector_state(connector->state); 11508 11509 if (!adev->dm.freesync_module) 11510 goto update; 11511 11512 if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || 11513 sink->sink_signal == SIGNAL_TYPE_EDP)) { 11514 bool edid_check_required = false; 11515 11516 if (is_dp_capable_without_timing_msa(adev->dm.dc, 11517 amdgpu_dm_connector)) { 11518 if (edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) { 11519 freesync_capable = true; 11520 amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq; 11521 amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq; 11522 } else { 11523 edid_check_required = edid->version > 1 || 11524 (edid->version == 1 && 11525 edid->revision > 1); 11526 } 11527 } 11528 11529 if (edid_check_required) { 11530 for (i = 0; i < 4; i++) { 11531 11532 timing = &edid->detailed_timings[i]; 11533 data = &timing->data.other_data; 11534 range = &data->data.range; 11535 /* 11536 * Check if monitor has continuous frequency mode 11537 */ 11538 if (data->type != EDID_DETAIL_MONITOR_RANGE) 11539 continue; 11540 /* 11541 * Check for flag range limits only. If flag == 1 then 11542 * no additional timing information provided. 11543 * Default GTF, GTF Secondary curve and CVT are not 11544 * supported 11545 */ 11546 if (range->flags != 1) 11547 continue; 11548 11549 connector->display_info.monitor_range.min_vfreq = range->min_vfreq; 11550 connector->display_info.monitor_range.max_vfreq = range->max_vfreq; 11551 11552 if (edid->revision >= 4) { 11553 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ) 11554 connector->display_info.monitor_range.min_vfreq += 255; 11555 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ) 11556 connector->display_info.monitor_range.max_vfreq += 255; 11557 } 11558 11559 amdgpu_dm_connector->min_vfreq = 11560 connector->display_info.monitor_range.min_vfreq; 11561 amdgpu_dm_connector->max_vfreq = 11562 connector->display_info.monitor_range.max_vfreq; 11563 amdgpu_dm_connector->pixel_clock_mhz = 11564 range->pixel_clock_mhz * 10; 11565 11566 break; 11567 } 11568 11569 if (amdgpu_dm_connector->max_vfreq - 11570 amdgpu_dm_connector->min_vfreq > 10) { 11571 11572 freesync_capable = true; 11573 } 11574 } 11575 parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 11576 11577 if (vsdb_info.replay_mode) { 11578 amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode; 11579 amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version; 11580 amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP; 11581 } 11582 11583 } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { 11584 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 11585 if (i >= 0 && vsdb_info.freesync_supported) { 11586 timing = &edid->detailed_timings[i]; 11587 data = &timing->data.other_data; 11588 11589 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; 11590 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; 11591 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 11592 freesync_capable = true; 11593 11594 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; 11595 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; 11596 } 11597 } 11598 11599 as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link); 11600 11601 if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) { 11602 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 11603 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) { 11604 11605 amdgpu_dm_connector->pack_sdp_v1_3 = true; 11606 amdgpu_dm_connector->as_type = as_type; 11607 amdgpu_dm_connector->vsdb_info = vsdb_info; 11608 11609 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; 11610 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; 11611 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 11612 freesync_capable = true; 11613 11614 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; 11615 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; 11616 } 11617 } 11618 11619 update: 11620 if (dm_con_state) 11621 dm_con_state->freesync_capable = freesync_capable; 11622 11623 if (connector->vrr_capable_property) 11624 drm_connector_set_vrr_capable_property(connector, 11625 freesync_capable); 11626 } 11627 11628 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) 11629 { 11630 struct amdgpu_device *adev = drm_to_adev(dev); 11631 struct dc *dc = adev->dm.dc; 11632 int i; 11633 11634 mutex_lock(&adev->dm.dc_lock); 11635 if (dc->current_state) { 11636 for (i = 0; i < dc->current_state->stream_count; ++i) 11637 dc->current_state->streams[i] 11638 ->triggered_crtc_reset.enabled = 11639 adev->dm.force_timing_sync; 11640 11641 dm_enable_per_frame_crtc_master_sync(dc->current_state); 11642 dc_trigger_sync(dc, dc->current_state); 11643 } 11644 mutex_unlock(&adev->dm.dc_lock); 11645 } 11646 11647 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, 11648 u32 value, const char *func_name) 11649 { 11650 #ifdef DM_CHECK_ADDR_0 11651 if (address == 0) { 11652 drm_err(adev_to_drm(ctx->driver_context), 11653 "invalid register write. address = 0"); 11654 return; 11655 } 11656 #endif 11657 cgs_write_register(ctx->cgs_device, address, value); 11658 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value); 11659 } 11660 11661 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, 11662 const char *func_name) 11663 { 11664 u32 value; 11665 #ifdef DM_CHECK_ADDR_0 11666 if (address == 0) { 11667 drm_err(adev_to_drm(ctx->driver_context), 11668 "invalid register read; address = 0\n"); 11669 return 0; 11670 } 11671 #endif 11672 11673 if (ctx->dmub_srv && 11674 ctx->dmub_srv->reg_helper_offload.gather_in_progress && 11675 !ctx->dmub_srv->reg_helper_offload.should_burst_write) { 11676 ASSERT(false); 11677 return 0; 11678 } 11679 11680 value = cgs_read_register(ctx->cgs_device, address); 11681 11682 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); 11683 11684 return value; 11685 } 11686 11687 int amdgpu_dm_process_dmub_aux_transfer_sync( 11688 struct dc_context *ctx, 11689 unsigned int link_index, 11690 struct aux_payload *payload, 11691 enum aux_return_code_type *operation_result) 11692 { 11693 struct amdgpu_device *adev = ctx->driver_context; 11694 struct dmub_notification *p_notify = adev->dm.dmub_notify; 11695 int ret = -1; 11696 11697 mutex_lock(&adev->dm.dpia_aux_lock); 11698 if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) { 11699 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE; 11700 goto out; 11701 } 11702 11703 if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { 11704 DRM_ERROR("wait_for_completion_timeout timeout!"); 11705 *operation_result = AUX_RET_ERROR_TIMEOUT; 11706 goto out; 11707 } 11708 11709 if (p_notify->result != AUX_RET_SUCCESS) { 11710 /* 11711 * Transient states before tunneling is enabled could 11712 * lead to this error. We can ignore this for now. 11713 */ 11714 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) { 11715 DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n", 11716 payload->address, payload->length, 11717 p_notify->result); 11718 } 11719 *operation_result = AUX_RET_ERROR_INVALID_REPLY; 11720 goto out; 11721 } 11722 11723 11724 payload->reply[0] = adev->dm.dmub_notify->aux_reply.command; 11725 if (!payload->write && p_notify->aux_reply.length && 11726 (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) { 11727 11728 if (payload->length != p_notify->aux_reply.length) { 11729 DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n", 11730 p_notify->aux_reply.length, 11731 payload->address, payload->length); 11732 *operation_result = AUX_RET_ERROR_INVALID_REPLY; 11733 goto out; 11734 } 11735 11736 memcpy(payload->data, p_notify->aux_reply.data, 11737 p_notify->aux_reply.length); 11738 } 11739 11740 /* success */ 11741 ret = p_notify->aux_reply.length; 11742 *operation_result = p_notify->result; 11743 out: 11744 reinit_completion(&adev->dm.dmub_aux_transfer_done); 11745 mutex_unlock(&adev->dm.dpia_aux_lock); 11746 return ret; 11747 } 11748 11749 int amdgpu_dm_process_dmub_set_config_sync( 11750 struct dc_context *ctx, 11751 unsigned int link_index, 11752 struct set_config_cmd_payload *payload, 11753 enum set_config_status *operation_result) 11754 { 11755 struct amdgpu_device *adev = ctx->driver_context; 11756 bool is_cmd_complete; 11757 int ret; 11758 11759 mutex_lock(&adev->dm.dpia_aux_lock); 11760 is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc, 11761 link_index, payload, adev->dm.dmub_notify); 11762 11763 if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { 11764 ret = 0; 11765 *operation_result = adev->dm.dmub_notify->sc_status; 11766 } else { 11767 DRM_ERROR("wait_for_completion_timeout timeout!"); 11768 ret = -1; 11769 *operation_result = SET_CONFIG_UNKNOWN_ERROR; 11770 } 11771 11772 if (!is_cmd_complete) 11773 reinit_completion(&adev->dm.dmub_aux_transfer_done); 11774 mutex_unlock(&adev->dm.dpia_aux_lock); 11775 return ret; 11776 } 11777 11778 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) 11779 { 11780 return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type); 11781 } 11782 11783 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) 11784 { 11785 return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type); 11786 } 11787