1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* The caprices of the preprocessor require that this be declared right here */ 27 #define CREATE_TRACE_POINTS 28 29 #include "dm_services_types.h" 30 #include "dc.h" 31 #include "link_enc_cfg.h" 32 #include "dc/inc/core_types.h" 33 #include "dal_asic_id.h" 34 #include "dmub/dmub_srv.h" 35 #include "dc/inc/hw/dmcu.h" 36 #include "dc/inc/hw/abm.h" 37 #include "dc/dc_dmub_srv.h" 38 #include "dc/dc_edid_parser.h" 39 #include "dc/dc_stat.h" 40 #include "dc/dc_state.h" 41 #include "amdgpu_dm_trace.h" 42 #include "dpcd_defs.h" 43 #include "link/protocols/link_dpcd.h" 44 #include "link_service_types.h" 45 #include "link/protocols/link_dp_capability.h" 46 #include "link/protocols/link_ddc.h" 47 48 #include "vid.h" 49 #include "amdgpu.h" 50 #include "amdgpu_display.h" 51 #include "amdgpu_ucode.h" 52 #include "atom.h" 53 #include "amdgpu_dm.h" 54 #include "amdgpu_dm_plane.h" 55 #include "amdgpu_dm_crtc.h" 56 #include "amdgpu_dm_hdcp.h" 57 #include <drm/display/drm_hdcp_helper.h> 58 #include "amdgpu_dm_wb.h" 59 #include "amdgpu_pm.h" 60 #include "amdgpu_atombios.h" 61 62 #include "amd_shared.h" 63 #include "amdgpu_dm_irq.h" 64 #include "dm_helpers.h" 65 #include "amdgpu_dm_mst_types.h" 66 #if defined(CONFIG_DEBUG_FS) 67 #include "amdgpu_dm_debugfs.h" 68 #endif 69 #include "amdgpu_dm_psr.h" 70 #include "amdgpu_dm_replay.h" 71 72 #include "ivsrcid/ivsrcid_vislands30.h" 73 74 #include <linux/backlight.h> 75 #include <linux/module.h> 76 #include <linux/moduleparam.h> 77 #include <linux/types.h> 78 #include <linux/pm_runtime.h> 79 #include <linux/pci.h> 80 #include <linux/power_supply.h> 81 #include <linux/firmware.h> 82 #include <linux/component.h> 83 #include <linux/dmi.h> 84 #include <linux/sort.h> 85 86 #include <drm/display/drm_dp_mst_helper.h> 87 #include <drm/display/drm_hdmi_helper.h> 88 #include <drm/drm_atomic.h> 89 #include <drm/drm_atomic_uapi.h> 90 #include <drm/drm_atomic_helper.h> 91 #include <drm/drm_blend.h> 92 #include <drm/drm_fixed.h> 93 #include <drm/drm_fourcc.h> 94 #include <drm/drm_edid.h> 95 #include <drm/drm_eld.h> 96 #include <drm/drm_vblank.h> 97 #include <drm/drm_audio_component.h> 98 #include <drm/drm_gem_atomic_helper.h> 99 100 #include <acpi/video.h> 101 102 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 103 104 #include "dcn/dcn_1_0_offset.h" 105 #include "dcn/dcn_1_0_sh_mask.h" 106 #include "soc15_hw_ip.h" 107 #include "soc15_common.h" 108 #include "vega10_ip_offset.h" 109 110 #include "gc/gc_11_0_0_offset.h" 111 #include "gc/gc_11_0_0_sh_mask.h" 112 113 #include "modules/inc/mod_freesync.h" 114 #include "modules/power/power_helpers.h" 115 116 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin" 117 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB); 118 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin" 119 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB); 120 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin" 121 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB); 122 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin" 123 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB); 124 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin" 125 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB); 126 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin" 127 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB); 128 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin" 129 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB); 130 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin" 131 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB); 132 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin" 133 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB); 134 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin" 135 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB); 136 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin" 137 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB); 138 139 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin" 140 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB); 141 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin" 142 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB); 143 144 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" 145 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 146 147 #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin" 148 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); 149 150 #define FIRMWARE_DCN_35_DMUB "amdgpu/dcn_3_5_dmcub.bin" 151 MODULE_FIRMWARE(FIRMWARE_DCN_35_DMUB); 152 153 #define FIRMWARE_DCN_351_DMUB "amdgpu/dcn_3_5_1_dmcub.bin" 154 MODULE_FIRMWARE(FIRMWARE_DCN_351_DMUB); 155 156 #define FIRMWARE_DCN_401_DMUB "amdgpu/dcn_4_0_1_dmcub.bin" 157 MODULE_FIRMWARE(FIRMWARE_DCN_401_DMUB); 158 159 /* Number of bytes in PSP header for firmware. */ 160 #define PSP_HEADER_BYTES 0x100 161 162 /* Number of bytes in PSP footer for firmware. */ 163 #define PSP_FOOTER_BYTES 0x100 164 165 /** 166 * DOC: overview 167 * 168 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 169 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM 170 * requests into DC requests, and DC responses into DRM responses. 171 * 172 * The root control structure is &struct amdgpu_display_manager. 173 */ 174 175 /* basic init/fini API */ 176 static int amdgpu_dm_init(struct amdgpu_device *adev); 177 static void amdgpu_dm_fini(struct amdgpu_device *adev); 178 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector); 179 180 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link) 181 { 182 switch (link->dpcd_caps.dongle_type) { 183 case DISPLAY_DONGLE_NONE: 184 return DRM_MODE_SUBCONNECTOR_Native; 185 case DISPLAY_DONGLE_DP_VGA_CONVERTER: 186 return DRM_MODE_SUBCONNECTOR_VGA; 187 case DISPLAY_DONGLE_DP_DVI_CONVERTER: 188 case DISPLAY_DONGLE_DP_DVI_DONGLE: 189 return DRM_MODE_SUBCONNECTOR_DVID; 190 case DISPLAY_DONGLE_DP_HDMI_CONVERTER: 191 case DISPLAY_DONGLE_DP_HDMI_DONGLE: 192 return DRM_MODE_SUBCONNECTOR_HDMIA; 193 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: 194 default: 195 return DRM_MODE_SUBCONNECTOR_Unknown; 196 } 197 } 198 199 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector) 200 { 201 struct dc_link *link = aconnector->dc_link; 202 struct drm_connector *connector = &aconnector->base; 203 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 204 205 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 206 return; 207 208 if (aconnector->dc_sink) 209 subconnector = get_subconnector_type(link); 210 211 drm_object_property_set_value(&connector->base, 212 connector->dev->mode_config.dp_subconnector_property, 213 subconnector); 214 } 215 216 /* 217 * initializes drm_device display related structures, based on the information 218 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 219 * drm_encoder, drm_mode_config 220 * 221 * Returns 0 on success 222 */ 223 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 224 /* removes and deallocates the drm structures, created by the above function */ 225 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 226 227 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 228 struct amdgpu_dm_connector *amdgpu_dm_connector, 229 u32 link_index, 230 struct amdgpu_encoder *amdgpu_encoder); 231 static int amdgpu_dm_encoder_init(struct drm_device *dev, 232 struct amdgpu_encoder *aencoder, 233 uint32_t link_index); 234 235 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); 236 237 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); 238 239 static int amdgpu_dm_atomic_check(struct drm_device *dev, 240 struct drm_atomic_state *state); 241 242 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector); 243 static void handle_hpd_rx_irq(void *param); 244 245 static bool 246 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 247 struct drm_crtc_state *new_crtc_state); 248 /* 249 * dm_vblank_get_counter 250 * 251 * @brief 252 * Get counter for number of vertical blanks 253 * 254 * @param 255 * struct amdgpu_device *adev - [in] desired amdgpu device 256 * int disp_idx - [in] which CRTC to get the counter from 257 * 258 * @return 259 * Counter for vertical blanks 260 */ 261 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 262 { 263 struct amdgpu_crtc *acrtc = NULL; 264 265 if (crtc >= adev->mode_info.num_crtc) 266 return 0; 267 268 acrtc = adev->mode_info.crtcs[crtc]; 269 270 if (!acrtc->dm_irq_params.stream) { 271 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 272 crtc); 273 return 0; 274 } 275 276 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); 277 } 278 279 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 280 u32 *vbl, u32 *position) 281 { 282 u32 v_blank_start = 0, v_blank_end = 0, h_position = 0, v_position = 0; 283 struct amdgpu_crtc *acrtc = NULL; 284 struct dc *dc = adev->dm.dc; 285 286 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 287 return -EINVAL; 288 289 acrtc = adev->mode_info.crtcs[crtc]; 290 291 if (!acrtc->dm_irq_params.stream) { 292 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 293 crtc); 294 return 0; 295 } 296 297 if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed) 298 dc_allow_idle_optimizations(dc, false); 299 300 /* 301 * TODO rework base driver to use values directly. 302 * for now parse it back into reg-format 303 */ 304 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, 305 &v_blank_start, 306 &v_blank_end, 307 &h_position, 308 &v_position); 309 310 *position = v_position | (h_position << 16); 311 *vbl = v_blank_start | (v_blank_end << 16); 312 313 return 0; 314 } 315 316 static bool dm_is_idle(void *handle) 317 { 318 /* XXX todo */ 319 return true; 320 } 321 322 static int dm_wait_for_idle(void *handle) 323 { 324 /* XXX todo */ 325 return 0; 326 } 327 328 static bool dm_check_soft_reset(void *handle) 329 { 330 return false; 331 } 332 333 static int dm_soft_reset(void *handle) 334 { 335 /* XXX todo */ 336 return 0; 337 } 338 339 static struct amdgpu_crtc * 340 get_crtc_by_otg_inst(struct amdgpu_device *adev, 341 int otg_inst) 342 { 343 struct drm_device *dev = adev_to_drm(adev); 344 struct drm_crtc *crtc; 345 struct amdgpu_crtc *amdgpu_crtc; 346 347 if (WARN_ON(otg_inst == -1)) 348 return adev->mode_info.crtcs[0]; 349 350 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 351 amdgpu_crtc = to_amdgpu_crtc(crtc); 352 353 if (amdgpu_crtc->otg_inst == otg_inst) 354 return amdgpu_crtc; 355 } 356 357 return NULL; 358 } 359 360 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, 361 struct dm_crtc_state *new_state) 362 { 363 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) 364 return true; 365 else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state)) 366 return true; 367 else 368 return false; 369 } 370 371 /* 372 * DC will program planes with their z-order determined by their ordering 373 * in the dc_surface_updates array. This comparator is used to sort them 374 * by descending zpos. 375 */ 376 static int dm_plane_layer_index_cmp(const void *a, const void *b) 377 { 378 const struct dc_surface_update *sa = (struct dc_surface_update *)a; 379 const struct dc_surface_update *sb = (struct dc_surface_update *)b; 380 381 /* Sort by descending dc_plane layer_index (i.e. normalized_zpos) */ 382 return sb->surface->layer_index - sa->surface->layer_index; 383 } 384 385 /** 386 * update_planes_and_stream_adapter() - Send planes to be updated in DC 387 * 388 * DC has a generic way to update planes and stream via 389 * dc_update_planes_and_stream function; however, DM might need some 390 * adjustments and preparation before calling it. This function is a wrapper 391 * for the dc_update_planes_and_stream that does any required configuration 392 * before passing control to DC. 393 * 394 * @dc: Display Core control structure 395 * @update_type: specify whether it is FULL/MEDIUM/FAST update 396 * @planes_count: planes count to update 397 * @stream: stream state 398 * @stream_update: stream update 399 * @array_of_surface_update: dc surface update pointer 400 * 401 */ 402 static inline bool update_planes_and_stream_adapter(struct dc *dc, 403 int update_type, 404 int planes_count, 405 struct dc_stream_state *stream, 406 struct dc_stream_update *stream_update, 407 struct dc_surface_update *array_of_surface_update) 408 { 409 sort(array_of_surface_update, planes_count, 410 sizeof(*array_of_surface_update), dm_plane_layer_index_cmp, NULL); 411 412 /* 413 * Previous frame finished and HW is ready for optimization. 414 */ 415 if (update_type == UPDATE_TYPE_FAST) 416 dc_post_update_surfaces_to_stream(dc); 417 418 return dc_update_planes_and_stream(dc, 419 array_of_surface_update, 420 planes_count, 421 stream, 422 stream_update); 423 } 424 425 /** 426 * dm_pflip_high_irq() - Handle pageflip interrupt 427 * @interrupt_params: ignored 428 * 429 * Handles the pageflip interrupt by notifying all interested parties 430 * that the pageflip has been completed. 431 */ 432 static void dm_pflip_high_irq(void *interrupt_params) 433 { 434 struct amdgpu_crtc *amdgpu_crtc; 435 struct common_irq_params *irq_params = interrupt_params; 436 struct amdgpu_device *adev = irq_params->adev; 437 struct drm_device *dev = adev_to_drm(adev); 438 unsigned long flags; 439 struct drm_pending_vblank_event *e; 440 u32 vpos, hpos, v_blank_start, v_blank_end; 441 bool vrr_active; 442 443 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); 444 445 /* IRQ could occur when in initial stage */ 446 /* TODO work and BO cleanup */ 447 if (amdgpu_crtc == NULL) { 448 drm_dbg_state(dev, "CRTC is null, returning.\n"); 449 return; 450 } 451 452 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 453 454 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 455 drm_dbg_state(dev, 456 "amdgpu_crtc->pflip_status = %d != AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n", 457 amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED, 458 amdgpu_crtc->crtc_id, amdgpu_crtc); 459 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 460 return; 461 } 462 463 /* page flip completed. */ 464 e = amdgpu_crtc->event; 465 amdgpu_crtc->event = NULL; 466 467 WARN_ON(!e); 468 469 vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc); 470 471 /* Fixed refresh rate, or VRR scanout position outside front-porch? */ 472 if (!vrr_active || 473 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start, 474 &v_blank_end, &hpos, &vpos) || 475 (vpos < v_blank_start)) { 476 /* Update to correct count and vblank timestamp if racing with 477 * vblank irq. This also updates to the correct vblank timestamp 478 * even in VRR mode, as scanout is past the front-porch atm. 479 */ 480 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); 481 482 /* Wake up userspace by sending the pageflip event with proper 483 * count and timestamp of vblank of flip completion. 484 */ 485 if (e) { 486 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); 487 488 /* Event sent, so done with vblank for this flip */ 489 drm_crtc_vblank_put(&amdgpu_crtc->base); 490 } 491 } else if (e) { 492 /* VRR active and inside front-porch: vblank count and 493 * timestamp for pageflip event will only be up to date after 494 * drm_crtc_handle_vblank() has been executed from late vblank 495 * irq handler after start of back-porch (vline 0). We queue the 496 * pageflip event for send-out by drm_crtc_handle_vblank() with 497 * updated timestamp and count, once it runs after us. 498 * 499 * We need to open-code this instead of using the helper 500 * drm_crtc_arm_vblank_event(), as that helper would 501 * call drm_crtc_accurate_vblank_count(), which we must 502 * not call in VRR mode while we are in front-porch! 503 */ 504 505 /* sequence will be replaced by real count during send-out. */ 506 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); 507 e->pipe = amdgpu_crtc->crtc_id; 508 509 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list); 510 e = NULL; 511 } 512 513 /* Keep track of vblank of this flip for flip throttling. We use the 514 * cooked hw counter, as that one incremented at start of this vblank 515 * of pageflip completion, so last_flip_vblank is the forbidden count 516 * for queueing new pageflips if vsync + VRR is enabled. 517 */ 518 amdgpu_crtc->dm_irq_params.last_flip_vblank = 519 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base); 520 521 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 522 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 523 524 drm_dbg_state(dev, 525 "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n", 526 amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int)!e); 527 } 528 529 static void dm_vupdate_high_irq(void *interrupt_params) 530 { 531 struct common_irq_params *irq_params = interrupt_params; 532 struct amdgpu_device *adev = irq_params->adev; 533 struct amdgpu_crtc *acrtc; 534 struct drm_device *drm_dev; 535 struct drm_vblank_crtc *vblank; 536 ktime_t frame_duration_ns, previous_timestamp; 537 unsigned long flags; 538 int vrr_active; 539 540 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); 541 542 if (acrtc) { 543 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); 544 drm_dev = acrtc->base.dev; 545 vblank = drm_crtc_vblank_crtc(&acrtc->base); 546 previous_timestamp = atomic64_read(&irq_params->previous_timestamp); 547 frame_duration_ns = vblank->time - previous_timestamp; 548 549 if (frame_duration_ns > 0) { 550 trace_amdgpu_refresh_rate_track(acrtc->base.index, 551 frame_duration_ns, 552 ktime_divns(NSEC_PER_SEC, frame_duration_ns)); 553 atomic64_set(&irq_params->previous_timestamp, vblank->time); 554 } 555 556 drm_dbg_vbl(drm_dev, 557 "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, 558 vrr_active); 559 560 /* Core vblank handling is done here after end of front-porch in 561 * vrr mode, as vblank timestamping will give valid results 562 * while now done after front-porch. This will also deliver 563 * page-flip completion events that have been queued to us 564 * if a pageflip happened inside front-porch. 565 */ 566 if (vrr_active) { 567 amdgpu_dm_crtc_handle_vblank(acrtc); 568 569 /* BTR processing for pre-DCE12 ASICs */ 570 if (acrtc->dm_irq_params.stream && 571 adev->family < AMDGPU_FAMILY_AI) { 572 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 573 mod_freesync_handle_v_update( 574 adev->dm.freesync_module, 575 acrtc->dm_irq_params.stream, 576 &acrtc->dm_irq_params.vrr_params); 577 578 dc_stream_adjust_vmin_vmax( 579 adev->dm.dc, 580 acrtc->dm_irq_params.stream, 581 &acrtc->dm_irq_params.vrr_params.adjust); 582 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 583 } 584 } 585 } 586 } 587 588 /** 589 * dm_crtc_high_irq() - Handles CRTC interrupt 590 * @interrupt_params: used for determining the CRTC instance 591 * 592 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK 593 * event handler. 594 */ 595 static void dm_crtc_high_irq(void *interrupt_params) 596 { 597 struct common_irq_params *irq_params = interrupt_params; 598 struct amdgpu_device *adev = irq_params->adev; 599 struct drm_writeback_job *job; 600 struct amdgpu_crtc *acrtc; 601 unsigned long flags; 602 int vrr_active; 603 604 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); 605 if (!acrtc) 606 return; 607 608 if (acrtc->wb_conn) { 609 spin_lock_irqsave(&acrtc->wb_conn->job_lock, flags); 610 611 if (acrtc->wb_pending) { 612 job = list_first_entry_or_null(&acrtc->wb_conn->job_queue, 613 struct drm_writeback_job, 614 list_entry); 615 acrtc->wb_pending = false; 616 spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags); 617 618 if (job) { 619 unsigned int v_total, refresh_hz; 620 struct dc_stream_state *stream = acrtc->dm_irq_params.stream; 621 622 v_total = stream->adjust.v_total_max ? 623 stream->adjust.v_total_max : stream->timing.v_total; 624 refresh_hz = div_u64((uint64_t) stream->timing.pix_clk_100hz * 625 100LL, (v_total * stream->timing.h_total)); 626 mdelay(1000 / refresh_hz); 627 628 drm_writeback_signal_completion(acrtc->wb_conn, 0); 629 dc_stream_fc_disable_writeback(adev->dm.dc, 630 acrtc->dm_irq_params.stream, 0); 631 } 632 } else 633 spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags); 634 } 635 636 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); 637 638 drm_dbg_vbl(adev_to_drm(adev), 639 "crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id, 640 vrr_active, acrtc->dm_irq_params.active_planes); 641 642 /** 643 * Core vblank handling at start of front-porch is only possible 644 * in non-vrr mode, as only there vblank timestamping will give 645 * valid results while done in front-porch. Otherwise defer it 646 * to dm_vupdate_high_irq after end of front-porch. 647 */ 648 if (!vrr_active) 649 amdgpu_dm_crtc_handle_vblank(acrtc); 650 651 /** 652 * Following stuff must happen at start of vblank, for crc 653 * computation and below-the-range btr support in vrr mode. 654 */ 655 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); 656 657 /* BTR updates need to happen before VUPDATE on Vega and above. */ 658 if (adev->family < AMDGPU_FAMILY_AI) 659 return; 660 661 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 662 663 if (acrtc->dm_irq_params.stream && 664 acrtc->dm_irq_params.vrr_params.supported && 665 acrtc->dm_irq_params.freesync_config.state == 666 VRR_STATE_ACTIVE_VARIABLE) { 667 mod_freesync_handle_v_update(adev->dm.freesync_module, 668 acrtc->dm_irq_params.stream, 669 &acrtc->dm_irq_params.vrr_params); 670 671 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream, 672 &acrtc->dm_irq_params.vrr_params.adjust); 673 } 674 675 /* 676 * If there aren't any active_planes then DCH HUBP may be clock-gated. 677 * In that case, pageflip completion interrupts won't fire and pageflip 678 * completion events won't get delivered. Prevent this by sending 679 * pending pageflip events from here if a flip is still pending. 680 * 681 * If any planes are enabled, use dm_pflip_high_irq() instead, to 682 * avoid race conditions between flip programming and completion, 683 * which could cause too early flip completion events. 684 */ 685 if (adev->family >= AMDGPU_FAMILY_RV && 686 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED && 687 acrtc->dm_irq_params.active_planes == 0) { 688 if (acrtc->event) { 689 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event); 690 acrtc->event = NULL; 691 drm_crtc_vblank_put(&acrtc->base); 692 } 693 acrtc->pflip_status = AMDGPU_FLIP_NONE; 694 } 695 696 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 697 } 698 699 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 700 /** 701 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for 702 * DCN generation ASICs 703 * @interrupt_params: interrupt parameters 704 * 705 * Used to set crc window/read out crc value at vertical line 0 position 706 */ 707 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params) 708 { 709 struct common_irq_params *irq_params = interrupt_params; 710 struct amdgpu_device *adev = irq_params->adev; 711 struct amdgpu_crtc *acrtc; 712 713 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0); 714 715 if (!acrtc) 716 return; 717 718 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base); 719 } 720 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */ 721 722 /** 723 * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command. 724 * @adev: amdgpu_device pointer 725 * @notify: dmub notification structure 726 * 727 * Dmub AUX or SET_CONFIG command completion processing callback 728 * Copies dmub notification to DM which is to be read by AUX command. 729 * issuing thread and also signals the event to wake up the thread. 730 */ 731 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev, 732 struct dmub_notification *notify) 733 { 734 if (adev->dm.dmub_notify) 735 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification)); 736 if (notify->type == DMUB_NOTIFICATION_AUX_REPLY) 737 complete(&adev->dm.dmub_aux_transfer_done); 738 } 739 740 /** 741 * dmub_hpd_callback - DMUB HPD interrupt processing callback. 742 * @adev: amdgpu_device pointer 743 * @notify: dmub notification structure 744 * 745 * Dmub Hpd interrupt processing callback. Gets displayindex through the 746 * ink index and calls helper to do the processing. 747 */ 748 static void dmub_hpd_callback(struct amdgpu_device *adev, 749 struct dmub_notification *notify) 750 { 751 struct amdgpu_dm_connector *aconnector; 752 struct amdgpu_dm_connector *hpd_aconnector = NULL; 753 struct drm_connector *connector; 754 struct drm_connector_list_iter iter; 755 struct dc_link *link; 756 u8 link_index = 0; 757 struct drm_device *dev; 758 759 if (adev == NULL) 760 return; 761 762 if (notify == NULL) { 763 DRM_ERROR("DMUB HPD callback notification was NULL"); 764 return; 765 } 766 767 if (notify->link_index > adev->dm.dc->link_count) { 768 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index); 769 return; 770 } 771 772 link_index = notify->link_index; 773 link = adev->dm.dc->links[link_index]; 774 dev = adev->dm.ddev; 775 776 drm_connector_list_iter_begin(dev, &iter); 777 drm_for_each_connector_iter(connector, &iter) { 778 779 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 780 continue; 781 782 aconnector = to_amdgpu_dm_connector(connector); 783 if (link && aconnector->dc_link == link) { 784 if (notify->type == DMUB_NOTIFICATION_HPD) 785 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index); 786 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) 787 DRM_INFO("DMUB HPD RX IRQ callback: link_index=%u\n", link_index); 788 else 789 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n", 790 notify->type, link_index); 791 792 hpd_aconnector = aconnector; 793 break; 794 } 795 } 796 drm_connector_list_iter_end(&iter); 797 798 if (hpd_aconnector) { 799 if (notify->type == DMUB_NOTIFICATION_HPD) { 800 if (hpd_aconnector->dc_link->hpd_status == (notify->hpd_status == DP_HPD_PLUG)) 801 DRM_WARN("DMUB reported hpd status unchanged. link_index=%u\n", link_index); 802 handle_hpd_irq_helper(hpd_aconnector); 803 } else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) { 804 handle_hpd_rx_irq(hpd_aconnector); 805 } 806 } 807 } 808 809 /** 810 * register_dmub_notify_callback - Sets callback for DMUB notify 811 * @adev: amdgpu_device pointer 812 * @type: Type of dmub notification 813 * @callback: Dmub interrupt callback function 814 * @dmub_int_thread_offload: offload indicator 815 * 816 * API to register a dmub callback handler for a dmub notification 817 * Also sets indicator whether callback processing to be offloaded. 818 * to dmub interrupt handling thread 819 * Return: true if successfully registered, false if there is existing registration 820 */ 821 static bool register_dmub_notify_callback(struct amdgpu_device *adev, 822 enum dmub_notification_type type, 823 dmub_notify_interrupt_callback_t callback, 824 bool dmub_int_thread_offload) 825 { 826 if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) { 827 adev->dm.dmub_callback[type] = callback; 828 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload; 829 } else 830 return false; 831 832 return true; 833 } 834 835 static void dm_handle_hpd_work(struct work_struct *work) 836 { 837 struct dmub_hpd_work *dmub_hpd_wrk; 838 839 dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work); 840 841 if (!dmub_hpd_wrk->dmub_notify) { 842 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL"); 843 return; 844 } 845 846 if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) { 847 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev, 848 dmub_hpd_wrk->dmub_notify); 849 } 850 851 kfree(dmub_hpd_wrk->dmub_notify); 852 kfree(dmub_hpd_wrk); 853 854 } 855 856 #define DMUB_TRACE_MAX_READ 64 857 /** 858 * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt 859 * @interrupt_params: used for determining the Outbox instance 860 * 861 * Handles the Outbox Interrupt 862 * event handler. 863 */ 864 static void dm_dmub_outbox1_low_irq(void *interrupt_params) 865 { 866 struct dmub_notification notify = {0}; 867 struct common_irq_params *irq_params = interrupt_params; 868 struct amdgpu_device *adev = irq_params->adev; 869 struct amdgpu_display_manager *dm = &adev->dm; 870 struct dmcub_trace_buf_entry entry = { 0 }; 871 u32 count = 0; 872 struct dmub_hpd_work *dmub_hpd_wrk; 873 static const char *const event_type[] = { 874 "NO_DATA", 875 "AUX_REPLY", 876 "HPD", 877 "HPD_IRQ", 878 "SET_CONFIGC_REPLY", 879 "DPIA_NOTIFICATION", 880 }; 881 882 do { 883 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) { 884 trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count, 885 entry.param0, entry.param1); 886 887 DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n", 888 entry.trace_code, entry.tick_count, entry.param0, entry.param1); 889 } else 890 break; 891 892 count++; 893 894 } while (count <= DMUB_TRACE_MAX_READ); 895 896 if (count > DMUB_TRACE_MAX_READ) 897 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ"); 898 899 if (dc_enable_dmub_notifications(adev->dm.dc) && 900 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) { 901 902 do { 903 dc_stat_get_dmub_notification(adev->dm.dc, ¬ify); 904 if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) { 905 DRM_ERROR("DM: notify type %d invalid!", notify.type); 906 continue; 907 } 908 if (!dm->dmub_callback[notify.type]) { 909 DRM_WARN("DMUB notification skipped due to no handler: type=%s\n", 910 event_type[notify.type]); 911 continue; 912 } 913 if (dm->dmub_thread_offload[notify.type] == true) { 914 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC); 915 if (!dmub_hpd_wrk) { 916 DRM_ERROR("Failed to allocate dmub_hpd_wrk"); 917 return; 918 } 919 dmub_hpd_wrk->dmub_notify = kmemdup(¬ify, sizeof(struct dmub_notification), 920 GFP_ATOMIC); 921 if (!dmub_hpd_wrk->dmub_notify) { 922 kfree(dmub_hpd_wrk); 923 DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify"); 924 return; 925 } 926 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work); 927 dmub_hpd_wrk->adev = adev; 928 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work); 929 } else { 930 dm->dmub_callback[notify.type](adev, ¬ify); 931 } 932 } while (notify.pending_notification); 933 } 934 } 935 936 static int dm_set_clockgating_state(void *handle, 937 enum amd_clockgating_state state) 938 { 939 return 0; 940 } 941 942 static int dm_set_powergating_state(void *handle, 943 enum amd_powergating_state state) 944 { 945 return 0; 946 } 947 948 /* Prototypes of private functions */ 949 static int dm_early_init(void *handle); 950 951 /* Allocate memory for FBC compressed data */ 952 static void amdgpu_dm_fbc_init(struct drm_connector *connector) 953 { 954 struct amdgpu_device *adev = drm_to_adev(connector->dev); 955 struct dm_compressor_info *compressor = &adev->dm.compressor; 956 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); 957 struct drm_display_mode *mode; 958 unsigned long max_size = 0; 959 960 if (adev->dm.dc->fbc_compressor == NULL) 961 return; 962 963 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) 964 return; 965 966 if (compressor->bo_ptr) 967 return; 968 969 970 list_for_each_entry(mode, &connector->modes, head) { 971 if (max_size < (unsigned long) mode->htotal * mode->vtotal) 972 max_size = (unsigned long) mode->htotal * mode->vtotal; 973 } 974 975 if (max_size) { 976 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, 977 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, 978 &compressor->gpu_addr, &compressor->cpu_addr); 979 980 if (r) 981 DRM_ERROR("DM: Failed to initialize FBC\n"); 982 else { 983 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; 984 DRM_INFO("DM: FBC alloc %lu\n", max_size*4); 985 } 986 987 } 988 989 } 990 991 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, 992 int pipe, bool *enabled, 993 unsigned char *buf, int max_bytes) 994 { 995 struct drm_device *dev = dev_get_drvdata(kdev); 996 struct amdgpu_device *adev = drm_to_adev(dev); 997 struct drm_connector *connector; 998 struct drm_connector_list_iter conn_iter; 999 struct amdgpu_dm_connector *aconnector; 1000 int ret = 0; 1001 1002 *enabled = false; 1003 1004 mutex_lock(&adev->dm.audio_lock); 1005 1006 drm_connector_list_iter_begin(dev, &conn_iter); 1007 drm_for_each_connector_iter(connector, &conn_iter) { 1008 1009 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 1010 continue; 1011 1012 aconnector = to_amdgpu_dm_connector(connector); 1013 if (aconnector->audio_inst != port) 1014 continue; 1015 1016 *enabled = true; 1017 ret = drm_eld_size(connector->eld); 1018 memcpy(buf, connector->eld, min(max_bytes, ret)); 1019 1020 break; 1021 } 1022 drm_connector_list_iter_end(&conn_iter); 1023 1024 mutex_unlock(&adev->dm.audio_lock); 1025 1026 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); 1027 1028 return ret; 1029 } 1030 1031 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { 1032 .get_eld = amdgpu_dm_audio_component_get_eld, 1033 }; 1034 1035 static int amdgpu_dm_audio_component_bind(struct device *kdev, 1036 struct device *hda_kdev, void *data) 1037 { 1038 struct drm_device *dev = dev_get_drvdata(kdev); 1039 struct amdgpu_device *adev = drm_to_adev(dev); 1040 struct drm_audio_component *acomp = data; 1041 1042 acomp->ops = &amdgpu_dm_audio_component_ops; 1043 acomp->dev = kdev; 1044 adev->dm.audio_component = acomp; 1045 1046 return 0; 1047 } 1048 1049 static void amdgpu_dm_audio_component_unbind(struct device *kdev, 1050 struct device *hda_kdev, void *data) 1051 { 1052 struct amdgpu_device *adev = drm_to_adev(dev_get_drvdata(kdev)); 1053 struct drm_audio_component *acomp = data; 1054 1055 acomp->ops = NULL; 1056 acomp->dev = NULL; 1057 adev->dm.audio_component = NULL; 1058 } 1059 1060 static const struct component_ops amdgpu_dm_audio_component_bind_ops = { 1061 .bind = amdgpu_dm_audio_component_bind, 1062 .unbind = amdgpu_dm_audio_component_unbind, 1063 }; 1064 1065 static int amdgpu_dm_audio_init(struct amdgpu_device *adev) 1066 { 1067 int i, ret; 1068 1069 if (!amdgpu_audio) 1070 return 0; 1071 1072 adev->mode_info.audio.enabled = true; 1073 1074 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; 1075 1076 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1077 adev->mode_info.audio.pin[i].channels = -1; 1078 adev->mode_info.audio.pin[i].rate = -1; 1079 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1080 adev->mode_info.audio.pin[i].status_bits = 0; 1081 adev->mode_info.audio.pin[i].category_code = 0; 1082 adev->mode_info.audio.pin[i].connected = false; 1083 adev->mode_info.audio.pin[i].id = 1084 adev->dm.dc->res_pool->audios[i]->inst; 1085 adev->mode_info.audio.pin[i].offset = 0; 1086 } 1087 1088 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops); 1089 if (ret < 0) 1090 return ret; 1091 1092 adev->dm.audio_registered = true; 1093 1094 return 0; 1095 } 1096 1097 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) 1098 { 1099 if (!amdgpu_audio) 1100 return; 1101 1102 if (!adev->mode_info.audio.enabled) 1103 return; 1104 1105 if (adev->dm.audio_registered) { 1106 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); 1107 adev->dm.audio_registered = false; 1108 } 1109 1110 /* TODO: Disable audio? */ 1111 1112 adev->mode_info.audio.enabled = false; 1113 } 1114 1115 static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) 1116 { 1117 struct drm_audio_component *acomp = adev->dm.audio_component; 1118 1119 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { 1120 DRM_DEBUG_KMS("Notify ELD: %d\n", pin); 1121 1122 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 1123 pin, -1); 1124 } 1125 } 1126 1127 static int dm_dmub_hw_init(struct amdgpu_device *adev) 1128 { 1129 const struct dmcub_firmware_header_v1_0 *hdr; 1130 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 1131 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 1132 const struct firmware *dmub_fw = adev->dm.dmub_fw; 1133 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; 1134 struct abm *abm = adev->dm.dc->res_pool->abm; 1135 struct dc_context *ctx = adev->dm.dc->ctx; 1136 struct dmub_srv_hw_params hw_params; 1137 enum dmub_status status; 1138 const unsigned char *fw_inst_const, *fw_bss_data; 1139 u32 i, fw_inst_const_size, fw_bss_data_size; 1140 bool has_hw_support; 1141 1142 if (!dmub_srv) 1143 /* DMUB isn't supported on the ASIC. */ 1144 return 0; 1145 1146 if (!fb_info) { 1147 DRM_ERROR("No framebuffer info for DMUB service.\n"); 1148 return -EINVAL; 1149 } 1150 1151 if (!dmub_fw) { 1152 /* Firmware required for DMUB support. */ 1153 DRM_ERROR("No firmware provided for DMUB.\n"); 1154 return -EINVAL; 1155 } 1156 1157 /* initialize register offsets for ASICs with runtime initialization available */ 1158 if (dmub_srv->hw_funcs.init_reg_offsets) 1159 dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx); 1160 1161 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support); 1162 if (status != DMUB_STATUS_OK) { 1163 DRM_ERROR("Error checking HW support for DMUB: %d\n", status); 1164 return -EINVAL; 1165 } 1166 1167 if (!has_hw_support) { 1168 DRM_INFO("DMUB unsupported on ASIC\n"); 1169 return 0; 1170 } 1171 1172 /* Reset DMCUB if it was previously running - before we overwrite its memory. */ 1173 status = dmub_srv_hw_reset(dmub_srv); 1174 if (status != DMUB_STATUS_OK) 1175 DRM_WARN("Error resetting DMUB HW: %d\n", status); 1176 1177 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data; 1178 1179 fw_inst_const = dmub_fw->data + 1180 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1181 PSP_HEADER_BYTES; 1182 1183 fw_bss_data = dmub_fw->data + 1184 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1185 le32_to_cpu(hdr->inst_const_bytes); 1186 1187 /* Copy firmware and bios info into FB memory. */ 1188 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 1189 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 1190 1191 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 1192 1193 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP, 1194 * amdgpu_ucode_init_single_fw will load dmub firmware 1195 * fw_inst_const part to cw0; otherwise, the firmware back door load 1196 * will be done by dm_dmub_hw_init 1197 */ 1198 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1199 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const, 1200 fw_inst_const_size); 1201 } 1202 1203 if (fw_bss_data_size) 1204 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr, 1205 fw_bss_data, fw_bss_data_size); 1206 1207 /* Copy firmware bios info into FB memory. */ 1208 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios, 1209 adev->bios_size); 1210 1211 /* Reset regions that need to be reset. */ 1212 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0, 1213 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size); 1214 1215 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0, 1216 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size); 1217 1218 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0, 1219 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size); 1220 1221 memset(fb_info->fb[DMUB_WINDOW_SHARED_STATE].cpu_addr, 0, 1222 fb_info->fb[DMUB_WINDOW_SHARED_STATE].size); 1223 1224 /* Initialize hardware. */ 1225 memset(&hw_params, 0, sizeof(hw_params)); 1226 hw_params.fb_base = adev->gmc.fb_start; 1227 hw_params.fb_offset = adev->vm_manager.vram_base_offset; 1228 1229 /* backdoor load firmware and trigger dmub running */ 1230 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 1231 hw_params.load_inst_const = true; 1232 1233 if (dmcu) 1234 hw_params.psp_version = dmcu->psp_version; 1235 1236 for (i = 0; i < fb_info->num_fb; ++i) 1237 hw_params.fb[i] = &fb_info->fb[i]; 1238 1239 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1240 case IP_VERSION(3, 1, 3): 1241 case IP_VERSION(3, 1, 4): 1242 case IP_VERSION(3, 5, 0): 1243 case IP_VERSION(3, 5, 1): 1244 case IP_VERSION(4, 0, 1): 1245 hw_params.dpia_supported = true; 1246 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia; 1247 break; 1248 default: 1249 break; 1250 } 1251 1252 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1253 case IP_VERSION(3, 5, 0): 1254 case IP_VERSION(3, 5, 1): 1255 hw_params.ips_sequential_ono = adev->external_rev_id > 0x10; 1256 break; 1257 default: 1258 break; 1259 } 1260 1261 status = dmub_srv_hw_init(dmub_srv, &hw_params); 1262 if (status != DMUB_STATUS_OK) { 1263 DRM_ERROR("Error initializing DMUB HW: %d\n", status); 1264 return -EINVAL; 1265 } 1266 1267 /* Wait for firmware load to finish. */ 1268 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); 1269 if (status != DMUB_STATUS_OK) 1270 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); 1271 1272 /* Init DMCU and ABM if available. */ 1273 if (dmcu && abm) { 1274 dmcu->funcs->dmcu_init(dmcu); 1275 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 1276 } 1277 1278 if (!adev->dm.dc->ctx->dmub_srv) 1279 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv); 1280 if (!adev->dm.dc->ctx->dmub_srv) { 1281 DRM_ERROR("Couldn't allocate DC DMUB server!\n"); 1282 return -ENOMEM; 1283 } 1284 1285 DRM_INFO("DMUB hardware initialized: version=0x%08X\n", 1286 adev->dm.dmcub_fw_version); 1287 1288 return 0; 1289 } 1290 1291 static void dm_dmub_hw_resume(struct amdgpu_device *adev) 1292 { 1293 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 1294 enum dmub_status status; 1295 bool init; 1296 int r; 1297 1298 if (!dmub_srv) { 1299 /* DMUB isn't supported on the ASIC. */ 1300 return; 1301 } 1302 1303 status = dmub_srv_is_hw_init(dmub_srv, &init); 1304 if (status != DMUB_STATUS_OK) 1305 DRM_WARN("DMUB hardware init check failed: %d\n", status); 1306 1307 if (status == DMUB_STATUS_OK && init) { 1308 /* Wait for firmware load to finish. */ 1309 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); 1310 if (status != DMUB_STATUS_OK) 1311 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); 1312 } else { 1313 /* Perform the full hardware initialization. */ 1314 r = dm_dmub_hw_init(adev); 1315 if (r) 1316 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 1317 } 1318 } 1319 1320 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) 1321 { 1322 u64 pt_base; 1323 u32 logical_addr_low; 1324 u32 logical_addr_high; 1325 u32 agp_base, agp_bot, agp_top; 1326 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; 1327 1328 memset(pa_config, 0, sizeof(*pa_config)); 1329 1330 agp_base = 0; 1331 agp_bot = adev->gmc.agp_start >> 24; 1332 agp_top = adev->gmc.agp_end >> 24; 1333 1334 /* AGP aperture is disabled */ 1335 if (agp_bot > agp_top) { 1336 logical_addr_low = adev->gmc.fb_start >> 18; 1337 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 1338 AMD_APU_IS_RENOIR | 1339 AMD_APU_IS_GREEN_SARDINE)) 1340 /* 1341 * Raven2 has a HW issue that it is unable to use the vram which 1342 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 1343 * workaround that increase system aperture high address (add 1) 1344 * to get rid of the VM fault and hardware hang. 1345 */ 1346 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1; 1347 else 1348 logical_addr_high = adev->gmc.fb_end >> 18; 1349 } else { 1350 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; 1351 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 1352 AMD_APU_IS_RENOIR | 1353 AMD_APU_IS_GREEN_SARDINE)) 1354 /* 1355 * Raven2 has a HW issue that it is unable to use the vram which 1356 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 1357 * workaround that increase system aperture high address (add 1) 1358 * to get rid of the VM fault and hardware hang. 1359 */ 1360 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); 1361 else 1362 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; 1363 } 1364 1365 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 1366 1367 page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >> 1368 AMDGPU_GPU_PAGE_SHIFT); 1369 page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >> 1370 AMDGPU_GPU_PAGE_SHIFT); 1371 page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >> 1372 AMDGPU_GPU_PAGE_SHIFT); 1373 page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >> 1374 AMDGPU_GPU_PAGE_SHIFT); 1375 page_table_base.high_part = upper_32_bits(pt_base); 1376 page_table_base.low_part = lower_32_bits(pt_base); 1377 1378 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; 1379 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; 1380 1381 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24; 1382 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; 1383 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; 1384 1385 pa_config->system_aperture.fb_base = adev->gmc.fb_start; 1386 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset; 1387 pa_config->system_aperture.fb_top = adev->gmc.fb_end; 1388 1389 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; 1390 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; 1391 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; 1392 1393 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support; 1394 1395 } 1396 1397 static void force_connector_state( 1398 struct amdgpu_dm_connector *aconnector, 1399 enum drm_connector_force force_state) 1400 { 1401 struct drm_connector *connector = &aconnector->base; 1402 1403 mutex_lock(&connector->dev->mode_config.mutex); 1404 aconnector->base.force = force_state; 1405 mutex_unlock(&connector->dev->mode_config.mutex); 1406 1407 mutex_lock(&aconnector->hpd_lock); 1408 drm_kms_helper_connector_hotplug_event(connector); 1409 mutex_unlock(&aconnector->hpd_lock); 1410 } 1411 1412 static void dm_handle_hpd_rx_offload_work(struct work_struct *work) 1413 { 1414 struct hpd_rx_irq_offload_work *offload_work; 1415 struct amdgpu_dm_connector *aconnector; 1416 struct dc_link *dc_link; 1417 struct amdgpu_device *adev; 1418 enum dc_connection_type new_connection_type = dc_connection_none; 1419 unsigned long flags; 1420 union test_response test_response; 1421 1422 memset(&test_response, 0, sizeof(test_response)); 1423 1424 offload_work = container_of(work, struct hpd_rx_irq_offload_work, work); 1425 aconnector = offload_work->offload_wq->aconnector; 1426 1427 if (!aconnector) { 1428 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work"); 1429 goto skip; 1430 } 1431 1432 adev = drm_to_adev(aconnector->base.dev); 1433 dc_link = aconnector->dc_link; 1434 1435 mutex_lock(&aconnector->hpd_lock); 1436 if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) 1437 DRM_ERROR("KMS: Failed to detect connector\n"); 1438 mutex_unlock(&aconnector->hpd_lock); 1439 1440 if (new_connection_type == dc_connection_none) 1441 goto skip; 1442 1443 if (amdgpu_in_reset(adev)) 1444 goto skip; 1445 1446 if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || 1447 offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { 1448 dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT); 1449 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); 1450 offload_work->offload_wq->is_handling_mst_msg_rdy_event = false; 1451 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); 1452 goto skip; 1453 } 1454 1455 mutex_lock(&adev->dm.dc_lock); 1456 if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) { 1457 dc_link_dp_handle_automated_test(dc_link); 1458 1459 if (aconnector->timing_changed) { 1460 /* force connector disconnect and reconnect */ 1461 force_connector_state(aconnector, DRM_FORCE_OFF); 1462 msleep(100); 1463 force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED); 1464 } 1465 1466 test_response.bits.ACK = 1; 1467 1468 core_link_write_dpcd( 1469 dc_link, 1470 DP_TEST_RESPONSE, 1471 &test_response.raw, 1472 sizeof(test_response)); 1473 } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) && 1474 dc_link_check_link_loss_status(dc_link, &offload_work->data) && 1475 dc_link_dp_allow_hpd_rx_irq(dc_link)) { 1476 /* offload_work->data is from handle_hpd_rx_irq-> 1477 * schedule_hpd_rx_offload_work.this is defer handle 1478 * for hpd short pulse. upon here, link status may be 1479 * changed, need get latest link status from dpcd 1480 * registers. if link status is good, skip run link 1481 * training again. 1482 */ 1483 union hpd_irq_data irq_data; 1484 1485 memset(&irq_data, 0, sizeof(irq_data)); 1486 1487 /* before dc_link_dp_handle_link_loss, allow new link lost handle 1488 * request be added to work queue if link lost at end of dc_link_ 1489 * dp_handle_link_loss 1490 */ 1491 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); 1492 offload_work->offload_wq->is_handling_link_loss = false; 1493 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); 1494 1495 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) && 1496 dc_link_check_link_loss_status(dc_link, &irq_data)) 1497 dc_link_dp_handle_link_loss(dc_link); 1498 } 1499 mutex_unlock(&adev->dm.dc_lock); 1500 1501 skip: 1502 kfree(offload_work); 1503 1504 } 1505 1506 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc) 1507 { 1508 int max_caps = dc->caps.max_links; 1509 int i = 0; 1510 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL; 1511 1512 hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL); 1513 1514 if (!hpd_rx_offload_wq) 1515 return NULL; 1516 1517 1518 for (i = 0; i < max_caps; i++) { 1519 hpd_rx_offload_wq[i].wq = 1520 create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq"); 1521 1522 if (hpd_rx_offload_wq[i].wq == NULL) { 1523 DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!"); 1524 goto out_err; 1525 } 1526 1527 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock); 1528 } 1529 1530 return hpd_rx_offload_wq; 1531 1532 out_err: 1533 for (i = 0; i < max_caps; i++) { 1534 if (hpd_rx_offload_wq[i].wq) 1535 destroy_workqueue(hpd_rx_offload_wq[i].wq); 1536 } 1537 kfree(hpd_rx_offload_wq); 1538 return NULL; 1539 } 1540 1541 struct amdgpu_stutter_quirk { 1542 u16 chip_vendor; 1543 u16 chip_device; 1544 u16 subsys_vendor; 1545 u16 subsys_device; 1546 u8 revision; 1547 }; 1548 1549 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = { 1550 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */ 1551 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, 1552 { 0, 0, 0, 0, 0 }, 1553 }; 1554 1555 static bool dm_should_disable_stutter(struct pci_dev *pdev) 1556 { 1557 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list; 1558 1559 while (p && p->chip_device != 0) { 1560 if (pdev->vendor == p->chip_vendor && 1561 pdev->device == p->chip_device && 1562 pdev->subsystem_vendor == p->subsys_vendor && 1563 pdev->subsystem_device == p->subsys_device && 1564 pdev->revision == p->revision) { 1565 return true; 1566 } 1567 ++p; 1568 } 1569 return false; 1570 } 1571 1572 static const struct dmi_system_id hpd_disconnect_quirk_table[] = { 1573 { 1574 .matches = { 1575 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1576 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"), 1577 }, 1578 }, 1579 { 1580 .matches = { 1581 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1582 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"), 1583 }, 1584 }, 1585 { 1586 .matches = { 1587 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1588 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"), 1589 }, 1590 }, 1591 { 1592 .matches = { 1593 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1594 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"), 1595 }, 1596 }, 1597 { 1598 .matches = { 1599 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1600 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"), 1601 }, 1602 }, 1603 { 1604 .matches = { 1605 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1606 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"), 1607 }, 1608 }, 1609 { 1610 .matches = { 1611 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1612 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"), 1613 }, 1614 }, 1615 { 1616 .matches = { 1617 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1618 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"), 1619 }, 1620 }, 1621 { 1622 .matches = { 1623 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1624 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"), 1625 }, 1626 }, 1627 {} 1628 /* TODO: refactor this from a fixed table to a dynamic option */ 1629 }; 1630 1631 static void retrieve_dmi_info(struct amdgpu_display_manager *dm) 1632 { 1633 const struct dmi_system_id *dmi_id; 1634 1635 dm->aux_hpd_discon_quirk = false; 1636 1637 dmi_id = dmi_first_match(hpd_disconnect_quirk_table); 1638 if (dmi_id) { 1639 dm->aux_hpd_discon_quirk = true; 1640 DRM_INFO("aux_hpd_discon_quirk attached\n"); 1641 } 1642 } 1643 1644 void* 1645 dm_allocate_gpu_mem( 1646 struct amdgpu_device *adev, 1647 enum dc_gpu_mem_alloc_type type, 1648 size_t size, 1649 long long *addr) 1650 { 1651 struct dal_allocation *da; 1652 u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ? 1653 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM; 1654 int ret; 1655 1656 da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL); 1657 if (!da) 1658 return NULL; 1659 1660 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 1661 domain, &da->bo, 1662 &da->gpu_addr, &da->cpu_ptr); 1663 1664 *addr = da->gpu_addr; 1665 1666 if (ret) { 1667 kfree(da); 1668 return NULL; 1669 } 1670 1671 /* add da to list in dm */ 1672 list_add(&da->list, &adev->dm.da_list); 1673 1674 return da->cpu_ptr; 1675 } 1676 1677 static enum dmub_status 1678 dm_dmub_send_vbios_gpint_command(struct amdgpu_device *adev, 1679 enum dmub_gpint_command command_code, 1680 uint16_t param, 1681 uint32_t timeout_us) 1682 { 1683 union dmub_gpint_data_register reg, test; 1684 uint32_t i; 1685 1686 /* Assume that VBIOS DMUB is ready to take commands */ 1687 1688 reg.bits.status = 1; 1689 reg.bits.command_code = command_code; 1690 reg.bits.param = param; 1691 1692 cgs_write_register(adev->dm.cgs_device, 0x34c0 + 0x01f8, reg.all); 1693 1694 for (i = 0; i < timeout_us; ++i) { 1695 udelay(1); 1696 1697 /* Check if our GPINT got acked */ 1698 reg.bits.status = 0; 1699 test = (union dmub_gpint_data_register) 1700 cgs_read_register(adev->dm.cgs_device, 0x34c0 + 0x01f8); 1701 1702 if (test.all == reg.all) 1703 return DMUB_STATUS_OK; 1704 } 1705 1706 return DMUB_STATUS_TIMEOUT; 1707 } 1708 1709 static struct dml2_soc_bb *dm_dmub_get_vbios_bounding_box(struct amdgpu_device *adev) 1710 { 1711 struct dml2_soc_bb *bb; 1712 long long addr; 1713 int i = 0; 1714 uint16_t chunk; 1715 enum dmub_gpint_command send_addrs[] = { 1716 DMUB_GPINT__SET_BB_ADDR_WORD0, 1717 DMUB_GPINT__SET_BB_ADDR_WORD1, 1718 DMUB_GPINT__SET_BB_ADDR_WORD2, 1719 DMUB_GPINT__SET_BB_ADDR_WORD3, 1720 }; 1721 enum dmub_status ret; 1722 1723 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1724 case IP_VERSION(4, 0, 1): 1725 break; 1726 default: 1727 return NULL; 1728 } 1729 1730 bb = dm_allocate_gpu_mem(adev, 1731 DC_MEM_ALLOC_TYPE_GART, 1732 sizeof(struct dml2_soc_bb), 1733 &addr); 1734 if (!bb) 1735 return NULL; 1736 1737 for (i = 0; i < 4; i++) { 1738 /* Extract 16-bit chunk */ 1739 chunk = ((uint64_t) addr >> (i * 16)) & 0xFFFF; 1740 /* Send the chunk */ 1741 ret = dm_dmub_send_vbios_gpint_command(adev, send_addrs[i], chunk, 30000); 1742 if (ret != DMUB_STATUS_OK) 1743 /* No need to free bb here since it shall be done unconditionally <elsewhere> */ 1744 return NULL; 1745 } 1746 1747 /* Now ask DMUB to copy the bb */ 1748 ret = dm_dmub_send_vbios_gpint_command(adev, DMUB_GPINT__BB_COPY, 1, 200000); 1749 if (ret != DMUB_STATUS_OK) 1750 return NULL; 1751 1752 return bb; 1753 } 1754 1755 static int amdgpu_dm_init(struct amdgpu_device *adev) 1756 { 1757 struct dc_init_data init_data; 1758 struct dc_callback_init init_params; 1759 int r; 1760 1761 adev->dm.ddev = adev_to_drm(adev); 1762 adev->dm.adev = adev; 1763 1764 /* Zero all the fields */ 1765 memset(&init_data, 0, sizeof(init_data)); 1766 memset(&init_params, 0, sizeof(init_params)); 1767 1768 mutex_init(&adev->dm.dpia_aux_lock); 1769 mutex_init(&adev->dm.dc_lock); 1770 mutex_init(&adev->dm.audio_lock); 1771 1772 if (amdgpu_dm_irq_init(adev)) { 1773 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); 1774 goto error; 1775 } 1776 1777 init_data.asic_id.chip_family = adev->family; 1778 1779 init_data.asic_id.pci_revision_id = adev->pdev->revision; 1780 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 1781 init_data.asic_id.chip_id = adev->pdev->device; 1782 1783 init_data.asic_id.vram_width = adev->gmc.vram_width; 1784 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 1785 init_data.asic_id.atombios_base_address = 1786 adev->mode_info.atom_context->bios; 1787 1788 init_data.driver = adev; 1789 1790 /* cgs_device was created in dm_sw_init() */ 1791 init_data.cgs_device = adev->dm.cgs_device; 1792 1793 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 1794 1795 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1796 case IP_VERSION(2, 1, 0): 1797 switch (adev->dm.dmcub_fw_version) { 1798 case 0: /* development */ 1799 case 0x1: /* linux-firmware.git hash 6d9f399 */ 1800 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */ 1801 init_data.flags.disable_dmcu = false; 1802 break; 1803 default: 1804 init_data.flags.disable_dmcu = true; 1805 } 1806 break; 1807 case IP_VERSION(2, 0, 3): 1808 init_data.flags.disable_dmcu = true; 1809 break; 1810 default: 1811 break; 1812 } 1813 1814 /* APU support S/G display by default except: 1815 * ASICs before Carrizo, 1816 * RAVEN1 (Users reported stability issue) 1817 */ 1818 1819 if (adev->asic_type < CHIP_CARRIZO) { 1820 init_data.flags.gpu_vm_support = false; 1821 } else if (adev->asic_type == CHIP_RAVEN) { 1822 if (adev->apu_flags & AMD_APU_IS_RAVEN) 1823 init_data.flags.gpu_vm_support = false; 1824 else 1825 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0); 1826 } else { 1827 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU); 1828 } 1829 1830 adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support; 1831 1832 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 1833 init_data.flags.fbc_support = true; 1834 1835 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) 1836 init_data.flags.multi_mon_pp_mclk_switch = true; 1837 1838 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) 1839 init_data.flags.disable_fractional_pwm = true; 1840 1841 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING) 1842 init_data.flags.edp_no_power_sequencing = true; 1843 1844 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A) 1845 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true; 1846 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0) 1847 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true; 1848 1849 init_data.flags.seamless_boot_edp_requested = false; 1850 1851 if (amdgpu_device_seamless_boot_supported(adev)) { 1852 init_data.flags.seamless_boot_edp_requested = true; 1853 init_data.flags.allow_seamless_boot_optimization = true; 1854 DRM_INFO("Seamless boot condition check passed\n"); 1855 } 1856 1857 init_data.flags.enable_mipi_converter_optimization = true; 1858 1859 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; 1860 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; 1861 init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0]; 1862 1863 if (amdgpu_dc_debug_mask & DC_DISABLE_IPS) 1864 init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL; 1865 else 1866 init_data.flags.disable_ips = DMUB_IPS_ENABLE; 1867 1868 init_data.flags.disable_ips_in_vpb = 0; 1869 1870 /* Enable DWB for tested platforms only */ 1871 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) 1872 init_data.num_virtual_links = 1; 1873 1874 retrieve_dmi_info(&adev->dm); 1875 1876 if (adev->dm.bb_from_dmub) 1877 init_data.bb_from_dmub = adev->dm.bb_from_dmub; 1878 else 1879 init_data.bb_from_dmub = NULL; 1880 1881 /* Display Core create. */ 1882 adev->dm.dc = dc_create(&init_data); 1883 1884 if (adev->dm.dc) { 1885 DRM_INFO("Display Core v%s initialized on %s\n", DC_VER, 1886 dce_version_to_string(adev->dm.dc->ctx->dce_version)); 1887 } else { 1888 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); 1889 goto error; 1890 } 1891 1892 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { 1893 adev->dm.dc->debug.force_single_disp_pipe_split = false; 1894 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; 1895 } 1896 1897 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 1898 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 1899 if (dm_should_disable_stutter(adev->pdev)) 1900 adev->dm.dc->debug.disable_stutter = true; 1901 1902 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) 1903 adev->dm.dc->debug.disable_stutter = true; 1904 1905 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 1906 adev->dm.dc->debug.disable_dsc = true; 1907 1908 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) 1909 adev->dm.dc->debug.disable_clock_gate = true; 1910 1911 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH) 1912 adev->dm.dc->debug.force_subvp_mclk_switch = true; 1913 1914 if (amdgpu_dc_debug_mask & DC_ENABLE_DML2) { 1915 adev->dm.dc->debug.using_dml2 = true; 1916 adev->dm.dc->debug.using_dml21 = true; 1917 } 1918 1919 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm; 1920 1921 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ 1922 adev->dm.dc->debug.ignore_cable_id = true; 1923 1924 if (adev->dm.dc->caps.dp_hdmi21_pcon_support) 1925 DRM_INFO("DP-HDMI FRL PCON supported\n"); 1926 1927 r = dm_dmub_hw_init(adev); 1928 if (r) { 1929 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 1930 goto error; 1931 } 1932 1933 dc_hardware_init(adev->dm.dc); 1934 1935 adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc); 1936 if (!adev->dm.hpd_rx_offload_wq) { 1937 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n"); 1938 goto error; 1939 } 1940 1941 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) { 1942 struct dc_phy_addr_space_config pa_config; 1943 1944 mmhub_read_system_context(adev, &pa_config); 1945 1946 // Call the DC init_memory func 1947 dc_setup_system_context(adev->dm.dc, &pa_config); 1948 } 1949 1950 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 1951 if (!adev->dm.freesync_module) { 1952 DRM_ERROR( 1953 "amdgpu: failed to initialize freesync_module.\n"); 1954 } else 1955 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", 1956 adev->dm.freesync_module); 1957 1958 amdgpu_dm_init_color_mod(); 1959 1960 if (adev->dm.dc->caps.max_links > 0) { 1961 adev->dm.vblank_control_workqueue = 1962 create_singlethread_workqueue("dm_vblank_control_workqueue"); 1963 if (!adev->dm.vblank_control_workqueue) 1964 DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n"); 1965 } 1966 1967 if (adev->dm.dc->caps.ips_support && adev->dm.dc->config.disable_ips == DMUB_IPS_ENABLE) 1968 adev->dm.idle_workqueue = idle_create_workqueue(adev); 1969 1970 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) { 1971 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); 1972 1973 if (!adev->dm.hdcp_workqueue) 1974 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n"); 1975 else 1976 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue); 1977 1978 dc_init_callbacks(adev->dm.dc, &init_params); 1979 } 1980 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 1981 init_completion(&adev->dm.dmub_aux_transfer_done); 1982 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL); 1983 if (!adev->dm.dmub_notify) { 1984 DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify"); 1985 goto error; 1986 } 1987 1988 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq"); 1989 if (!adev->dm.delayed_hpd_wq) { 1990 DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n"); 1991 goto error; 1992 } 1993 1994 amdgpu_dm_outbox_init(adev); 1995 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY, 1996 dmub_aux_setconfig_callback, false)) { 1997 DRM_ERROR("amdgpu: fail to register dmub aux callback"); 1998 goto error; 1999 } 2000 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive. 2001 * It is expected that DMUB will resend any pending notifications at this point. Note 2002 * that hpd and hpd_irq handler registration are deferred to register_hpd_handlers() to 2003 * align legacy interface initialization sequence. Connection status will be proactivly 2004 * detected once in the amdgpu_dm_initialize_drm_device. 2005 */ 2006 dc_enable_dmub_outbox(adev->dm.dc); 2007 2008 /* DPIA trace goes to dmesg logs only if outbox is enabled */ 2009 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE) 2010 dc_dmub_srv_enable_dpia_trace(adev->dm.dc); 2011 } 2012 2013 if (amdgpu_dm_initialize_drm_device(adev)) { 2014 DRM_ERROR( 2015 "amdgpu: failed to initialize sw for display support.\n"); 2016 goto error; 2017 } 2018 2019 /* create fake encoders for MST */ 2020 dm_dp_create_fake_mst_encoders(adev); 2021 2022 /* TODO: Add_display_info? */ 2023 2024 /* TODO use dynamic cursor width */ 2025 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 2026 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 2027 2028 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { 2029 DRM_ERROR( 2030 "amdgpu: failed to initialize sw for display support.\n"); 2031 goto error; 2032 } 2033 2034 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 2035 adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev); 2036 if (!adev->dm.secure_display_ctxs) 2037 DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n"); 2038 #endif 2039 2040 DRM_DEBUG_DRIVER("KMS initialized.\n"); 2041 2042 return 0; 2043 error: 2044 amdgpu_dm_fini(adev); 2045 2046 return -EINVAL; 2047 } 2048 2049 static int amdgpu_dm_early_fini(void *handle) 2050 { 2051 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2052 2053 amdgpu_dm_audio_fini(adev); 2054 2055 return 0; 2056 } 2057 2058 static void amdgpu_dm_fini(struct amdgpu_device *adev) 2059 { 2060 int i; 2061 2062 if (adev->dm.vblank_control_workqueue) { 2063 destroy_workqueue(adev->dm.vblank_control_workqueue); 2064 adev->dm.vblank_control_workqueue = NULL; 2065 } 2066 2067 if (adev->dm.idle_workqueue) { 2068 if (adev->dm.idle_workqueue->running) { 2069 adev->dm.idle_workqueue->enable = false; 2070 flush_work(&adev->dm.idle_workqueue->work); 2071 } 2072 2073 kfree(adev->dm.idle_workqueue); 2074 adev->dm.idle_workqueue = NULL; 2075 } 2076 2077 amdgpu_dm_destroy_drm_device(&adev->dm); 2078 2079 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 2080 if (adev->dm.secure_display_ctxs) { 2081 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2082 if (adev->dm.secure_display_ctxs[i].crtc) { 2083 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work); 2084 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work); 2085 } 2086 } 2087 kfree(adev->dm.secure_display_ctxs); 2088 adev->dm.secure_display_ctxs = NULL; 2089 } 2090 #endif 2091 if (adev->dm.hdcp_workqueue) { 2092 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); 2093 adev->dm.hdcp_workqueue = NULL; 2094 } 2095 2096 if (adev->dm.dc) { 2097 dc_deinit_callbacks(adev->dm.dc); 2098 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); 2099 if (dc_enable_dmub_notifications(adev->dm.dc)) { 2100 kfree(adev->dm.dmub_notify); 2101 adev->dm.dmub_notify = NULL; 2102 destroy_workqueue(adev->dm.delayed_hpd_wq); 2103 adev->dm.delayed_hpd_wq = NULL; 2104 } 2105 } 2106 2107 if (adev->dm.dmub_bo) 2108 amdgpu_bo_free_kernel(&adev->dm.dmub_bo, 2109 &adev->dm.dmub_bo_gpu_addr, 2110 &adev->dm.dmub_bo_cpu_addr); 2111 2112 if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) { 2113 for (i = 0; i < adev->dm.dc->caps.max_links; i++) { 2114 if (adev->dm.hpd_rx_offload_wq[i].wq) { 2115 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq); 2116 adev->dm.hpd_rx_offload_wq[i].wq = NULL; 2117 } 2118 } 2119 2120 kfree(adev->dm.hpd_rx_offload_wq); 2121 adev->dm.hpd_rx_offload_wq = NULL; 2122 } 2123 2124 /* DC Destroy TODO: Replace destroy DAL */ 2125 if (adev->dm.dc) 2126 dc_destroy(&adev->dm.dc); 2127 /* 2128 * TODO: pageflip, vlank interrupt 2129 * 2130 * amdgpu_dm_irq_fini(adev); 2131 */ 2132 2133 if (adev->dm.cgs_device) { 2134 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 2135 adev->dm.cgs_device = NULL; 2136 } 2137 if (adev->dm.freesync_module) { 2138 mod_freesync_destroy(adev->dm.freesync_module); 2139 adev->dm.freesync_module = NULL; 2140 } 2141 2142 mutex_destroy(&adev->dm.audio_lock); 2143 mutex_destroy(&adev->dm.dc_lock); 2144 mutex_destroy(&adev->dm.dpia_aux_lock); 2145 } 2146 2147 static int load_dmcu_fw(struct amdgpu_device *adev) 2148 { 2149 const char *fw_name_dmcu = NULL; 2150 int r; 2151 const struct dmcu_firmware_header_v1_0 *hdr; 2152 2153 switch (adev->asic_type) { 2154 #if defined(CONFIG_DRM_AMD_DC_SI) 2155 case CHIP_TAHITI: 2156 case CHIP_PITCAIRN: 2157 case CHIP_VERDE: 2158 case CHIP_OLAND: 2159 #endif 2160 case CHIP_BONAIRE: 2161 case CHIP_HAWAII: 2162 case CHIP_KAVERI: 2163 case CHIP_KABINI: 2164 case CHIP_MULLINS: 2165 case CHIP_TONGA: 2166 case CHIP_FIJI: 2167 case CHIP_CARRIZO: 2168 case CHIP_STONEY: 2169 case CHIP_POLARIS11: 2170 case CHIP_POLARIS10: 2171 case CHIP_POLARIS12: 2172 case CHIP_VEGAM: 2173 case CHIP_VEGA10: 2174 case CHIP_VEGA12: 2175 case CHIP_VEGA20: 2176 return 0; 2177 case CHIP_NAVI12: 2178 fw_name_dmcu = FIRMWARE_NAVI12_DMCU; 2179 break; 2180 case CHIP_RAVEN: 2181 if (ASICREV_IS_PICASSO(adev->external_rev_id)) 2182 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 2183 else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) 2184 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 2185 else 2186 return 0; 2187 break; 2188 default: 2189 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2190 case IP_VERSION(2, 0, 2): 2191 case IP_VERSION(2, 0, 3): 2192 case IP_VERSION(2, 0, 0): 2193 case IP_VERSION(2, 1, 0): 2194 case IP_VERSION(3, 0, 0): 2195 case IP_VERSION(3, 0, 2): 2196 case IP_VERSION(3, 0, 3): 2197 case IP_VERSION(3, 0, 1): 2198 case IP_VERSION(3, 1, 2): 2199 case IP_VERSION(3, 1, 3): 2200 case IP_VERSION(3, 1, 4): 2201 case IP_VERSION(3, 1, 5): 2202 case IP_VERSION(3, 1, 6): 2203 case IP_VERSION(3, 2, 0): 2204 case IP_VERSION(3, 2, 1): 2205 case IP_VERSION(3, 5, 0): 2206 case IP_VERSION(3, 5, 1): 2207 case IP_VERSION(4, 0, 1): 2208 return 0; 2209 default: 2210 break; 2211 } 2212 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 2213 return -EINVAL; 2214 } 2215 2216 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2217 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); 2218 return 0; 2219 } 2220 2221 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu); 2222 if (r == -ENODEV) { 2223 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 2224 DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); 2225 adev->dm.fw_dmcu = NULL; 2226 return 0; 2227 } 2228 if (r) { 2229 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", 2230 fw_name_dmcu); 2231 amdgpu_ucode_release(&adev->dm.fw_dmcu); 2232 return r; 2233 } 2234 2235 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 2236 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 2237 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 2238 adev->firmware.fw_size += 2239 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 2240 2241 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 2242 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 2243 adev->firmware.fw_size += 2244 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 2245 2246 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 2247 2248 DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); 2249 2250 return 0; 2251 } 2252 2253 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address) 2254 { 2255 struct amdgpu_device *adev = ctx; 2256 2257 return dm_read_reg(adev->dm.dc->ctx, address); 2258 } 2259 2260 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address, 2261 uint32_t value) 2262 { 2263 struct amdgpu_device *adev = ctx; 2264 2265 return dm_write_reg(adev->dm.dc->ctx, address, value); 2266 } 2267 2268 static int dm_dmub_sw_init(struct amdgpu_device *adev) 2269 { 2270 struct dmub_srv_create_params create_params; 2271 struct dmub_srv_region_params region_params; 2272 struct dmub_srv_region_info region_info; 2273 struct dmub_srv_memory_params memory_params; 2274 struct dmub_srv_fb_info *fb_info; 2275 struct dmub_srv *dmub_srv; 2276 const struct dmcub_firmware_header_v1_0 *hdr; 2277 enum dmub_asic dmub_asic; 2278 enum dmub_status status; 2279 static enum dmub_window_memory_type window_memory_type[DMUB_WINDOW_TOTAL] = { 2280 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_0_INST_CONST 2281 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_1_STACK 2282 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_2_BSS_DATA 2283 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_3_VBIOS 2284 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_4_MAILBOX 2285 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_5_TRACEBUFF 2286 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_6_FW_STATE 2287 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_7_SCRATCH_MEM 2288 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_SHARED_STATE 2289 }; 2290 int r; 2291 2292 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2293 case IP_VERSION(2, 1, 0): 2294 dmub_asic = DMUB_ASIC_DCN21; 2295 break; 2296 case IP_VERSION(3, 0, 0): 2297 dmub_asic = DMUB_ASIC_DCN30; 2298 break; 2299 case IP_VERSION(3, 0, 1): 2300 dmub_asic = DMUB_ASIC_DCN301; 2301 break; 2302 case IP_VERSION(3, 0, 2): 2303 dmub_asic = DMUB_ASIC_DCN302; 2304 break; 2305 case IP_VERSION(3, 0, 3): 2306 dmub_asic = DMUB_ASIC_DCN303; 2307 break; 2308 case IP_VERSION(3, 1, 2): 2309 case IP_VERSION(3, 1, 3): 2310 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31; 2311 break; 2312 case IP_VERSION(3, 1, 4): 2313 dmub_asic = DMUB_ASIC_DCN314; 2314 break; 2315 case IP_VERSION(3, 1, 5): 2316 dmub_asic = DMUB_ASIC_DCN315; 2317 break; 2318 case IP_VERSION(3, 1, 6): 2319 dmub_asic = DMUB_ASIC_DCN316; 2320 break; 2321 case IP_VERSION(3, 2, 0): 2322 dmub_asic = DMUB_ASIC_DCN32; 2323 break; 2324 case IP_VERSION(3, 2, 1): 2325 dmub_asic = DMUB_ASIC_DCN321; 2326 break; 2327 case IP_VERSION(3, 5, 0): 2328 case IP_VERSION(3, 5, 1): 2329 dmub_asic = DMUB_ASIC_DCN35; 2330 break; 2331 case IP_VERSION(4, 0, 1): 2332 dmub_asic = DMUB_ASIC_DCN401; 2333 break; 2334 2335 default: 2336 /* ASIC doesn't support DMUB. */ 2337 return 0; 2338 } 2339 2340 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data; 2341 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version); 2342 2343 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2344 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id = 2345 AMDGPU_UCODE_ID_DMCUB; 2346 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = 2347 adev->dm.dmub_fw; 2348 adev->firmware.fw_size += 2349 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE); 2350 2351 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n", 2352 adev->dm.dmcub_fw_version); 2353 } 2354 2355 2356 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL); 2357 dmub_srv = adev->dm.dmub_srv; 2358 2359 if (!dmub_srv) { 2360 DRM_ERROR("Failed to allocate DMUB service!\n"); 2361 return -ENOMEM; 2362 } 2363 2364 memset(&create_params, 0, sizeof(create_params)); 2365 create_params.user_ctx = adev; 2366 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read; 2367 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write; 2368 create_params.asic = dmub_asic; 2369 2370 /* Create the DMUB service. */ 2371 status = dmub_srv_create(dmub_srv, &create_params); 2372 if (status != DMUB_STATUS_OK) { 2373 DRM_ERROR("Error creating DMUB service: %d\n", status); 2374 return -EINVAL; 2375 } 2376 2377 /* Calculate the size of all the regions for the DMUB service. */ 2378 memset(®ion_params, 0, sizeof(region_params)); 2379 2380 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 2381 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 2382 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 2383 region_params.vbios_size = adev->bios_size; 2384 region_params.fw_bss_data = region_params.bss_data_size ? 2385 adev->dm.dmub_fw->data + 2386 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 2387 le32_to_cpu(hdr->inst_const_bytes) : NULL; 2388 region_params.fw_inst_const = 2389 adev->dm.dmub_fw->data + 2390 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 2391 PSP_HEADER_BYTES; 2392 region_params.window_memory_type = window_memory_type; 2393 2394 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params, 2395 ®ion_info); 2396 2397 if (status != DMUB_STATUS_OK) { 2398 DRM_ERROR("Error calculating DMUB region info: %d\n", status); 2399 return -EINVAL; 2400 } 2401 2402 /* 2403 * Allocate a framebuffer based on the total size of all the regions. 2404 * TODO: Move this into GART. 2405 */ 2406 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE, 2407 AMDGPU_GEM_DOMAIN_VRAM | 2408 AMDGPU_GEM_DOMAIN_GTT, 2409 &adev->dm.dmub_bo, 2410 &adev->dm.dmub_bo_gpu_addr, 2411 &adev->dm.dmub_bo_cpu_addr); 2412 if (r) 2413 return r; 2414 2415 /* Rebase the regions on the framebuffer address. */ 2416 memset(&memory_params, 0, sizeof(memory_params)); 2417 memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr; 2418 memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr; 2419 memory_params.region_info = ®ion_info; 2420 memory_params.window_memory_type = window_memory_type; 2421 2422 adev->dm.dmub_fb_info = 2423 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL); 2424 fb_info = adev->dm.dmub_fb_info; 2425 2426 if (!fb_info) { 2427 DRM_ERROR( 2428 "Failed to allocate framebuffer info for DMUB service!\n"); 2429 return -ENOMEM; 2430 } 2431 2432 status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info); 2433 if (status != DMUB_STATUS_OK) { 2434 DRM_ERROR("Error calculating DMUB FB info: %d\n", status); 2435 return -EINVAL; 2436 } 2437 2438 adev->dm.bb_from_dmub = dm_dmub_get_vbios_bounding_box(adev); 2439 2440 return 0; 2441 } 2442 2443 static int dm_sw_init(void *handle) 2444 { 2445 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2446 int r; 2447 2448 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 2449 2450 if (!adev->dm.cgs_device) { 2451 DRM_ERROR("amdgpu: failed to create cgs device.\n"); 2452 return -EINVAL; 2453 } 2454 2455 /* Moved from dm init since we need to use allocations for storing bounding box data */ 2456 INIT_LIST_HEAD(&adev->dm.da_list); 2457 2458 r = dm_dmub_sw_init(adev); 2459 if (r) 2460 return r; 2461 2462 return load_dmcu_fw(adev); 2463 } 2464 2465 static int dm_sw_fini(void *handle) 2466 { 2467 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2468 2469 kfree(adev->dm.bb_from_dmub); 2470 adev->dm.bb_from_dmub = NULL; 2471 2472 kfree(adev->dm.dmub_fb_info); 2473 adev->dm.dmub_fb_info = NULL; 2474 2475 if (adev->dm.dmub_srv) { 2476 dmub_srv_destroy(adev->dm.dmub_srv); 2477 kfree(adev->dm.dmub_srv); 2478 adev->dm.dmub_srv = NULL; 2479 } 2480 2481 amdgpu_ucode_release(&adev->dm.dmub_fw); 2482 amdgpu_ucode_release(&adev->dm.fw_dmcu); 2483 2484 return 0; 2485 } 2486 2487 static int detect_mst_link_for_all_connectors(struct drm_device *dev) 2488 { 2489 struct amdgpu_dm_connector *aconnector; 2490 struct drm_connector *connector; 2491 struct drm_connector_list_iter iter; 2492 int ret = 0; 2493 2494 drm_connector_list_iter_begin(dev, &iter); 2495 drm_for_each_connector_iter(connector, &iter) { 2496 2497 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 2498 continue; 2499 2500 aconnector = to_amdgpu_dm_connector(connector); 2501 if (aconnector->dc_link->type == dc_connection_mst_branch && 2502 aconnector->mst_mgr.aux) { 2503 drm_dbg_kms(dev, "DM_MST: starting TM on aconnector: %p [id: %d]\n", 2504 aconnector, 2505 aconnector->base.base.id); 2506 2507 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 2508 if (ret < 0) { 2509 drm_err(dev, "DM_MST: Failed to start MST\n"); 2510 aconnector->dc_link->type = 2511 dc_connection_single; 2512 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, 2513 aconnector->dc_link); 2514 break; 2515 } 2516 } 2517 } 2518 drm_connector_list_iter_end(&iter); 2519 2520 return ret; 2521 } 2522 2523 static int dm_late_init(void *handle) 2524 { 2525 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2526 2527 struct dmcu_iram_parameters params; 2528 unsigned int linear_lut[16]; 2529 int i; 2530 struct dmcu *dmcu = NULL; 2531 2532 dmcu = adev->dm.dc->res_pool->dmcu; 2533 2534 for (i = 0; i < 16; i++) 2535 linear_lut[i] = 0xFFFF * i / 15; 2536 2537 params.set = 0; 2538 params.backlight_ramping_override = false; 2539 params.backlight_ramping_start = 0xCCCC; 2540 params.backlight_ramping_reduction = 0xCCCCCCCC; 2541 params.backlight_lut_array_size = 16; 2542 params.backlight_lut_array = linear_lut; 2543 2544 /* Min backlight level after ABM reduction, Don't allow below 1% 2545 * 0xFFFF x 0.01 = 0x28F 2546 */ 2547 params.min_abm_backlight = 0x28F; 2548 /* In the case where abm is implemented on dmcub, 2549 * dmcu object will be null. 2550 * ABM 2.4 and up are implemented on dmcub. 2551 */ 2552 if (dmcu) { 2553 if (!dmcu_load_iram(dmcu, params)) 2554 return -EINVAL; 2555 } else if (adev->dm.dc->ctx->dmub_srv) { 2556 struct dc_link *edp_links[MAX_NUM_EDP]; 2557 int edp_num; 2558 2559 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num); 2560 for (i = 0; i < edp_num; i++) { 2561 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) 2562 return -EINVAL; 2563 } 2564 } 2565 2566 return detect_mst_link_for_all_connectors(adev_to_drm(adev)); 2567 } 2568 2569 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) 2570 { 2571 u8 buf[UUID_SIZE]; 2572 guid_t guid; 2573 int ret; 2574 2575 mutex_lock(&mgr->lock); 2576 if (!mgr->mst_primary) 2577 goto out_fail; 2578 2579 if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) { 2580 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 2581 goto out_fail; 2582 } 2583 2584 ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 2585 DP_MST_EN | 2586 DP_UP_REQ_EN | 2587 DP_UPSTREAM_IS_SRC); 2588 if (ret < 0) { 2589 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n"); 2590 goto out_fail; 2591 } 2592 2593 /* Some hubs forget their guids after they resume */ 2594 ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, buf, sizeof(buf)); 2595 if (ret != sizeof(buf)) { 2596 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 2597 goto out_fail; 2598 } 2599 2600 import_guid(&guid, buf); 2601 2602 if (guid_is_null(&guid)) { 2603 guid_gen(&guid); 2604 export_guid(buf, &guid); 2605 2606 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, buf, sizeof(buf)); 2607 2608 if (ret != sizeof(buf)) { 2609 drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n"); 2610 goto out_fail; 2611 } 2612 } 2613 2614 guid_copy(&mgr->mst_primary->guid, &guid); 2615 2616 out_fail: 2617 mutex_unlock(&mgr->lock); 2618 } 2619 2620 static void s3_handle_mst(struct drm_device *dev, bool suspend) 2621 { 2622 struct amdgpu_dm_connector *aconnector; 2623 struct drm_connector *connector; 2624 struct drm_connector_list_iter iter; 2625 struct drm_dp_mst_topology_mgr *mgr; 2626 2627 drm_connector_list_iter_begin(dev, &iter); 2628 drm_for_each_connector_iter(connector, &iter) { 2629 2630 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 2631 continue; 2632 2633 aconnector = to_amdgpu_dm_connector(connector); 2634 if (aconnector->dc_link->type != dc_connection_mst_branch || 2635 aconnector->mst_root) 2636 continue; 2637 2638 mgr = &aconnector->mst_mgr; 2639 2640 if (suspend) { 2641 drm_dp_mst_topology_mgr_suspend(mgr); 2642 } else { 2643 /* if extended timeout is supported in hardware, 2644 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer 2645 * CTS 4.2.1.1 regression introduced by CTS specs requirement update. 2646 */ 2647 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); 2648 if (!dp_is_lttpr_present(aconnector->dc_link)) 2649 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); 2650 2651 /* TODO: move resume_mst_branch_status() into drm mst resume again 2652 * once topology probing work is pulled out from mst resume into mst 2653 * resume 2nd step. mst resume 2nd step should be called after old 2654 * state getting restored (i.e. drm_atomic_helper_resume()). 2655 */ 2656 resume_mst_branch_status(mgr); 2657 } 2658 } 2659 drm_connector_list_iter_end(&iter); 2660 } 2661 2662 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) 2663 { 2664 int ret = 0; 2665 2666 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends 2667 * on window driver dc implementation. 2668 * For Navi1x, clock settings of dcn watermarks are fixed. the settings 2669 * should be passed to smu during boot up and resume from s3. 2670 * boot up: dc calculate dcn watermark clock settings within dc_create, 2671 * dcn20_resource_construct 2672 * then call pplib functions below to pass the settings to smu: 2673 * smu_set_watermarks_for_clock_ranges 2674 * smu_set_watermarks_table 2675 * navi10_set_watermarks_table 2676 * smu_write_watermarks_table 2677 * 2678 * For Renoir, clock settings of dcn watermark are also fixed values. 2679 * dc has implemented different flow for window driver: 2680 * dc_hardware_init / dc_set_power_state 2681 * dcn10_init_hw 2682 * notify_wm_ranges 2683 * set_wm_ranges 2684 * -- Linux 2685 * smu_set_watermarks_for_clock_ranges 2686 * renoir_set_watermarks_table 2687 * smu_write_watermarks_table 2688 * 2689 * For Linux, 2690 * dc_hardware_init -> amdgpu_dm_init 2691 * dc_set_power_state --> dm_resume 2692 * 2693 * therefore, this function apply to navi10/12/14 but not Renoir 2694 * * 2695 */ 2696 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2697 case IP_VERSION(2, 0, 2): 2698 case IP_VERSION(2, 0, 0): 2699 break; 2700 default: 2701 return 0; 2702 } 2703 2704 ret = amdgpu_dpm_write_watermarks_table(adev); 2705 if (ret) { 2706 DRM_ERROR("Failed to update WMTABLE!\n"); 2707 return ret; 2708 } 2709 2710 return 0; 2711 } 2712 2713 /** 2714 * dm_hw_init() - Initialize DC device 2715 * @handle: The base driver device containing the amdgpu_dm device. 2716 * 2717 * Initialize the &struct amdgpu_display_manager device. This involves calling 2718 * the initializers of each DM component, then populating the struct with them. 2719 * 2720 * Although the function implies hardware initialization, both hardware and 2721 * software are initialized here. Splitting them out to their relevant init 2722 * hooks is a future TODO item. 2723 * 2724 * Some notable things that are initialized here: 2725 * 2726 * - Display Core, both software and hardware 2727 * - DC modules that we need (freesync and color management) 2728 * - DRM software states 2729 * - Interrupt sources and handlers 2730 * - Vblank support 2731 * - Debug FS entries, if enabled 2732 */ 2733 static int dm_hw_init(void *handle) 2734 { 2735 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2736 int r; 2737 2738 /* Create DAL display manager */ 2739 r = amdgpu_dm_init(adev); 2740 if (r) 2741 return r; 2742 amdgpu_dm_hpd_init(adev); 2743 2744 return 0; 2745 } 2746 2747 /** 2748 * dm_hw_fini() - Teardown DC device 2749 * @handle: The base driver device containing the amdgpu_dm device. 2750 * 2751 * Teardown components within &struct amdgpu_display_manager that require 2752 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 2753 * were loaded. Also flush IRQ workqueues and disable them. 2754 */ 2755 static int dm_hw_fini(void *handle) 2756 { 2757 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2758 2759 amdgpu_dm_hpd_fini(adev); 2760 2761 amdgpu_dm_irq_fini(adev); 2762 amdgpu_dm_fini(adev); 2763 return 0; 2764 } 2765 2766 2767 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, 2768 struct dc_state *state, bool enable) 2769 { 2770 enum dc_irq_source irq_source; 2771 struct amdgpu_crtc *acrtc; 2772 int rc = -EBUSY; 2773 int i = 0; 2774 2775 for (i = 0; i < state->stream_count; i++) { 2776 acrtc = get_crtc_by_otg_inst( 2777 adev, state->stream_status[i].primary_otg_inst); 2778 2779 if (acrtc && state->stream_status[i].plane_count != 0) { 2780 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; 2781 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 2782 if (rc) 2783 DRM_WARN("Failed to %s pflip interrupts\n", 2784 enable ? "enable" : "disable"); 2785 2786 if (enable) { 2787 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state))) 2788 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true); 2789 } else 2790 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false); 2791 2792 if (rc) 2793 DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis"); 2794 2795 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 2796 /* During gpu-reset we disable and then enable vblank irq, so 2797 * don't use amdgpu_irq_get/put() to avoid refcount change. 2798 */ 2799 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable)) 2800 DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis"); 2801 } 2802 } 2803 2804 } 2805 2806 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) 2807 { 2808 struct dc_state *context = NULL; 2809 enum dc_status res = DC_ERROR_UNEXPECTED; 2810 int i; 2811 struct dc_stream_state *del_streams[MAX_PIPES]; 2812 int del_streams_count = 0; 2813 struct dc_commit_streams_params params = {}; 2814 2815 memset(del_streams, 0, sizeof(del_streams)); 2816 2817 context = dc_state_create_current_copy(dc); 2818 if (context == NULL) 2819 goto context_alloc_fail; 2820 2821 /* First remove from context all streams */ 2822 for (i = 0; i < context->stream_count; i++) { 2823 struct dc_stream_state *stream = context->streams[i]; 2824 2825 del_streams[del_streams_count++] = stream; 2826 } 2827 2828 /* Remove all planes for removed streams and then remove the streams */ 2829 for (i = 0; i < del_streams_count; i++) { 2830 if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) { 2831 res = DC_FAIL_DETACH_SURFACES; 2832 goto fail; 2833 } 2834 2835 res = dc_state_remove_stream(dc, context, del_streams[i]); 2836 if (res != DC_OK) 2837 goto fail; 2838 } 2839 2840 params.streams = context->streams; 2841 params.stream_count = context->stream_count; 2842 res = dc_commit_streams(dc, ¶ms); 2843 2844 fail: 2845 dc_state_release(context); 2846 2847 context_alloc_fail: 2848 return res; 2849 } 2850 2851 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm) 2852 { 2853 int i; 2854 2855 if (dm->hpd_rx_offload_wq) { 2856 for (i = 0; i < dm->dc->caps.max_links; i++) 2857 flush_workqueue(dm->hpd_rx_offload_wq[i].wq); 2858 } 2859 } 2860 2861 static int dm_suspend(void *handle) 2862 { 2863 struct amdgpu_device *adev = handle; 2864 struct amdgpu_display_manager *dm = &adev->dm; 2865 int ret = 0; 2866 2867 if (amdgpu_in_reset(adev)) { 2868 mutex_lock(&dm->dc_lock); 2869 2870 dc_allow_idle_optimizations(adev->dm.dc, false); 2871 2872 dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state); 2873 2874 if (dm->cached_dc_state) 2875 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); 2876 2877 amdgpu_dm_commit_zero_streams(dm->dc); 2878 2879 amdgpu_dm_irq_suspend(adev); 2880 2881 hpd_rx_irq_work_suspend(dm); 2882 2883 return ret; 2884 } 2885 2886 WARN_ON(adev->dm.cached_state); 2887 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); 2888 if (IS_ERR(adev->dm.cached_state)) 2889 return PTR_ERR(adev->dm.cached_state); 2890 2891 s3_handle_mst(adev_to_drm(adev), true); 2892 2893 amdgpu_dm_irq_suspend(adev); 2894 2895 hpd_rx_irq_work_suspend(dm); 2896 2897 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 2898 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3); 2899 2900 return 0; 2901 } 2902 2903 struct drm_connector * 2904 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 2905 struct drm_crtc *crtc) 2906 { 2907 u32 i; 2908 struct drm_connector_state *new_con_state; 2909 struct drm_connector *connector; 2910 struct drm_crtc *crtc_from_state; 2911 2912 for_each_new_connector_in_state(state, connector, new_con_state, i) { 2913 crtc_from_state = new_con_state->crtc; 2914 2915 if (crtc_from_state == crtc) 2916 return connector; 2917 } 2918 2919 return NULL; 2920 } 2921 2922 static void emulated_link_detect(struct dc_link *link) 2923 { 2924 struct dc_sink_init_data sink_init_data = { 0 }; 2925 struct display_sink_capability sink_caps = { 0 }; 2926 enum dc_edid_status edid_status; 2927 struct dc_context *dc_ctx = link->ctx; 2928 struct drm_device *dev = adev_to_drm(dc_ctx->driver_context); 2929 struct dc_sink *sink = NULL; 2930 struct dc_sink *prev_sink = NULL; 2931 2932 link->type = dc_connection_none; 2933 prev_sink = link->local_sink; 2934 2935 if (prev_sink) 2936 dc_sink_release(prev_sink); 2937 2938 switch (link->connector_signal) { 2939 case SIGNAL_TYPE_HDMI_TYPE_A: { 2940 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2941 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 2942 break; 2943 } 2944 2945 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 2946 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2947 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 2948 break; 2949 } 2950 2951 case SIGNAL_TYPE_DVI_DUAL_LINK: { 2952 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2953 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 2954 break; 2955 } 2956 2957 case SIGNAL_TYPE_LVDS: { 2958 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2959 sink_caps.signal = SIGNAL_TYPE_LVDS; 2960 break; 2961 } 2962 2963 case SIGNAL_TYPE_EDP: { 2964 sink_caps.transaction_type = 2965 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 2966 sink_caps.signal = SIGNAL_TYPE_EDP; 2967 break; 2968 } 2969 2970 case SIGNAL_TYPE_DISPLAY_PORT: { 2971 sink_caps.transaction_type = 2972 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 2973 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 2974 break; 2975 } 2976 2977 default: 2978 drm_err(dev, "Invalid connector type! signal:%d\n", 2979 link->connector_signal); 2980 return; 2981 } 2982 2983 sink_init_data.link = link; 2984 sink_init_data.sink_signal = sink_caps.signal; 2985 2986 sink = dc_sink_create(&sink_init_data); 2987 if (!sink) { 2988 drm_err(dev, "Failed to create sink!\n"); 2989 return; 2990 } 2991 2992 /* dc_sink_create returns a new reference */ 2993 link->local_sink = sink; 2994 2995 edid_status = dm_helpers_read_local_edid( 2996 link->ctx, 2997 link, 2998 sink); 2999 3000 if (edid_status != EDID_OK) 3001 drm_err(dev, "Failed to read EDID\n"); 3002 3003 } 3004 3005 static void dm_gpureset_commit_state(struct dc_state *dc_state, 3006 struct amdgpu_display_manager *dm) 3007 { 3008 struct { 3009 struct dc_surface_update surface_updates[MAX_SURFACES]; 3010 struct dc_plane_info plane_infos[MAX_SURFACES]; 3011 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 3012 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 3013 struct dc_stream_update stream_update; 3014 } *bundle; 3015 int k, m; 3016 3017 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 3018 3019 if (!bundle) { 3020 drm_err(dm->ddev, "Failed to allocate update bundle\n"); 3021 goto cleanup; 3022 } 3023 3024 for (k = 0; k < dc_state->stream_count; k++) { 3025 bundle->stream_update.stream = dc_state->streams[k]; 3026 3027 for (m = 0; m < dc_state->stream_status->plane_count; m++) { 3028 bundle->surface_updates[m].surface = 3029 dc_state->stream_status->plane_states[m]; 3030 bundle->surface_updates[m].surface->force_full_update = 3031 true; 3032 } 3033 3034 update_planes_and_stream_adapter(dm->dc, 3035 UPDATE_TYPE_FULL, 3036 dc_state->stream_status->plane_count, 3037 dc_state->streams[k], 3038 &bundle->stream_update, 3039 bundle->surface_updates); 3040 } 3041 3042 cleanup: 3043 kfree(bundle); 3044 } 3045 3046 static int dm_resume(void *handle) 3047 { 3048 struct amdgpu_device *adev = handle; 3049 struct drm_device *ddev = adev_to_drm(adev); 3050 struct amdgpu_display_manager *dm = &adev->dm; 3051 struct amdgpu_dm_connector *aconnector; 3052 struct drm_connector *connector; 3053 struct drm_connector_list_iter iter; 3054 struct drm_crtc *crtc; 3055 struct drm_crtc_state *new_crtc_state; 3056 struct dm_crtc_state *dm_new_crtc_state; 3057 struct drm_plane *plane; 3058 struct drm_plane_state *new_plane_state; 3059 struct dm_plane_state *dm_new_plane_state; 3060 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 3061 enum dc_connection_type new_connection_type = dc_connection_none; 3062 struct dc_state *dc_state; 3063 int i, r, j, ret; 3064 bool need_hotplug = false; 3065 struct dc_commit_streams_params commit_params = {}; 3066 3067 if (dm->dc->caps.ips_support) { 3068 dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false); 3069 } 3070 3071 if (amdgpu_in_reset(adev)) { 3072 dc_state = dm->cached_dc_state; 3073 3074 /* 3075 * The dc->current_state is backed up into dm->cached_dc_state 3076 * before we commit 0 streams. 3077 * 3078 * DC will clear link encoder assignments on the real state 3079 * but the changes won't propagate over to the copy we made 3080 * before the 0 streams commit. 3081 * 3082 * DC expects that link encoder assignments are *not* valid 3083 * when committing a state, so as a workaround we can copy 3084 * off of the current state. 3085 * 3086 * We lose the previous assignments, but we had already 3087 * commit 0 streams anyway. 3088 */ 3089 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state); 3090 3091 r = dm_dmub_hw_init(adev); 3092 if (r) 3093 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 3094 3095 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 3096 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 3097 3098 dc_resume(dm->dc); 3099 3100 amdgpu_dm_irq_resume_early(adev); 3101 3102 for (i = 0; i < dc_state->stream_count; i++) { 3103 dc_state->streams[i]->mode_changed = true; 3104 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { 3105 dc_state->stream_status[i].plane_states[j]->update_flags.raw 3106 = 0xffffffff; 3107 } 3108 } 3109 3110 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 3111 amdgpu_dm_outbox_init(adev); 3112 dc_enable_dmub_outbox(adev->dm.dc); 3113 } 3114 3115 commit_params.streams = dc_state->streams; 3116 commit_params.stream_count = dc_state->stream_count; 3117 dc_exit_ips_for_hw_access(dm->dc); 3118 WARN_ON(!dc_commit_streams(dm->dc, &commit_params)); 3119 3120 dm_gpureset_commit_state(dm->cached_dc_state, dm); 3121 3122 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); 3123 3124 dc_state_release(dm->cached_dc_state); 3125 dm->cached_dc_state = NULL; 3126 3127 amdgpu_dm_irq_resume_late(adev); 3128 3129 mutex_unlock(&dm->dc_lock); 3130 3131 return 0; 3132 } 3133 /* Recreate dc_state - DC invalidates it when setting power state to S3. */ 3134 dc_state_release(dm_state->context); 3135 dm_state->context = dc_state_create(dm->dc, NULL); 3136 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ 3137 3138 /* Before powering on DC we need to re-initialize DMUB. */ 3139 dm_dmub_hw_resume(adev); 3140 3141 /* Re-enable outbox interrupts for DPIA. */ 3142 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 3143 amdgpu_dm_outbox_init(adev); 3144 dc_enable_dmub_outbox(adev->dm.dc); 3145 } 3146 3147 /* power on hardware */ 3148 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 3149 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 3150 3151 /* program HPD filter */ 3152 dc_resume(dm->dc); 3153 3154 /* 3155 * early enable HPD Rx IRQ, should be done before set mode as short 3156 * pulse interrupts are used for MST 3157 */ 3158 amdgpu_dm_irq_resume_early(adev); 3159 3160 /* On resume we need to rewrite the MSTM control bits to enable MST*/ 3161 s3_handle_mst(ddev, false); 3162 3163 /* Do detection*/ 3164 drm_connector_list_iter_begin(ddev, &iter); 3165 drm_for_each_connector_iter(connector, &iter) { 3166 3167 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 3168 continue; 3169 3170 aconnector = to_amdgpu_dm_connector(connector); 3171 3172 if (!aconnector->dc_link) 3173 continue; 3174 3175 /* 3176 * this is the case when traversing through already created end sink 3177 * MST connectors, should be skipped 3178 */ 3179 if (aconnector->mst_root) 3180 continue; 3181 3182 mutex_lock(&aconnector->hpd_lock); 3183 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) 3184 DRM_ERROR("KMS: Failed to detect connector\n"); 3185 3186 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3187 emulated_link_detect(aconnector->dc_link); 3188 } else { 3189 mutex_lock(&dm->dc_lock); 3190 dc_exit_ips_for_hw_access(dm->dc); 3191 dc_link_detect(aconnector->dc_link, DETECT_REASON_RESUMEFROMS3S4); 3192 mutex_unlock(&dm->dc_lock); 3193 } 3194 3195 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 3196 aconnector->fake_enable = false; 3197 3198 if (aconnector->dc_sink) 3199 dc_sink_release(aconnector->dc_sink); 3200 aconnector->dc_sink = NULL; 3201 amdgpu_dm_update_connector_after_detect(aconnector); 3202 mutex_unlock(&aconnector->hpd_lock); 3203 } 3204 drm_connector_list_iter_end(&iter); 3205 3206 /* Force mode set in atomic commit */ 3207 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) 3208 new_crtc_state->active_changed = true; 3209 3210 /* 3211 * atomic_check is expected to create the dc states. We need to release 3212 * them here, since they were duplicated as part of the suspend 3213 * procedure. 3214 */ 3215 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 3216 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 3217 if (dm_new_crtc_state->stream) { 3218 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 3219 dc_stream_release(dm_new_crtc_state->stream); 3220 dm_new_crtc_state->stream = NULL; 3221 } 3222 dm_new_crtc_state->base.color_mgmt_changed = true; 3223 } 3224 3225 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 3226 dm_new_plane_state = to_dm_plane_state(new_plane_state); 3227 if (dm_new_plane_state->dc_state) { 3228 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 3229 dc_plane_state_release(dm_new_plane_state->dc_state); 3230 dm_new_plane_state->dc_state = NULL; 3231 } 3232 } 3233 3234 drm_atomic_helper_resume(ddev, dm->cached_state); 3235 3236 dm->cached_state = NULL; 3237 3238 /* Do mst topology probing after resuming cached state*/ 3239 drm_connector_list_iter_begin(ddev, &iter); 3240 drm_for_each_connector_iter(connector, &iter) { 3241 3242 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 3243 continue; 3244 3245 aconnector = to_amdgpu_dm_connector(connector); 3246 if (aconnector->dc_link->type != dc_connection_mst_branch || 3247 aconnector->mst_root) 3248 continue; 3249 3250 ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true); 3251 3252 if (ret < 0) { 3253 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, 3254 aconnector->dc_link); 3255 need_hotplug = true; 3256 } 3257 } 3258 drm_connector_list_iter_end(&iter); 3259 3260 if (need_hotplug) 3261 drm_kms_helper_hotplug_event(ddev); 3262 3263 amdgpu_dm_irq_resume_late(adev); 3264 3265 amdgpu_dm_smu_write_watermarks_table(adev); 3266 3267 return 0; 3268 } 3269 3270 /** 3271 * DOC: DM Lifecycle 3272 * 3273 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 3274 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 3275 * the base driver's device list to be initialized and torn down accordingly. 3276 * 3277 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 3278 */ 3279 3280 static const struct amd_ip_funcs amdgpu_dm_funcs = { 3281 .name = "dm", 3282 .early_init = dm_early_init, 3283 .late_init = dm_late_init, 3284 .sw_init = dm_sw_init, 3285 .sw_fini = dm_sw_fini, 3286 .early_fini = amdgpu_dm_early_fini, 3287 .hw_init = dm_hw_init, 3288 .hw_fini = dm_hw_fini, 3289 .suspend = dm_suspend, 3290 .resume = dm_resume, 3291 .is_idle = dm_is_idle, 3292 .wait_for_idle = dm_wait_for_idle, 3293 .check_soft_reset = dm_check_soft_reset, 3294 .soft_reset = dm_soft_reset, 3295 .set_clockgating_state = dm_set_clockgating_state, 3296 .set_powergating_state = dm_set_powergating_state, 3297 .dump_ip_state = NULL, 3298 .print_ip_state = NULL, 3299 }; 3300 3301 const struct amdgpu_ip_block_version dm_ip_block = { 3302 .type = AMD_IP_BLOCK_TYPE_DCE, 3303 .major = 1, 3304 .minor = 0, 3305 .rev = 0, 3306 .funcs = &amdgpu_dm_funcs, 3307 }; 3308 3309 3310 /** 3311 * DOC: atomic 3312 * 3313 * *WIP* 3314 */ 3315 3316 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 3317 .fb_create = amdgpu_display_user_framebuffer_create, 3318 .get_format_info = amdgpu_dm_plane_get_format_info, 3319 .atomic_check = amdgpu_dm_atomic_check, 3320 .atomic_commit = drm_atomic_helper_commit, 3321 }; 3322 3323 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 3324 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, 3325 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, 3326 }; 3327 3328 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) 3329 { 3330 struct amdgpu_dm_backlight_caps *caps; 3331 struct drm_connector *conn_base; 3332 struct amdgpu_device *adev; 3333 struct drm_luminance_range_info *luminance_range; 3334 3335 if (aconnector->bl_idx == -1 || 3336 aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP) 3337 return; 3338 3339 conn_base = &aconnector->base; 3340 adev = drm_to_adev(conn_base->dev); 3341 3342 caps = &adev->dm.backlight_caps[aconnector->bl_idx]; 3343 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; 3344 caps->aux_support = false; 3345 3346 if (caps->ext_caps->bits.oled == 1 3347 /* 3348 * || 3349 * caps->ext_caps->bits.sdr_aux_backlight_control == 1 || 3350 * caps->ext_caps->bits.hdr_aux_backlight_control == 1 3351 */) 3352 caps->aux_support = true; 3353 3354 if (amdgpu_backlight == 0) 3355 caps->aux_support = false; 3356 else if (amdgpu_backlight == 1) 3357 caps->aux_support = true; 3358 3359 luminance_range = &conn_base->display_info.luminance_range; 3360 3361 if (luminance_range->max_luminance) { 3362 caps->aux_min_input_signal = luminance_range->min_luminance; 3363 caps->aux_max_input_signal = luminance_range->max_luminance; 3364 } else { 3365 caps->aux_min_input_signal = 0; 3366 caps->aux_max_input_signal = 512; 3367 } 3368 } 3369 3370 void amdgpu_dm_update_connector_after_detect( 3371 struct amdgpu_dm_connector *aconnector) 3372 { 3373 struct drm_connector *connector = &aconnector->base; 3374 struct drm_device *dev = connector->dev; 3375 struct dc_sink *sink; 3376 3377 /* MST handled by drm_mst framework */ 3378 if (aconnector->mst_mgr.mst_state == true) 3379 return; 3380 3381 sink = aconnector->dc_link->local_sink; 3382 if (sink) 3383 dc_sink_retain(sink); 3384 3385 /* 3386 * Edid mgmt connector gets first update only in mode_valid hook and then 3387 * the connector sink is set to either fake or physical sink depends on link status. 3388 * Skip if already done during boot. 3389 */ 3390 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED 3391 && aconnector->dc_em_sink) { 3392 3393 /* 3394 * For S3 resume with headless use eml_sink to fake stream 3395 * because on resume connector->sink is set to NULL 3396 */ 3397 mutex_lock(&dev->mode_config.mutex); 3398 3399 if (sink) { 3400 if (aconnector->dc_sink) { 3401 amdgpu_dm_update_freesync_caps(connector, NULL); 3402 /* 3403 * retain and release below are used to 3404 * bump up refcount for sink because the link doesn't point 3405 * to it anymore after disconnect, so on next crtc to connector 3406 * reshuffle by UMD we will get into unwanted dc_sink release 3407 */ 3408 dc_sink_release(aconnector->dc_sink); 3409 } 3410 aconnector->dc_sink = sink; 3411 dc_sink_retain(aconnector->dc_sink); 3412 amdgpu_dm_update_freesync_caps(connector, 3413 aconnector->edid); 3414 } else { 3415 amdgpu_dm_update_freesync_caps(connector, NULL); 3416 if (!aconnector->dc_sink) { 3417 aconnector->dc_sink = aconnector->dc_em_sink; 3418 dc_sink_retain(aconnector->dc_sink); 3419 } 3420 } 3421 3422 mutex_unlock(&dev->mode_config.mutex); 3423 3424 if (sink) 3425 dc_sink_release(sink); 3426 return; 3427 } 3428 3429 /* 3430 * TODO: temporary guard to look for proper fix 3431 * if this sink is MST sink, we should not do anything 3432 */ 3433 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 3434 dc_sink_release(sink); 3435 return; 3436 } 3437 3438 if (aconnector->dc_sink == sink) { 3439 /* 3440 * We got a DP short pulse (Link Loss, DP CTS, etc...). 3441 * Do nothing!! 3442 */ 3443 drm_dbg_kms(dev, "DCHPD: connector_id=%d: dc_sink didn't change.\n", 3444 aconnector->connector_id); 3445 if (sink) 3446 dc_sink_release(sink); 3447 return; 3448 } 3449 3450 drm_dbg_kms(dev, "DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 3451 aconnector->connector_id, aconnector->dc_sink, sink); 3452 3453 mutex_lock(&dev->mode_config.mutex); 3454 3455 /* 3456 * 1. Update status of the drm connector 3457 * 2. Send an event and let userspace tell us what to do 3458 */ 3459 if (sink) { 3460 /* 3461 * TODO: check if we still need the S3 mode update workaround. 3462 * If yes, put it here. 3463 */ 3464 if (aconnector->dc_sink) { 3465 amdgpu_dm_update_freesync_caps(connector, NULL); 3466 dc_sink_release(aconnector->dc_sink); 3467 } 3468 3469 aconnector->dc_sink = sink; 3470 dc_sink_retain(aconnector->dc_sink); 3471 if (sink->dc_edid.length == 0) { 3472 aconnector->edid = NULL; 3473 if (aconnector->dc_link->aux_mode) { 3474 drm_dp_cec_unset_edid( 3475 &aconnector->dm_dp_aux.aux); 3476 } 3477 } else { 3478 aconnector->edid = 3479 (struct edid *)sink->dc_edid.raw_edid; 3480 3481 if (aconnector->dc_link->aux_mode) 3482 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, 3483 aconnector->edid); 3484 } 3485 3486 if (!aconnector->timing_requested) { 3487 aconnector->timing_requested = 3488 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL); 3489 if (!aconnector->timing_requested) 3490 drm_err(dev, 3491 "failed to create aconnector->requested_timing\n"); 3492 } 3493 3494 drm_connector_update_edid_property(connector, aconnector->edid); 3495 amdgpu_dm_update_freesync_caps(connector, aconnector->edid); 3496 update_connector_ext_caps(aconnector); 3497 } else { 3498 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 3499 amdgpu_dm_update_freesync_caps(connector, NULL); 3500 drm_connector_update_edid_property(connector, NULL); 3501 aconnector->num_modes = 0; 3502 dc_sink_release(aconnector->dc_sink); 3503 aconnector->dc_sink = NULL; 3504 aconnector->edid = NULL; 3505 kfree(aconnector->timing_requested); 3506 aconnector->timing_requested = NULL; 3507 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ 3508 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 3509 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3510 } 3511 3512 mutex_unlock(&dev->mode_config.mutex); 3513 3514 update_subconnector_property(aconnector); 3515 3516 if (sink) 3517 dc_sink_release(sink); 3518 } 3519 3520 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) 3521 { 3522 struct drm_connector *connector = &aconnector->base; 3523 struct drm_device *dev = connector->dev; 3524 enum dc_connection_type new_connection_type = dc_connection_none; 3525 struct amdgpu_device *adev = drm_to_adev(dev); 3526 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 3527 struct dc *dc = aconnector->dc_link->ctx->dc; 3528 bool ret = false; 3529 3530 if (adev->dm.disable_hpd_irq) 3531 return; 3532 3533 /* 3534 * In case of failure or MST no need to update connector status or notify the OS 3535 * since (for MST case) MST does this in its own context. 3536 */ 3537 mutex_lock(&aconnector->hpd_lock); 3538 3539 if (adev->dm.hdcp_workqueue) { 3540 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 3541 dm_con_state->update_hdcp = true; 3542 } 3543 if (aconnector->fake_enable) 3544 aconnector->fake_enable = false; 3545 3546 aconnector->timing_changed = false; 3547 3548 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) 3549 DRM_ERROR("KMS: Failed to detect connector\n"); 3550 3551 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3552 emulated_link_detect(aconnector->dc_link); 3553 3554 drm_modeset_lock_all(dev); 3555 dm_restore_drm_connector_state(dev, connector); 3556 drm_modeset_unlock_all(dev); 3557 3558 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 3559 drm_kms_helper_connector_hotplug_event(connector); 3560 } else { 3561 mutex_lock(&adev->dm.dc_lock); 3562 dc_exit_ips_for_hw_access(dc); 3563 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3564 mutex_unlock(&adev->dm.dc_lock); 3565 if (ret) { 3566 amdgpu_dm_update_connector_after_detect(aconnector); 3567 3568 drm_modeset_lock_all(dev); 3569 dm_restore_drm_connector_state(dev, connector); 3570 drm_modeset_unlock_all(dev); 3571 3572 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 3573 drm_kms_helper_connector_hotplug_event(connector); 3574 } 3575 } 3576 mutex_unlock(&aconnector->hpd_lock); 3577 3578 } 3579 3580 static void handle_hpd_irq(void *param) 3581 { 3582 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 3583 3584 handle_hpd_irq_helper(aconnector); 3585 3586 } 3587 3588 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq, 3589 union hpd_irq_data hpd_irq_data) 3590 { 3591 struct hpd_rx_irq_offload_work *offload_work = 3592 kzalloc(sizeof(*offload_work), GFP_KERNEL); 3593 3594 if (!offload_work) { 3595 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n"); 3596 return; 3597 } 3598 3599 INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work); 3600 offload_work->data = hpd_irq_data; 3601 offload_work->offload_wq = offload_wq; 3602 3603 queue_work(offload_wq->wq, &offload_work->work); 3604 DRM_DEBUG_KMS("queue work to handle hpd_rx offload work"); 3605 } 3606 3607 static void handle_hpd_rx_irq(void *param) 3608 { 3609 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 3610 struct drm_connector *connector = &aconnector->base; 3611 struct drm_device *dev = connector->dev; 3612 struct dc_link *dc_link = aconnector->dc_link; 3613 bool is_mst_root_connector = aconnector->mst_mgr.mst_state; 3614 bool result = false; 3615 enum dc_connection_type new_connection_type = dc_connection_none; 3616 struct amdgpu_device *adev = drm_to_adev(dev); 3617 union hpd_irq_data hpd_irq_data; 3618 bool link_loss = false; 3619 bool has_left_work = false; 3620 int idx = dc_link->link_index; 3621 struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx]; 3622 struct dc *dc = aconnector->dc_link->ctx->dc; 3623 3624 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data)); 3625 3626 if (adev->dm.disable_hpd_irq) 3627 return; 3628 3629 /* 3630 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio 3631 * conflict, after implement i2c helper, this mutex should be 3632 * retired. 3633 */ 3634 mutex_lock(&aconnector->hpd_lock); 3635 3636 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, 3637 &link_loss, true, &has_left_work); 3638 3639 if (!has_left_work) 3640 goto out; 3641 3642 if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) { 3643 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3644 goto out; 3645 } 3646 3647 if (dc_link_dp_allow_hpd_rx_irq(dc_link)) { 3648 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || 3649 hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { 3650 bool skip = false; 3651 3652 /* 3653 * DOWN_REP_MSG_RDY is also handled by polling method 3654 * mgr->cbs->poll_hpd_irq() 3655 */ 3656 spin_lock(&offload_wq->offload_lock); 3657 skip = offload_wq->is_handling_mst_msg_rdy_event; 3658 3659 if (!skip) 3660 offload_wq->is_handling_mst_msg_rdy_event = true; 3661 3662 spin_unlock(&offload_wq->offload_lock); 3663 3664 if (!skip) 3665 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3666 3667 goto out; 3668 } 3669 3670 if (link_loss) { 3671 bool skip = false; 3672 3673 spin_lock(&offload_wq->offload_lock); 3674 skip = offload_wq->is_handling_link_loss; 3675 3676 if (!skip) 3677 offload_wq->is_handling_link_loss = true; 3678 3679 spin_unlock(&offload_wq->offload_lock); 3680 3681 if (!skip) 3682 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3683 3684 goto out; 3685 } 3686 } 3687 3688 out: 3689 if (result && !is_mst_root_connector) { 3690 /* Downstream Port status changed. */ 3691 if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) 3692 DRM_ERROR("KMS: Failed to detect connector\n"); 3693 3694 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3695 emulated_link_detect(dc_link); 3696 3697 if (aconnector->fake_enable) 3698 aconnector->fake_enable = false; 3699 3700 amdgpu_dm_update_connector_after_detect(aconnector); 3701 3702 3703 drm_modeset_lock_all(dev); 3704 dm_restore_drm_connector_state(dev, connector); 3705 drm_modeset_unlock_all(dev); 3706 3707 drm_kms_helper_connector_hotplug_event(connector); 3708 } else { 3709 bool ret = false; 3710 3711 mutex_lock(&adev->dm.dc_lock); 3712 dc_exit_ips_for_hw_access(dc); 3713 ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX); 3714 mutex_unlock(&adev->dm.dc_lock); 3715 3716 if (ret) { 3717 if (aconnector->fake_enable) 3718 aconnector->fake_enable = false; 3719 3720 amdgpu_dm_update_connector_after_detect(aconnector); 3721 3722 drm_modeset_lock_all(dev); 3723 dm_restore_drm_connector_state(dev, connector); 3724 drm_modeset_unlock_all(dev); 3725 3726 drm_kms_helper_connector_hotplug_event(connector); 3727 } 3728 } 3729 } 3730 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) { 3731 if (adev->dm.hdcp_workqueue) 3732 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index); 3733 } 3734 3735 if (dc_link->type != dc_connection_mst_branch) 3736 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); 3737 3738 mutex_unlock(&aconnector->hpd_lock); 3739 } 3740 3741 static int register_hpd_handlers(struct amdgpu_device *adev) 3742 { 3743 struct drm_device *dev = adev_to_drm(adev); 3744 struct drm_connector *connector; 3745 struct amdgpu_dm_connector *aconnector; 3746 const struct dc_link *dc_link; 3747 struct dc_interrupt_params int_params = {0}; 3748 3749 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3750 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3751 3752 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 3753 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, 3754 dmub_hpd_callback, true)) { 3755 DRM_ERROR("amdgpu: fail to register dmub hpd callback"); 3756 return -EINVAL; 3757 } 3758 3759 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, 3760 dmub_hpd_callback, true)) { 3761 DRM_ERROR("amdgpu: fail to register dmub hpd callback"); 3762 return -EINVAL; 3763 } 3764 } 3765 3766 list_for_each_entry(connector, 3767 &dev->mode_config.connector_list, head) { 3768 3769 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 3770 continue; 3771 3772 aconnector = to_amdgpu_dm_connector(connector); 3773 dc_link = aconnector->dc_link; 3774 3775 if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) { 3776 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3777 int_params.irq_source = dc_link->irq_source_hpd; 3778 3779 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 3780 int_params.irq_source < DC_IRQ_SOURCE_HPD1 || 3781 int_params.irq_source > DC_IRQ_SOURCE_HPD6) { 3782 DRM_ERROR("Failed to register hpd irq!\n"); 3783 return -EINVAL; 3784 } 3785 3786 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 3787 handle_hpd_irq, (void *) aconnector)) 3788 return -ENOMEM; 3789 } 3790 3791 if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) { 3792 3793 /* Also register for DP short pulse (hpd_rx). */ 3794 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3795 int_params.irq_source = dc_link->irq_source_hpd_rx; 3796 3797 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 3798 int_params.irq_source < DC_IRQ_SOURCE_HPD1RX || 3799 int_params.irq_source > DC_IRQ_SOURCE_HPD6RX) { 3800 DRM_ERROR("Failed to register hpd rx irq!\n"); 3801 return -EINVAL; 3802 } 3803 3804 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 3805 handle_hpd_rx_irq, (void *) aconnector)) 3806 return -ENOMEM; 3807 } 3808 } 3809 return 0; 3810 } 3811 3812 #if defined(CONFIG_DRM_AMD_DC_SI) 3813 /* Register IRQ sources and initialize IRQ callbacks */ 3814 static int dce60_register_irq_handlers(struct amdgpu_device *adev) 3815 { 3816 struct dc *dc = adev->dm.dc; 3817 struct common_irq_params *c_irq_params; 3818 struct dc_interrupt_params int_params = {0}; 3819 int r; 3820 int i; 3821 unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3822 3823 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3824 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3825 3826 /* 3827 * Actions of amdgpu_irq_add_id(): 3828 * 1. Register a set() function with base driver. 3829 * Base driver will call set() function to enable/disable an 3830 * interrupt in DC hardware. 3831 * 2. Register amdgpu_dm_irq_handler(). 3832 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3833 * coming from DC hardware. 3834 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3835 * for acknowledging and handling. 3836 */ 3837 3838 /* Use VBLANK interrupt */ 3839 for (i = 0; i < adev->mode_info.num_crtc; i++) { 3840 r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq); 3841 if (r) { 3842 DRM_ERROR("Failed to add crtc irq id!\n"); 3843 return r; 3844 } 3845 3846 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3847 int_params.irq_source = 3848 dc_interrupt_to_irq_source(dc, i + 1, 0); 3849 3850 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 3851 int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 || 3852 int_params.irq_source > DC_IRQ_SOURCE_VBLANK6) { 3853 DRM_ERROR("Failed to register vblank irq!\n"); 3854 return -EINVAL; 3855 } 3856 3857 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3858 3859 c_irq_params->adev = adev; 3860 c_irq_params->irq_src = int_params.irq_source; 3861 3862 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 3863 dm_crtc_high_irq, c_irq_params)) 3864 return -ENOMEM; 3865 } 3866 3867 /* Use GRPH_PFLIP interrupt */ 3868 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 3869 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 3870 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 3871 if (r) { 3872 DRM_ERROR("Failed to add page flip irq id!\n"); 3873 return r; 3874 } 3875 3876 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3877 int_params.irq_source = 3878 dc_interrupt_to_irq_source(dc, i, 0); 3879 3880 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 3881 int_params.irq_source < DC_IRQ_SOURCE_PFLIP_FIRST || 3882 int_params.irq_source > DC_IRQ_SOURCE_PFLIP_LAST) { 3883 DRM_ERROR("Failed to register pflip irq!\n"); 3884 return -EINVAL; 3885 } 3886 3887 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 3888 3889 c_irq_params->adev = adev; 3890 c_irq_params->irq_src = int_params.irq_source; 3891 3892 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 3893 dm_pflip_high_irq, c_irq_params)) 3894 return -ENOMEM; 3895 } 3896 3897 /* HPD */ 3898 r = amdgpu_irq_add_id(adev, client_id, 3899 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 3900 if (r) { 3901 DRM_ERROR("Failed to add hpd irq id!\n"); 3902 return r; 3903 } 3904 3905 r = register_hpd_handlers(adev); 3906 3907 return r; 3908 } 3909 #endif 3910 3911 /* Register IRQ sources and initialize IRQ callbacks */ 3912 static int dce110_register_irq_handlers(struct amdgpu_device *adev) 3913 { 3914 struct dc *dc = adev->dm.dc; 3915 struct common_irq_params *c_irq_params; 3916 struct dc_interrupt_params int_params = {0}; 3917 int r; 3918 int i; 3919 unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3920 3921 if (adev->family >= AMDGPU_FAMILY_AI) 3922 client_id = SOC15_IH_CLIENTID_DCE; 3923 3924 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3925 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3926 3927 /* 3928 * Actions of amdgpu_irq_add_id(): 3929 * 1. Register a set() function with base driver. 3930 * Base driver will call set() function to enable/disable an 3931 * interrupt in DC hardware. 3932 * 2. Register amdgpu_dm_irq_handler(). 3933 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3934 * coming from DC hardware. 3935 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3936 * for acknowledging and handling. 3937 */ 3938 3939 /* Use VBLANK interrupt */ 3940 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { 3941 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); 3942 if (r) { 3943 DRM_ERROR("Failed to add crtc irq id!\n"); 3944 return r; 3945 } 3946 3947 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3948 int_params.irq_source = 3949 dc_interrupt_to_irq_source(dc, i, 0); 3950 3951 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 3952 int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 || 3953 int_params.irq_source > DC_IRQ_SOURCE_VBLANK6) { 3954 DRM_ERROR("Failed to register vblank irq!\n"); 3955 return -EINVAL; 3956 } 3957 3958 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3959 3960 c_irq_params->adev = adev; 3961 c_irq_params->irq_src = int_params.irq_source; 3962 3963 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 3964 dm_crtc_high_irq, c_irq_params)) 3965 return -ENOMEM; 3966 } 3967 3968 /* Use VUPDATE interrupt */ 3969 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { 3970 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); 3971 if (r) { 3972 DRM_ERROR("Failed to add vupdate irq id!\n"); 3973 return r; 3974 } 3975 3976 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3977 int_params.irq_source = 3978 dc_interrupt_to_irq_source(dc, i, 0); 3979 3980 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 3981 int_params.irq_source < DC_IRQ_SOURCE_VUPDATE1 || 3982 int_params.irq_source > DC_IRQ_SOURCE_VUPDATE6) { 3983 DRM_ERROR("Failed to register vupdate irq!\n"); 3984 return -EINVAL; 3985 } 3986 3987 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 3988 3989 c_irq_params->adev = adev; 3990 c_irq_params->irq_src = int_params.irq_source; 3991 3992 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 3993 dm_vupdate_high_irq, c_irq_params)) 3994 return -ENOMEM; 3995 } 3996 3997 /* Use GRPH_PFLIP interrupt */ 3998 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 3999 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 4000 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 4001 if (r) { 4002 DRM_ERROR("Failed to add page flip irq id!\n"); 4003 return r; 4004 } 4005 4006 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 4007 int_params.irq_source = 4008 dc_interrupt_to_irq_source(dc, i, 0); 4009 4010 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 4011 int_params.irq_source < DC_IRQ_SOURCE_PFLIP_FIRST || 4012 int_params.irq_source > DC_IRQ_SOURCE_PFLIP_LAST) { 4013 DRM_ERROR("Failed to register pflip irq!\n"); 4014 return -EINVAL; 4015 } 4016 4017 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 4018 4019 c_irq_params->adev = adev; 4020 c_irq_params->irq_src = int_params.irq_source; 4021 4022 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4023 dm_pflip_high_irq, c_irq_params)) 4024 return -ENOMEM; 4025 } 4026 4027 /* HPD */ 4028 r = amdgpu_irq_add_id(adev, client_id, 4029 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 4030 if (r) { 4031 DRM_ERROR("Failed to add hpd irq id!\n"); 4032 return r; 4033 } 4034 4035 r = register_hpd_handlers(adev); 4036 4037 return r; 4038 } 4039 4040 /* Register IRQ sources and initialize IRQ callbacks */ 4041 static int dcn10_register_irq_handlers(struct amdgpu_device *adev) 4042 { 4043 struct dc *dc = adev->dm.dc; 4044 struct common_irq_params *c_irq_params; 4045 struct dc_interrupt_params int_params = {0}; 4046 int r; 4047 int i; 4048 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 4049 static const unsigned int vrtl_int_srcid[] = { 4050 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL, 4051 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL, 4052 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL, 4053 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL, 4054 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL, 4055 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL 4056 }; 4057 #endif 4058 4059 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 4060 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 4061 4062 /* 4063 * Actions of amdgpu_irq_add_id(): 4064 * 1. Register a set() function with base driver. 4065 * Base driver will call set() function to enable/disable an 4066 * interrupt in DC hardware. 4067 * 2. Register amdgpu_dm_irq_handler(). 4068 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 4069 * coming from DC hardware. 4070 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 4071 * for acknowledging and handling. 4072 */ 4073 4074 /* Use VSTARTUP interrupt */ 4075 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; 4076 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; 4077 i++) { 4078 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); 4079 4080 if (r) { 4081 DRM_ERROR("Failed to add crtc irq id!\n"); 4082 return r; 4083 } 4084 4085 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 4086 int_params.irq_source = 4087 dc_interrupt_to_irq_source(dc, i, 0); 4088 4089 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 4090 int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 || 4091 int_params.irq_source > DC_IRQ_SOURCE_VBLANK6) { 4092 DRM_ERROR("Failed to register vblank irq!\n"); 4093 return -EINVAL; 4094 } 4095 4096 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 4097 4098 c_irq_params->adev = adev; 4099 c_irq_params->irq_src = int_params.irq_source; 4100 4101 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4102 dm_crtc_high_irq, c_irq_params)) 4103 return -ENOMEM; 4104 } 4105 4106 /* Use otg vertical line interrupt */ 4107 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 4108 for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) { 4109 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, 4110 vrtl_int_srcid[i], &adev->vline0_irq); 4111 4112 if (r) { 4113 DRM_ERROR("Failed to add vline0 irq id!\n"); 4114 return r; 4115 } 4116 4117 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 4118 int_params.irq_source = 4119 dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0); 4120 4121 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 4122 int_params.irq_source < DC_IRQ_SOURCE_DC1_VLINE0 || 4123 int_params.irq_source > DC_IRQ_SOURCE_DC6_VLINE0) { 4124 DRM_ERROR("Failed to register vline0 irq!\n"); 4125 return -EINVAL; 4126 } 4127 4128 c_irq_params = &adev->dm.vline0_params[int_params.irq_source 4129 - DC_IRQ_SOURCE_DC1_VLINE0]; 4130 4131 c_irq_params->adev = adev; 4132 c_irq_params->irq_src = int_params.irq_source; 4133 4134 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4135 dm_dcn_vertical_interrupt0_high_irq, 4136 c_irq_params)) 4137 return -ENOMEM; 4138 } 4139 #endif 4140 4141 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to 4142 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx 4143 * to trigger at end of each vblank, regardless of state of the lock, 4144 * matching DCE behaviour. 4145 */ 4146 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT; 4147 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1; 4148 i++) { 4149 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq); 4150 4151 if (r) { 4152 DRM_ERROR("Failed to add vupdate irq id!\n"); 4153 return r; 4154 } 4155 4156 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 4157 int_params.irq_source = 4158 dc_interrupt_to_irq_source(dc, i, 0); 4159 4160 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 4161 int_params.irq_source < DC_IRQ_SOURCE_VUPDATE1 || 4162 int_params.irq_source > DC_IRQ_SOURCE_VUPDATE6) { 4163 DRM_ERROR("Failed to register vupdate irq!\n"); 4164 return -EINVAL; 4165 } 4166 4167 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 4168 4169 c_irq_params->adev = adev; 4170 c_irq_params->irq_src = int_params.irq_source; 4171 4172 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4173 dm_vupdate_high_irq, c_irq_params)) 4174 return -ENOMEM; 4175 } 4176 4177 /* Use GRPH_PFLIP interrupt */ 4178 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; 4179 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1; 4180 i++) { 4181 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); 4182 if (r) { 4183 DRM_ERROR("Failed to add page flip irq id!\n"); 4184 return r; 4185 } 4186 4187 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 4188 int_params.irq_source = 4189 dc_interrupt_to_irq_source(dc, i, 0); 4190 4191 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 4192 int_params.irq_source < DC_IRQ_SOURCE_PFLIP_FIRST || 4193 int_params.irq_source > DC_IRQ_SOURCE_PFLIP_LAST) { 4194 DRM_ERROR("Failed to register pflip irq!\n"); 4195 return -EINVAL; 4196 } 4197 4198 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 4199 4200 c_irq_params->adev = adev; 4201 c_irq_params->irq_src = int_params.irq_source; 4202 4203 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4204 dm_pflip_high_irq, c_irq_params)) 4205 return -ENOMEM; 4206 } 4207 4208 /* HPD */ 4209 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, 4210 &adev->hpd_irq); 4211 if (r) { 4212 DRM_ERROR("Failed to add hpd irq id!\n"); 4213 return r; 4214 } 4215 4216 r = register_hpd_handlers(adev); 4217 4218 return r; 4219 } 4220 /* Register Outbox IRQ sources and initialize IRQ callbacks */ 4221 static int register_outbox_irq_handlers(struct amdgpu_device *adev) 4222 { 4223 struct dc *dc = adev->dm.dc; 4224 struct common_irq_params *c_irq_params; 4225 struct dc_interrupt_params int_params = {0}; 4226 int r, i; 4227 4228 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 4229 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 4230 4231 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT, 4232 &adev->dmub_outbox_irq); 4233 if (r) { 4234 DRM_ERROR("Failed to add outbox irq id!\n"); 4235 return r; 4236 } 4237 4238 if (dc->ctx->dmub_srv) { 4239 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT; 4240 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 4241 int_params.irq_source = 4242 dc_interrupt_to_irq_source(dc, i, 0); 4243 4244 c_irq_params = &adev->dm.dmub_outbox_params[0]; 4245 4246 c_irq_params->adev = adev; 4247 c_irq_params->irq_src = int_params.irq_source; 4248 4249 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4250 dm_dmub_outbox1_low_irq, c_irq_params)) 4251 return -ENOMEM; 4252 } 4253 4254 return 0; 4255 } 4256 4257 /* 4258 * Acquires the lock for the atomic state object and returns 4259 * the new atomic state. 4260 * 4261 * This should only be called during atomic check. 4262 */ 4263 int dm_atomic_get_state(struct drm_atomic_state *state, 4264 struct dm_atomic_state **dm_state) 4265 { 4266 struct drm_device *dev = state->dev; 4267 struct amdgpu_device *adev = drm_to_adev(dev); 4268 struct amdgpu_display_manager *dm = &adev->dm; 4269 struct drm_private_state *priv_state; 4270 4271 if (*dm_state) 4272 return 0; 4273 4274 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 4275 if (IS_ERR(priv_state)) 4276 return PTR_ERR(priv_state); 4277 4278 *dm_state = to_dm_atomic_state(priv_state); 4279 4280 return 0; 4281 } 4282 4283 static struct dm_atomic_state * 4284 dm_atomic_get_new_state(struct drm_atomic_state *state) 4285 { 4286 struct drm_device *dev = state->dev; 4287 struct amdgpu_device *adev = drm_to_adev(dev); 4288 struct amdgpu_display_manager *dm = &adev->dm; 4289 struct drm_private_obj *obj; 4290 struct drm_private_state *new_obj_state; 4291 int i; 4292 4293 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 4294 if (obj->funcs == dm->atomic_obj.funcs) 4295 return to_dm_atomic_state(new_obj_state); 4296 } 4297 4298 return NULL; 4299 } 4300 4301 static struct drm_private_state * 4302 dm_atomic_duplicate_state(struct drm_private_obj *obj) 4303 { 4304 struct dm_atomic_state *old_state, *new_state; 4305 4306 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 4307 if (!new_state) 4308 return NULL; 4309 4310 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 4311 4312 old_state = to_dm_atomic_state(obj->state); 4313 4314 if (old_state && old_state->context) 4315 new_state->context = dc_state_create_copy(old_state->context); 4316 4317 if (!new_state->context) { 4318 kfree(new_state); 4319 return NULL; 4320 } 4321 4322 return &new_state->base; 4323 } 4324 4325 static void dm_atomic_destroy_state(struct drm_private_obj *obj, 4326 struct drm_private_state *state) 4327 { 4328 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 4329 4330 if (dm_state && dm_state->context) 4331 dc_state_release(dm_state->context); 4332 4333 kfree(dm_state); 4334 } 4335 4336 static struct drm_private_state_funcs dm_atomic_state_funcs = { 4337 .atomic_duplicate_state = dm_atomic_duplicate_state, 4338 .atomic_destroy_state = dm_atomic_destroy_state, 4339 }; 4340 4341 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 4342 { 4343 struct dm_atomic_state *state; 4344 int r; 4345 4346 adev->mode_info.mode_config_initialized = true; 4347 4348 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 4349 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 4350 4351 adev_to_drm(adev)->mode_config.max_width = 16384; 4352 adev_to_drm(adev)->mode_config.max_height = 16384; 4353 4354 adev_to_drm(adev)->mode_config.preferred_depth = 24; 4355 if (adev->asic_type == CHIP_HAWAII) 4356 /* disable prefer shadow for now due to hibernation issues */ 4357 adev_to_drm(adev)->mode_config.prefer_shadow = 0; 4358 else 4359 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 4360 /* indicates support for immediate flip */ 4361 adev_to_drm(adev)->mode_config.async_page_flip = true; 4362 4363 state = kzalloc(sizeof(*state), GFP_KERNEL); 4364 if (!state) 4365 return -ENOMEM; 4366 4367 state->context = dc_state_create_current_copy(adev->dm.dc); 4368 if (!state->context) { 4369 kfree(state); 4370 return -ENOMEM; 4371 } 4372 4373 drm_atomic_private_obj_init(adev_to_drm(adev), 4374 &adev->dm.atomic_obj, 4375 &state->base, 4376 &dm_atomic_state_funcs); 4377 4378 r = amdgpu_display_modeset_create_props(adev); 4379 if (r) { 4380 dc_state_release(state->context); 4381 kfree(state); 4382 return r; 4383 } 4384 4385 #ifdef AMD_PRIVATE_COLOR 4386 if (amdgpu_dm_create_color_properties(adev)) { 4387 dc_state_release(state->context); 4388 kfree(state); 4389 return -ENOMEM; 4390 } 4391 #endif 4392 4393 r = amdgpu_dm_audio_init(adev); 4394 if (r) { 4395 dc_state_release(state->context); 4396 kfree(state); 4397 return r; 4398 } 4399 4400 return 0; 4401 } 4402 4403 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 4404 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 4405 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 4406 4407 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, 4408 int bl_idx) 4409 { 4410 #if defined(CONFIG_ACPI) 4411 struct amdgpu_dm_backlight_caps caps; 4412 4413 memset(&caps, 0, sizeof(caps)); 4414 4415 if (dm->backlight_caps[bl_idx].caps_valid) 4416 return; 4417 4418 amdgpu_acpi_get_backlight_caps(&caps); 4419 if (caps.caps_valid) { 4420 dm->backlight_caps[bl_idx].caps_valid = true; 4421 if (caps.aux_support) 4422 return; 4423 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal; 4424 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal; 4425 } else { 4426 dm->backlight_caps[bl_idx].min_input_signal = 4427 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 4428 dm->backlight_caps[bl_idx].max_input_signal = 4429 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 4430 } 4431 #else 4432 if (dm->backlight_caps[bl_idx].aux_support) 4433 return; 4434 4435 dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 4436 dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 4437 #endif 4438 } 4439 4440 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, 4441 unsigned int *min, unsigned int *max) 4442 { 4443 if (!caps) 4444 return 0; 4445 4446 if (caps->aux_support) { 4447 // Firmware limits are in nits, DC API wants millinits. 4448 *max = 1000 * caps->aux_max_input_signal; 4449 *min = 1000 * caps->aux_min_input_signal; 4450 } else { 4451 // Firmware limits are 8-bit, PWM control is 16-bit. 4452 *max = 0x101 * caps->max_input_signal; 4453 *min = 0x101 * caps->min_input_signal; 4454 } 4455 return 1; 4456 } 4457 4458 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps, 4459 uint32_t brightness) 4460 { 4461 unsigned int min, max; 4462 4463 if (!get_brightness_range(caps, &min, &max)) 4464 return brightness; 4465 4466 // Rescale 0..255 to min..max 4467 return min + DIV_ROUND_CLOSEST((max - min) * brightness, 4468 AMDGPU_MAX_BL_LEVEL); 4469 } 4470 4471 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps, 4472 uint32_t brightness) 4473 { 4474 unsigned int min, max; 4475 4476 if (!get_brightness_range(caps, &min, &max)) 4477 return brightness; 4478 4479 if (brightness < min) 4480 return 0; 4481 // Rescale min..max to 0..255 4482 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min), 4483 max - min); 4484 } 4485 4486 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, 4487 int bl_idx, 4488 u32 user_brightness) 4489 { 4490 struct amdgpu_dm_backlight_caps caps; 4491 struct dc_link *link; 4492 u32 brightness; 4493 bool rc; 4494 4495 amdgpu_dm_update_backlight_caps(dm, bl_idx); 4496 caps = dm->backlight_caps[bl_idx]; 4497 4498 dm->brightness[bl_idx] = user_brightness; 4499 /* update scratch register */ 4500 if (bl_idx == 0) 4501 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]); 4502 brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]); 4503 link = (struct dc_link *)dm->backlight_link[bl_idx]; 4504 4505 /* Change brightness based on AUX property */ 4506 if (caps.aux_support) { 4507 rc = dc_link_set_backlight_level_nits(link, true, brightness, 4508 AUX_BL_DEFAULT_TRANSITION_TIME_MS); 4509 if (!rc) 4510 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx); 4511 } else { 4512 rc = dc_link_set_backlight_level(link, brightness, 0); 4513 if (!rc) 4514 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx); 4515 } 4516 4517 if (rc) 4518 dm->actual_brightness[bl_idx] = user_brightness; 4519 } 4520 4521 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) 4522 { 4523 struct amdgpu_display_manager *dm = bl_get_data(bd); 4524 int i; 4525 4526 for (i = 0; i < dm->num_of_edps; i++) { 4527 if (bd == dm->backlight_dev[i]) 4528 break; 4529 } 4530 if (i >= AMDGPU_DM_MAX_NUM_EDP) 4531 i = 0; 4532 amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness); 4533 4534 return 0; 4535 } 4536 4537 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, 4538 int bl_idx) 4539 { 4540 int ret; 4541 struct amdgpu_dm_backlight_caps caps; 4542 struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx]; 4543 4544 amdgpu_dm_update_backlight_caps(dm, bl_idx); 4545 caps = dm->backlight_caps[bl_idx]; 4546 4547 if (caps.aux_support) { 4548 u32 avg, peak; 4549 bool rc; 4550 4551 rc = dc_link_get_backlight_level_nits(link, &avg, &peak); 4552 if (!rc) 4553 return dm->brightness[bl_idx]; 4554 return convert_brightness_to_user(&caps, avg); 4555 } 4556 4557 ret = dc_link_get_backlight_level(link); 4558 4559 if (ret == DC_ERROR_UNEXPECTED) 4560 return dm->brightness[bl_idx]; 4561 4562 return convert_brightness_to_user(&caps, ret); 4563 } 4564 4565 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) 4566 { 4567 struct amdgpu_display_manager *dm = bl_get_data(bd); 4568 int i; 4569 4570 for (i = 0; i < dm->num_of_edps; i++) { 4571 if (bd == dm->backlight_dev[i]) 4572 break; 4573 } 4574 if (i >= AMDGPU_DM_MAX_NUM_EDP) 4575 i = 0; 4576 return amdgpu_dm_backlight_get_level(dm, i); 4577 } 4578 4579 static const struct backlight_ops amdgpu_dm_backlight_ops = { 4580 .options = BL_CORE_SUSPENDRESUME, 4581 .get_brightness = amdgpu_dm_backlight_get_brightness, 4582 .update_status = amdgpu_dm_backlight_update_status, 4583 }; 4584 4585 static void 4586 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector) 4587 { 4588 struct drm_device *drm = aconnector->base.dev; 4589 struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm; 4590 struct backlight_properties props = { 0 }; 4591 struct amdgpu_dm_backlight_caps caps = { 0 }; 4592 char bl_name[16]; 4593 4594 if (aconnector->bl_idx == -1) 4595 return; 4596 4597 if (!acpi_video_backlight_use_native()) { 4598 drm_info(drm, "Skipping amdgpu DM backlight registration\n"); 4599 /* Try registering an ACPI video backlight device instead. */ 4600 acpi_video_register_backlight(); 4601 return; 4602 } 4603 4604 amdgpu_acpi_get_backlight_caps(&caps); 4605 if (caps.caps_valid) { 4606 if (power_supply_is_system_supplied() > 0) 4607 props.brightness = caps.ac_level; 4608 else 4609 props.brightness = caps.dc_level; 4610 } else 4611 props.brightness = AMDGPU_MAX_BL_LEVEL; 4612 4613 props.max_brightness = AMDGPU_MAX_BL_LEVEL; 4614 props.type = BACKLIGHT_RAW; 4615 4616 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", 4617 drm->primary->index + aconnector->bl_idx); 4618 4619 dm->backlight_dev[aconnector->bl_idx] = 4620 backlight_device_register(bl_name, aconnector->base.kdev, dm, 4621 &amdgpu_dm_backlight_ops, &props); 4622 4623 if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) { 4624 DRM_ERROR("DM: Backlight registration failed!\n"); 4625 dm->backlight_dev[aconnector->bl_idx] = NULL; 4626 } else 4627 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); 4628 } 4629 4630 static int initialize_plane(struct amdgpu_display_manager *dm, 4631 struct amdgpu_mode_info *mode_info, int plane_id, 4632 enum drm_plane_type plane_type, 4633 const struct dc_plane_cap *plane_cap) 4634 { 4635 struct drm_plane *plane; 4636 unsigned long possible_crtcs; 4637 int ret = 0; 4638 4639 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); 4640 if (!plane) { 4641 DRM_ERROR("KMS: Failed to allocate plane\n"); 4642 return -ENOMEM; 4643 } 4644 plane->type = plane_type; 4645 4646 /* 4647 * HACK: IGT tests expect that the primary plane for a CRTC 4648 * can only have one possible CRTC. Only expose support for 4649 * any CRTC if they're not going to be used as a primary plane 4650 * for a CRTC - like overlay or underlay planes. 4651 */ 4652 possible_crtcs = 1 << plane_id; 4653 if (plane_id >= dm->dc->caps.max_streams) 4654 possible_crtcs = 0xff; 4655 4656 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); 4657 4658 if (ret) { 4659 DRM_ERROR("KMS: Failed to initialize plane\n"); 4660 kfree(plane); 4661 return ret; 4662 } 4663 4664 if (mode_info) 4665 mode_info->planes[plane_id] = plane; 4666 4667 return ret; 4668 } 4669 4670 4671 static void setup_backlight_device(struct amdgpu_display_manager *dm, 4672 struct amdgpu_dm_connector *aconnector) 4673 { 4674 struct dc_link *link = aconnector->dc_link; 4675 int bl_idx = dm->num_of_edps; 4676 4677 if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) || 4678 link->type == dc_connection_none) 4679 return; 4680 4681 if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) { 4682 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n"); 4683 return; 4684 } 4685 4686 aconnector->bl_idx = bl_idx; 4687 4688 amdgpu_dm_update_backlight_caps(dm, bl_idx); 4689 dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL; 4690 dm->backlight_link[bl_idx] = link; 4691 dm->num_of_edps++; 4692 4693 update_connector_ext_caps(aconnector); 4694 } 4695 4696 static void amdgpu_set_panel_orientation(struct drm_connector *connector); 4697 4698 /* 4699 * In this architecture, the association 4700 * connector -> encoder -> crtc 4701 * id not really requried. The crtc and connector will hold the 4702 * display_index as an abstraction to use with DAL component 4703 * 4704 * Returns 0 on success 4705 */ 4706 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 4707 { 4708 struct amdgpu_display_manager *dm = &adev->dm; 4709 s32 i; 4710 struct amdgpu_dm_connector *aconnector = NULL; 4711 struct amdgpu_encoder *aencoder = NULL; 4712 struct amdgpu_mode_info *mode_info = &adev->mode_info; 4713 u32 link_cnt; 4714 s32 primary_planes; 4715 enum dc_connection_type new_connection_type = dc_connection_none; 4716 const struct dc_plane_cap *plane; 4717 bool psr_feature_enabled = false; 4718 bool replay_feature_enabled = false; 4719 int max_overlay = dm->dc->caps.max_slave_planes; 4720 4721 dm->display_indexes_num = dm->dc->caps.max_streams; 4722 /* Update the actual used number of crtc */ 4723 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 4724 4725 amdgpu_dm_set_irq_funcs(adev); 4726 4727 link_cnt = dm->dc->caps.max_links; 4728 if (amdgpu_dm_mode_config_init(dm->adev)) { 4729 DRM_ERROR("DM: Failed to initialize mode config\n"); 4730 return -EINVAL; 4731 } 4732 4733 /* There is one primary plane per CRTC */ 4734 primary_planes = dm->dc->caps.max_streams; 4735 if (primary_planes > AMDGPU_MAX_PLANES) { 4736 DRM_ERROR("DM: Plane nums out of 6 planes\n"); 4737 return -EINVAL; 4738 } 4739 4740 /* 4741 * Initialize primary planes, implicit planes for legacy IOCTLS. 4742 * Order is reversed to match iteration order in atomic check. 4743 */ 4744 for (i = (primary_planes - 1); i >= 0; i--) { 4745 plane = &dm->dc->caps.planes[i]; 4746 4747 if (initialize_plane(dm, mode_info, i, 4748 DRM_PLANE_TYPE_PRIMARY, plane)) { 4749 DRM_ERROR("KMS: Failed to initialize primary plane\n"); 4750 goto fail; 4751 } 4752 } 4753 4754 /* 4755 * Initialize overlay planes, index starting after primary planes. 4756 * These planes have a higher DRM index than the primary planes since 4757 * they should be considered as having a higher z-order. 4758 * Order is reversed to match iteration order in atomic check. 4759 * 4760 * Only support DCN for now, and only expose one so we don't encourage 4761 * userspace to use up all the pipes. 4762 */ 4763 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 4764 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 4765 4766 /* Do not create overlay if MPO disabled */ 4767 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO) 4768 break; 4769 4770 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) 4771 continue; 4772 4773 if (!plane->pixel_format_support.argb8888) 4774 continue; 4775 4776 if (max_overlay-- == 0) 4777 break; 4778 4779 if (initialize_plane(dm, NULL, primary_planes + i, 4780 DRM_PLANE_TYPE_OVERLAY, plane)) { 4781 DRM_ERROR("KMS: Failed to initialize overlay plane\n"); 4782 goto fail; 4783 } 4784 } 4785 4786 for (i = 0; i < dm->dc->caps.max_streams; i++) 4787 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 4788 DRM_ERROR("KMS: Failed to initialize crtc\n"); 4789 goto fail; 4790 } 4791 4792 /* Use Outbox interrupt */ 4793 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 4794 case IP_VERSION(3, 0, 0): 4795 case IP_VERSION(3, 1, 2): 4796 case IP_VERSION(3, 1, 3): 4797 case IP_VERSION(3, 1, 4): 4798 case IP_VERSION(3, 1, 5): 4799 case IP_VERSION(3, 1, 6): 4800 case IP_VERSION(3, 2, 0): 4801 case IP_VERSION(3, 2, 1): 4802 case IP_VERSION(2, 1, 0): 4803 case IP_VERSION(3, 5, 0): 4804 case IP_VERSION(3, 5, 1): 4805 case IP_VERSION(4, 0, 1): 4806 if (register_outbox_irq_handlers(dm->adev)) { 4807 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4808 goto fail; 4809 } 4810 break; 4811 default: 4812 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n", 4813 amdgpu_ip_version(adev, DCE_HWIP, 0)); 4814 } 4815 4816 /* Determine whether to enable PSR support by default. */ 4817 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) { 4818 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 4819 case IP_VERSION(3, 1, 2): 4820 case IP_VERSION(3, 1, 3): 4821 case IP_VERSION(3, 1, 4): 4822 case IP_VERSION(3, 1, 5): 4823 case IP_VERSION(3, 1, 6): 4824 case IP_VERSION(3, 2, 0): 4825 case IP_VERSION(3, 2, 1): 4826 case IP_VERSION(3, 5, 0): 4827 case IP_VERSION(3, 5, 1): 4828 case IP_VERSION(4, 0, 1): 4829 psr_feature_enabled = true; 4830 break; 4831 default: 4832 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK; 4833 break; 4834 } 4835 } 4836 4837 /* Determine whether to enable Replay support by default. */ 4838 if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) { 4839 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 4840 /* 4841 * Disabled by default due to https://gitlab.freedesktop.org/drm/amd/-/issues/3344 4842 * case IP_VERSION(3, 1, 4): 4843 * case IP_VERSION(3, 1, 5): 4844 * case IP_VERSION(3, 1, 6): 4845 * case IP_VERSION(3, 2, 0): 4846 * case IP_VERSION(3, 2, 1): 4847 * case IP_VERSION(3, 5, 0): 4848 * case IP_VERSION(3, 5, 1): 4849 * replay_feature_enabled = true; 4850 * break; 4851 */ 4852 default: 4853 replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK; 4854 break; 4855 } 4856 } 4857 4858 if (link_cnt > MAX_LINKS) { 4859 DRM_ERROR( 4860 "KMS: Cannot support more than %d display indexes\n", 4861 MAX_LINKS); 4862 goto fail; 4863 } 4864 4865 /* loops over all connectors on the board */ 4866 for (i = 0; i < link_cnt; i++) { 4867 struct dc_link *link = NULL; 4868 4869 link = dc_get_link_at_index(dm->dc, i); 4870 4871 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) { 4872 struct amdgpu_dm_wb_connector *wbcon = kzalloc(sizeof(*wbcon), GFP_KERNEL); 4873 4874 if (!wbcon) { 4875 DRM_ERROR("KMS: Failed to allocate writeback connector\n"); 4876 continue; 4877 } 4878 4879 if (amdgpu_dm_wb_connector_init(dm, wbcon, i)) { 4880 DRM_ERROR("KMS: Failed to initialize writeback connector\n"); 4881 kfree(wbcon); 4882 continue; 4883 } 4884 4885 link->psr_settings.psr_feature_enabled = false; 4886 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; 4887 4888 continue; 4889 } 4890 4891 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 4892 if (!aconnector) 4893 goto fail; 4894 4895 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); 4896 if (!aencoder) 4897 goto fail; 4898 4899 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 4900 DRM_ERROR("KMS: Failed to initialize encoder\n"); 4901 goto fail; 4902 } 4903 4904 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 4905 DRM_ERROR("KMS: Failed to initialize connector\n"); 4906 goto fail; 4907 } 4908 4909 if (dm->hpd_rx_offload_wq) 4910 dm->hpd_rx_offload_wq[aconnector->base.index].aconnector = 4911 aconnector; 4912 4913 if (!dc_link_detect_connection_type(link, &new_connection_type)) 4914 DRM_ERROR("KMS: Failed to detect connector\n"); 4915 4916 if (aconnector->base.force && new_connection_type == dc_connection_none) { 4917 emulated_link_detect(link); 4918 amdgpu_dm_update_connector_after_detect(aconnector); 4919 } else { 4920 bool ret = false; 4921 4922 mutex_lock(&dm->dc_lock); 4923 dc_exit_ips_for_hw_access(dm->dc); 4924 ret = dc_link_detect(link, DETECT_REASON_BOOT); 4925 mutex_unlock(&dm->dc_lock); 4926 4927 if (ret) { 4928 amdgpu_dm_update_connector_after_detect(aconnector); 4929 setup_backlight_device(dm, aconnector); 4930 4931 /* Disable PSR if Replay can be enabled */ 4932 if (replay_feature_enabled) 4933 if (amdgpu_dm_set_replay_caps(link, aconnector)) 4934 psr_feature_enabled = false; 4935 4936 if (psr_feature_enabled) 4937 amdgpu_dm_set_psr_caps(link); 4938 } 4939 } 4940 amdgpu_set_panel_orientation(&aconnector->base); 4941 } 4942 4943 /* Software is initialized. Now we can register interrupt handlers. */ 4944 switch (adev->asic_type) { 4945 #if defined(CONFIG_DRM_AMD_DC_SI) 4946 case CHIP_TAHITI: 4947 case CHIP_PITCAIRN: 4948 case CHIP_VERDE: 4949 case CHIP_OLAND: 4950 if (dce60_register_irq_handlers(dm->adev)) { 4951 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4952 goto fail; 4953 } 4954 break; 4955 #endif 4956 case CHIP_BONAIRE: 4957 case CHIP_HAWAII: 4958 case CHIP_KAVERI: 4959 case CHIP_KABINI: 4960 case CHIP_MULLINS: 4961 case CHIP_TONGA: 4962 case CHIP_FIJI: 4963 case CHIP_CARRIZO: 4964 case CHIP_STONEY: 4965 case CHIP_POLARIS11: 4966 case CHIP_POLARIS10: 4967 case CHIP_POLARIS12: 4968 case CHIP_VEGAM: 4969 case CHIP_VEGA10: 4970 case CHIP_VEGA12: 4971 case CHIP_VEGA20: 4972 if (dce110_register_irq_handlers(dm->adev)) { 4973 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4974 goto fail; 4975 } 4976 break; 4977 default: 4978 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 4979 case IP_VERSION(1, 0, 0): 4980 case IP_VERSION(1, 0, 1): 4981 case IP_VERSION(2, 0, 2): 4982 case IP_VERSION(2, 0, 3): 4983 case IP_VERSION(2, 0, 0): 4984 case IP_VERSION(2, 1, 0): 4985 case IP_VERSION(3, 0, 0): 4986 case IP_VERSION(3, 0, 2): 4987 case IP_VERSION(3, 0, 3): 4988 case IP_VERSION(3, 0, 1): 4989 case IP_VERSION(3, 1, 2): 4990 case IP_VERSION(3, 1, 3): 4991 case IP_VERSION(3, 1, 4): 4992 case IP_VERSION(3, 1, 5): 4993 case IP_VERSION(3, 1, 6): 4994 case IP_VERSION(3, 2, 0): 4995 case IP_VERSION(3, 2, 1): 4996 case IP_VERSION(3, 5, 0): 4997 case IP_VERSION(3, 5, 1): 4998 case IP_VERSION(4, 0, 1): 4999 if (dcn10_register_irq_handlers(dm->adev)) { 5000 DRM_ERROR("DM: Failed to initialize IRQ\n"); 5001 goto fail; 5002 } 5003 break; 5004 default: 5005 DRM_ERROR("Unsupported DCE IP versions: 0x%X\n", 5006 amdgpu_ip_version(adev, DCE_HWIP, 0)); 5007 goto fail; 5008 } 5009 break; 5010 } 5011 5012 return 0; 5013 fail: 5014 kfree(aencoder); 5015 kfree(aconnector); 5016 5017 return -EINVAL; 5018 } 5019 5020 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 5021 { 5022 drm_atomic_private_obj_fini(&dm->atomic_obj); 5023 } 5024 5025 /****************************************************************************** 5026 * amdgpu_display_funcs functions 5027 *****************************************************************************/ 5028 5029 /* 5030 * dm_bandwidth_update - program display watermarks 5031 * 5032 * @adev: amdgpu_device pointer 5033 * 5034 * Calculate and program the display watermarks and line buffer allocation. 5035 */ 5036 static void dm_bandwidth_update(struct amdgpu_device *adev) 5037 { 5038 /* TODO: implement later */ 5039 } 5040 5041 static const struct amdgpu_display_funcs dm_display_funcs = { 5042 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 5043 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 5044 .backlight_set_level = NULL, /* never called for DC */ 5045 .backlight_get_level = NULL, /* never called for DC */ 5046 .hpd_sense = NULL,/* called unconditionally */ 5047 .hpd_set_polarity = NULL, /* called unconditionally */ 5048 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 5049 .page_flip_get_scanoutpos = 5050 dm_crtc_get_scanoutpos,/* called unconditionally */ 5051 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 5052 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 5053 }; 5054 5055 #if defined(CONFIG_DEBUG_KERNEL_DC) 5056 5057 static ssize_t s3_debug_store(struct device *device, 5058 struct device_attribute *attr, 5059 const char *buf, 5060 size_t count) 5061 { 5062 int ret; 5063 int s3_state; 5064 struct drm_device *drm_dev = dev_get_drvdata(device); 5065 struct amdgpu_device *adev = drm_to_adev(drm_dev); 5066 5067 ret = kstrtoint(buf, 0, &s3_state); 5068 5069 if (ret == 0) { 5070 if (s3_state) { 5071 dm_resume(adev); 5072 drm_kms_helper_hotplug_event(adev_to_drm(adev)); 5073 } else 5074 dm_suspend(adev); 5075 } 5076 5077 return ret == 0 ? count : 0; 5078 } 5079 5080 DEVICE_ATTR_WO(s3_debug); 5081 5082 #endif 5083 5084 static int dm_init_microcode(struct amdgpu_device *adev) 5085 { 5086 char *fw_name_dmub; 5087 int r; 5088 5089 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 5090 case IP_VERSION(2, 1, 0): 5091 fw_name_dmub = FIRMWARE_RENOIR_DMUB; 5092 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) 5093 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB; 5094 break; 5095 case IP_VERSION(3, 0, 0): 5096 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0)) 5097 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB; 5098 else 5099 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB; 5100 break; 5101 case IP_VERSION(3, 0, 1): 5102 fw_name_dmub = FIRMWARE_VANGOGH_DMUB; 5103 break; 5104 case IP_VERSION(3, 0, 2): 5105 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB; 5106 break; 5107 case IP_VERSION(3, 0, 3): 5108 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB; 5109 break; 5110 case IP_VERSION(3, 1, 2): 5111 case IP_VERSION(3, 1, 3): 5112 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB; 5113 break; 5114 case IP_VERSION(3, 1, 4): 5115 fw_name_dmub = FIRMWARE_DCN_314_DMUB; 5116 break; 5117 case IP_VERSION(3, 1, 5): 5118 fw_name_dmub = FIRMWARE_DCN_315_DMUB; 5119 break; 5120 case IP_VERSION(3, 1, 6): 5121 fw_name_dmub = FIRMWARE_DCN316_DMUB; 5122 break; 5123 case IP_VERSION(3, 2, 0): 5124 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB; 5125 break; 5126 case IP_VERSION(3, 2, 1): 5127 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB; 5128 break; 5129 case IP_VERSION(3, 5, 0): 5130 fw_name_dmub = FIRMWARE_DCN_35_DMUB; 5131 break; 5132 case IP_VERSION(3, 5, 1): 5133 fw_name_dmub = FIRMWARE_DCN_351_DMUB; 5134 break; 5135 case IP_VERSION(4, 0, 1): 5136 fw_name_dmub = FIRMWARE_DCN_401_DMUB; 5137 break; 5138 default: 5139 /* ASIC doesn't support DMUB. */ 5140 return 0; 5141 } 5142 r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub); 5143 return r; 5144 } 5145 5146 static int dm_early_init(void *handle) 5147 { 5148 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5149 struct amdgpu_mode_info *mode_info = &adev->mode_info; 5150 struct atom_context *ctx = mode_info->atom_context; 5151 int index = GetIndexIntoMasterTable(DATA, Object_Header); 5152 u16 data_offset; 5153 5154 /* if there is no object header, skip DM */ 5155 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { 5156 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 5157 dev_info(adev->dev, "No object header, skipping DM\n"); 5158 return -ENOENT; 5159 } 5160 5161 switch (adev->asic_type) { 5162 #if defined(CONFIG_DRM_AMD_DC_SI) 5163 case CHIP_TAHITI: 5164 case CHIP_PITCAIRN: 5165 case CHIP_VERDE: 5166 adev->mode_info.num_crtc = 6; 5167 adev->mode_info.num_hpd = 6; 5168 adev->mode_info.num_dig = 6; 5169 break; 5170 case CHIP_OLAND: 5171 adev->mode_info.num_crtc = 2; 5172 adev->mode_info.num_hpd = 2; 5173 adev->mode_info.num_dig = 2; 5174 break; 5175 #endif 5176 case CHIP_BONAIRE: 5177 case CHIP_HAWAII: 5178 adev->mode_info.num_crtc = 6; 5179 adev->mode_info.num_hpd = 6; 5180 adev->mode_info.num_dig = 6; 5181 break; 5182 case CHIP_KAVERI: 5183 adev->mode_info.num_crtc = 4; 5184 adev->mode_info.num_hpd = 6; 5185 adev->mode_info.num_dig = 7; 5186 break; 5187 case CHIP_KABINI: 5188 case CHIP_MULLINS: 5189 adev->mode_info.num_crtc = 2; 5190 adev->mode_info.num_hpd = 6; 5191 adev->mode_info.num_dig = 6; 5192 break; 5193 case CHIP_FIJI: 5194 case CHIP_TONGA: 5195 adev->mode_info.num_crtc = 6; 5196 adev->mode_info.num_hpd = 6; 5197 adev->mode_info.num_dig = 7; 5198 break; 5199 case CHIP_CARRIZO: 5200 adev->mode_info.num_crtc = 3; 5201 adev->mode_info.num_hpd = 6; 5202 adev->mode_info.num_dig = 9; 5203 break; 5204 case CHIP_STONEY: 5205 adev->mode_info.num_crtc = 2; 5206 adev->mode_info.num_hpd = 6; 5207 adev->mode_info.num_dig = 9; 5208 break; 5209 case CHIP_POLARIS11: 5210 case CHIP_POLARIS12: 5211 adev->mode_info.num_crtc = 5; 5212 adev->mode_info.num_hpd = 5; 5213 adev->mode_info.num_dig = 5; 5214 break; 5215 case CHIP_POLARIS10: 5216 case CHIP_VEGAM: 5217 adev->mode_info.num_crtc = 6; 5218 adev->mode_info.num_hpd = 6; 5219 adev->mode_info.num_dig = 6; 5220 break; 5221 case CHIP_VEGA10: 5222 case CHIP_VEGA12: 5223 case CHIP_VEGA20: 5224 adev->mode_info.num_crtc = 6; 5225 adev->mode_info.num_hpd = 6; 5226 adev->mode_info.num_dig = 6; 5227 break; 5228 default: 5229 5230 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 5231 case IP_VERSION(2, 0, 2): 5232 case IP_VERSION(3, 0, 0): 5233 adev->mode_info.num_crtc = 6; 5234 adev->mode_info.num_hpd = 6; 5235 adev->mode_info.num_dig = 6; 5236 break; 5237 case IP_VERSION(2, 0, 0): 5238 case IP_VERSION(3, 0, 2): 5239 adev->mode_info.num_crtc = 5; 5240 adev->mode_info.num_hpd = 5; 5241 adev->mode_info.num_dig = 5; 5242 break; 5243 case IP_VERSION(2, 0, 3): 5244 case IP_VERSION(3, 0, 3): 5245 adev->mode_info.num_crtc = 2; 5246 adev->mode_info.num_hpd = 2; 5247 adev->mode_info.num_dig = 2; 5248 break; 5249 case IP_VERSION(1, 0, 0): 5250 case IP_VERSION(1, 0, 1): 5251 case IP_VERSION(3, 0, 1): 5252 case IP_VERSION(2, 1, 0): 5253 case IP_VERSION(3, 1, 2): 5254 case IP_VERSION(3, 1, 3): 5255 case IP_VERSION(3, 1, 4): 5256 case IP_VERSION(3, 1, 5): 5257 case IP_VERSION(3, 1, 6): 5258 case IP_VERSION(3, 2, 0): 5259 case IP_VERSION(3, 2, 1): 5260 case IP_VERSION(3, 5, 0): 5261 case IP_VERSION(3, 5, 1): 5262 case IP_VERSION(4, 0, 1): 5263 adev->mode_info.num_crtc = 4; 5264 adev->mode_info.num_hpd = 4; 5265 adev->mode_info.num_dig = 4; 5266 break; 5267 default: 5268 DRM_ERROR("Unsupported DCE IP versions: 0x%x\n", 5269 amdgpu_ip_version(adev, DCE_HWIP, 0)); 5270 return -EINVAL; 5271 } 5272 break; 5273 } 5274 5275 if (adev->mode_info.funcs == NULL) 5276 adev->mode_info.funcs = &dm_display_funcs; 5277 5278 /* 5279 * Note: Do NOT change adev->audio_endpt_rreg and 5280 * adev->audio_endpt_wreg because they are initialised in 5281 * amdgpu_device_init() 5282 */ 5283 #if defined(CONFIG_DEBUG_KERNEL_DC) 5284 device_create_file( 5285 adev_to_drm(adev)->dev, 5286 &dev_attr_s3_debug); 5287 #endif 5288 adev->dc_enabled = true; 5289 5290 return dm_init_microcode(adev); 5291 } 5292 5293 static bool modereset_required(struct drm_crtc_state *crtc_state) 5294 { 5295 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 5296 } 5297 5298 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 5299 { 5300 drm_encoder_cleanup(encoder); 5301 kfree(encoder); 5302 } 5303 5304 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 5305 .destroy = amdgpu_dm_encoder_destroy, 5306 }; 5307 5308 static int 5309 fill_plane_color_attributes(const struct drm_plane_state *plane_state, 5310 const enum surface_pixel_format format, 5311 enum dc_color_space *color_space) 5312 { 5313 bool full_range; 5314 5315 *color_space = COLOR_SPACE_SRGB; 5316 5317 /* DRM color properties only affect non-RGB formats. */ 5318 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 5319 return 0; 5320 5321 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); 5322 5323 switch (plane_state->color_encoding) { 5324 case DRM_COLOR_YCBCR_BT601: 5325 if (full_range) 5326 *color_space = COLOR_SPACE_YCBCR601; 5327 else 5328 *color_space = COLOR_SPACE_YCBCR601_LIMITED; 5329 break; 5330 5331 case DRM_COLOR_YCBCR_BT709: 5332 if (full_range) 5333 *color_space = COLOR_SPACE_YCBCR709; 5334 else 5335 *color_space = COLOR_SPACE_YCBCR709_LIMITED; 5336 break; 5337 5338 case DRM_COLOR_YCBCR_BT2020: 5339 if (full_range) 5340 *color_space = COLOR_SPACE_2020_YCBCR; 5341 else 5342 return -EINVAL; 5343 break; 5344 5345 default: 5346 return -EINVAL; 5347 } 5348 5349 return 0; 5350 } 5351 5352 static int 5353 fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 5354 const struct drm_plane_state *plane_state, 5355 const u64 tiling_flags, 5356 struct dc_plane_info *plane_info, 5357 struct dc_plane_address *address, 5358 bool tmz_surface, 5359 bool force_disable_dcc) 5360 { 5361 const struct drm_framebuffer *fb = plane_state->fb; 5362 const struct amdgpu_framebuffer *afb = 5363 to_amdgpu_framebuffer(plane_state->fb); 5364 int ret; 5365 5366 memset(plane_info, 0, sizeof(*plane_info)); 5367 5368 switch (fb->format->format) { 5369 case DRM_FORMAT_C8: 5370 plane_info->format = 5371 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 5372 break; 5373 case DRM_FORMAT_RGB565: 5374 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 5375 break; 5376 case DRM_FORMAT_XRGB8888: 5377 case DRM_FORMAT_ARGB8888: 5378 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 5379 break; 5380 case DRM_FORMAT_XRGB2101010: 5381 case DRM_FORMAT_ARGB2101010: 5382 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 5383 break; 5384 case DRM_FORMAT_XBGR2101010: 5385 case DRM_FORMAT_ABGR2101010: 5386 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 5387 break; 5388 case DRM_FORMAT_XBGR8888: 5389 case DRM_FORMAT_ABGR8888: 5390 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 5391 break; 5392 case DRM_FORMAT_NV21: 5393 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 5394 break; 5395 case DRM_FORMAT_NV12: 5396 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 5397 break; 5398 case DRM_FORMAT_P010: 5399 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; 5400 break; 5401 case DRM_FORMAT_XRGB16161616F: 5402 case DRM_FORMAT_ARGB16161616F: 5403 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; 5404 break; 5405 case DRM_FORMAT_XBGR16161616F: 5406 case DRM_FORMAT_ABGR16161616F: 5407 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; 5408 break; 5409 case DRM_FORMAT_XRGB16161616: 5410 case DRM_FORMAT_ARGB16161616: 5411 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; 5412 break; 5413 case DRM_FORMAT_XBGR16161616: 5414 case DRM_FORMAT_ABGR16161616: 5415 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; 5416 break; 5417 default: 5418 DRM_ERROR( 5419 "Unsupported screen format %p4cc\n", 5420 &fb->format->format); 5421 return -EINVAL; 5422 } 5423 5424 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 5425 case DRM_MODE_ROTATE_0: 5426 plane_info->rotation = ROTATION_ANGLE_0; 5427 break; 5428 case DRM_MODE_ROTATE_90: 5429 plane_info->rotation = ROTATION_ANGLE_90; 5430 break; 5431 case DRM_MODE_ROTATE_180: 5432 plane_info->rotation = ROTATION_ANGLE_180; 5433 break; 5434 case DRM_MODE_ROTATE_270: 5435 plane_info->rotation = ROTATION_ANGLE_270; 5436 break; 5437 default: 5438 plane_info->rotation = ROTATION_ANGLE_0; 5439 break; 5440 } 5441 5442 5443 plane_info->visible = true; 5444 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; 5445 5446 plane_info->layer_index = plane_state->normalized_zpos; 5447 5448 ret = fill_plane_color_attributes(plane_state, plane_info->format, 5449 &plane_info->color_space); 5450 if (ret) 5451 return ret; 5452 5453 ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format, 5454 plane_info->rotation, tiling_flags, 5455 &plane_info->tiling_info, 5456 &plane_info->plane_size, 5457 &plane_info->dcc, address, 5458 tmz_surface, force_disable_dcc); 5459 if (ret) 5460 return ret; 5461 5462 amdgpu_dm_plane_fill_blending_from_plane_state( 5463 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha, 5464 &plane_info->global_alpha, &plane_info->global_alpha_value); 5465 5466 return 0; 5467 } 5468 5469 static int fill_dc_plane_attributes(struct amdgpu_device *adev, 5470 struct dc_plane_state *dc_plane_state, 5471 struct drm_plane_state *plane_state, 5472 struct drm_crtc_state *crtc_state) 5473 { 5474 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 5475 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; 5476 struct dc_scaling_info scaling_info; 5477 struct dc_plane_info plane_info; 5478 int ret; 5479 bool force_disable_dcc = false; 5480 5481 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info); 5482 if (ret) 5483 return ret; 5484 5485 dc_plane_state->src_rect = scaling_info.src_rect; 5486 dc_plane_state->dst_rect = scaling_info.dst_rect; 5487 dc_plane_state->clip_rect = scaling_info.clip_rect; 5488 dc_plane_state->scaling_quality = scaling_info.scaling_quality; 5489 5490 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend; 5491 ret = fill_dc_plane_info_and_addr(adev, plane_state, 5492 afb->tiling_flags, 5493 &plane_info, 5494 &dc_plane_state->address, 5495 afb->tmz_surface, 5496 force_disable_dcc); 5497 if (ret) 5498 return ret; 5499 5500 dc_plane_state->format = plane_info.format; 5501 dc_plane_state->color_space = plane_info.color_space; 5502 dc_plane_state->format = plane_info.format; 5503 dc_plane_state->plane_size = plane_info.plane_size; 5504 dc_plane_state->rotation = plane_info.rotation; 5505 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; 5506 dc_plane_state->stereo_format = plane_info.stereo_format; 5507 dc_plane_state->tiling_info = plane_info.tiling_info; 5508 dc_plane_state->visible = plane_info.visible; 5509 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 5510 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha; 5511 dc_plane_state->global_alpha = plane_info.global_alpha; 5512 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 5513 dc_plane_state->dcc = plane_info.dcc; 5514 dc_plane_state->layer_index = plane_info.layer_index; 5515 dc_plane_state->flip_int_enabled = true; 5516 5517 /* 5518 * Always set input transfer function, since plane state is refreshed 5519 * every time. 5520 */ 5521 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, 5522 plane_state, 5523 dc_plane_state); 5524 if (ret) 5525 return ret; 5526 5527 return 0; 5528 } 5529 5530 static inline void fill_dc_dirty_rect(struct drm_plane *plane, 5531 struct rect *dirty_rect, int32_t x, 5532 s32 y, s32 width, s32 height, 5533 int *i, bool ffu) 5534 { 5535 WARN_ON(*i >= DC_MAX_DIRTY_RECTS); 5536 5537 dirty_rect->x = x; 5538 dirty_rect->y = y; 5539 dirty_rect->width = width; 5540 dirty_rect->height = height; 5541 5542 if (ffu) 5543 drm_dbg(plane->dev, 5544 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n", 5545 plane->base.id, width, height); 5546 else 5547 drm_dbg(plane->dev, 5548 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)", 5549 plane->base.id, x, y, width, height); 5550 5551 (*i)++; 5552 } 5553 5554 /** 5555 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates 5556 * 5557 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP 5558 * remote fb 5559 * @old_plane_state: Old state of @plane 5560 * @new_plane_state: New state of @plane 5561 * @crtc_state: New state of CRTC connected to the @plane 5562 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects 5563 * @is_psr_su: Flag indicating whether Panel Self Refresh Selective Update (PSR SU) is enabled. 5564 * If PSR SU is enabled and damage clips are available, only the regions of the screen 5565 * that have changed will be updated. If PSR SU is not enabled, 5566 * or if damage clips are not available, the entire screen will be updated. 5567 * @dirty_regions_changed: dirty regions changed 5568 * 5569 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions 5570 * (referred to as "damage clips" in DRM nomenclature) that require updating on 5571 * the eDP remote buffer. The responsibility of specifying the dirty regions is 5572 * amdgpu_dm's. 5573 * 5574 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the 5575 * plane with regions that require flushing to the eDP remote buffer. In 5576 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - 5577 * implicitly provide damage clips without any client support via the plane 5578 * bounds. 5579 */ 5580 static void fill_dc_dirty_rects(struct drm_plane *plane, 5581 struct drm_plane_state *old_plane_state, 5582 struct drm_plane_state *new_plane_state, 5583 struct drm_crtc_state *crtc_state, 5584 struct dc_flip_addrs *flip_addrs, 5585 bool is_psr_su, 5586 bool *dirty_regions_changed) 5587 { 5588 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 5589 struct rect *dirty_rects = flip_addrs->dirty_rects; 5590 u32 num_clips; 5591 struct drm_mode_rect *clips; 5592 bool bb_changed; 5593 bool fb_changed; 5594 u32 i = 0; 5595 *dirty_regions_changed = false; 5596 5597 /* 5598 * Cursor plane has it's own dirty rect update interface. See 5599 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data 5600 */ 5601 if (plane->type == DRM_PLANE_TYPE_CURSOR) 5602 return; 5603 5604 if (new_plane_state->rotation != DRM_MODE_ROTATE_0) 5605 goto ffu; 5606 5607 num_clips = drm_plane_get_damage_clips_count(new_plane_state); 5608 clips = drm_plane_get_damage_clips(new_plane_state); 5609 5610 if (num_clips && (!amdgpu_damage_clips || (amdgpu_damage_clips < 0 && 5611 is_psr_su))) 5612 goto ffu; 5613 5614 if (!dm_crtc_state->mpo_requested) { 5615 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS) 5616 goto ffu; 5617 5618 for (; flip_addrs->dirty_rect_count < num_clips; clips++) 5619 fill_dc_dirty_rect(new_plane_state->plane, 5620 &dirty_rects[flip_addrs->dirty_rect_count], 5621 clips->x1, clips->y1, 5622 clips->x2 - clips->x1, clips->y2 - clips->y1, 5623 &flip_addrs->dirty_rect_count, 5624 false); 5625 return; 5626 } 5627 5628 /* 5629 * MPO is requested. Add entire plane bounding box to dirty rects if 5630 * flipped to or damaged. 5631 * 5632 * If plane is moved or resized, also add old bounding box to dirty 5633 * rects. 5634 */ 5635 fb_changed = old_plane_state->fb->base.id != 5636 new_plane_state->fb->base.id; 5637 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x || 5638 old_plane_state->crtc_y != new_plane_state->crtc_y || 5639 old_plane_state->crtc_w != new_plane_state->crtc_w || 5640 old_plane_state->crtc_h != new_plane_state->crtc_h); 5641 5642 drm_dbg(plane->dev, 5643 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n", 5644 new_plane_state->plane->base.id, 5645 bb_changed, fb_changed, num_clips); 5646 5647 *dirty_regions_changed = bb_changed; 5648 5649 if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS) 5650 goto ffu; 5651 5652 if (bb_changed) { 5653 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 5654 new_plane_state->crtc_x, 5655 new_plane_state->crtc_y, 5656 new_plane_state->crtc_w, 5657 new_plane_state->crtc_h, &i, false); 5658 5659 /* Add old plane bounding-box if plane is moved or resized */ 5660 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 5661 old_plane_state->crtc_x, 5662 old_plane_state->crtc_y, 5663 old_plane_state->crtc_w, 5664 old_plane_state->crtc_h, &i, false); 5665 } 5666 5667 if (num_clips) { 5668 for (; i < num_clips; clips++) 5669 fill_dc_dirty_rect(new_plane_state->plane, 5670 &dirty_rects[i], clips->x1, 5671 clips->y1, clips->x2 - clips->x1, 5672 clips->y2 - clips->y1, &i, false); 5673 } else if (fb_changed && !bb_changed) { 5674 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 5675 new_plane_state->crtc_x, 5676 new_plane_state->crtc_y, 5677 new_plane_state->crtc_w, 5678 new_plane_state->crtc_h, &i, false); 5679 } 5680 5681 flip_addrs->dirty_rect_count = i; 5682 return; 5683 5684 ffu: 5685 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0, 5686 dm_crtc_state->base.mode.crtc_hdisplay, 5687 dm_crtc_state->base.mode.crtc_vdisplay, 5688 &flip_addrs->dirty_rect_count, true); 5689 } 5690 5691 static void update_stream_scaling_settings(const struct drm_display_mode *mode, 5692 const struct dm_connector_state *dm_state, 5693 struct dc_stream_state *stream) 5694 { 5695 enum amdgpu_rmx_type rmx_type; 5696 5697 struct rect src = { 0 }; /* viewport in composition space*/ 5698 struct rect dst = { 0 }; /* stream addressable area */ 5699 5700 /* no mode. nothing to be done */ 5701 if (!mode) 5702 return; 5703 5704 /* Full screen scaling by default */ 5705 src.width = mode->hdisplay; 5706 src.height = mode->vdisplay; 5707 dst.width = stream->timing.h_addressable; 5708 dst.height = stream->timing.v_addressable; 5709 5710 if (dm_state) { 5711 rmx_type = dm_state->scaling; 5712 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 5713 if (src.width * dst.height < 5714 src.height * dst.width) { 5715 /* height needs less upscaling/more downscaling */ 5716 dst.width = src.width * 5717 dst.height / src.height; 5718 } else { 5719 /* width needs less upscaling/more downscaling */ 5720 dst.height = src.height * 5721 dst.width / src.width; 5722 } 5723 } else if (rmx_type == RMX_CENTER) { 5724 dst = src; 5725 } 5726 5727 dst.x = (stream->timing.h_addressable - dst.width) / 2; 5728 dst.y = (stream->timing.v_addressable - dst.height) / 2; 5729 5730 if (dm_state->underscan_enable) { 5731 dst.x += dm_state->underscan_hborder / 2; 5732 dst.y += dm_state->underscan_vborder / 2; 5733 dst.width -= dm_state->underscan_hborder; 5734 dst.height -= dm_state->underscan_vborder; 5735 } 5736 } 5737 5738 stream->src = src; 5739 stream->dst = dst; 5740 5741 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n", 5742 dst.x, dst.y, dst.width, dst.height); 5743 5744 } 5745 5746 static enum dc_color_depth 5747 convert_color_depth_from_display_info(const struct drm_connector *connector, 5748 bool is_y420, int requested_bpc) 5749 { 5750 u8 bpc; 5751 5752 if (is_y420) { 5753 bpc = 8; 5754 5755 /* Cap display bpc based on HDMI 2.0 HF-VSDB */ 5756 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) 5757 bpc = 16; 5758 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) 5759 bpc = 12; 5760 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) 5761 bpc = 10; 5762 } else { 5763 bpc = (uint8_t)connector->display_info.bpc; 5764 /* Assume 8 bpc by default if no bpc is specified. */ 5765 bpc = bpc ? bpc : 8; 5766 } 5767 5768 if (requested_bpc > 0) { 5769 /* 5770 * Cap display bpc based on the user requested value. 5771 * 5772 * The value for state->max_bpc may not correctly updated 5773 * depending on when the connector gets added to the state 5774 * or if this was called outside of atomic check, so it 5775 * can't be used directly. 5776 */ 5777 bpc = min_t(u8, bpc, requested_bpc); 5778 5779 /* Round down to the nearest even number. */ 5780 bpc = bpc - (bpc & 1); 5781 } 5782 5783 switch (bpc) { 5784 case 0: 5785 /* 5786 * Temporary Work around, DRM doesn't parse color depth for 5787 * EDID revision before 1.4 5788 * TODO: Fix edid parsing 5789 */ 5790 return COLOR_DEPTH_888; 5791 case 6: 5792 return COLOR_DEPTH_666; 5793 case 8: 5794 return COLOR_DEPTH_888; 5795 case 10: 5796 return COLOR_DEPTH_101010; 5797 case 12: 5798 return COLOR_DEPTH_121212; 5799 case 14: 5800 return COLOR_DEPTH_141414; 5801 case 16: 5802 return COLOR_DEPTH_161616; 5803 default: 5804 return COLOR_DEPTH_UNDEFINED; 5805 } 5806 } 5807 5808 static enum dc_aspect_ratio 5809 get_aspect_ratio(const struct drm_display_mode *mode_in) 5810 { 5811 /* 1-1 mapping, since both enums follow the HDMI spec. */ 5812 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; 5813 } 5814 5815 static enum dc_color_space 5816 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, 5817 const struct drm_connector_state *connector_state) 5818 { 5819 enum dc_color_space color_space = COLOR_SPACE_SRGB; 5820 5821 switch (connector_state->colorspace) { 5822 case DRM_MODE_COLORIMETRY_BT601_YCC: 5823 if (dc_crtc_timing->flags.Y_ONLY) 5824 color_space = COLOR_SPACE_YCBCR601_LIMITED; 5825 else 5826 color_space = COLOR_SPACE_YCBCR601; 5827 break; 5828 case DRM_MODE_COLORIMETRY_BT709_YCC: 5829 if (dc_crtc_timing->flags.Y_ONLY) 5830 color_space = COLOR_SPACE_YCBCR709_LIMITED; 5831 else 5832 color_space = COLOR_SPACE_YCBCR709; 5833 break; 5834 case DRM_MODE_COLORIMETRY_OPRGB: 5835 color_space = COLOR_SPACE_ADOBERGB; 5836 break; 5837 case DRM_MODE_COLORIMETRY_BT2020_RGB: 5838 case DRM_MODE_COLORIMETRY_BT2020_YCC: 5839 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) 5840 color_space = COLOR_SPACE_2020_RGB_FULLRANGE; 5841 else 5842 color_space = COLOR_SPACE_2020_YCBCR; 5843 break; 5844 case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601 5845 default: 5846 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) { 5847 color_space = COLOR_SPACE_SRGB; 5848 /* 5849 * 27030khz is the separation point between HDTV and SDTV 5850 * according to HDMI spec, we use YCbCr709 and YCbCr601 5851 * respectively 5852 */ 5853 } else if (dc_crtc_timing->pix_clk_100hz > 270300) { 5854 if (dc_crtc_timing->flags.Y_ONLY) 5855 color_space = 5856 COLOR_SPACE_YCBCR709_LIMITED; 5857 else 5858 color_space = COLOR_SPACE_YCBCR709; 5859 } else { 5860 if (dc_crtc_timing->flags.Y_ONLY) 5861 color_space = 5862 COLOR_SPACE_YCBCR601_LIMITED; 5863 else 5864 color_space = COLOR_SPACE_YCBCR601; 5865 } 5866 break; 5867 } 5868 5869 return color_space; 5870 } 5871 5872 static enum display_content_type 5873 get_output_content_type(const struct drm_connector_state *connector_state) 5874 { 5875 switch (connector_state->content_type) { 5876 default: 5877 case DRM_MODE_CONTENT_TYPE_NO_DATA: 5878 return DISPLAY_CONTENT_TYPE_NO_DATA; 5879 case DRM_MODE_CONTENT_TYPE_GRAPHICS: 5880 return DISPLAY_CONTENT_TYPE_GRAPHICS; 5881 case DRM_MODE_CONTENT_TYPE_PHOTO: 5882 return DISPLAY_CONTENT_TYPE_PHOTO; 5883 case DRM_MODE_CONTENT_TYPE_CINEMA: 5884 return DISPLAY_CONTENT_TYPE_CINEMA; 5885 case DRM_MODE_CONTENT_TYPE_GAME: 5886 return DISPLAY_CONTENT_TYPE_GAME; 5887 } 5888 } 5889 5890 static bool adjust_colour_depth_from_display_info( 5891 struct dc_crtc_timing *timing_out, 5892 const struct drm_display_info *info) 5893 { 5894 enum dc_color_depth depth = timing_out->display_color_depth; 5895 int normalized_clk; 5896 5897 do { 5898 normalized_clk = timing_out->pix_clk_100hz / 10; 5899 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 5900 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 5901 normalized_clk /= 2; 5902 /* Adjusting pix clock following on HDMI spec based on colour depth */ 5903 switch (depth) { 5904 case COLOR_DEPTH_888: 5905 break; 5906 case COLOR_DEPTH_101010: 5907 normalized_clk = (normalized_clk * 30) / 24; 5908 break; 5909 case COLOR_DEPTH_121212: 5910 normalized_clk = (normalized_clk * 36) / 24; 5911 break; 5912 case COLOR_DEPTH_161616: 5913 normalized_clk = (normalized_clk * 48) / 24; 5914 break; 5915 default: 5916 /* The above depths are the only ones valid for HDMI. */ 5917 return false; 5918 } 5919 if (normalized_clk <= info->max_tmds_clock) { 5920 timing_out->display_color_depth = depth; 5921 return true; 5922 } 5923 } while (--depth > COLOR_DEPTH_666); 5924 return false; 5925 } 5926 5927 static void fill_stream_properties_from_drm_display_mode( 5928 struct dc_stream_state *stream, 5929 const struct drm_display_mode *mode_in, 5930 const struct drm_connector *connector, 5931 const struct drm_connector_state *connector_state, 5932 const struct dc_stream_state *old_stream, 5933 int requested_bpc) 5934 { 5935 struct dc_crtc_timing *timing_out = &stream->timing; 5936 const struct drm_display_info *info = &connector->display_info; 5937 struct amdgpu_dm_connector *aconnector = NULL; 5938 struct hdmi_vendor_infoframe hv_frame; 5939 struct hdmi_avi_infoframe avi_frame; 5940 5941 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 5942 aconnector = to_amdgpu_dm_connector(connector); 5943 5944 memset(&hv_frame, 0, sizeof(hv_frame)); 5945 memset(&avi_frame, 0, sizeof(avi_frame)); 5946 5947 timing_out->h_border_left = 0; 5948 timing_out->h_border_right = 0; 5949 timing_out->v_border_top = 0; 5950 timing_out->v_border_bottom = 0; 5951 /* TODO: un-hardcode */ 5952 if (drm_mode_is_420_only(info, mode_in) 5953 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 5954 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5955 else if (drm_mode_is_420_also(info, mode_in) 5956 && aconnector 5957 && aconnector->force_yuv420_output) 5958 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5959 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444) 5960 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 5961 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; 5962 else 5963 timing_out->pixel_encoding = PIXEL_ENCODING_RGB; 5964 5965 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; 5966 timing_out->display_color_depth = convert_color_depth_from_display_info( 5967 connector, 5968 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420), 5969 requested_bpc); 5970 timing_out->scan_type = SCANNING_TYPE_NODATA; 5971 timing_out->hdmi_vic = 0; 5972 5973 if (old_stream) { 5974 timing_out->vic = old_stream->timing.vic; 5975 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; 5976 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; 5977 } else { 5978 timing_out->vic = drm_match_cea_mode(mode_in); 5979 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) 5980 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; 5981 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) 5982 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; 5983 } 5984 5985 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 5986 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in); 5987 timing_out->vic = avi_frame.video_code; 5988 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in); 5989 timing_out->hdmi_vic = hv_frame.vic; 5990 } 5991 5992 if (aconnector && is_freesync_video_mode(mode_in, aconnector)) { 5993 timing_out->h_addressable = mode_in->hdisplay; 5994 timing_out->h_total = mode_in->htotal; 5995 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start; 5996 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay; 5997 timing_out->v_total = mode_in->vtotal; 5998 timing_out->v_addressable = mode_in->vdisplay; 5999 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay; 6000 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start; 6001 timing_out->pix_clk_100hz = mode_in->clock * 10; 6002 } else { 6003 timing_out->h_addressable = mode_in->crtc_hdisplay; 6004 timing_out->h_total = mode_in->crtc_htotal; 6005 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; 6006 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; 6007 timing_out->v_total = mode_in->crtc_vtotal; 6008 timing_out->v_addressable = mode_in->crtc_vdisplay; 6009 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; 6010 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; 6011 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; 6012 } 6013 6014 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 6015 6016 stream->out_transfer_func.type = TF_TYPE_PREDEFINED; 6017 stream->out_transfer_func.tf = TRANSFER_FUNCTION_SRGB; 6018 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 6019 if (!adjust_colour_depth_from_display_info(timing_out, info) && 6020 drm_mode_is_420_also(info, mode_in) && 6021 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) { 6022 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 6023 adjust_colour_depth_from_display_info(timing_out, info); 6024 } 6025 } 6026 6027 stream->output_color_space = get_output_color_space(timing_out, connector_state); 6028 stream->content_type = get_output_content_type(connector_state); 6029 } 6030 6031 static void fill_audio_info(struct audio_info *audio_info, 6032 const struct drm_connector *drm_connector, 6033 const struct dc_sink *dc_sink) 6034 { 6035 int i = 0; 6036 int cea_revision = 0; 6037 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; 6038 6039 audio_info->manufacture_id = edid_caps->manufacturer_id; 6040 audio_info->product_id = edid_caps->product_id; 6041 6042 cea_revision = drm_connector->display_info.cea_rev; 6043 6044 strscpy(audio_info->display_name, 6045 edid_caps->display_name, 6046 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 6047 6048 if (cea_revision >= 3) { 6049 audio_info->mode_count = edid_caps->audio_mode_count; 6050 6051 for (i = 0; i < audio_info->mode_count; ++i) { 6052 audio_info->modes[i].format_code = 6053 (enum audio_format_code) 6054 (edid_caps->audio_modes[i].format_code); 6055 audio_info->modes[i].channel_count = 6056 edid_caps->audio_modes[i].channel_count; 6057 audio_info->modes[i].sample_rates.all = 6058 edid_caps->audio_modes[i].sample_rate; 6059 audio_info->modes[i].sample_size = 6060 edid_caps->audio_modes[i].sample_size; 6061 } 6062 } 6063 6064 audio_info->flags.all = edid_caps->speaker_flags; 6065 6066 /* TODO: We only check for the progressive mode, check for interlace mode too */ 6067 if (drm_connector->latency_present[0]) { 6068 audio_info->video_latency = drm_connector->video_latency[0]; 6069 audio_info->audio_latency = drm_connector->audio_latency[0]; 6070 } 6071 6072 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ 6073 6074 } 6075 6076 static void 6077 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 6078 struct drm_display_mode *dst_mode) 6079 { 6080 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; 6081 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; 6082 dst_mode->crtc_clock = src_mode->crtc_clock; 6083 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; 6084 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; 6085 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; 6086 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; 6087 dst_mode->crtc_htotal = src_mode->crtc_htotal; 6088 dst_mode->crtc_hskew = src_mode->crtc_hskew; 6089 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; 6090 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; 6091 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; 6092 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; 6093 dst_mode->crtc_vtotal = src_mode->crtc_vtotal; 6094 } 6095 6096 static void 6097 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 6098 const struct drm_display_mode *native_mode, 6099 bool scale_enabled) 6100 { 6101 if (scale_enabled) { 6102 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 6103 } else if (native_mode->clock == drm_mode->clock && 6104 native_mode->htotal == drm_mode->htotal && 6105 native_mode->vtotal == drm_mode->vtotal) { 6106 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 6107 } else { 6108 /* no scaling nor amdgpu inserted, no need to patch */ 6109 } 6110 } 6111 6112 static struct dc_sink * 6113 create_fake_sink(struct dc_link *link) 6114 { 6115 struct dc_sink_init_data sink_init_data = { 0 }; 6116 struct dc_sink *sink = NULL; 6117 6118 sink_init_data.link = link; 6119 sink_init_data.sink_signal = link->connector_signal; 6120 6121 sink = dc_sink_create(&sink_init_data); 6122 if (!sink) { 6123 DRM_ERROR("Failed to create sink!\n"); 6124 return NULL; 6125 } 6126 sink->sink_signal = SIGNAL_TYPE_VIRTUAL; 6127 6128 return sink; 6129 } 6130 6131 static void set_multisync_trigger_params( 6132 struct dc_stream_state *stream) 6133 { 6134 struct dc_stream_state *master = NULL; 6135 6136 if (stream->triggered_crtc_reset.enabled) { 6137 master = stream->triggered_crtc_reset.event_source; 6138 stream->triggered_crtc_reset.event = 6139 master->timing.flags.VSYNC_POSITIVE_POLARITY ? 6140 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING; 6141 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; 6142 } 6143 } 6144 6145 static void set_master_stream(struct dc_stream_state *stream_set[], 6146 int stream_count) 6147 { 6148 int j, highest_rfr = 0, master_stream = 0; 6149 6150 for (j = 0; j < stream_count; j++) { 6151 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 6152 int refresh_rate = 0; 6153 6154 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 6155 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 6156 if (refresh_rate > highest_rfr) { 6157 highest_rfr = refresh_rate; 6158 master_stream = j; 6159 } 6160 } 6161 } 6162 for (j = 0; j < stream_count; j++) { 6163 if (stream_set[j]) 6164 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 6165 } 6166 } 6167 6168 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 6169 { 6170 int i = 0; 6171 struct dc_stream_state *stream; 6172 6173 if (context->stream_count < 2) 6174 return; 6175 for (i = 0; i < context->stream_count ; i++) { 6176 if (!context->streams[i]) 6177 continue; 6178 /* 6179 * TODO: add a function to read AMD VSDB bits and set 6180 * crtc_sync_master.multi_sync_enabled flag 6181 * For now it's set to false 6182 */ 6183 } 6184 6185 set_master_stream(context->streams, context->stream_count); 6186 6187 for (i = 0; i < context->stream_count ; i++) { 6188 stream = context->streams[i]; 6189 6190 if (!stream) 6191 continue; 6192 6193 set_multisync_trigger_params(stream); 6194 } 6195 } 6196 6197 /** 6198 * DOC: FreeSync Video 6199 * 6200 * When a userspace application wants to play a video, the content follows a 6201 * standard format definition that usually specifies the FPS for that format. 6202 * The below list illustrates some video format and the expected FPS, 6203 * respectively: 6204 * 6205 * - TV/NTSC (23.976 FPS) 6206 * - Cinema (24 FPS) 6207 * - TV/PAL (25 FPS) 6208 * - TV/NTSC (29.97 FPS) 6209 * - TV/NTSC (30 FPS) 6210 * - Cinema HFR (48 FPS) 6211 * - TV/PAL (50 FPS) 6212 * - Commonly used (60 FPS) 6213 * - Multiples of 24 (48,72,96 FPS) 6214 * 6215 * The list of standards video format is not huge and can be added to the 6216 * connector modeset list beforehand. With that, userspace can leverage 6217 * FreeSync to extends the front porch in order to attain the target refresh 6218 * rate. Such a switch will happen seamlessly, without screen blanking or 6219 * reprogramming of the output in any other way. If the userspace requests a 6220 * modesetting change compatible with FreeSync modes that only differ in the 6221 * refresh rate, DC will skip the full update and avoid blink during the 6222 * transition. For example, the video player can change the modesetting from 6223 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without 6224 * causing any display blink. This same concept can be applied to a mode 6225 * setting change. 6226 */ 6227 static struct drm_display_mode * 6228 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, 6229 bool use_probed_modes) 6230 { 6231 struct drm_display_mode *m, *m_pref = NULL; 6232 u16 current_refresh, highest_refresh; 6233 struct list_head *list_head = use_probed_modes ? 6234 &aconnector->base.probed_modes : 6235 &aconnector->base.modes; 6236 6237 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 6238 return NULL; 6239 6240 if (aconnector->freesync_vid_base.clock != 0) 6241 return &aconnector->freesync_vid_base; 6242 6243 /* Find the preferred mode */ 6244 list_for_each_entry(m, list_head, head) { 6245 if (m->type & DRM_MODE_TYPE_PREFERRED) { 6246 m_pref = m; 6247 break; 6248 } 6249 } 6250 6251 if (!m_pref) { 6252 /* Probably an EDID with no preferred mode. Fallback to first entry */ 6253 m_pref = list_first_entry_or_null( 6254 &aconnector->base.modes, struct drm_display_mode, head); 6255 if (!m_pref) { 6256 DRM_DEBUG_DRIVER("No preferred mode found in EDID\n"); 6257 return NULL; 6258 } 6259 } 6260 6261 highest_refresh = drm_mode_vrefresh(m_pref); 6262 6263 /* 6264 * Find the mode with highest refresh rate with same resolution. 6265 * For some monitors, preferred mode is not the mode with highest 6266 * supported refresh rate. 6267 */ 6268 list_for_each_entry(m, list_head, head) { 6269 current_refresh = drm_mode_vrefresh(m); 6270 6271 if (m->hdisplay == m_pref->hdisplay && 6272 m->vdisplay == m_pref->vdisplay && 6273 highest_refresh < current_refresh) { 6274 highest_refresh = current_refresh; 6275 m_pref = m; 6276 } 6277 } 6278 6279 drm_mode_copy(&aconnector->freesync_vid_base, m_pref); 6280 return m_pref; 6281 } 6282 6283 static bool is_freesync_video_mode(const struct drm_display_mode *mode, 6284 struct amdgpu_dm_connector *aconnector) 6285 { 6286 struct drm_display_mode *high_mode; 6287 int timing_diff; 6288 6289 high_mode = get_highest_refresh_rate_mode(aconnector, false); 6290 if (!high_mode || !mode) 6291 return false; 6292 6293 timing_diff = high_mode->vtotal - mode->vtotal; 6294 6295 if (high_mode->clock == 0 || high_mode->clock != mode->clock || 6296 high_mode->hdisplay != mode->hdisplay || 6297 high_mode->vdisplay != mode->vdisplay || 6298 high_mode->hsync_start != mode->hsync_start || 6299 high_mode->hsync_end != mode->hsync_end || 6300 high_mode->htotal != mode->htotal || 6301 high_mode->hskew != mode->hskew || 6302 high_mode->vscan != mode->vscan || 6303 high_mode->vsync_start - mode->vsync_start != timing_diff || 6304 high_mode->vsync_end - mode->vsync_end != timing_diff) 6305 return false; 6306 else 6307 return true; 6308 } 6309 6310 #if defined(CONFIG_DRM_AMD_DC_FP) 6311 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector, 6312 struct dc_sink *sink, struct dc_stream_state *stream, 6313 struct dsc_dec_dpcd_caps *dsc_caps) 6314 { 6315 stream->timing.flags.DSC = 0; 6316 dsc_caps->is_dsc_supported = false; 6317 6318 if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || 6319 sink->sink_signal == SIGNAL_TYPE_EDP)) { 6320 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE || 6321 sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) 6322 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 6323 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, 6324 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, 6325 dsc_caps); 6326 } 6327 } 6328 6329 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector, 6330 struct dc_sink *sink, struct dc_stream_state *stream, 6331 struct dsc_dec_dpcd_caps *dsc_caps, 6332 uint32_t max_dsc_target_bpp_limit_override) 6333 { 6334 const struct dc_link_settings *verified_link_cap = NULL; 6335 u32 link_bw_in_kbps; 6336 u32 edp_min_bpp_x16, edp_max_bpp_x16; 6337 struct dc *dc = sink->ctx->dc; 6338 struct dc_dsc_bw_range bw_range = {0}; 6339 struct dc_dsc_config dsc_cfg = {0}; 6340 struct dc_dsc_config_options dsc_options = {0}; 6341 6342 dc_dsc_get_default_config_option(dc, &dsc_options); 6343 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; 6344 6345 verified_link_cap = dc_link_get_link_cap(stream->link); 6346 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap); 6347 edp_min_bpp_x16 = 8 * 16; 6348 edp_max_bpp_x16 = 8 * 16; 6349 6350 if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel) 6351 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel; 6352 6353 if (edp_max_bpp_x16 < edp_min_bpp_x16) 6354 edp_min_bpp_x16 = edp_max_bpp_x16; 6355 6356 if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0], 6357 dc->debug.dsc_min_slice_height_override, 6358 edp_min_bpp_x16, edp_max_bpp_x16, 6359 dsc_caps, 6360 &stream->timing, 6361 dc_link_get_highest_encoding_format(aconnector->dc_link), 6362 &bw_range)) { 6363 6364 if (bw_range.max_kbps < link_bw_in_kbps) { 6365 if (dc_dsc_compute_config(dc->res_pool->dscs[0], 6366 dsc_caps, 6367 &dsc_options, 6368 0, 6369 &stream->timing, 6370 dc_link_get_highest_encoding_format(aconnector->dc_link), 6371 &dsc_cfg)) { 6372 stream->timing.dsc_cfg = dsc_cfg; 6373 stream->timing.flags.DSC = 1; 6374 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16; 6375 } 6376 return; 6377 } 6378 } 6379 6380 if (dc_dsc_compute_config(dc->res_pool->dscs[0], 6381 dsc_caps, 6382 &dsc_options, 6383 link_bw_in_kbps, 6384 &stream->timing, 6385 dc_link_get_highest_encoding_format(aconnector->dc_link), 6386 &dsc_cfg)) { 6387 stream->timing.dsc_cfg = dsc_cfg; 6388 stream->timing.flags.DSC = 1; 6389 } 6390 } 6391 6392 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, 6393 struct dc_sink *sink, struct dc_stream_state *stream, 6394 struct dsc_dec_dpcd_caps *dsc_caps) 6395 { 6396 struct drm_connector *drm_connector = &aconnector->base; 6397 u32 link_bandwidth_kbps; 6398 struct dc *dc = sink->ctx->dc; 6399 u32 max_supported_bw_in_kbps, timing_bw_in_kbps; 6400 u32 dsc_max_supported_bw_in_kbps; 6401 u32 max_dsc_target_bpp_limit_override = 6402 drm_connector->display_info.max_dsc_bpp; 6403 struct dc_dsc_config_options dsc_options = {0}; 6404 6405 dc_dsc_get_default_config_option(dc, &dsc_options); 6406 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; 6407 6408 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, 6409 dc_link_get_link_cap(aconnector->dc_link)); 6410 6411 /* Set DSC policy according to dsc_clock_en */ 6412 dc_dsc_policy_set_enable_dsc_when_not_needed( 6413 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE); 6414 6415 if (sink->sink_signal == SIGNAL_TYPE_EDP && 6416 !aconnector->dc_link->panel_config.dsc.disable_dsc_edp && 6417 dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) { 6418 6419 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override); 6420 6421 } else if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { 6422 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { 6423 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 6424 dsc_caps, 6425 &dsc_options, 6426 link_bandwidth_kbps, 6427 &stream->timing, 6428 dc_link_get_highest_encoding_format(aconnector->dc_link), 6429 &stream->timing.dsc_cfg)) { 6430 stream->timing.flags.DSC = 1; 6431 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name); 6432 } 6433 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 6434 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing, 6435 dc_link_get_highest_encoding_format(aconnector->dc_link)); 6436 max_supported_bw_in_kbps = link_bandwidth_kbps; 6437 dsc_max_supported_bw_in_kbps = link_bandwidth_kbps; 6438 6439 if (timing_bw_in_kbps > max_supported_bw_in_kbps && 6440 max_supported_bw_in_kbps > 0 && 6441 dsc_max_supported_bw_in_kbps > 0) 6442 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 6443 dsc_caps, 6444 &dsc_options, 6445 dsc_max_supported_bw_in_kbps, 6446 &stream->timing, 6447 dc_link_get_highest_encoding_format(aconnector->dc_link), 6448 &stream->timing.dsc_cfg)) { 6449 stream->timing.flags.DSC = 1; 6450 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n", 6451 __func__, drm_connector->name); 6452 } 6453 } 6454 } 6455 6456 /* Overwrite the stream flag if DSC is enabled through debugfs */ 6457 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE) 6458 stream->timing.flags.DSC = 1; 6459 6460 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h) 6461 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; 6462 6463 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v) 6464 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; 6465 6466 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel) 6467 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel; 6468 } 6469 #endif 6470 6471 static struct dc_stream_state * 6472 create_stream_for_sink(struct drm_connector *connector, 6473 const struct drm_display_mode *drm_mode, 6474 const struct dm_connector_state *dm_state, 6475 const struct dc_stream_state *old_stream, 6476 int requested_bpc) 6477 { 6478 struct amdgpu_dm_connector *aconnector = NULL; 6479 struct drm_display_mode *preferred_mode = NULL; 6480 const struct drm_connector_state *con_state = &dm_state->base; 6481 struct dc_stream_state *stream = NULL; 6482 struct drm_display_mode mode; 6483 struct drm_display_mode saved_mode; 6484 struct drm_display_mode *freesync_mode = NULL; 6485 bool native_mode_found = false; 6486 bool recalculate_timing = false; 6487 bool scale = dm_state->scaling != RMX_OFF; 6488 int mode_refresh; 6489 int preferred_refresh = 0; 6490 enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN; 6491 #if defined(CONFIG_DRM_AMD_DC_FP) 6492 struct dsc_dec_dpcd_caps dsc_caps; 6493 #endif 6494 struct dc_link *link = NULL; 6495 struct dc_sink *sink = NULL; 6496 6497 drm_mode_init(&mode, drm_mode); 6498 memset(&saved_mode, 0, sizeof(saved_mode)); 6499 6500 if (connector == NULL) { 6501 DRM_ERROR("connector is NULL!\n"); 6502 return stream; 6503 } 6504 6505 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) { 6506 aconnector = NULL; 6507 aconnector = to_amdgpu_dm_connector(connector); 6508 link = aconnector->dc_link; 6509 } else { 6510 struct drm_writeback_connector *wbcon = NULL; 6511 struct amdgpu_dm_wb_connector *dm_wbcon = NULL; 6512 6513 wbcon = drm_connector_to_writeback(connector); 6514 dm_wbcon = to_amdgpu_dm_wb_connector(wbcon); 6515 link = dm_wbcon->link; 6516 } 6517 6518 if (!aconnector || !aconnector->dc_sink) { 6519 sink = create_fake_sink(link); 6520 if (!sink) 6521 return stream; 6522 6523 } else { 6524 sink = aconnector->dc_sink; 6525 dc_sink_retain(sink); 6526 } 6527 6528 stream = dc_create_stream_for_sink(sink); 6529 6530 if (stream == NULL) { 6531 DRM_ERROR("Failed to create stream for sink!\n"); 6532 goto finish; 6533 } 6534 6535 /* We leave this NULL for writeback connectors */ 6536 stream->dm_stream_context = aconnector; 6537 6538 stream->timing.flags.LTE_340MCSC_SCRAMBLE = 6539 connector->display_info.hdmi.scdc.scrambling.low_rates; 6540 6541 list_for_each_entry(preferred_mode, &connector->modes, head) { 6542 /* Search for preferred mode */ 6543 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { 6544 native_mode_found = true; 6545 break; 6546 } 6547 } 6548 if (!native_mode_found) 6549 preferred_mode = list_first_entry_or_null( 6550 &connector->modes, 6551 struct drm_display_mode, 6552 head); 6553 6554 mode_refresh = drm_mode_vrefresh(&mode); 6555 6556 if (preferred_mode == NULL) { 6557 /* 6558 * This may not be an error, the use case is when we have no 6559 * usermode calls to reset and set mode upon hotplug. In this 6560 * case, we call set mode ourselves to restore the previous mode 6561 * and the modelist may not be filled in time. 6562 */ 6563 DRM_DEBUG_DRIVER("No preferred mode found\n"); 6564 } else if (aconnector) { 6565 recalculate_timing = amdgpu_freesync_vid_mode && 6566 is_freesync_video_mode(&mode, aconnector); 6567 if (recalculate_timing) { 6568 freesync_mode = get_highest_refresh_rate_mode(aconnector, false); 6569 drm_mode_copy(&saved_mode, &mode); 6570 saved_mode.picture_aspect_ratio = mode.picture_aspect_ratio; 6571 drm_mode_copy(&mode, freesync_mode); 6572 mode.picture_aspect_ratio = saved_mode.picture_aspect_ratio; 6573 } else { 6574 decide_crtc_timing_for_drm_display_mode( 6575 &mode, preferred_mode, scale); 6576 6577 preferred_refresh = drm_mode_vrefresh(preferred_mode); 6578 } 6579 } 6580 6581 if (recalculate_timing) 6582 drm_mode_set_crtcinfo(&saved_mode, 0); 6583 6584 /* 6585 * If scaling is enabled and refresh rate didn't change 6586 * we copy the vic and polarities of the old timings 6587 */ 6588 if (!scale || mode_refresh != preferred_refresh) 6589 fill_stream_properties_from_drm_display_mode( 6590 stream, &mode, connector, con_state, NULL, 6591 requested_bpc); 6592 else 6593 fill_stream_properties_from_drm_display_mode( 6594 stream, &mode, connector, con_state, old_stream, 6595 requested_bpc); 6596 6597 /* The rest isn't needed for writeback connectors */ 6598 if (!aconnector) 6599 goto finish; 6600 6601 if (aconnector->timing_changed) { 6602 drm_dbg(aconnector->base.dev, 6603 "overriding timing for automated test, bpc %d, changing to %d\n", 6604 stream->timing.display_color_depth, 6605 aconnector->timing_requested->display_color_depth); 6606 stream->timing = *aconnector->timing_requested; 6607 } 6608 6609 #if defined(CONFIG_DRM_AMD_DC_FP) 6610 /* SST DSC determination policy */ 6611 update_dsc_caps(aconnector, sink, stream, &dsc_caps); 6612 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) 6613 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps); 6614 #endif 6615 6616 update_stream_scaling_settings(&mode, dm_state, stream); 6617 6618 fill_audio_info( 6619 &stream->audio_info, 6620 connector, 6621 sink); 6622 6623 update_stream_signal(stream, sink); 6624 6625 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 6626 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket); 6627 6628 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 6629 stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 6630 stream->signal == SIGNAL_TYPE_EDP) { 6631 // 6632 // should decide stream support vsc sdp colorimetry capability 6633 // before building vsc info packet 6634 // 6635 stream->use_vsc_sdp_for_colorimetry = stream->link->dpcd_caps.dpcd_rev.raw >= 0x14 && 6636 stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED; 6637 6638 if (stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) 6639 tf = TRANSFER_FUNC_GAMMA_22; 6640 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf); 6641 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY; 6642 6643 } 6644 finish: 6645 dc_sink_release(sink); 6646 6647 return stream; 6648 } 6649 6650 static enum drm_connector_status 6651 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 6652 { 6653 bool connected; 6654 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6655 6656 /* 6657 * Notes: 6658 * 1. This interface is NOT called in context of HPD irq. 6659 * 2. This interface *is called* in context of user-mode ioctl. Which 6660 * makes it a bad place for *any* MST-related activity. 6661 */ 6662 6663 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && 6664 !aconnector->fake_enable) 6665 connected = (aconnector->dc_sink != NULL); 6666 else 6667 connected = (aconnector->base.force == DRM_FORCE_ON || 6668 aconnector->base.force == DRM_FORCE_ON_DIGITAL); 6669 6670 update_subconnector_property(aconnector); 6671 6672 return (connected ? connector_status_connected : 6673 connector_status_disconnected); 6674 } 6675 6676 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 6677 struct drm_connector_state *connector_state, 6678 struct drm_property *property, 6679 uint64_t val) 6680 { 6681 struct drm_device *dev = connector->dev; 6682 struct amdgpu_device *adev = drm_to_adev(dev); 6683 struct dm_connector_state *dm_old_state = 6684 to_dm_connector_state(connector->state); 6685 struct dm_connector_state *dm_new_state = 6686 to_dm_connector_state(connector_state); 6687 6688 int ret = -EINVAL; 6689 6690 if (property == dev->mode_config.scaling_mode_property) { 6691 enum amdgpu_rmx_type rmx_type; 6692 6693 switch (val) { 6694 case DRM_MODE_SCALE_CENTER: 6695 rmx_type = RMX_CENTER; 6696 break; 6697 case DRM_MODE_SCALE_ASPECT: 6698 rmx_type = RMX_ASPECT; 6699 break; 6700 case DRM_MODE_SCALE_FULLSCREEN: 6701 rmx_type = RMX_FULL; 6702 break; 6703 case DRM_MODE_SCALE_NONE: 6704 default: 6705 rmx_type = RMX_OFF; 6706 break; 6707 } 6708 6709 if (dm_old_state->scaling == rmx_type) 6710 return 0; 6711 6712 dm_new_state->scaling = rmx_type; 6713 ret = 0; 6714 } else if (property == adev->mode_info.underscan_hborder_property) { 6715 dm_new_state->underscan_hborder = val; 6716 ret = 0; 6717 } else if (property == adev->mode_info.underscan_vborder_property) { 6718 dm_new_state->underscan_vborder = val; 6719 ret = 0; 6720 } else if (property == adev->mode_info.underscan_property) { 6721 dm_new_state->underscan_enable = val; 6722 ret = 0; 6723 } 6724 6725 return ret; 6726 } 6727 6728 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 6729 const struct drm_connector_state *state, 6730 struct drm_property *property, 6731 uint64_t *val) 6732 { 6733 struct drm_device *dev = connector->dev; 6734 struct amdgpu_device *adev = drm_to_adev(dev); 6735 struct dm_connector_state *dm_state = 6736 to_dm_connector_state(state); 6737 int ret = -EINVAL; 6738 6739 if (property == dev->mode_config.scaling_mode_property) { 6740 switch (dm_state->scaling) { 6741 case RMX_CENTER: 6742 *val = DRM_MODE_SCALE_CENTER; 6743 break; 6744 case RMX_ASPECT: 6745 *val = DRM_MODE_SCALE_ASPECT; 6746 break; 6747 case RMX_FULL: 6748 *val = DRM_MODE_SCALE_FULLSCREEN; 6749 break; 6750 case RMX_OFF: 6751 default: 6752 *val = DRM_MODE_SCALE_NONE; 6753 break; 6754 } 6755 ret = 0; 6756 } else if (property == adev->mode_info.underscan_hborder_property) { 6757 *val = dm_state->underscan_hborder; 6758 ret = 0; 6759 } else if (property == adev->mode_info.underscan_vborder_property) { 6760 *val = dm_state->underscan_vborder; 6761 ret = 0; 6762 } else if (property == adev->mode_info.underscan_property) { 6763 *val = dm_state->underscan_enable; 6764 ret = 0; 6765 } 6766 6767 return ret; 6768 } 6769 6770 /** 6771 * DOC: panel power savings 6772 * 6773 * The display manager allows you to set your desired **panel power savings** 6774 * level (between 0-4, with 0 representing off), e.g. using the following:: 6775 * 6776 * # echo 3 > /sys/class/drm/card0-eDP-1/amdgpu/panel_power_savings 6777 * 6778 * Modifying this value can have implications on color accuracy, so tread 6779 * carefully. 6780 */ 6781 6782 static ssize_t panel_power_savings_show(struct device *device, 6783 struct device_attribute *attr, 6784 char *buf) 6785 { 6786 struct drm_connector *connector = dev_get_drvdata(device); 6787 struct drm_device *dev = connector->dev; 6788 u8 val; 6789 6790 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 6791 val = to_dm_connector_state(connector->state)->abm_level == 6792 ABM_LEVEL_IMMEDIATE_DISABLE ? 0 : 6793 to_dm_connector_state(connector->state)->abm_level; 6794 drm_modeset_unlock(&dev->mode_config.connection_mutex); 6795 6796 return sysfs_emit(buf, "%u\n", val); 6797 } 6798 6799 static ssize_t panel_power_savings_store(struct device *device, 6800 struct device_attribute *attr, 6801 const char *buf, size_t count) 6802 { 6803 struct drm_connector *connector = dev_get_drvdata(device); 6804 struct drm_device *dev = connector->dev; 6805 long val; 6806 int ret; 6807 6808 ret = kstrtol(buf, 0, &val); 6809 6810 if (ret) 6811 return ret; 6812 6813 if (val < 0 || val > 4) 6814 return -EINVAL; 6815 6816 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 6817 to_dm_connector_state(connector->state)->abm_level = val ?: 6818 ABM_LEVEL_IMMEDIATE_DISABLE; 6819 drm_modeset_unlock(&dev->mode_config.connection_mutex); 6820 6821 drm_kms_helper_hotplug_event(dev); 6822 6823 return count; 6824 } 6825 6826 static DEVICE_ATTR_RW(panel_power_savings); 6827 6828 static struct attribute *amdgpu_attrs[] = { 6829 &dev_attr_panel_power_savings.attr, 6830 NULL 6831 }; 6832 6833 static const struct attribute_group amdgpu_group = { 6834 .name = "amdgpu", 6835 .attrs = amdgpu_attrs 6836 }; 6837 6838 static bool 6839 amdgpu_dm_should_create_sysfs(struct amdgpu_dm_connector *amdgpu_dm_connector) 6840 { 6841 if (amdgpu_dm_abm_level >= 0) 6842 return false; 6843 6844 if (amdgpu_dm_connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) 6845 return false; 6846 6847 /* check for OLED panels */ 6848 if (amdgpu_dm_connector->bl_idx >= 0) { 6849 struct drm_device *drm = amdgpu_dm_connector->base.dev; 6850 struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm; 6851 struct amdgpu_dm_backlight_caps *caps; 6852 6853 caps = &dm->backlight_caps[amdgpu_dm_connector->bl_idx]; 6854 if (caps->aux_support) 6855 return false; 6856 } 6857 6858 return true; 6859 } 6860 6861 static void amdgpu_dm_connector_unregister(struct drm_connector *connector) 6862 { 6863 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); 6864 6865 if (amdgpu_dm_should_create_sysfs(amdgpu_dm_connector)) 6866 sysfs_remove_group(&connector->kdev->kobj, &amdgpu_group); 6867 6868 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); 6869 } 6870 6871 static void amdgpu_dm_connector_destroy(struct drm_connector *connector) 6872 { 6873 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6874 struct amdgpu_device *adev = drm_to_adev(connector->dev); 6875 struct amdgpu_display_manager *dm = &adev->dm; 6876 6877 /* 6878 * Call only if mst_mgr was initialized before since it's not done 6879 * for all connector types. 6880 */ 6881 if (aconnector->mst_mgr.dev) 6882 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr); 6883 6884 if (aconnector->bl_idx != -1) { 6885 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]); 6886 dm->backlight_dev[aconnector->bl_idx] = NULL; 6887 } 6888 6889 if (aconnector->dc_em_sink) 6890 dc_sink_release(aconnector->dc_em_sink); 6891 aconnector->dc_em_sink = NULL; 6892 if (aconnector->dc_sink) 6893 dc_sink_release(aconnector->dc_sink); 6894 aconnector->dc_sink = NULL; 6895 6896 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); 6897 drm_connector_unregister(connector); 6898 drm_connector_cleanup(connector); 6899 if (aconnector->i2c) { 6900 i2c_del_adapter(&aconnector->i2c->base); 6901 kfree(aconnector->i2c); 6902 } 6903 kfree(aconnector->dm_dp_aux.aux.name); 6904 6905 kfree(connector); 6906 } 6907 6908 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) 6909 { 6910 struct dm_connector_state *state = 6911 to_dm_connector_state(connector->state); 6912 6913 if (connector->state) 6914 __drm_atomic_helper_connector_destroy_state(connector->state); 6915 6916 kfree(state); 6917 6918 state = kzalloc(sizeof(*state), GFP_KERNEL); 6919 6920 if (state) { 6921 state->scaling = RMX_OFF; 6922 state->underscan_enable = false; 6923 state->underscan_hborder = 0; 6924 state->underscan_vborder = 0; 6925 state->base.max_requested_bpc = 8; 6926 state->vcpi_slots = 0; 6927 state->pbn = 0; 6928 6929 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 6930 if (amdgpu_dm_abm_level <= 0) 6931 state->abm_level = ABM_LEVEL_IMMEDIATE_DISABLE; 6932 else 6933 state->abm_level = amdgpu_dm_abm_level; 6934 } 6935 6936 __drm_atomic_helper_connector_reset(connector, &state->base); 6937 } 6938 } 6939 6940 struct drm_connector_state * 6941 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) 6942 { 6943 struct dm_connector_state *state = 6944 to_dm_connector_state(connector->state); 6945 6946 struct dm_connector_state *new_state = 6947 kmemdup(state, sizeof(*state), GFP_KERNEL); 6948 6949 if (!new_state) 6950 return NULL; 6951 6952 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 6953 6954 new_state->freesync_capable = state->freesync_capable; 6955 new_state->abm_level = state->abm_level; 6956 new_state->scaling = state->scaling; 6957 new_state->underscan_enable = state->underscan_enable; 6958 new_state->underscan_hborder = state->underscan_hborder; 6959 new_state->underscan_vborder = state->underscan_vborder; 6960 new_state->vcpi_slots = state->vcpi_slots; 6961 new_state->pbn = state->pbn; 6962 return &new_state->base; 6963 } 6964 6965 static int 6966 amdgpu_dm_connector_late_register(struct drm_connector *connector) 6967 { 6968 struct amdgpu_dm_connector *amdgpu_dm_connector = 6969 to_amdgpu_dm_connector(connector); 6970 int r; 6971 6972 if (amdgpu_dm_should_create_sysfs(amdgpu_dm_connector)) { 6973 r = sysfs_create_group(&connector->kdev->kobj, 6974 &amdgpu_group); 6975 if (r) 6976 return r; 6977 } 6978 6979 amdgpu_dm_register_backlight_device(amdgpu_dm_connector); 6980 6981 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 6982 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 6983 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev; 6984 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux); 6985 if (r) 6986 return r; 6987 } 6988 6989 #if defined(CONFIG_DEBUG_FS) 6990 connector_debugfs_init(amdgpu_dm_connector); 6991 #endif 6992 6993 return 0; 6994 } 6995 6996 static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) 6997 { 6998 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6999 struct dc_link *dc_link = aconnector->dc_link; 7000 struct dc_sink *dc_em_sink = aconnector->dc_em_sink; 7001 struct edid *edid; 7002 struct i2c_adapter *ddc; 7003 7004 if (dc_link && dc_link->aux_mode) 7005 ddc = &aconnector->dm_dp_aux.aux.ddc; 7006 else 7007 ddc = &aconnector->i2c->base; 7008 7009 /* 7010 * Note: drm_get_edid gets edid in the following order: 7011 * 1) override EDID if set via edid_override debugfs, 7012 * 2) firmware EDID if set via edid_firmware module parameter 7013 * 3) regular DDC read. 7014 */ 7015 edid = drm_get_edid(connector, ddc); 7016 if (!edid) { 7017 DRM_ERROR("No EDID found on connector: %s.\n", connector->name); 7018 return; 7019 } 7020 7021 aconnector->edid = edid; 7022 7023 /* Update emulated (virtual) sink's EDID */ 7024 if (dc_em_sink && dc_link) { 7025 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps)); 7026 memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH); 7027 dm_helpers_parse_edid_caps( 7028 dc_link, 7029 &dc_em_sink->dc_edid, 7030 &dc_em_sink->edid_caps); 7031 } 7032 } 7033 7034 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 7035 .reset = amdgpu_dm_connector_funcs_reset, 7036 .detect = amdgpu_dm_connector_detect, 7037 .fill_modes = drm_helper_probe_single_connector_modes, 7038 .destroy = amdgpu_dm_connector_destroy, 7039 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 7040 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 7041 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 7042 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 7043 .late_register = amdgpu_dm_connector_late_register, 7044 .early_unregister = amdgpu_dm_connector_unregister, 7045 .force = amdgpu_dm_connector_funcs_force 7046 }; 7047 7048 static int get_modes(struct drm_connector *connector) 7049 { 7050 return amdgpu_dm_connector_get_modes(connector); 7051 } 7052 7053 static void create_eml_sink(struct amdgpu_dm_connector *aconnector) 7054 { 7055 struct drm_connector *connector = &aconnector->base; 7056 struct dc_link *dc_link = aconnector->dc_link; 7057 struct dc_sink_init_data init_params = { 7058 .link = aconnector->dc_link, 7059 .sink_signal = SIGNAL_TYPE_VIRTUAL 7060 }; 7061 struct edid *edid; 7062 struct i2c_adapter *ddc; 7063 7064 if (dc_link->aux_mode) 7065 ddc = &aconnector->dm_dp_aux.aux.ddc; 7066 else 7067 ddc = &aconnector->i2c->base; 7068 7069 /* 7070 * Note: drm_get_edid gets edid in the following order: 7071 * 1) override EDID if set via edid_override debugfs, 7072 * 2) firmware EDID if set via edid_firmware module parameter 7073 * 3) regular DDC read. 7074 */ 7075 edid = drm_get_edid(connector, ddc); 7076 if (!edid) { 7077 DRM_ERROR("No EDID found on connector: %s.\n", connector->name); 7078 return; 7079 } 7080 7081 if (drm_detect_hdmi_monitor(edid)) 7082 init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A; 7083 7084 aconnector->edid = edid; 7085 7086 aconnector->dc_em_sink = dc_link_add_remote_sink( 7087 aconnector->dc_link, 7088 (uint8_t *)edid, 7089 (edid->extensions + 1) * EDID_LENGTH, 7090 &init_params); 7091 7092 if (aconnector->base.force == DRM_FORCE_ON) { 7093 aconnector->dc_sink = aconnector->dc_link->local_sink ? 7094 aconnector->dc_link->local_sink : 7095 aconnector->dc_em_sink; 7096 if (aconnector->dc_sink) 7097 dc_sink_retain(aconnector->dc_sink); 7098 } 7099 } 7100 7101 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) 7102 { 7103 struct dc_link *link = (struct dc_link *)aconnector->dc_link; 7104 7105 /* 7106 * In case of headless boot with force on for DP managed connector 7107 * Those settings have to be != 0 to get initial modeset 7108 */ 7109 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { 7110 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; 7111 link->verified_link_cap.link_rate = LINK_RATE_HIGH2; 7112 } 7113 7114 create_eml_sink(aconnector); 7115 } 7116 7117 static enum dc_status dm_validate_stream_and_context(struct dc *dc, 7118 struct dc_stream_state *stream) 7119 { 7120 enum dc_status dc_result = DC_ERROR_UNEXPECTED; 7121 struct dc_plane_state *dc_plane_state = NULL; 7122 struct dc_state *dc_state = NULL; 7123 7124 if (!stream) 7125 goto cleanup; 7126 7127 dc_plane_state = dc_create_plane_state(dc); 7128 if (!dc_plane_state) 7129 goto cleanup; 7130 7131 dc_state = dc_state_create(dc, NULL); 7132 if (!dc_state) 7133 goto cleanup; 7134 7135 /* populate stream to plane */ 7136 dc_plane_state->src_rect.height = stream->src.height; 7137 dc_plane_state->src_rect.width = stream->src.width; 7138 dc_plane_state->dst_rect.height = stream->src.height; 7139 dc_plane_state->dst_rect.width = stream->src.width; 7140 dc_plane_state->clip_rect.height = stream->src.height; 7141 dc_plane_state->clip_rect.width = stream->src.width; 7142 dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256; 7143 dc_plane_state->plane_size.surface_size.height = stream->src.height; 7144 dc_plane_state->plane_size.surface_size.width = stream->src.width; 7145 dc_plane_state->plane_size.chroma_size.height = stream->src.height; 7146 dc_plane_state->plane_size.chroma_size.width = stream->src.width; 7147 dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 7148 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; 7149 dc_plane_state->rotation = ROTATION_ANGLE_0; 7150 dc_plane_state->is_tiling_rotated = false; 7151 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL; 7152 7153 dc_result = dc_validate_stream(dc, stream); 7154 if (dc_result == DC_OK) 7155 dc_result = dc_validate_plane(dc, dc_plane_state); 7156 7157 if (dc_result == DC_OK) 7158 dc_result = dc_state_add_stream(dc, dc_state, stream); 7159 7160 if (dc_result == DC_OK && !dc_state_add_plane( 7161 dc, 7162 stream, 7163 dc_plane_state, 7164 dc_state)) 7165 dc_result = DC_FAIL_ATTACH_SURFACES; 7166 7167 if (dc_result == DC_OK) 7168 dc_result = dc_validate_global_state(dc, dc_state, true); 7169 7170 cleanup: 7171 if (dc_state) 7172 dc_state_release(dc_state); 7173 7174 if (dc_plane_state) 7175 dc_plane_state_release(dc_plane_state); 7176 7177 return dc_result; 7178 } 7179 7180 struct dc_stream_state * 7181 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, 7182 const struct drm_display_mode *drm_mode, 7183 const struct dm_connector_state *dm_state, 7184 const struct dc_stream_state *old_stream) 7185 { 7186 struct drm_connector *connector = &aconnector->base; 7187 struct amdgpu_device *adev = drm_to_adev(connector->dev); 7188 struct dc_stream_state *stream; 7189 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL; 7190 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8; 7191 enum dc_status dc_result = DC_OK; 7192 7193 do { 7194 stream = create_stream_for_sink(connector, drm_mode, 7195 dm_state, old_stream, 7196 requested_bpc); 7197 if (stream == NULL) { 7198 DRM_ERROR("Failed to create stream for sink!\n"); 7199 break; 7200 } 7201 7202 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 7203 return stream; 7204 7205 dc_result = dc_validate_stream(adev->dm.dc, stream); 7206 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 7207 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream); 7208 7209 if (dc_result == DC_OK) 7210 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream); 7211 7212 if (dc_result != DC_OK) { 7213 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n", 7214 drm_mode->hdisplay, 7215 drm_mode->vdisplay, 7216 drm_mode->clock, 7217 dc_result, 7218 dc_status_to_str(dc_result)); 7219 7220 dc_stream_release(stream); 7221 stream = NULL; 7222 requested_bpc -= 2; /* lower bpc to retry validation */ 7223 } 7224 7225 } while (stream == NULL && requested_bpc >= 6); 7226 7227 if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) { 7228 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n"); 7229 7230 aconnector->force_yuv420_output = true; 7231 stream = create_validate_stream_for_sink(aconnector, drm_mode, 7232 dm_state, old_stream); 7233 aconnector->force_yuv420_output = false; 7234 } 7235 7236 return stream; 7237 } 7238 7239 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 7240 struct drm_display_mode *mode) 7241 { 7242 int result = MODE_ERROR; 7243 struct dc_sink *dc_sink; 7244 /* TODO: Unhardcode stream count */ 7245 struct dc_stream_state *stream; 7246 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 7247 7248 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 7249 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) 7250 return result; 7251 7252 /* 7253 * Only run this the first time mode_valid is called to initilialize 7254 * EDID mgmt 7255 */ 7256 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && 7257 !aconnector->dc_em_sink) 7258 handle_edid_mgmt(aconnector); 7259 7260 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; 7261 7262 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL && 7263 aconnector->base.force != DRM_FORCE_ON) { 7264 DRM_ERROR("dc_sink is NULL!\n"); 7265 goto fail; 7266 } 7267 7268 drm_mode_set_crtcinfo(mode, 0); 7269 7270 stream = create_validate_stream_for_sink(aconnector, mode, 7271 to_dm_connector_state(connector->state), 7272 NULL); 7273 if (stream) { 7274 dc_stream_release(stream); 7275 result = MODE_OK; 7276 } 7277 7278 fail: 7279 /* TODO: error handling*/ 7280 return result; 7281 } 7282 7283 static int fill_hdr_info_packet(const struct drm_connector_state *state, 7284 struct dc_info_packet *out) 7285 { 7286 struct hdmi_drm_infoframe frame; 7287 unsigned char buf[30]; /* 26 + 4 */ 7288 ssize_t len; 7289 int ret, i; 7290 7291 memset(out, 0, sizeof(*out)); 7292 7293 if (!state->hdr_output_metadata) 7294 return 0; 7295 7296 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); 7297 if (ret) 7298 return ret; 7299 7300 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); 7301 if (len < 0) 7302 return (int)len; 7303 7304 /* Static metadata is a fixed 26 bytes + 4 byte header. */ 7305 if (len != 30) 7306 return -EINVAL; 7307 7308 /* Prepare the infopacket for DC. */ 7309 switch (state->connector->connector_type) { 7310 case DRM_MODE_CONNECTOR_HDMIA: 7311 out->hb0 = 0x87; /* type */ 7312 out->hb1 = 0x01; /* version */ 7313 out->hb2 = 0x1A; /* length */ 7314 out->sb[0] = buf[3]; /* checksum */ 7315 i = 1; 7316 break; 7317 7318 case DRM_MODE_CONNECTOR_DisplayPort: 7319 case DRM_MODE_CONNECTOR_eDP: 7320 out->hb0 = 0x00; /* sdp id, zero */ 7321 out->hb1 = 0x87; /* type */ 7322 out->hb2 = 0x1D; /* payload len - 1 */ 7323 out->hb3 = (0x13 << 2); /* sdp version */ 7324 out->sb[0] = 0x01; /* version */ 7325 out->sb[1] = 0x1A; /* length */ 7326 i = 2; 7327 break; 7328 7329 default: 7330 return -EINVAL; 7331 } 7332 7333 memcpy(&out->sb[i], &buf[4], 26); 7334 out->valid = true; 7335 7336 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, 7337 sizeof(out->sb), false); 7338 7339 return 0; 7340 } 7341 7342 static int 7343 amdgpu_dm_connector_atomic_check(struct drm_connector *conn, 7344 struct drm_atomic_state *state) 7345 { 7346 struct drm_connector_state *new_con_state = 7347 drm_atomic_get_new_connector_state(state, conn); 7348 struct drm_connector_state *old_con_state = 7349 drm_atomic_get_old_connector_state(state, conn); 7350 struct drm_crtc *crtc = new_con_state->crtc; 7351 struct drm_crtc_state *new_crtc_state; 7352 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn); 7353 int ret; 7354 7355 trace_amdgpu_dm_connector_atomic_check(new_con_state); 7356 7357 if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 7358 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr); 7359 if (ret < 0) 7360 return ret; 7361 } 7362 7363 if (!crtc) 7364 return 0; 7365 7366 if (new_con_state->colorspace != old_con_state->colorspace) { 7367 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 7368 if (IS_ERR(new_crtc_state)) 7369 return PTR_ERR(new_crtc_state); 7370 7371 new_crtc_state->mode_changed = true; 7372 } 7373 7374 if (new_con_state->content_type != old_con_state->content_type) { 7375 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 7376 if (IS_ERR(new_crtc_state)) 7377 return PTR_ERR(new_crtc_state); 7378 7379 new_crtc_state->mode_changed = true; 7380 } 7381 7382 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) { 7383 struct dc_info_packet hdr_infopacket; 7384 7385 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); 7386 if (ret) 7387 return ret; 7388 7389 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 7390 if (IS_ERR(new_crtc_state)) 7391 return PTR_ERR(new_crtc_state); 7392 7393 /* 7394 * DC considers the stream backends changed if the 7395 * static metadata changes. Forcing the modeset also 7396 * gives a simple way for userspace to switch from 7397 * 8bpc to 10bpc when setting the metadata to enter 7398 * or exit HDR. 7399 * 7400 * Changing the static metadata after it's been 7401 * set is permissible, however. So only force a 7402 * modeset if we're entering or exiting HDR. 7403 */ 7404 new_crtc_state->mode_changed = new_crtc_state->mode_changed || 7405 !old_con_state->hdr_output_metadata || 7406 !new_con_state->hdr_output_metadata; 7407 } 7408 7409 return 0; 7410 } 7411 7412 static const struct drm_connector_helper_funcs 7413 amdgpu_dm_connector_helper_funcs = { 7414 /* 7415 * If hotplugging a second bigger display in FB Con mode, bigger resolution 7416 * modes will be filtered by drm_mode_validate_size(), and those modes 7417 * are missing after user start lightdm. So we need to renew modes list. 7418 * in get_modes call back, not just return the modes count 7419 */ 7420 .get_modes = get_modes, 7421 .mode_valid = amdgpu_dm_connector_mode_valid, 7422 .atomic_check = amdgpu_dm_connector_atomic_check, 7423 }; 7424 7425 static void dm_encoder_helper_disable(struct drm_encoder *encoder) 7426 { 7427 7428 } 7429 7430 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) 7431 { 7432 switch (display_color_depth) { 7433 case COLOR_DEPTH_666: 7434 return 6; 7435 case COLOR_DEPTH_888: 7436 return 8; 7437 case COLOR_DEPTH_101010: 7438 return 10; 7439 case COLOR_DEPTH_121212: 7440 return 12; 7441 case COLOR_DEPTH_141414: 7442 return 14; 7443 case COLOR_DEPTH_161616: 7444 return 16; 7445 default: 7446 break; 7447 } 7448 return 0; 7449 } 7450 7451 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 7452 struct drm_crtc_state *crtc_state, 7453 struct drm_connector_state *conn_state) 7454 { 7455 struct drm_atomic_state *state = crtc_state->state; 7456 struct drm_connector *connector = conn_state->connector; 7457 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 7458 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state); 7459 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 7460 struct drm_dp_mst_topology_mgr *mst_mgr; 7461 struct drm_dp_mst_port *mst_port; 7462 struct drm_dp_mst_topology_state *mst_state; 7463 enum dc_color_depth color_depth; 7464 int clock, bpp = 0; 7465 bool is_y420 = false; 7466 7467 if (!aconnector->mst_output_port) 7468 return 0; 7469 7470 mst_port = aconnector->mst_output_port; 7471 mst_mgr = &aconnector->mst_root->mst_mgr; 7472 7473 if (!crtc_state->connectors_changed && !crtc_state->mode_changed) 7474 return 0; 7475 7476 mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr); 7477 if (IS_ERR(mst_state)) 7478 return PTR_ERR(mst_state); 7479 7480 mst_state->pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector->mst_root->dc_link)); 7481 7482 if (!state->duplicated) { 7483 int max_bpc = conn_state->max_requested_bpc; 7484 7485 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && 7486 aconnector->force_yuv420_output; 7487 color_depth = convert_color_depth_from_display_info(connector, 7488 is_y420, 7489 max_bpc); 7490 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; 7491 clock = adjusted_mode->clock; 7492 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4); 7493 } 7494 7495 dm_new_connector_state->vcpi_slots = 7496 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port, 7497 dm_new_connector_state->pbn); 7498 if (dm_new_connector_state->vcpi_slots < 0) { 7499 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); 7500 return dm_new_connector_state->vcpi_slots; 7501 } 7502 return 0; 7503 } 7504 7505 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 7506 .disable = dm_encoder_helper_disable, 7507 .atomic_check = dm_encoder_helper_atomic_check 7508 }; 7509 7510 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, 7511 struct dc_state *dc_state, 7512 struct dsc_mst_fairness_vars *vars) 7513 { 7514 struct dc_stream_state *stream = NULL; 7515 struct drm_connector *connector; 7516 struct drm_connector_state *new_con_state; 7517 struct amdgpu_dm_connector *aconnector; 7518 struct dm_connector_state *dm_conn_state; 7519 int i, j, ret; 7520 int vcpi, pbn_div, pbn = 0, slot_num = 0; 7521 7522 for_each_new_connector_in_state(state, connector, new_con_state, i) { 7523 7524 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 7525 continue; 7526 7527 aconnector = to_amdgpu_dm_connector(connector); 7528 7529 if (!aconnector->mst_output_port) 7530 continue; 7531 7532 if (!new_con_state || !new_con_state->crtc) 7533 continue; 7534 7535 dm_conn_state = to_dm_connector_state(new_con_state); 7536 7537 for (j = 0; j < dc_state->stream_count; j++) { 7538 stream = dc_state->streams[j]; 7539 if (!stream) 7540 continue; 7541 7542 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector) 7543 break; 7544 7545 stream = NULL; 7546 } 7547 7548 if (!stream) 7549 continue; 7550 7551 pbn_div = dm_mst_get_pbn_divider(stream->link); 7552 /* pbn is calculated by compute_mst_dsc_configs_for_state*/ 7553 for (j = 0; j < dc_state->stream_count; j++) { 7554 if (vars[j].aconnector == aconnector) { 7555 pbn = vars[j].pbn; 7556 break; 7557 } 7558 } 7559 7560 if (j == dc_state->stream_count || pbn_div == 0) 7561 continue; 7562 7563 slot_num = DIV_ROUND_UP(pbn, pbn_div); 7564 7565 if (stream->timing.flags.DSC != 1) { 7566 dm_conn_state->pbn = pbn; 7567 dm_conn_state->vcpi_slots = slot_num; 7568 7569 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, 7570 dm_conn_state->pbn, false); 7571 if (ret < 0) 7572 return ret; 7573 7574 continue; 7575 } 7576 7577 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true); 7578 if (vcpi < 0) 7579 return vcpi; 7580 7581 dm_conn_state->pbn = pbn; 7582 dm_conn_state->vcpi_slots = vcpi; 7583 } 7584 return 0; 7585 } 7586 7587 static int to_drm_connector_type(enum signal_type st) 7588 { 7589 switch (st) { 7590 case SIGNAL_TYPE_HDMI_TYPE_A: 7591 return DRM_MODE_CONNECTOR_HDMIA; 7592 case SIGNAL_TYPE_EDP: 7593 return DRM_MODE_CONNECTOR_eDP; 7594 case SIGNAL_TYPE_LVDS: 7595 return DRM_MODE_CONNECTOR_LVDS; 7596 case SIGNAL_TYPE_RGB: 7597 return DRM_MODE_CONNECTOR_VGA; 7598 case SIGNAL_TYPE_DISPLAY_PORT: 7599 case SIGNAL_TYPE_DISPLAY_PORT_MST: 7600 return DRM_MODE_CONNECTOR_DisplayPort; 7601 case SIGNAL_TYPE_DVI_DUAL_LINK: 7602 case SIGNAL_TYPE_DVI_SINGLE_LINK: 7603 return DRM_MODE_CONNECTOR_DVID; 7604 case SIGNAL_TYPE_VIRTUAL: 7605 return DRM_MODE_CONNECTOR_VIRTUAL; 7606 7607 default: 7608 return DRM_MODE_CONNECTOR_Unknown; 7609 } 7610 } 7611 7612 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) 7613 { 7614 struct drm_encoder *encoder; 7615 7616 /* There is only one encoder per connector */ 7617 drm_connector_for_each_possible_encoder(connector, encoder) 7618 return encoder; 7619 7620 return NULL; 7621 } 7622 7623 static void amdgpu_dm_get_native_mode(struct drm_connector *connector) 7624 { 7625 struct drm_encoder *encoder; 7626 struct amdgpu_encoder *amdgpu_encoder; 7627 7628 encoder = amdgpu_dm_connector_to_encoder(connector); 7629 7630 if (encoder == NULL) 7631 return; 7632 7633 amdgpu_encoder = to_amdgpu_encoder(encoder); 7634 7635 amdgpu_encoder->native_mode.clock = 0; 7636 7637 if (!list_empty(&connector->probed_modes)) { 7638 struct drm_display_mode *preferred_mode = NULL; 7639 7640 list_for_each_entry(preferred_mode, 7641 &connector->probed_modes, 7642 head) { 7643 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) 7644 amdgpu_encoder->native_mode = *preferred_mode; 7645 7646 break; 7647 } 7648 7649 } 7650 } 7651 7652 static struct drm_display_mode * 7653 amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 7654 char *name, 7655 int hdisplay, int vdisplay) 7656 { 7657 struct drm_device *dev = encoder->dev; 7658 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 7659 struct drm_display_mode *mode = NULL; 7660 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 7661 7662 mode = drm_mode_duplicate(dev, native_mode); 7663 7664 if (mode == NULL) 7665 return NULL; 7666 7667 mode->hdisplay = hdisplay; 7668 mode->vdisplay = vdisplay; 7669 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 7670 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 7671 7672 return mode; 7673 7674 } 7675 7676 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 7677 struct drm_connector *connector) 7678 { 7679 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 7680 struct drm_display_mode *mode = NULL; 7681 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 7682 struct amdgpu_dm_connector *amdgpu_dm_connector = 7683 to_amdgpu_dm_connector(connector); 7684 int i; 7685 int n; 7686 struct mode_size { 7687 char name[DRM_DISPLAY_MODE_LEN]; 7688 int w; 7689 int h; 7690 } common_modes[] = { 7691 { "640x480", 640, 480}, 7692 { "800x600", 800, 600}, 7693 { "1024x768", 1024, 768}, 7694 { "1280x720", 1280, 720}, 7695 { "1280x800", 1280, 800}, 7696 {"1280x1024", 1280, 1024}, 7697 { "1440x900", 1440, 900}, 7698 {"1680x1050", 1680, 1050}, 7699 {"1600x1200", 1600, 1200}, 7700 {"1920x1080", 1920, 1080}, 7701 {"1920x1200", 1920, 1200} 7702 }; 7703 7704 n = ARRAY_SIZE(common_modes); 7705 7706 for (i = 0; i < n; i++) { 7707 struct drm_display_mode *curmode = NULL; 7708 bool mode_existed = false; 7709 7710 if (common_modes[i].w > native_mode->hdisplay || 7711 common_modes[i].h > native_mode->vdisplay || 7712 (common_modes[i].w == native_mode->hdisplay && 7713 common_modes[i].h == native_mode->vdisplay)) 7714 continue; 7715 7716 list_for_each_entry(curmode, &connector->probed_modes, head) { 7717 if (common_modes[i].w == curmode->hdisplay && 7718 common_modes[i].h == curmode->vdisplay) { 7719 mode_existed = true; 7720 break; 7721 } 7722 } 7723 7724 if (mode_existed) 7725 continue; 7726 7727 mode = amdgpu_dm_create_common_mode(encoder, 7728 common_modes[i].name, common_modes[i].w, 7729 common_modes[i].h); 7730 if (!mode) 7731 continue; 7732 7733 drm_mode_probed_add(connector, mode); 7734 amdgpu_dm_connector->num_modes++; 7735 } 7736 } 7737 7738 static void amdgpu_set_panel_orientation(struct drm_connector *connector) 7739 { 7740 struct drm_encoder *encoder; 7741 struct amdgpu_encoder *amdgpu_encoder; 7742 const struct drm_display_mode *native_mode; 7743 7744 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP && 7745 connector->connector_type != DRM_MODE_CONNECTOR_LVDS) 7746 return; 7747 7748 mutex_lock(&connector->dev->mode_config.mutex); 7749 amdgpu_dm_connector_get_modes(connector); 7750 mutex_unlock(&connector->dev->mode_config.mutex); 7751 7752 encoder = amdgpu_dm_connector_to_encoder(connector); 7753 if (!encoder) 7754 return; 7755 7756 amdgpu_encoder = to_amdgpu_encoder(encoder); 7757 7758 native_mode = &amdgpu_encoder->native_mode; 7759 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0) 7760 return; 7761 7762 drm_connector_set_panel_orientation_with_quirk(connector, 7763 DRM_MODE_PANEL_ORIENTATION_UNKNOWN, 7764 native_mode->hdisplay, 7765 native_mode->vdisplay); 7766 } 7767 7768 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 7769 struct edid *edid) 7770 { 7771 struct amdgpu_dm_connector *amdgpu_dm_connector = 7772 to_amdgpu_dm_connector(connector); 7773 7774 if (edid) { 7775 /* empty probed_modes */ 7776 INIT_LIST_HEAD(&connector->probed_modes); 7777 amdgpu_dm_connector->num_modes = 7778 drm_add_edid_modes(connector, edid); 7779 7780 /* sorting the probed modes before calling function 7781 * amdgpu_dm_get_native_mode() since EDID can have 7782 * more than one preferred mode. The modes that are 7783 * later in the probed mode list could be of higher 7784 * and preferred resolution. For example, 3840x2160 7785 * resolution in base EDID preferred timing and 4096x2160 7786 * preferred resolution in DID extension block later. 7787 */ 7788 drm_mode_sort(&connector->probed_modes); 7789 amdgpu_dm_get_native_mode(connector); 7790 7791 /* Freesync capabilities are reset by calling 7792 * drm_add_edid_modes() and need to be 7793 * restored here. 7794 */ 7795 amdgpu_dm_update_freesync_caps(connector, edid); 7796 } else { 7797 amdgpu_dm_connector->num_modes = 0; 7798 } 7799 } 7800 7801 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector, 7802 struct drm_display_mode *mode) 7803 { 7804 struct drm_display_mode *m; 7805 7806 list_for_each_entry(m, &aconnector->base.probed_modes, head) { 7807 if (drm_mode_equal(m, mode)) 7808 return true; 7809 } 7810 7811 return false; 7812 } 7813 7814 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) 7815 { 7816 const struct drm_display_mode *m; 7817 struct drm_display_mode *new_mode; 7818 uint i; 7819 u32 new_modes_count = 0; 7820 7821 /* Standard FPS values 7822 * 7823 * 23.976 - TV/NTSC 7824 * 24 - Cinema 7825 * 25 - TV/PAL 7826 * 29.97 - TV/NTSC 7827 * 30 - TV/NTSC 7828 * 48 - Cinema HFR 7829 * 50 - TV/PAL 7830 * 60 - Commonly used 7831 * 48,72,96,120 - Multiples of 24 7832 */ 7833 static const u32 common_rates[] = { 7834 23976, 24000, 25000, 29970, 30000, 7835 48000, 50000, 60000, 72000, 96000, 120000 7836 }; 7837 7838 /* 7839 * Find mode with highest refresh rate with the same resolution 7840 * as the preferred mode. Some monitors report a preferred mode 7841 * with lower resolution than the highest refresh rate supported. 7842 */ 7843 7844 m = get_highest_refresh_rate_mode(aconnector, true); 7845 if (!m) 7846 return 0; 7847 7848 for (i = 0; i < ARRAY_SIZE(common_rates); i++) { 7849 u64 target_vtotal, target_vtotal_diff; 7850 u64 num, den; 7851 7852 if (drm_mode_vrefresh(m) * 1000 < common_rates[i]) 7853 continue; 7854 7855 if (common_rates[i] < aconnector->min_vfreq * 1000 || 7856 common_rates[i] > aconnector->max_vfreq * 1000) 7857 continue; 7858 7859 num = (unsigned long long)m->clock * 1000 * 1000; 7860 den = common_rates[i] * (unsigned long long)m->htotal; 7861 target_vtotal = div_u64(num, den); 7862 target_vtotal_diff = target_vtotal - m->vtotal; 7863 7864 /* Check for illegal modes */ 7865 if (m->vsync_start + target_vtotal_diff < m->vdisplay || 7866 m->vsync_end + target_vtotal_diff < m->vsync_start || 7867 m->vtotal + target_vtotal_diff < m->vsync_end) 7868 continue; 7869 7870 new_mode = drm_mode_duplicate(aconnector->base.dev, m); 7871 if (!new_mode) 7872 goto out; 7873 7874 new_mode->vtotal += (u16)target_vtotal_diff; 7875 new_mode->vsync_start += (u16)target_vtotal_diff; 7876 new_mode->vsync_end += (u16)target_vtotal_diff; 7877 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 7878 new_mode->type |= DRM_MODE_TYPE_DRIVER; 7879 7880 if (!is_duplicate_mode(aconnector, new_mode)) { 7881 drm_mode_probed_add(&aconnector->base, new_mode); 7882 new_modes_count += 1; 7883 } else 7884 drm_mode_destroy(aconnector->base.dev, new_mode); 7885 } 7886 out: 7887 return new_modes_count; 7888 } 7889 7890 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, 7891 struct edid *edid) 7892 { 7893 struct amdgpu_dm_connector *amdgpu_dm_connector = 7894 to_amdgpu_dm_connector(connector); 7895 7896 if (!(amdgpu_freesync_vid_mode && edid)) 7897 return; 7898 7899 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 7900 amdgpu_dm_connector->num_modes += 7901 add_fs_modes(amdgpu_dm_connector); 7902 } 7903 7904 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) 7905 { 7906 struct amdgpu_dm_connector *amdgpu_dm_connector = 7907 to_amdgpu_dm_connector(connector); 7908 struct drm_encoder *encoder; 7909 struct edid *edid = amdgpu_dm_connector->edid; 7910 struct dc_link_settings *verified_link_cap = 7911 &amdgpu_dm_connector->dc_link->verified_link_cap; 7912 const struct dc *dc = amdgpu_dm_connector->dc_link->dc; 7913 7914 encoder = amdgpu_dm_connector_to_encoder(connector); 7915 7916 if (!drm_edid_is_valid(edid)) { 7917 amdgpu_dm_connector->num_modes = 7918 drm_add_modes_noedid(connector, 640, 480); 7919 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING) 7920 amdgpu_dm_connector->num_modes += 7921 drm_add_modes_noedid(connector, 1920, 1080); 7922 } else { 7923 amdgpu_dm_connector_ddc_get_modes(connector, edid); 7924 if (encoder) 7925 amdgpu_dm_connector_add_common_modes(encoder, connector); 7926 amdgpu_dm_connector_add_freesync_modes(connector, edid); 7927 } 7928 amdgpu_dm_fbc_init(connector); 7929 7930 return amdgpu_dm_connector->num_modes; 7931 } 7932 7933 static const u32 supported_colorspaces = 7934 BIT(DRM_MODE_COLORIMETRY_BT709_YCC) | 7935 BIT(DRM_MODE_COLORIMETRY_OPRGB) | 7936 BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) | 7937 BIT(DRM_MODE_COLORIMETRY_BT2020_YCC); 7938 7939 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 7940 struct amdgpu_dm_connector *aconnector, 7941 int connector_type, 7942 struct dc_link *link, 7943 int link_index) 7944 { 7945 struct amdgpu_device *adev = drm_to_adev(dm->ddev); 7946 7947 /* 7948 * Some of the properties below require access to state, like bpc. 7949 * Allocate some default initial connector state with our reset helper. 7950 */ 7951 if (aconnector->base.funcs->reset) 7952 aconnector->base.funcs->reset(&aconnector->base); 7953 7954 aconnector->connector_id = link_index; 7955 aconnector->bl_idx = -1; 7956 aconnector->dc_link = link; 7957 aconnector->base.interlace_allowed = false; 7958 aconnector->base.doublescan_allowed = false; 7959 aconnector->base.stereo_allowed = false; 7960 aconnector->base.dpms = DRM_MODE_DPMS_OFF; 7961 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ 7962 aconnector->audio_inst = -1; 7963 aconnector->pack_sdp_v1_3 = false; 7964 aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE; 7965 memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); 7966 mutex_init(&aconnector->hpd_lock); 7967 mutex_init(&aconnector->handle_mst_msg_ready); 7968 7969 /* 7970 * configure support HPD hot plug connector_>polled default value is 0 7971 * which means HPD hot plug not supported 7972 */ 7973 switch (connector_type) { 7974 case DRM_MODE_CONNECTOR_HDMIA: 7975 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7976 aconnector->base.ycbcr_420_allowed = 7977 link->link_enc->features.hdmi_ycbcr420_supported ? true : false; 7978 break; 7979 case DRM_MODE_CONNECTOR_DisplayPort: 7980 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7981 link->link_enc = link_enc_cfg_get_link_enc(link); 7982 ASSERT(link->link_enc); 7983 if (link->link_enc) 7984 aconnector->base.ycbcr_420_allowed = 7985 link->link_enc->features.dp_ycbcr420_supported ? true : false; 7986 break; 7987 case DRM_MODE_CONNECTOR_DVID: 7988 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7989 break; 7990 default: 7991 break; 7992 } 7993 7994 drm_object_attach_property(&aconnector->base.base, 7995 dm->ddev->mode_config.scaling_mode_property, 7996 DRM_MODE_SCALE_NONE); 7997 7998 drm_object_attach_property(&aconnector->base.base, 7999 adev->mode_info.underscan_property, 8000 UNDERSCAN_OFF); 8001 drm_object_attach_property(&aconnector->base.base, 8002 adev->mode_info.underscan_hborder_property, 8003 0); 8004 drm_object_attach_property(&aconnector->base.base, 8005 adev->mode_info.underscan_vborder_property, 8006 0); 8007 8008 if (!aconnector->mst_root) 8009 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); 8010 8011 aconnector->base.state->max_bpc = 16; 8012 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc; 8013 8014 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) { 8015 /* Content Type is currently only implemented for HDMI. */ 8016 drm_connector_attach_content_type_property(&aconnector->base); 8017 } 8018 8019 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) { 8020 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces)) 8021 drm_connector_attach_colorspace_property(&aconnector->base); 8022 } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) || 8023 connector_type == DRM_MODE_CONNECTOR_eDP) { 8024 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces)) 8025 drm_connector_attach_colorspace_property(&aconnector->base); 8026 } 8027 8028 if (connector_type == DRM_MODE_CONNECTOR_HDMIA || 8029 connector_type == DRM_MODE_CONNECTOR_DisplayPort || 8030 connector_type == DRM_MODE_CONNECTOR_eDP) { 8031 drm_connector_attach_hdr_output_metadata_property(&aconnector->base); 8032 8033 if (!aconnector->mst_root) 8034 drm_connector_attach_vrr_capable_property(&aconnector->base); 8035 8036 if (adev->dm.hdcp_workqueue) 8037 drm_connector_attach_content_protection_property(&aconnector->base, true); 8038 } 8039 } 8040 8041 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 8042 struct i2c_msg *msgs, int num) 8043 { 8044 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); 8045 struct ddc_service *ddc_service = i2c->ddc_service; 8046 struct i2c_command cmd; 8047 int i; 8048 int result = -EIO; 8049 8050 if (!ddc_service->ddc_pin || !ddc_service->ddc_pin->hw_info.hw_supported) 8051 return result; 8052 8053 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); 8054 8055 if (!cmd.payloads) 8056 return result; 8057 8058 cmd.number_of_payloads = num; 8059 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 8060 cmd.speed = 100; 8061 8062 for (i = 0; i < num; i++) { 8063 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); 8064 cmd.payloads[i].address = msgs[i].addr; 8065 cmd.payloads[i].length = msgs[i].len; 8066 cmd.payloads[i].data = msgs[i].buf; 8067 } 8068 8069 if (dc_submit_i2c( 8070 ddc_service->ctx->dc, 8071 ddc_service->link->link_index, 8072 &cmd)) 8073 result = num; 8074 8075 kfree(cmd.payloads); 8076 return result; 8077 } 8078 8079 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) 8080 { 8081 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 8082 } 8083 8084 static const struct i2c_algorithm amdgpu_dm_i2c_algo = { 8085 .master_xfer = amdgpu_dm_i2c_xfer, 8086 .functionality = amdgpu_dm_i2c_func, 8087 }; 8088 8089 static struct amdgpu_i2c_adapter * 8090 create_i2c(struct ddc_service *ddc_service, 8091 int link_index, 8092 int *res) 8093 { 8094 struct amdgpu_device *adev = ddc_service->ctx->driver_context; 8095 struct amdgpu_i2c_adapter *i2c; 8096 8097 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); 8098 if (!i2c) 8099 return NULL; 8100 i2c->base.owner = THIS_MODULE; 8101 i2c->base.dev.parent = &adev->pdev->dev; 8102 i2c->base.algo = &amdgpu_dm_i2c_algo; 8103 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); 8104 i2c_set_adapdata(&i2c->base, i2c); 8105 i2c->ddc_service = ddc_service; 8106 8107 return i2c; 8108 } 8109 8110 8111 /* 8112 * Note: this function assumes that dc_link_detect() was called for the 8113 * dc_link which will be represented by this aconnector. 8114 */ 8115 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 8116 struct amdgpu_dm_connector *aconnector, 8117 u32 link_index, 8118 struct amdgpu_encoder *aencoder) 8119 { 8120 int res = 0; 8121 int connector_type; 8122 struct dc *dc = dm->dc; 8123 struct dc_link *link = dc_get_link_at_index(dc, link_index); 8124 struct amdgpu_i2c_adapter *i2c; 8125 8126 /* Not needed for writeback connector */ 8127 link->priv = aconnector; 8128 8129 8130 i2c = create_i2c(link->ddc, link->link_index, &res); 8131 if (!i2c) { 8132 DRM_ERROR("Failed to create i2c adapter data\n"); 8133 return -ENOMEM; 8134 } 8135 8136 aconnector->i2c = i2c; 8137 res = i2c_add_adapter(&i2c->base); 8138 8139 if (res) { 8140 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); 8141 goto out_free; 8142 } 8143 8144 connector_type = to_drm_connector_type(link->connector_signal); 8145 8146 res = drm_connector_init_with_ddc( 8147 dm->ddev, 8148 &aconnector->base, 8149 &amdgpu_dm_connector_funcs, 8150 connector_type, 8151 &i2c->base); 8152 8153 if (res) { 8154 DRM_ERROR("connector_init failed\n"); 8155 aconnector->connector_id = -1; 8156 goto out_free; 8157 } 8158 8159 drm_connector_helper_add( 8160 &aconnector->base, 8161 &amdgpu_dm_connector_helper_funcs); 8162 8163 amdgpu_dm_connector_init_helper( 8164 dm, 8165 aconnector, 8166 connector_type, 8167 link, 8168 link_index); 8169 8170 drm_connector_attach_encoder( 8171 &aconnector->base, &aencoder->base); 8172 8173 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort 8174 || connector_type == DRM_MODE_CONNECTOR_eDP) 8175 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index); 8176 8177 out_free: 8178 if (res) { 8179 kfree(i2c); 8180 aconnector->i2c = NULL; 8181 } 8182 return res; 8183 } 8184 8185 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) 8186 { 8187 switch (adev->mode_info.num_crtc) { 8188 case 1: 8189 return 0x1; 8190 case 2: 8191 return 0x3; 8192 case 3: 8193 return 0x7; 8194 case 4: 8195 return 0xf; 8196 case 5: 8197 return 0x1f; 8198 case 6: 8199 default: 8200 return 0x3f; 8201 } 8202 } 8203 8204 static int amdgpu_dm_encoder_init(struct drm_device *dev, 8205 struct amdgpu_encoder *aencoder, 8206 uint32_t link_index) 8207 { 8208 struct amdgpu_device *adev = drm_to_adev(dev); 8209 8210 int res = drm_encoder_init(dev, 8211 &aencoder->base, 8212 &amdgpu_dm_encoder_funcs, 8213 DRM_MODE_ENCODER_TMDS, 8214 NULL); 8215 8216 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 8217 8218 if (!res) 8219 aencoder->encoder_id = link_index; 8220 else 8221 aencoder->encoder_id = -1; 8222 8223 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); 8224 8225 return res; 8226 } 8227 8228 static void manage_dm_interrupts(struct amdgpu_device *adev, 8229 struct amdgpu_crtc *acrtc, 8230 struct dm_crtc_state *acrtc_state) 8231 { 8232 /* 8233 * We have no guarantee that the frontend index maps to the same 8234 * backend index - some even map to more than one. 8235 * 8236 * TODO: Use a different interrupt or check DC itself for the mapping. 8237 */ 8238 int irq_type = 8239 amdgpu_display_crtc_idx_to_irq_type( 8240 adev, 8241 acrtc->crtc_id); 8242 struct drm_vblank_crtc_config config = {0}; 8243 struct dc_crtc_timing *timing; 8244 int offdelay; 8245 8246 if (acrtc_state) { 8247 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < 8248 IP_VERSION(3, 5, 0) || 8249 acrtc_state->stream->link->psr_settings.psr_version < 8250 DC_PSR_VERSION_UNSUPPORTED) { 8251 timing = &acrtc_state->stream->timing; 8252 8253 /* at least 2 frames */ 8254 offdelay = DIV64_U64_ROUND_UP((u64)20 * 8255 timing->v_total * 8256 timing->h_total, 8257 timing->pix_clk_100hz); 8258 8259 config.offdelay_ms = offdelay ?: 30; 8260 } else { 8261 config.disable_immediate = true; 8262 } 8263 8264 drm_crtc_vblank_on_config(&acrtc->base, 8265 &config); 8266 8267 amdgpu_irq_get( 8268 adev, 8269 &adev->pageflip_irq, 8270 irq_type); 8271 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 8272 amdgpu_irq_get( 8273 adev, 8274 &adev->vline0_irq, 8275 irq_type); 8276 #endif 8277 } else { 8278 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 8279 amdgpu_irq_put( 8280 adev, 8281 &adev->vline0_irq, 8282 irq_type); 8283 #endif 8284 amdgpu_irq_put( 8285 adev, 8286 &adev->pageflip_irq, 8287 irq_type); 8288 drm_crtc_vblank_off(&acrtc->base); 8289 } 8290 } 8291 8292 static void dm_update_pflip_irq_state(struct amdgpu_device *adev, 8293 struct amdgpu_crtc *acrtc) 8294 { 8295 int irq_type = 8296 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); 8297 8298 /** 8299 * This reads the current state for the IRQ and force reapplies 8300 * the setting to hardware. 8301 */ 8302 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type); 8303 } 8304 8305 static bool 8306 is_scaling_state_different(const struct dm_connector_state *dm_state, 8307 const struct dm_connector_state *old_dm_state) 8308 { 8309 if (dm_state->scaling != old_dm_state->scaling) 8310 return true; 8311 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 8312 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 8313 return true; 8314 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 8315 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 8316 return true; 8317 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 8318 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 8319 return true; 8320 return false; 8321 } 8322 8323 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state, 8324 struct drm_crtc_state *old_crtc_state, 8325 struct drm_connector_state *new_conn_state, 8326 struct drm_connector_state *old_conn_state, 8327 const struct drm_connector *connector, 8328 struct hdcp_workqueue *hdcp_w) 8329 { 8330 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 8331 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 8332 8333 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 8334 connector->index, connector->status, connector->dpms); 8335 pr_debug("[HDCP_DM] state protection old: %x new: %x\n", 8336 old_conn_state->content_protection, new_conn_state->content_protection); 8337 8338 if (old_crtc_state) 8339 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 8340 old_crtc_state->enable, 8341 old_crtc_state->active, 8342 old_crtc_state->mode_changed, 8343 old_crtc_state->active_changed, 8344 old_crtc_state->connectors_changed); 8345 8346 if (new_crtc_state) 8347 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 8348 new_crtc_state->enable, 8349 new_crtc_state->active, 8350 new_crtc_state->mode_changed, 8351 new_crtc_state->active_changed, 8352 new_crtc_state->connectors_changed); 8353 8354 /* hdcp content type change */ 8355 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type && 8356 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 8357 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 8358 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__); 8359 return true; 8360 } 8361 8362 /* CP is being re enabled, ignore this */ 8363 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && 8364 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 8365 if (new_crtc_state && new_crtc_state->mode_changed) { 8366 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 8367 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__); 8368 return true; 8369 } 8370 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; 8371 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__); 8372 return false; 8373 } 8374 8375 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED 8376 * 8377 * Handles: UNDESIRED -> ENABLED 8378 */ 8379 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && 8380 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 8381 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 8382 8383 /* Stream removed and re-enabled 8384 * 8385 * Can sometimes overlap with the HPD case, 8386 * thus set update_hdcp to false to avoid 8387 * setting HDCP multiple times. 8388 * 8389 * Handles: DESIRED -> DESIRED (Special case) 8390 */ 8391 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) && 8392 new_conn_state->crtc && new_conn_state->crtc->enabled && 8393 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 8394 dm_con_state->update_hdcp = false; 8395 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n", 8396 __func__); 8397 return true; 8398 } 8399 8400 /* Hot-plug, headless s3, dpms 8401 * 8402 * Only start HDCP if the display is connected/enabled. 8403 * update_hdcp flag will be set to false until the next 8404 * HPD comes in. 8405 * 8406 * Handles: DESIRED -> DESIRED (Special case) 8407 */ 8408 if (dm_con_state->update_hdcp && 8409 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && 8410 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) { 8411 dm_con_state->update_hdcp = false; 8412 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n", 8413 __func__); 8414 return true; 8415 } 8416 8417 if (old_conn_state->content_protection == new_conn_state->content_protection) { 8418 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) { 8419 if (new_crtc_state && new_crtc_state->mode_changed) { 8420 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n", 8421 __func__); 8422 return true; 8423 } 8424 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n", 8425 __func__); 8426 return false; 8427 } 8428 8429 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__); 8430 return false; 8431 } 8432 8433 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 8434 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n", 8435 __func__); 8436 return true; 8437 } 8438 8439 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__); 8440 return false; 8441 } 8442 8443 static void remove_stream(struct amdgpu_device *adev, 8444 struct amdgpu_crtc *acrtc, 8445 struct dc_stream_state *stream) 8446 { 8447 /* this is the update mode case */ 8448 8449 acrtc->otg_inst = -1; 8450 acrtc->enabled = false; 8451 } 8452 8453 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 8454 { 8455 8456 assert_spin_locked(&acrtc->base.dev->event_lock); 8457 WARN_ON(acrtc->event); 8458 8459 acrtc->event = acrtc->base.state->event; 8460 8461 /* Set the flip status */ 8462 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 8463 8464 /* Mark this event as consumed */ 8465 acrtc->base.state->event = NULL; 8466 8467 drm_dbg_state(acrtc->base.dev, 8468 "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 8469 acrtc->crtc_id); 8470 } 8471 8472 static void update_freesync_state_on_stream( 8473 struct amdgpu_display_manager *dm, 8474 struct dm_crtc_state *new_crtc_state, 8475 struct dc_stream_state *new_stream, 8476 struct dc_plane_state *surface, 8477 u32 flip_timestamp_in_us) 8478 { 8479 struct mod_vrr_params vrr_params; 8480 struct dc_info_packet vrr_infopacket = {0}; 8481 struct amdgpu_device *adev = dm->adev; 8482 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 8483 unsigned long flags; 8484 bool pack_sdp_v1_3 = false; 8485 struct amdgpu_dm_connector *aconn; 8486 enum vrr_packet_type packet_type = PACKET_TYPE_VRR; 8487 8488 if (!new_stream) 8489 return; 8490 8491 /* 8492 * TODO: Determine why min/max totals and vrefresh can be 0 here. 8493 * For now it's sufficient to just guard against these conditions. 8494 */ 8495 8496 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 8497 return; 8498 8499 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 8500 vrr_params = acrtc->dm_irq_params.vrr_params; 8501 8502 if (surface) { 8503 mod_freesync_handle_preflip( 8504 dm->freesync_module, 8505 surface, 8506 new_stream, 8507 flip_timestamp_in_us, 8508 &vrr_params); 8509 8510 if (adev->family < AMDGPU_FAMILY_AI && 8511 amdgpu_dm_crtc_vrr_active(new_crtc_state)) { 8512 mod_freesync_handle_v_update(dm->freesync_module, 8513 new_stream, &vrr_params); 8514 8515 /* Need to call this before the frame ends. */ 8516 dc_stream_adjust_vmin_vmax(dm->dc, 8517 new_crtc_state->stream, 8518 &vrr_params.adjust); 8519 } 8520 } 8521 8522 aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context; 8523 8524 if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) { 8525 pack_sdp_v1_3 = aconn->pack_sdp_v1_3; 8526 8527 if (aconn->vsdb_info.amd_vsdb_version == 1) 8528 packet_type = PACKET_TYPE_FS_V1; 8529 else if (aconn->vsdb_info.amd_vsdb_version == 2) 8530 packet_type = PACKET_TYPE_FS_V2; 8531 else if (aconn->vsdb_info.amd_vsdb_version == 3) 8532 packet_type = PACKET_TYPE_FS_V3; 8533 8534 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL, 8535 &new_stream->adaptive_sync_infopacket); 8536 } 8537 8538 mod_freesync_build_vrr_infopacket( 8539 dm->freesync_module, 8540 new_stream, 8541 &vrr_params, 8542 packet_type, 8543 TRANSFER_FUNC_UNKNOWN, 8544 &vrr_infopacket, 8545 pack_sdp_v1_3); 8546 8547 new_crtc_state->freesync_vrr_info_changed |= 8548 (memcmp(&new_crtc_state->vrr_infopacket, 8549 &vrr_infopacket, 8550 sizeof(vrr_infopacket)) != 0); 8551 8552 acrtc->dm_irq_params.vrr_params = vrr_params; 8553 new_crtc_state->vrr_infopacket = vrr_infopacket; 8554 8555 new_stream->vrr_infopacket = vrr_infopacket; 8556 new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params); 8557 8558 if (new_crtc_state->freesync_vrr_info_changed) 8559 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", 8560 new_crtc_state->base.crtc->base.id, 8561 (int)new_crtc_state->base.vrr_enabled, 8562 (int)vrr_params.state); 8563 8564 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 8565 } 8566 8567 static void update_stream_irq_parameters( 8568 struct amdgpu_display_manager *dm, 8569 struct dm_crtc_state *new_crtc_state) 8570 { 8571 struct dc_stream_state *new_stream = new_crtc_state->stream; 8572 struct mod_vrr_params vrr_params; 8573 struct mod_freesync_config config = new_crtc_state->freesync_config; 8574 struct amdgpu_device *adev = dm->adev; 8575 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 8576 unsigned long flags; 8577 8578 if (!new_stream) 8579 return; 8580 8581 /* 8582 * TODO: Determine why min/max totals and vrefresh can be 0 here. 8583 * For now it's sufficient to just guard against these conditions. 8584 */ 8585 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 8586 return; 8587 8588 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 8589 vrr_params = acrtc->dm_irq_params.vrr_params; 8590 8591 if (new_crtc_state->vrr_supported && 8592 config.min_refresh_in_uhz && 8593 config.max_refresh_in_uhz) { 8594 /* 8595 * if freesync compatible mode was set, config.state will be set 8596 * in atomic check 8597 */ 8598 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz && 8599 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) || 8600 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) { 8601 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz; 8602 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz; 8603 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz; 8604 vrr_params.state = VRR_STATE_ACTIVE_FIXED; 8605 } else { 8606 config.state = new_crtc_state->base.vrr_enabled ? 8607 VRR_STATE_ACTIVE_VARIABLE : 8608 VRR_STATE_INACTIVE; 8609 } 8610 } else { 8611 config.state = VRR_STATE_UNSUPPORTED; 8612 } 8613 8614 mod_freesync_build_vrr_params(dm->freesync_module, 8615 new_stream, 8616 &config, &vrr_params); 8617 8618 new_crtc_state->freesync_config = config; 8619 /* Copy state for access from DM IRQ handler */ 8620 acrtc->dm_irq_params.freesync_config = config; 8621 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; 8622 acrtc->dm_irq_params.vrr_params = vrr_params; 8623 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 8624 } 8625 8626 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, 8627 struct dm_crtc_state *new_state) 8628 { 8629 bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state); 8630 bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state); 8631 8632 if (!old_vrr_active && new_vrr_active) { 8633 /* Transition VRR inactive -> active: 8634 * While VRR is active, we must not disable vblank irq, as a 8635 * reenable after disable would compute bogus vblank/pflip 8636 * timestamps if it likely happened inside display front-porch. 8637 * 8638 * We also need vupdate irq for the actual core vblank handling 8639 * at end of vblank. 8640 */ 8641 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0); 8642 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0); 8643 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n", 8644 __func__, new_state->base.crtc->base.id); 8645 } else if (old_vrr_active && !new_vrr_active) { 8646 /* Transition VRR active -> inactive: 8647 * Allow vblank irq disable again for fixed refresh rate. 8648 */ 8649 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0); 8650 drm_crtc_vblank_put(new_state->base.crtc); 8651 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n", 8652 __func__, new_state->base.crtc->base.id); 8653 } 8654 } 8655 8656 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) 8657 { 8658 struct drm_plane *plane; 8659 struct drm_plane_state *old_plane_state; 8660 int i; 8661 8662 /* 8663 * TODO: Make this per-stream so we don't issue redundant updates for 8664 * commits with multiple streams. 8665 */ 8666 for_each_old_plane_in_state(state, plane, old_plane_state, i) 8667 if (plane->type == DRM_PLANE_TYPE_CURSOR) 8668 amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); 8669 } 8670 8671 static inline uint32_t get_mem_type(struct drm_framebuffer *fb) 8672 { 8673 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); 8674 8675 return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; 8676 } 8677 8678 static void amdgpu_dm_update_cursor(struct drm_plane *plane, 8679 struct drm_plane_state *old_plane_state, 8680 struct dc_stream_update *update) 8681 { 8682 struct amdgpu_device *adev = drm_to_adev(plane->dev); 8683 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 8684 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 8685 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 8686 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 8687 uint64_t address = afb ? afb->address : 0; 8688 struct dc_cursor_position position = {0}; 8689 struct dc_cursor_attributes attributes; 8690 int ret; 8691 8692 if (!plane->state->fb && !old_plane_state->fb) 8693 return; 8694 8695 drm_dbg_atomic(plane->dev, "crtc_id=%d with size %d to %d\n", 8696 amdgpu_crtc->crtc_id, plane->state->crtc_w, 8697 plane->state->crtc_h); 8698 8699 ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position); 8700 if (ret) 8701 return; 8702 8703 if (!position.enable) { 8704 /* turn off cursor */ 8705 if (crtc_state && crtc_state->stream) { 8706 dc_stream_set_cursor_position(crtc_state->stream, 8707 &position); 8708 update->cursor_position = &crtc_state->stream->cursor_position; 8709 } 8710 return; 8711 } 8712 8713 amdgpu_crtc->cursor_width = plane->state->crtc_w; 8714 amdgpu_crtc->cursor_height = plane->state->crtc_h; 8715 8716 memset(&attributes, 0, sizeof(attributes)); 8717 attributes.address.high_part = upper_32_bits(address); 8718 attributes.address.low_part = lower_32_bits(address); 8719 attributes.width = plane->state->crtc_w; 8720 attributes.height = plane->state->crtc_h; 8721 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 8722 attributes.rotation_angle = 0; 8723 attributes.attribute_flags.value = 0; 8724 8725 /* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM 8726 * legacy gamma setup. 8727 */ 8728 if (crtc_state->cm_is_degamma_srgb && 8729 adev->dm.dc->caps.color.dpp.gamma_corr) 8730 attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1; 8731 8732 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0]; 8733 8734 if (crtc_state->stream) { 8735 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 8736 &attributes)) 8737 DRM_ERROR("DC failed to set cursor attributes\n"); 8738 8739 update->cursor_attributes = &crtc_state->stream->cursor_attributes; 8740 8741 if (!dc_stream_set_cursor_position(crtc_state->stream, 8742 &position)) 8743 DRM_ERROR("DC failed to set cursor position\n"); 8744 8745 update->cursor_position = &crtc_state->stream->cursor_position; 8746 } 8747 } 8748 8749 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 8750 struct drm_device *dev, 8751 struct amdgpu_display_manager *dm, 8752 struct drm_crtc *pcrtc, 8753 bool wait_for_vblank) 8754 { 8755 u32 i; 8756 u64 timestamp_ns = ktime_get_ns(); 8757 struct drm_plane *plane; 8758 struct drm_plane_state *old_plane_state, *new_plane_state; 8759 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 8760 struct drm_crtc_state *new_pcrtc_state = 8761 drm_atomic_get_new_crtc_state(state, pcrtc); 8762 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 8763 struct dm_crtc_state *dm_old_crtc_state = 8764 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 8765 int planes_count = 0, vpos, hpos; 8766 unsigned long flags; 8767 u32 target_vblank, last_flip_vblank; 8768 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); 8769 bool cursor_update = false; 8770 bool pflip_present = false; 8771 bool dirty_rects_changed = false; 8772 bool updated_planes_and_streams = false; 8773 struct { 8774 struct dc_surface_update surface_updates[MAX_SURFACES]; 8775 struct dc_plane_info plane_infos[MAX_SURFACES]; 8776 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 8777 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 8778 struct dc_stream_update stream_update; 8779 } *bundle; 8780 8781 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 8782 8783 if (!bundle) { 8784 drm_err(dev, "Failed to allocate update bundle\n"); 8785 goto cleanup; 8786 } 8787 8788 /* 8789 * Disable the cursor first if we're disabling all the planes. 8790 * It'll remain on the screen after the planes are re-enabled 8791 * if we don't. 8792 * 8793 * If the cursor is transitioning from native to overlay mode, the 8794 * native cursor needs to be disabled first. 8795 */ 8796 if (acrtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE && 8797 dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) { 8798 struct dc_cursor_position cursor_position = {0}; 8799 8800 if (!dc_stream_set_cursor_position(acrtc_state->stream, 8801 &cursor_position)) 8802 drm_err(dev, "DC failed to disable native cursor\n"); 8803 8804 bundle->stream_update.cursor_position = 8805 &acrtc_state->stream->cursor_position; 8806 } 8807 8808 if (acrtc_state->active_planes == 0 && 8809 dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) 8810 amdgpu_dm_commit_cursors(state); 8811 8812 /* update planes when needed */ 8813 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 8814 struct drm_crtc *crtc = new_plane_state->crtc; 8815 struct drm_crtc_state *new_crtc_state; 8816 struct drm_framebuffer *fb = new_plane_state->fb; 8817 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb; 8818 bool plane_needs_flip; 8819 struct dc_plane_state *dc_plane; 8820 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 8821 8822 /* Cursor plane is handled after stream updates */ 8823 if (plane->type == DRM_PLANE_TYPE_CURSOR && 8824 acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) { 8825 if ((fb && crtc == pcrtc) || 8826 (old_plane_state->fb && old_plane_state->crtc == pcrtc)) { 8827 cursor_update = true; 8828 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) != 0) 8829 amdgpu_dm_update_cursor(plane, old_plane_state, &bundle->stream_update); 8830 } 8831 8832 continue; 8833 } 8834 8835 if (!fb || !crtc || pcrtc != crtc) 8836 continue; 8837 8838 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 8839 if (!new_crtc_state->active) 8840 continue; 8841 8842 dc_plane = dm_new_plane_state->dc_state; 8843 if (!dc_plane) 8844 continue; 8845 8846 bundle->surface_updates[planes_count].surface = dc_plane; 8847 if (new_pcrtc_state->color_mgmt_changed) { 8848 bundle->surface_updates[planes_count].gamma = &dc_plane->gamma_correction; 8849 bundle->surface_updates[planes_count].in_transfer_func = &dc_plane->in_transfer_func; 8850 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; 8851 bundle->surface_updates[planes_count].hdr_mult = dc_plane->hdr_mult; 8852 bundle->surface_updates[planes_count].func_shaper = &dc_plane->in_shaper_func; 8853 bundle->surface_updates[planes_count].lut3d_func = &dc_plane->lut3d_func; 8854 bundle->surface_updates[planes_count].blend_tf = &dc_plane->blend_tf; 8855 } 8856 8857 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, 8858 &bundle->scaling_infos[planes_count]); 8859 8860 bundle->surface_updates[planes_count].scaling_info = 8861 &bundle->scaling_infos[planes_count]; 8862 8863 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 8864 8865 pflip_present = pflip_present || plane_needs_flip; 8866 8867 if (!plane_needs_flip) { 8868 planes_count += 1; 8869 continue; 8870 } 8871 8872 fill_dc_plane_info_and_addr( 8873 dm->adev, new_plane_state, 8874 afb->tiling_flags, 8875 &bundle->plane_infos[planes_count], 8876 &bundle->flip_addrs[planes_count].address, 8877 afb->tmz_surface, false); 8878 8879 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", 8880 new_plane_state->plane->index, 8881 bundle->plane_infos[planes_count].dcc.enable); 8882 8883 bundle->surface_updates[planes_count].plane_info = 8884 &bundle->plane_infos[planes_count]; 8885 8886 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled || 8887 acrtc_state->stream->link->replay_settings.replay_feature_enabled) { 8888 fill_dc_dirty_rects(plane, old_plane_state, 8889 new_plane_state, new_crtc_state, 8890 &bundle->flip_addrs[planes_count], 8891 acrtc_state->stream->link->psr_settings.psr_version == 8892 DC_PSR_VERSION_SU_1, 8893 &dirty_rects_changed); 8894 8895 /* 8896 * If the dirty regions changed, PSR-SU need to be disabled temporarily 8897 * and enabled it again after dirty regions are stable to avoid video glitch. 8898 * PSR-SU will be enabled in vblank_control_worker() if user pause the video 8899 * during the PSR-SU was disabled. 8900 */ 8901 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 8902 acrtc_attach->dm_irq_params.allow_psr_entry && 8903 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 8904 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && 8905 #endif 8906 dirty_rects_changed) { 8907 mutex_lock(&dm->dc_lock); 8908 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns = 8909 timestamp_ns; 8910 if (acrtc_state->stream->link->psr_settings.psr_allow_active) 8911 amdgpu_dm_psr_disable(acrtc_state->stream); 8912 mutex_unlock(&dm->dc_lock); 8913 } 8914 } 8915 8916 /* 8917 * Only allow immediate flips for fast updates that don't 8918 * change memory domain, FB pitch, DCC state, rotation or 8919 * mirroring. 8920 * 8921 * dm_crtc_helper_atomic_check() only accepts async flips with 8922 * fast updates. 8923 */ 8924 if (crtc->state->async_flip && 8925 (acrtc_state->update_type != UPDATE_TYPE_FAST || 8926 get_mem_type(old_plane_state->fb) != get_mem_type(fb))) 8927 drm_warn_once(state->dev, 8928 "[PLANE:%d:%s] async flip with non-fast update\n", 8929 plane->base.id, plane->name); 8930 8931 bundle->flip_addrs[planes_count].flip_immediate = 8932 crtc->state->async_flip && 8933 acrtc_state->update_type == UPDATE_TYPE_FAST && 8934 get_mem_type(old_plane_state->fb) == get_mem_type(fb); 8935 8936 timestamp_ns = ktime_get_ns(); 8937 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 8938 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 8939 bundle->surface_updates[planes_count].surface = dc_plane; 8940 8941 if (!bundle->surface_updates[planes_count].surface) { 8942 DRM_ERROR("No surface for CRTC: id=%d\n", 8943 acrtc_attach->crtc_id); 8944 continue; 8945 } 8946 8947 if (plane == pcrtc->primary) 8948 update_freesync_state_on_stream( 8949 dm, 8950 acrtc_state, 8951 acrtc_state->stream, 8952 dc_plane, 8953 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 8954 8955 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n", 8956 __func__, 8957 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 8958 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 8959 8960 planes_count += 1; 8961 8962 } 8963 8964 if (pflip_present) { 8965 if (!vrr_active) { 8966 /* Use old throttling in non-vrr fixed refresh rate mode 8967 * to keep flip scheduling based on target vblank counts 8968 * working in a backwards compatible way, e.g., for 8969 * clients using the GLX_OML_sync_control extension or 8970 * DRI3/Present extension with defined target_msc. 8971 */ 8972 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); 8973 } else { 8974 /* For variable refresh rate mode only: 8975 * Get vblank of last completed flip to avoid > 1 vrr 8976 * flips per video frame by use of throttling, but allow 8977 * flip programming anywhere in the possibly large 8978 * variable vrr vblank interval for fine-grained flip 8979 * timing control and more opportunity to avoid stutter 8980 * on late submission of flips. 8981 */ 8982 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8983 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank; 8984 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8985 } 8986 8987 target_vblank = last_flip_vblank + wait_for_vblank; 8988 8989 /* 8990 * Wait until we're out of the vertical blank period before the one 8991 * targeted by the flip 8992 */ 8993 while ((acrtc_attach->enabled && 8994 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 8995 0, &vpos, &hpos, NULL, 8996 NULL, &pcrtc->hwmode) 8997 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 8998 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 8999 (int)(target_vblank - 9000 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) { 9001 usleep_range(1000, 1100); 9002 } 9003 9004 /** 9005 * Prepare the flip event for the pageflip interrupt to handle. 9006 * 9007 * This only works in the case where we've already turned on the 9008 * appropriate hardware blocks (eg. HUBP) so in the transition case 9009 * from 0 -> n planes we have to skip a hardware generated event 9010 * and rely on sending it from software. 9011 */ 9012 if (acrtc_attach->base.state->event && 9013 acrtc_state->active_planes > 0) { 9014 drm_crtc_vblank_get(pcrtc); 9015 9016 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 9017 9018 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); 9019 prepare_flip_isr(acrtc_attach); 9020 9021 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 9022 } 9023 9024 if (acrtc_state->stream) { 9025 if (acrtc_state->freesync_vrr_info_changed) 9026 bundle->stream_update.vrr_infopacket = 9027 &acrtc_state->stream->vrr_infopacket; 9028 } 9029 } else if (cursor_update && acrtc_state->active_planes > 0) { 9030 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 9031 if (acrtc_attach->base.state->event) { 9032 drm_crtc_vblank_get(pcrtc); 9033 acrtc_attach->event = acrtc_attach->base.state->event; 9034 acrtc_attach->base.state->event = NULL; 9035 } 9036 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 9037 } 9038 9039 /* Update the planes if changed or disable if we don't have any. */ 9040 if ((planes_count || acrtc_state->active_planes == 0) && 9041 acrtc_state->stream) { 9042 /* 9043 * If PSR or idle optimizations are enabled then flush out 9044 * any pending work before hardware programming. 9045 */ 9046 if (dm->vblank_control_workqueue) 9047 flush_workqueue(dm->vblank_control_workqueue); 9048 9049 bundle->stream_update.stream = acrtc_state->stream; 9050 if (new_pcrtc_state->mode_changed) { 9051 bundle->stream_update.src = acrtc_state->stream->src; 9052 bundle->stream_update.dst = acrtc_state->stream->dst; 9053 } 9054 9055 if (new_pcrtc_state->color_mgmt_changed) { 9056 /* 9057 * TODO: This isn't fully correct since we've actually 9058 * already modified the stream in place. 9059 */ 9060 bundle->stream_update.gamut_remap = 9061 &acrtc_state->stream->gamut_remap_matrix; 9062 bundle->stream_update.output_csc_transform = 9063 &acrtc_state->stream->csc_color_matrix; 9064 bundle->stream_update.out_transfer_func = 9065 &acrtc_state->stream->out_transfer_func; 9066 bundle->stream_update.lut3d_func = 9067 (struct dc_3dlut *) acrtc_state->stream->lut3d_func; 9068 bundle->stream_update.func_shaper = 9069 (struct dc_transfer_func *) acrtc_state->stream->func_shaper; 9070 } 9071 9072 acrtc_state->stream->abm_level = acrtc_state->abm_level; 9073 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 9074 bundle->stream_update.abm_level = &acrtc_state->abm_level; 9075 9076 mutex_lock(&dm->dc_lock); 9077 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && 9078 acrtc_state->stream->link->psr_settings.psr_allow_active) 9079 amdgpu_dm_psr_disable(acrtc_state->stream); 9080 mutex_unlock(&dm->dc_lock); 9081 9082 /* 9083 * If FreeSync state on the stream has changed then we need to 9084 * re-adjust the min/max bounds now that DC doesn't handle this 9085 * as part of commit. 9086 */ 9087 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) { 9088 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 9089 dc_stream_adjust_vmin_vmax( 9090 dm->dc, acrtc_state->stream, 9091 &acrtc_attach->dm_irq_params.vrr_params.adjust); 9092 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 9093 } 9094 mutex_lock(&dm->dc_lock); 9095 update_planes_and_stream_adapter(dm->dc, 9096 acrtc_state->update_type, 9097 planes_count, 9098 acrtc_state->stream, 9099 &bundle->stream_update, 9100 bundle->surface_updates); 9101 updated_planes_and_streams = true; 9102 9103 /** 9104 * Enable or disable the interrupts on the backend. 9105 * 9106 * Most pipes are put into power gating when unused. 9107 * 9108 * When power gating is enabled on a pipe we lose the 9109 * interrupt enablement state when power gating is disabled. 9110 * 9111 * So we need to update the IRQ control state in hardware 9112 * whenever the pipe turns on (since it could be previously 9113 * power gated) or off (since some pipes can't be power gated 9114 * on some ASICs). 9115 */ 9116 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) 9117 dm_update_pflip_irq_state(drm_to_adev(dev), 9118 acrtc_attach); 9119 9120 if (acrtc_state->update_type > UPDATE_TYPE_FAST) { 9121 if (acrtc_state->stream->link->replay_settings.config.replay_supported && 9122 !acrtc_state->stream->link->replay_settings.replay_feature_enabled) { 9123 struct amdgpu_dm_connector *aconn = 9124 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; 9125 amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn); 9126 } else if (acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED && 9127 !acrtc_state->stream->link->psr_settings.psr_feature_enabled) { 9128 9129 struct amdgpu_dm_connector *aconn = (struct amdgpu_dm_connector *) 9130 acrtc_state->stream->dm_stream_context; 9131 9132 if (!aconn->disallow_edp_enter_psr) 9133 amdgpu_dm_link_setup_psr(acrtc_state->stream); 9134 } 9135 } 9136 9137 /* Decrement skip count when PSR is enabled and we're doing fast updates. */ 9138 if (acrtc_state->update_type == UPDATE_TYPE_FAST && 9139 acrtc_state->stream->link->psr_settings.psr_feature_enabled) { 9140 struct amdgpu_dm_connector *aconn = 9141 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; 9142 9143 if (aconn->psr_skip_count > 0) 9144 aconn->psr_skip_count--; 9145 9146 /* Allow PSR when skip count is 0. */ 9147 acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count; 9148 9149 /* 9150 * If sink supports PSR SU, there is no need to rely on 9151 * a vblank event disable request to enable PSR. PSR SU 9152 * can be enabled immediately once OS demonstrates an 9153 * adequate number of fast atomic commits to notify KMD 9154 * of update events. See `vblank_control_worker()`. 9155 */ 9156 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 9157 acrtc_attach->dm_irq_params.allow_psr_entry && 9158 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 9159 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && 9160 #endif 9161 !acrtc_state->stream->link->psr_settings.psr_allow_active && 9162 !aconn->disallow_edp_enter_psr && 9163 (timestamp_ns - 9164 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) > 9165 500000000) 9166 amdgpu_dm_psr_enable(acrtc_state->stream); 9167 } else { 9168 acrtc_attach->dm_irq_params.allow_psr_entry = false; 9169 } 9170 9171 mutex_unlock(&dm->dc_lock); 9172 } 9173 9174 /* 9175 * Update cursor state *after* programming all the planes. 9176 * This avoids redundant programming in the case where we're going 9177 * to be disabling a single plane - those pipes are being disabled. 9178 */ 9179 if (acrtc_state->active_planes && 9180 (!updated_planes_and_streams || amdgpu_ip_version(dm->adev, DCE_HWIP, 0) == 0) && 9181 acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) 9182 amdgpu_dm_commit_cursors(state); 9183 9184 cleanup: 9185 kfree(bundle); 9186 } 9187 9188 static void amdgpu_dm_commit_audio(struct drm_device *dev, 9189 struct drm_atomic_state *state) 9190 { 9191 struct amdgpu_device *adev = drm_to_adev(dev); 9192 struct amdgpu_dm_connector *aconnector; 9193 struct drm_connector *connector; 9194 struct drm_connector_state *old_con_state, *new_con_state; 9195 struct drm_crtc_state *new_crtc_state; 9196 struct dm_crtc_state *new_dm_crtc_state; 9197 const struct dc_stream_status *status; 9198 int i, inst; 9199 9200 /* Notify device removals. */ 9201 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 9202 if (old_con_state->crtc != new_con_state->crtc) { 9203 /* CRTC changes require notification. */ 9204 goto notify; 9205 } 9206 9207 if (!new_con_state->crtc) 9208 continue; 9209 9210 new_crtc_state = drm_atomic_get_new_crtc_state( 9211 state, new_con_state->crtc); 9212 9213 if (!new_crtc_state) 9214 continue; 9215 9216 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 9217 continue; 9218 9219 notify: 9220 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 9221 continue; 9222 9223 aconnector = to_amdgpu_dm_connector(connector); 9224 9225 mutex_lock(&adev->dm.audio_lock); 9226 inst = aconnector->audio_inst; 9227 aconnector->audio_inst = -1; 9228 mutex_unlock(&adev->dm.audio_lock); 9229 9230 amdgpu_dm_audio_eld_notify(adev, inst); 9231 } 9232 9233 /* Notify audio device additions. */ 9234 for_each_new_connector_in_state(state, connector, new_con_state, i) { 9235 if (!new_con_state->crtc) 9236 continue; 9237 9238 new_crtc_state = drm_atomic_get_new_crtc_state( 9239 state, new_con_state->crtc); 9240 9241 if (!new_crtc_state) 9242 continue; 9243 9244 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 9245 continue; 9246 9247 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 9248 if (!new_dm_crtc_state->stream) 9249 continue; 9250 9251 status = dc_stream_get_status(new_dm_crtc_state->stream); 9252 if (!status) 9253 continue; 9254 9255 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 9256 continue; 9257 9258 aconnector = to_amdgpu_dm_connector(connector); 9259 9260 mutex_lock(&adev->dm.audio_lock); 9261 inst = status->audio_inst; 9262 aconnector->audio_inst = inst; 9263 mutex_unlock(&adev->dm.audio_lock); 9264 9265 amdgpu_dm_audio_eld_notify(adev, inst); 9266 } 9267 } 9268 9269 /* 9270 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 9271 * @crtc_state: the DRM CRTC state 9272 * @stream_state: the DC stream state. 9273 * 9274 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 9275 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 9276 */ 9277 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 9278 struct dc_stream_state *stream_state) 9279 { 9280 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 9281 } 9282 9283 static void dm_clear_writeback(struct amdgpu_display_manager *dm, 9284 struct dm_crtc_state *crtc_state) 9285 { 9286 dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0); 9287 } 9288 9289 static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, 9290 struct dc_state *dc_state) 9291 { 9292 struct drm_device *dev = state->dev; 9293 struct amdgpu_device *adev = drm_to_adev(dev); 9294 struct amdgpu_display_manager *dm = &adev->dm; 9295 struct drm_crtc *crtc; 9296 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 9297 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 9298 struct drm_connector_state *old_con_state; 9299 struct drm_connector *connector; 9300 bool mode_set_reset_required = false; 9301 u32 i; 9302 struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count}; 9303 9304 /* Disable writeback */ 9305 for_each_old_connector_in_state(state, connector, old_con_state, i) { 9306 struct dm_connector_state *dm_old_con_state; 9307 struct amdgpu_crtc *acrtc; 9308 9309 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 9310 continue; 9311 9312 old_crtc_state = NULL; 9313 9314 dm_old_con_state = to_dm_connector_state(old_con_state); 9315 if (!dm_old_con_state->base.crtc) 9316 continue; 9317 9318 acrtc = to_amdgpu_crtc(dm_old_con_state->base.crtc); 9319 if (acrtc) 9320 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 9321 9322 if (!acrtc->wb_enabled) 9323 continue; 9324 9325 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9326 9327 dm_clear_writeback(dm, dm_old_crtc_state); 9328 acrtc->wb_enabled = false; 9329 } 9330 9331 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 9332 new_crtc_state, i) { 9333 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 9334 9335 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9336 9337 if (old_crtc_state->active && 9338 (!new_crtc_state->active || 9339 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 9340 manage_dm_interrupts(adev, acrtc, NULL); 9341 dc_stream_release(dm_old_crtc_state->stream); 9342 } 9343 } 9344 9345 drm_atomic_helper_calc_timestamping_constants(state); 9346 9347 /* update changed items */ 9348 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 9349 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 9350 9351 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9352 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9353 9354 drm_dbg_state(state->dev, 9355 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 9356 acrtc->crtc_id, 9357 new_crtc_state->enable, 9358 new_crtc_state->active, 9359 new_crtc_state->planes_changed, 9360 new_crtc_state->mode_changed, 9361 new_crtc_state->active_changed, 9362 new_crtc_state->connectors_changed); 9363 9364 /* Disable cursor if disabling crtc */ 9365 if (old_crtc_state->active && !new_crtc_state->active) { 9366 struct dc_cursor_position position; 9367 9368 memset(&position, 0, sizeof(position)); 9369 mutex_lock(&dm->dc_lock); 9370 dc_exit_ips_for_hw_access(dm->dc); 9371 dc_stream_program_cursor_position(dm_old_crtc_state->stream, &position); 9372 mutex_unlock(&dm->dc_lock); 9373 } 9374 9375 /* Copy all transient state flags into dc state */ 9376 if (dm_new_crtc_state->stream) { 9377 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 9378 dm_new_crtc_state->stream); 9379 } 9380 9381 /* handles headless hotplug case, updating new_state and 9382 * aconnector as needed 9383 */ 9384 9385 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 9386 9387 drm_dbg_atomic(dev, 9388 "Atomic commit: SET crtc id %d: [%p]\n", 9389 acrtc->crtc_id, acrtc); 9390 9391 if (!dm_new_crtc_state->stream) { 9392 /* 9393 * this could happen because of issues with 9394 * userspace notifications delivery. 9395 * In this case userspace tries to set mode on 9396 * display which is disconnected in fact. 9397 * dc_sink is NULL in this case on aconnector. 9398 * We expect reset mode will come soon. 9399 * 9400 * This can also happen when unplug is done 9401 * during resume sequence ended 9402 * 9403 * In this case, we want to pretend we still 9404 * have a sink to keep the pipe running so that 9405 * hw state is consistent with the sw state 9406 */ 9407 drm_dbg_atomic(dev, 9408 "Failed to create new stream for crtc %d\n", 9409 acrtc->base.base.id); 9410 continue; 9411 } 9412 9413 if (dm_old_crtc_state->stream) 9414 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 9415 9416 pm_runtime_get_noresume(dev->dev); 9417 9418 acrtc->enabled = true; 9419 acrtc->hw_mode = new_crtc_state->mode; 9420 crtc->hwmode = new_crtc_state->mode; 9421 mode_set_reset_required = true; 9422 } else if (modereset_required(new_crtc_state)) { 9423 drm_dbg_atomic(dev, 9424 "Atomic commit: RESET. crtc id %d:[%p]\n", 9425 acrtc->crtc_id, acrtc); 9426 /* i.e. reset mode */ 9427 if (dm_old_crtc_state->stream) 9428 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 9429 9430 mode_set_reset_required = true; 9431 } 9432 } /* for_each_crtc_in_state() */ 9433 9434 /* if there mode set or reset, disable eDP PSR, Replay */ 9435 if (mode_set_reset_required) { 9436 if (dm->vblank_control_workqueue) 9437 flush_workqueue(dm->vblank_control_workqueue); 9438 9439 amdgpu_dm_replay_disable_all(dm); 9440 amdgpu_dm_psr_disable_all(dm); 9441 } 9442 9443 dm_enable_per_frame_crtc_master_sync(dc_state); 9444 mutex_lock(&dm->dc_lock); 9445 dc_exit_ips_for_hw_access(dm->dc); 9446 WARN_ON(!dc_commit_streams(dm->dc, ¶ms)); 9447 9448 /* Allow idle optimization when vblank count is 0 for display off */ 9449 if (dm->active_vblank_irq_count == 0) 9450 dc_allow_idle_optimizations(dm->dc, true); 9451 mutex_unlock(&dm->dc_lock); 9452 9453 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 9454 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 9455 9456 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9457 9458 if (dm_new_crtc_state->stream != NULL) { 9459 const struct dc_stream_status *status = 9460 dc_stream_get_status(dm_new_crtc_state->stream); 9461 9462 if (!status) 9463 status = dc_state_get_stream_status(dc_state, 9464 dm_new_crtc_state->stream); 9465 if (!status) 9466 drm_err(dev, 9467 "got no status for stream %p on acrtc%p\n", 9468 dm_new_crtc_state->stream, acrtc); 9469 else 9470 acrtc->otg_inst = status->primary_otg_inst; 9471 } 9472 } 9473 } 9474 9475 static void dm_set_writeback(struct amdgpu_display_manager *dm, 9476 struct dm_crtc_state *crtc_state, 9477 struct drm_connector *connector, 9478 struct drm_connector_state *new_con_state) 9479 { 9480 struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector); 9481 struct amdgpu_device *adev = dm->adev; 9482 struct amdgpu_crtc *acrtc; 9483 struct dc_writeback_info *wb_info; 9484 struct pipe_ctx *pipe = NULL; 9485 struct amdgpu_framebuffer *afb; 9486 int i = 0; 9487 9488 wb_info = kzalloc(sizeof(*wb_info), GFP_KERNEL); 9489 if (!wb_info) { 9490 DRM_ERROR("Failed to allocate wb_info\n"); 9491 return; 9492 } 9493 9494 acrtc = to_amdgpu_crtc(wb_conn->encoder.crtc); 9495 if (!acrtc) { 9496 DRM_ERROR("no amdgpu_crtc found\n"); 9497 kfree(wb_info); 9498 return; 9499 } 9500 9501 afb = to_amdgpu_framebuffer(new_con_state->writeback_job->fb); 9502 if (!afb) { 9503 DRM_ERROR("No amdgpu_framebuffer found\n"); 9504 kfree(wb_info); 9505 return; 9506 } 9507 9508 for (i = 0; i < MAX_PIPES; i++) { 9509 if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) { 9510 pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i]; 9511 break; 9512 } 9513 } 9514 9515 /* fill in wb_info */ 9516 wb_info->wb_enabled = true; 9517 9518 wb_info->dwb_pipe_inst = 0; 9519 wb_info->dwb_params.dwbscl_black_color = 0; 9520 wb_info->dwb_params.hdr_mult = 0x1F000; 9521 wb_info->dwb_params.csc_params.gamut_adjust_type = CM_GAMUT_ADJUST_TYPE_BYPASS; 9522 wb_info->dwb_params.csc_params.gamut_coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13; 9523 wb_info->dwb_params.output_depth = DWB_OUTPUT_PIXEL_DEPTH_10BPC; 9524 wb_info->dwb_params.cnv_params.cnv_out_bpc = DWB_CNV_OUT_BPC_10BPC; 9525 9526 /* width & height from crtc */ 9527 wb_info->dwb_params.cnv_params.src_width = acrtc->base.mode.crtc_hdisplay; 9528 wb_info->dwb_params.cnv_params.src_height = acrtc->base.mode.crtc_vdisplay; 9529 wb_info->dwb_params.dest_width = acrtc->base.mode.crtc_hdisplay; 9530 wb_info->dwb_params.dest_height = acrtc->base.mode.crtc_vdisplay; 9531 9532 wb_info->dwb_params.cnv_params.crop_en = false; 9533 wb_info->dwb_params.stereo_params.stereo_enabled = false; 9534 9535 wb_info->dwb_params.cnv_params.out_max_pix_val = 0x3ff; // 10 bits 9536 wb_info->dwb_params.cnv_params.out_min_pix_val = 0; 9537 wb_info->dwb_params.cnv_params.fc_out_format = DWB_OUT_FORMAT_32BPP_ARGB; 9538 wb_info->dwb_params.cnv_params.out_denorm_mode = DWB_OUT_DENORM_BYPASS; 9539 9540 wb_info->dwb_params.out_format = dwb_scaler_mode_bypass444; 9541 9542 wb_info->dwb_params.capture_rate = dwb_capture_rate_0; 9543 9544 wb_info->dwb_params.scaler_taps.h_taps = 4; 9545 wb_info->dwb_params.scaler_taps.v_taps = 4; 9546 wb_info->dwb_params.scaler_taps.h_taps_c = 2; 9547 wb_info->dwb_params.scaler_taps.v_taps_c = 2; 9548 wb_info->dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING; 9549 9550 wb_info->mcif_buf_params.luma_pitch = afb->base.pitches[0]; 9551 wb_info->mcif_buf_params.chroma_pitch = afb->base.pitches[1]; 9552 9553 for (i = 0; i < DWB_MCIF_BUF_COUNT; i++) { 9554 wb_info->mcif_buf_params.luma_address[i] = afb->address; 9555 wb_info->mcif_buf_params.chroma_address[i] = 0; 9556 } 9557 9558 wb_info->mcif_buf_params.p_vmid = 1; 9559 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) { 9560 wb_info->mcif_warmup_params.start_address.quad_part = afb->address; 9561 wb_info->mcif_warmup_params.region_size = 9562 wb_info->mcif_buf_params.luma_pitch * wb_info->dwb_params.dest_height; 9563 } 9564 wb_info->mcif_warmup_params.p_vmid = 1; 9565 wb_info->writeback_source_plane = pipe->plane_state; 9566 9567 dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info); 9568 9569 acrtc->wb_pending = true; 9570 acrtc->wb_conn = wb_conn; 9571 drm_writeback_queue_job(wb_conn, new_con_state); 9572 } 9573 9574 /** 9575 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 9576 * @state: The atomic state to commit 9577 * 9578 * This will tell DC to commit the constructed DC state from atomic_check, 9579 * programming the hardware. Any failures here implies a hardware failure, since 9580 * atomic check should have filtered anything non-kosher. 9581 */ 9582 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) 9583 { 9584 struct drm_device *dev = state->dev; 9585 struct amdgpu_device *adev = drm_to_adev(dev); 9586 struct amdgpu_display_manager *dm = &adev->dm; 9587 struct dm_atomic_state *dm_state; 9588 struct dc_state *dc_state = NULL; 9589 u32 i, j; 9590 struct drm_crtc *crtc; 9591 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 9592 unsigned long flags; 9593 bool wait_for_vblank = true; 9594 struct drm_connector *connector; 9595 struct drm_connector_state *old_con_state, *new_con_state; 9596 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 9597 int crtc_disable_count = 0; 9598 9599 trace_amdgpu_dm_atomic_commit_tail_begin(state); 9600 9601 drm_atomic_helper_update_legacy_modeset_state(dev, state); 9602 drm_dp_mst_atomic_wait_for_dependencies(state); 9603 9604 dm_state = dm_atomic_get_new_state(state); 9605 if (dm_state && dm_state->context) { 9606 dc_state = dm_state->context; 9607 amdgpu_dm_commit_streams(state, dc_state); 9608 } 9609 9610 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 9611 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9612 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 9613 struct amdgpu_dm_connector *aconnector; 9614 9615 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 9616 continue; 9617 9618 aconnector = to_amdgpu_dm_connector(connector); 9619 9620 if (!adev->dm.hdcp_workqueue) 9621 continue; 9622 9623 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i); 9624 9625 if (!connector) 9626 continue; 9627 9628 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 9629 connector->index, connector->status, connector->dpms); 9630 pr_debug("[HDCP_DM] state protection old: %x new: %x\n", 9631 old_con_state->content_protection, new_con_state->content_protection); 9632 9633 if (aconnector->dc_sink) { 9634 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 9635 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) { 9636 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n", 9637 aconnector->dc_sink->edid_caps.display_name); 9638 } 9639 } 9640 9641 new_crtc_state = NULL; 9642 old_crtc_state = NULL; 9643 9644 if (acrtc) { 9645 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 9646 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 9647 } 9648 9649 if (old_crtc_state) 9650 pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 9651 old_crtc_state->enable, 9652 old_crtc_state->active, 9653 old_crtc_state->mode_changed, 9654 old_crtc_state->active_changed, 9655 old_crtc_state->connectors_changed); 9656 9657 if (new_crtc_state) 9658 pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 9659 new_crtc_state->enable, 9660 new_crtc_state->active, 9661 new_crtc_state->mode_changed, 9662 new_crtc_state->active_changed, 9663 new_crtc_state->connectors_changed); 9664 } 9665 9666 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 9667 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9668 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 9669 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 9670 9671 if (!adev->dm.hdcp_workqueue) 9672 continue; 9673 9674 new_crtc_state = NULL; 9675 old_crtc_state = NULL; 9676 9677 if (acrtc) { 9678 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 9679 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 9680 } 9681 9682 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9683 9684 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && 9685 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 9686 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 9687 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 9688 dm_new_con_state->update_hdcp = true; 9689 continue; 9690 } 9691 9692 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state, 9693 old_con_state, connector, adev->dm.hdcp_workqueue)) { 9694 /* when display is unplugged from mst hub, connctor will 9695 * be destroyed within dm_dp_mst_connector_destroy. connector 9696 * hdcp perperties, like type, undesired, desired, enabled, 9697 * will be lost. So, save hdcp properties into hdcp_work within 9698 * amdgpu_dm_atomic_commit_tail. if the same display is 9699 * plugged back with same display index, its hdcp properties 9700 * will be retrieved from hdcp_work within dm_dp_mst_get_modes 9701 */ 9702 9703 bool enable_encryption = false; 9704 9705 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) 9706 enable_encryption = true; 9707 9708 if (aconnector->dc_link && aconnector->dc_sink && 9709 aconnector->dc_link->type == dc_connection_mst_branch) { 9710 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; 9711 struct hdcp_workqueue *hdcp_w = 9712 &hdcp_work[aconnector->dc_link->link_index]; 9713 9714 hdcp_w->hdcp_content_type[connector->index] = 9715 new_con_state->hdcp_content_type; 9716 hdcp_w->content_protection[connector->index] = 9717 new_con_state->content_protection; 9718 } 9719 9720 if (new_crtc_state && new_crtc_state->mode_changed && 9721 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) 9722 enable_encryption = true; 9723 9724 DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption); 9725 9726 hdcp_update_display( 9727 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, 9728 new_con_state->hdcp_content_type, enable_encryption); 9729 } 9730 } 9731 9732 /* Handle connector state changes */ 9733 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 9734 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9735 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 9736 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 9737 struct dc_surface_update *dummy_updates; 9738 struct dc_stream_update stream_update; 9739 struct dc_info_packet hdr_packet; 9740 struct dc_stream_status *status = NULL; 9741 bool abm_changed, hdr_changed, scaling_changed; 9742 9743 memset(&stream_update, 0, sizeof(stream_update)); 9744 9745 if (acrtc) { 9746 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 9747 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 9748 } 9749 9750 /* Skip any modesets/resets */ 9751 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 9752 continue; 9753 9754 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9755 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9756 9757 scaling_changed = is_scaling_state_different(dm_new_con_state, 9758 dm_old_con_state); 9759 9760 abm_changed = dm_new_crtc_state->abm_level != 9761 dm_old_crtc_state->abm_level; 9762 9763 hdr_changed = 9764 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); 9765 9766 if (!scaling_changed && !abm_changed && !hdr_changed) 9767 continue; 9768 9769 stream_update.stream = dm_new_crtc_state->stream; 9770 if (scaling_changed) { 9771 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, 9772 dm_new_con_state, dm_new_crtc_state->stream); 9773 9774 stream_update.src = dm_new_crtc_state->stream->src; 9775 stream_update.dst = dm_new_crtc_state->stream->dst; 9776 } 9777 9778 if (abm_changed) { 9779 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 9780 9781 stream_update.abm_level = &dm_new_crtc_state->abm_level; 9782 } 9783 9784 if (hdr_changed) { 9785 fill_hdr_info_packet(new_con_state, &hdr_packet); 9786 stream_update.hdr_static_metadata = &hdr_packet; 9787 } 9788 9789 status = dc_stream_get_status(dm_new_crtc_state->stream); 9790 9791 if (WARN_ON(!status)) 9792 continue; 9793 9794 WARN_ON(!status->plane_count); 9795 9796 /* 9797 * TODO: DC refuses to perform stream updates without a dc_surface_update. 9798 * Here we create an empty update on each plane. 9799 * To fix this, DC should permit updating only stream properties. 9800 */ 9801 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC); 9802 if (!dummy_updates) { 9803 DRM_ERROR("Failed to allocate memory for dummy_updates.\n"); 9804 continue; 9805 } 9806 for (j = 0; j < status->plane_count; j++) 9807 dummy_updates[j].surface = status->plane_states[0]; 9808 9809 sort(dummy_updates, status->plane_count, 9810 sizeof(*dummy_updates), dm_plane_layer_index_cmp, NULL); 9811 9812 mutex_lock(&dm->dc_lock); 9813 dc_exit_ips_for_hw_access(dm->dc); 9814 dc_update_planes_and_stream(dm->dc, 9815 dummy_updates, 9816 status->plane_count, 9817 dm_new_crtc_state->stream, 9818 &stream_update); 9819 mutex_unlock(&dm->dc_lock); 9820 kfree(dummy_updates); 9821 } 9822 9823 /** 9824 * Enable interrupts for CRTCs that are newly enabled or went through 9825 * a modeset. It was intentionally deferred until after the front end 9826 * state was modified to wait until the OTG was on and so the IRQ 9827 * handlers didn't access stale or invalid state. 9828 */ 9829 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 9830 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 9831 #ifdef CONFIG_DEBUG_FS 9832 enum amdgpu_dm_pipe_crc_source cur_crc_src; 9833 #endif 9834 /* Count number of newly disabled CRTCs for dropping PM refs later. */ 9835 if (old_crtc_state->active && !new_crtc_state->active) 9836 crtc_disable_count++; 9837 9838 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9839 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9840 9841 /* For freesync config update on crtc state and params for irq */ 9842 update_stream_irq_parameters(dm, dm_new_crtc_state); 9843 9844 #ifdef CONFIG_DEBUG_FS 9845 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 9846 cur_crc_src = acrtc->dm_irq_params.crc_src; 9847 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 9848 #endif 9849 9850 if (new_crtc_state->active && 9851 (!old_crtc_state->active || 9852 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 9853 dc_stream_retain(dm_new_crtc_state->stream); 9854 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; 9855 manage_dm_interrupts(adev, acrtc, dm_new_crtc_state); 9856 } 9857 /* Handle vrr on->off / off->on transitions */ 9858 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state); 9859 9860 #ifdef CONFIG_DEBUG_FS 9861 if (new_crtc_state->active && 9862 (!old_crtc_state->active || 9863 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 9864 /** 9865 * Frontend may have changed so reapply the CRC capture 9866 * settings for the stream. 9867 */ 9868 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { 9869 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 9870 if (amdgpu_dm_crc_window_is_activated(crtc)) { 9871 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 9872 acrtc->dm_irq_params.window_param.update_win = true; 9873 9874 /** 9875 * It takes 2 frames for HW to stably generate CRC when 9876 * resuming from suspend, so we set skip_frame_cnt 2. 9877 */ 9878 acrtc->dm_irq_params.window_param.skip_frame_cnt = 2; 9879 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 9880 } 9881 #endif 9882 if (amdgpu_dm_crtc_configure_crc_source( 9883 crtc, dm_new_crtc_state, cur_crc_src)) 9884 drm_dbg_atomic(dev, "Failed to configure crc source"); 9885 } 9886 } 9887 #endif 9888 } 9889 9890 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 9891 if (new_crtc_state->async_flip) 9892 wait_for_vblank = false; 9893 9894 /* update planes when needed per crtc*/ 9895 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 9896 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9897 9898 if (dm_new_crtc_state->stream) 9899 amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank); 9900 } 9901 9902 /* Enable writeback */ 9903 for_each_new_connector_in_state(state, connector, new_con_state, i) { 9904 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9905 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 9906 9907 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 9908 continue; 9909 9910 if (!new_con_state->writeback_job) 9911 continue; 9912 9913 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 9914 9915 if (!new_crtc_state) 9916 continue; 9917 9918 if (acrtc->wb_enabled) 9919 continue; 9920 9921 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9922 9923 dm_set_writeback(dm, dm_new_crtc_state, connector, new_con_state); 9924 acrtc->wb_enabled = true; 9925 } 9926 9927 /* Update audio instances for each connector. */ 9928 amdgpu_dm_commit_audio(dev, state); 9929 9930 /* restore the backlight level */ 9931 for (i = 0; i < dm->num_of_edps; i++) { 9932 if (dm->backlight_dev[i] && 9933 (dm->actual_brightness[i] != dm->brightness[i])) 9934 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 9935 } 9936 9937 /* 9938 * send vblank event on all events not handled in flip and 9939 * mark consumed event for drm_atomic_helper_commit_hw_done 9940 */ 9941 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 9942 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 9943 9944 if (new_crtc_state->event) 9945 drm_send_event_locked(dev, &new_crtc_state->event->base); 9946 9947 new_crtc_state->event = NULL; 9948 } 9949 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 9950 9951 /* Signal HW programming completion */ 9952 drm_atomic_helper_commit_hw_done(state); 9953 9954 if (wait_for_vblank) 9955 drm_atomic_helper_wait_for_flip_done(dev, state); 9956 9957 drm_atomic_helper_cleanup_planes(dev, state); 9958 9959 /* Don't free the memory if we are hitting this as part of suspend. 9960 * This way we don't free any memory during suspend; see 9961 * amdgpu_bo_free_kernel(). The memory will be freed in the first 9962 * non-suspend modeset or when the driver is torn down. 9963 */ 9964 if (!adev->in_suspend) { 9965 /* return the stolen vga memory back to VRAM */ 9966 if (!adev->mman.keep_stolen_vga_memory) 9967 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 9968 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 9969 } 9970 9971 /* 9972 * Finally, drop a runtime PM reference for each newly disabled CRTC, 9973 * so we can put the GPU into runtime suspend if we're not driving any 9974 * displays anymore 9975 */ 9976 for (i = 0; i < crtc_disable_count; i++) 9977 pm_runtime_put_autosuspend(dev->dev); 9978 pm_runtime_mark_last_busy(dev->dev); 9979 } 9980 9981 static int dm_force_atomic_commit(struct drm_connector *connector) 9982 { 9983 int ret = 0; 9984 struct drm_device *ddev = connector->dev; 9985 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); 9986 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 9987 struct drm_plane *plane = disconnected_acrtc->base.primary; 9988 struct drm_connector_state *conn_state; 9989 struct drm_crtc_state *crtc_state; 9990 struct drm_plane_state *plane_state; 9991 9992 if (!state) 9993 return -ENOMEM; 9994 9995 state->acquire_ctx = ddev->mode_config.acquire_ctx; 9996 9997 /* Construct an atomic state to restore previous display setting */ 9998 9999 /* 10000 * Attach connectors to drm_atomic_state 10001 */ 10002 conn_state = drm_atomic_get_connector_state(state, connector); 10003 10004 ret = PTR_ERR_OR_ZERO(conn_state); 10005 if (ret) 10006 goto out; 10007 10008 /* Attach crtc to drm_atomic_state*/ 10009 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 10010 10011 ret = PTR_ERR_OR_ZERO(crtc_state); 10012 if (ret) 10013 goto out; 10014 10015 /* force a restore */ 10016 crtc_state->mode_changed = true; 10017 10018 /* Attach plane to drm_atomic_state */ 10019 plane_state = drm_atomic_get_plane_state(state, plane); 10020 10021 ret = PTR_ERR_OR_ZERO(plane_state); 10022 if (ret) 10023 goto out; 10024 10025 /* Call commit internally with the state we just constructed */ 10026 ret = drm_atomic_commit(state); 10027 10028 out: 10029 drm_atomic_state_put(state); 10030 if (ret) 10031 DRM_ERROR("Restoring old state failed with %i\n", ret); 10032 10033 return ret; 10034 } 10035 10036 /* 10037 * This function handles all cases when set mode does not come upon hotplug. 10038 * This includes when a display is unplugged then plugged back into the 10039 * same port and when running without usermode desktop manager supprot 10040 */ 10041 void dm_restore_drm_connector_state(struct drm_device *dev, 10042 struct drm_connector *connector) 10043 { 10044 struct amdgpu_dm_connector *aconnector; 10045 struct amdgpu_crtc *disconnected_acrtc; 10046 struct dm_crtc_state *acrtc_state; 10047 10048 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 10049 return; 10050 10051 aconnector = to_amdgpu_dm_connector(connector); 10052 10053 if (!aconnector->dc_sink || !connector->state || !connector->encoder) 10054 return; 10055 10056 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 10057 if (!disconnected_acrtc) 10058 return; 10059 10060 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); 10061 if (!acrtc_state->stream) 10062 return; 10063 10064 /* 10065 * If the previous sink is not released and different from the current, 10066 * we deduce we are in a state where we can not rely on usermode call 10067 * to turn on the display, so we do it here 10068 */ 10069 if (acrtc_state->stream->sink != aconnector->dc_sink) 10070 dm_force_atomic_commit(&aconnector->base); 10071 } 10072 10073 /* 10074 * Grabs all modesetting locks to serialize against any blocking commits, 10075 * Waits for completion of all non blocking commits. 10076 */ 10077 static int do_aquire_global_lock(struct drm_device *dev, 10078 struct drm_atomic_state *state) 10079 { 10080 struct drm_crtc *crtc; 10081 struct drm_crtc_commit *commit; 10082 long ret; 10083 10084 /* 10085 * Adding all modeset locks to aquire_ctx will 10086 * ensure that when the framework release it the 10087 * extra locks we are locking here will get released to 10088 */ 10089 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 10090 if (ret) 10091 return ret; 10092 10093 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 10094 spin_lock(&crtc->commit_lock); 10095 commit = list_first_entry_or_null(&crtc->commit_list, 10096 struct drm_crtc_commit, commit_entry); 10097 if (commit) 10098 drm_crtc_commit_get(commit); 10099 spin_unlock(&crtc->commit_lock); 10100 10101 if (!commit) 10102 continue; 10103 10104 /* 10105 * Make sure all pending HW programming completed and 10106 * page flips done 10107 */ 10108 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 10109 10110 if (ret > 0) 10111 ret = wait_for_completion_interruptible_timeout( 10112 &commit->flip_done, 10*HZ); 10113 10114 if (ret == 0) 10115 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n", 10116 crtc->base.id, crtc->name); 10117 10118 drm_crtc_commit_put(commit); 10119 } 10120 10121 return ret < 0 ? ret : 0; 10122 } 10123 10124 static void get_freesync_config_for_crtc( 10125 struct dm_crtc_state *new_crtc_state, 10126 struct dm_connector_state *new_con_state) 10127 { 10128 struct mod_freesync_config config = {0}; 10129 struct amdgpu_dm_connector *aconnector; 10130 struct drm_display_mode *mode = &new_crtc_state->base.mode; 10131 int vrefresh = drm_mode_vrefresh(mode); 10132 bool fs_vid_mode = false; 10133 10134 if (new_con_state->base.connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 10135 return; 10136 10137 aconnector = to_amdgpu_dm_connector(new_con_state->base.connector); 10138 10139 new_crtc_state->vrr_supported = new_con_state->freesync_capable && 10140 vrefresh >= aconnector->min_vfreq && 10141 vrefresh <= aconnector->max_vfreq; 10142 10143 if (new_crtc_state->vrr_supported) { 10144 new_crtc_state->stream->ignore_msa_timing_param = true; 10145 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 10146 10147 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000; 10148 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000; 10149 config.vsif_supported = true; 10150 config.btr = true; 10151 10152 if (fs_vid_mode) { 10153 config.state = VRR_STATE_ACTIVE_FIXED; 10154 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz; 10155 goto out; 10156 } else if (new_crtc_state->base.vrr_enabled) { 10157 config.state = VRR_STATE_ACTIVE_VARIABLE; 10158 } else { 10159 config.state = VRR_STATE_INACTIVE; 10160 } 10161 } 10162 out: 10163 new_crtc_state->freesync_config = config; 10164 } 10165 10166 static void reset_freesync_config_for_crtc( 10167 struct dm_crtc_state *new_crtc_state) 10168 { 10169 new_crtc_state->vrr_supported = false; 10170 10171 memset(&new_crtc_state->vrr_infopacket, 0, 10172 sizeof(new_crtc_state->vrr_infopacket)); 10173 } 10174 10175 static bool 10176 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 10177 struct drm_crtc_state *new_crtc_state) 10178 { 10179 const struct drm_display_mode *old_mode, *new_mode; 10180 10181 if (!old_crtc_state || !new_crtc_state) 10182 return false; 10183 10184 old_mode = &old_crtc_state->mode; 10185 new_mode = &new_crtc_state->mode; 10186 10187 if (old_mode->clock == new_mode->clock && 10188 old_mode->hdisplay == new_mode->hdisplay && 10189 old_mode->vdisplay == new_mode->vdisplay && 10190 old_mode->htotal == new_mode->htotal && 10191 old_mode->vtotal != new_mode->vtotal && 10192 old_mode->hsync_start == new_mode->hsync_start && 10193 old_mode->vsync_start != new_mode->vsync_start && 10194 old_mode->hsync_end == new_mode->hsync_end && 10195 old_mode->vsync_end != new_mode->vsync_end && 10196 old_mode->hskew == new_mode->hskew && 10197 old_mode->vscan == new_mode->vscan && 10198 (old_mode->vsync_end - old_mode->vsync_start) == 10199 (new_mode->vsync_end - new_mode->vsync_start)) 10200 return true; 10201 10202 return false; 10203 } 10204 10205 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) 10206 { 10207 u64 num, den, res; 10208 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base; 10209 10210 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED; 10211 10212 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000; 10213 den = (unsigned long long)new_crtc_state->mode.htotal * 10214 (unsigned long long)new_crtc_state->mode.vtotal; 10215 10216 res = div_u64(num, den); 10217 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res; 10218 } 10219 10220 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 10221 struct drm_atomic_state *state, 10222 struct drm_crtc *crtc, 10223 struct drm_crtc_state *old_crtc_state, 10224 struct drm_crtc_state *new_crtc_state, 10225 bool enable, 10226 bool *lock_and_validation_needed) 10227 { 10228 struct dm_atomic_state *dm_state = NULL; 10229 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 10230 struct dc_stream_state *new_stream; 10231 int ret = 0; 10232 10233 /* 10234 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 10235 * update changed items 10236 */ 10237 struct amdgpu_crtc *acrtc = NULL; 10238 struct drm_connector *connector = NULL; 10239 struct amdgpu_dm_connector *aconnector = NULL; 10240 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 10241 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 10242 10243 new_stream = NULL; 10244 10245 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 10246 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 10247 acrtc = to_amdgpu_crtc(crtc); 10248 connector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 10249 if (connector) 10250 aconnector = to_amdgpu_dm_connector(connector); 10251 10252 /* TODO This hack should go away */ 10253 if (connector && enable) { 10254 /* Make sure fake sink is created in plug-in scenario */ 10255 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 10256 connector); 10257 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 10258 connector); 10259 10260 if (IS_ERR(drm_new_conn_state)) { 10261 ret = PTR_ERR_OR_ZERO(drm_new_conn_state); 10262 goto fail; 10263 } 10264 10265 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 10266 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 10267 10268 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 10269 goto skip_modeset; 10270 10271 new_stream = create_validate_stream_for_sink(aconnector, 10272 &new_crtc_state->mode, 10273 dm_new_conn_state, 10274 dm_old_crtc_state->stream); 10275 10276 /* 10277 * we can have no stream on ACTION_SET if a display 10278 * was disconnected during S3, in this case it is not an 10279 * error, the OS will be updated after detection, and 10280 * will do the right thing on next atomic commit 10281 */ 10282 10283 if (!new_stream) { 10284 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 10285 __func__, acrtc->base.base.id); 10286 ret = -ENOMEM; 10287 goto fail; 10288 } 10289 10290 /* 10291 * TODO: Check VSDB bits to decide whether this should 10292 * be enabled or not. 10293 */ 10294 new_stream->triggered_crtc_reset.enabled = 10295 dm->force_timing_sync; 10296 10297 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 10298 10299 ret = fill_hdr_info_packet(drm_new_conn_state, 10300 &new_stream->hdr_static_metadata); 10301 if (ret) 10302 goto fail; 10303 10304 /* 10305 * If we already removed the old stream from the context 10306 * (and set the new stream to NULL) then we can't reuse 10307 * the old stream even if the stream and scaling are unchanged. 10308 * We'll hit the BUG_ON and black screen. 10309 * 10310 * TODO: Refactor this function to allow this check to work 10311 * in all conditions. 10312 */ 10313 if (amdgpu_freesync_vid_mode && 10314 dm_new_crtc_state->stream && 10315 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state)) 10316 goto skip_modeset; 10317 10318 if (dm_new_crtc_state->stream && 10319 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 10320 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 10321 new_crtc_state->mode_changed = false; 10322 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", 10323 new_crtc_state->mode_changed); 10324 } 10325 } 10326 10327 /* mode_changed flag may get updated above, need to check again */ 10328 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 10329 goto skip_modeset; 10330 10331 drm_dbg_state(state->dev, 10332 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 10333 acrtc->crtc_id, 10334 new_crtc_state->enable, 10335 new_crtc_state->active, 10336 new_crtc_state->planes_changed, 10337 new_crtc_state->mode_changed, 10338 new_crtc_state->active_changed, 10339 new_crtc_state->connectors_changed); 10340 10341 /* Remove stream for any changed/disabled CRTC */ 10342 if (!enable) { 10343 10344 if (!dm_old_crtc_state->stream) 10345 goto skip_modeset; 10346 10347 /* Unset freesync video if it was active before */ 10348 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) { 10349 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE; 10350 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0; 10351 } 10352 10353 /* Now check if we should set freesync video mode */ 10354 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream && 10355 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 10356 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) && 10357 is_timing_unchanged_for_freesync(new_crtc_state, 10358 old_crtc_state)) { 10359 new_crtc_state->mode_changed = false; 10360 DRM_DEBUG_DRIVER( 10361 "Mode change not required for front porch change, setting mode_changed to %d", 10362 new_crtc_state->mode_changed); 10363 10364 set_freesync_fixed_config(dm_new_crtc_state); 10365 10366 goto skip_modeset; 10367 } else if (amdgpu_freesync_vid_mode && aconnector && 10368 is_freesync_video_mode(&new_crtc_state->mode, 10369 aconnector)) { 10370 struct drm_display_mode *high_mode; 10371 10372 high_mode = get_highest_refresh_rate_mode(aconnector, false); 10373 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) 10374 set_freesync_fixed_config(dm_new_crtc_state); 10375 } 10376 10377 ret = dm_atomic_get_state(state, &dm_state); 10378 if (ret) 10379 goto fail; 10380 10381 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", 10382 crtc->base.id); 10383 10384 /* i.e. reset mode */ 10385 if (dc_state_remove_stream( 10386 dm->dc, 10387 dm_state->context, 10388 dm_old_crtc_state->stream) != DC_OK) { 10389 ret = -EINVAL; 10390 goto fail; 10391 } 10392 10393 dc_stream_release(dm_old_crtc_state->stream); 10394 dm_new_crtc_state->stream = NULL; 10395 10396 reset_freesync_config_for_crtc(dm_new_crtc_state); 10397 10398 *lock_and_validation_needed = true; 10399 10400 } else {/* Add stream for any updated/enabled CRTC */ 10401 /* 10402 * Quick fix to prevent NULL pointer on new_stream when 10403 * added MST connectors not found in existing crtc_state in the chained mode 10404 * TODO: need to dig out the root cause of that 10405 */ 10406 if (!connector) 10407 goto skip_modeset; 10408 10409 if (modereset_required(new_crtc_state)) 10410 goto skip_modeset; 10411 10412 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream, 10413 dm_old_crtc_state->stream)) { 10414 10415 WARN_ON(dm_new_crtc_state->stream); 10416 10417 ret = dm_atomic_get_state(state, &dm_state); 10418 if (ret) 10419 goto fail; 10420 10421 dm_new_crtc_state->stream = new_stream; 10422 10423 dc_stream_retain(new_stream); 10424 10425 DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n", 10426 crtc->base.id); 10427 10428 if (dc_state_add_stream( 10429 dm->dc, 10430 dm_state->context, 10431 dm_new_crtc_state->stream) != DC_OK) { 10432 ret = -EINVAL; 10433 goto fail; 10434 } 10435 10436 *lock_and_validation_needed = true; 10437 } 10438 } 10439 10440 skip_modeset: 10441 /* Release extra reference */ 10442 if (new_stream) 10443 dc_stream_release(new_stream); 10444 10445 /* 10446 * We want to do dc stream updates that do not require a 10447 * full modeset below. 10448 */ 10449 if (!(enable && connector && new_crtc_state->active)) 10450 return 0; 10451 /* 10452 * Given above conditions, the dc state cannot be NULL because: 10453 * 1. We're in the process of enabling CRTCs (just been added 10454 * to the dc context, or already is on the context) 10455 * 2. Has a valid connector attached, and 10456 * 3. Is currently active and enabled. 10457 * => The dc stream state currently exists. 10458 */ 10459 BUG_ON(dm_new_crtc_state->stream == NULL); 10460 10461 /* Scaling or underscan settings */ 10462 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || 10463 drm_atomic_crtc_needs_modeset(new_crtc_state)) 10464 update_stream_scaling_settings( 10465 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 10466 10467 /* ABM settings */ 10468 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 10469 10470 /* 10471 * Color management settings. We also update color properties 10472 * when a modeset is needed, to ensure it gets reprogrammed. 10473 */ 10474 if (dm_new_crtc_state->base.color_mgmt_changed || 10475 dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf || 10476 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 10477 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); 10478 if (ret) 10479 goto fail; 10480 } 10481 10482 /* Update Freesync settings. */ 10483 get_freesync_config_for_crtc(dm_new_crtc_state, 10484 dm_new_conn_state); 10485 10486 return ret; 10487 10488 fail: 10489 if (new_stream) 10490 dc_stream_release(new_stream); 10491 return ret; 10492 } 10493 10494 static bool should_reset_plane(struct drm_atomic_state *state, 10495 struct drm_plane *plane, 10496 struct drm_plane_state *old_plane_state, 10497 struct drm_plane_state *new_plane_state) 10498 { 10499 struct drm_plane *other; 10500 struct drm_plane_state *old_other_state, *new_other_state; 10501 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 10502 struct dm_crtc_state *old_dm_crtc_state, *new_dm_crtc_state; 10503 struct amdgpu_device *adev = drm_to_adev(plane->dev); 10504 int i; 10505 10506 /* 10507 * TODO: Remove this hack for all asics once it proves that the 10508 * fast updates works fine on DCN3.2+. 10509 */ 10510 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 2, 0) && 10511 state->allow_modeset) 10512 return true; 10513 10514 /* Exit early if we know that we're adding or removing the plane. */ 10515 if (old_plane_state->crtc != new_plane_state->crtc) 10516 return true; 10517 10518 /* old crtc == new_crtc == NULL, plane not in context. */ 10519 if (!new_plane_state->crtc) 10520 return false; 10521 10522 new_crtc_state = 10523 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 10524 old_crtc_state = 10525 drm_atomic_get_old_crtc_state(state, old_plane_state->crtc); 10526 10527 if (!new_crtc_state) 10528 return true; 10529 10530 /* 10531 * A change in cursor mode means a new dc pipe needs to be acquired or 10532 * released from the state 10533 */ 10534 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state); 10535 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 10536 if (plane->type == DRM_PLANE_TYPE_CURSOR && 10537 old_dm_crtc_state != NULL && 10538 old_dm_crtc_state->cursor_mode != new_dm_crtc_state->cursor_mode) { 10539 return true; 10540 } 10541 10542 /* CRTC Degamma changes currently require us to recreate planes. */ 10543 if (new_crtc_state->color_mgmt_changed) 10544 return true; 10545 10546 /* 10547 * On zpos change, planes need to be reordered by removing and re-adding 10548 * them one by one to the dc state, in order of descending zpos. 10549 * 10550 * TODO: We can likely skip bandwidth validation if the only thing that 10551 * changed about the plane was it'z z-ordering. 10552 */ 10553 if (new_crtc_state->zpos_changed) 10554 return true; 10555 10556 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) 10557 return true; 10558 10559 /* 10560 * If there are any new primary or overlay planes being added or 10561 * removed then the z-order can potentially change. To ensure 10562 * correct z-order and pipe acquisition the current DC architecture 10563 * requires us to remove and recreate all existing planes. 10564 * 10565 * TODO: Come up with a more elegant solution for this. 10566 */ 10567 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 10568 struct amdgpu_framebuffer *old_afb, *new_afb; 10569 struct dm_plane_state *dm_new_other_state, *dm_old_other_state; 10570 10571 dm_new_other_state = to_dm_plane_state(new_other_state); 10572 dm_old_other_state = to_dm_plane_state(old_other_state); 10573 10574 if (other->type == DRM_PLANE_TYPE_CURSOR) 10575 continue; 10576 10577 if (old_other_state->crtc != new_plane_state->crtc && 10578 new_other_state->crtc != new_plane_state->crtc) 10579 continue; 10580 10581 if (old_other_state->crtc != new_other_state->crtc) 10582 return true; 10583 10584 /* Src/dst size and scaling updates. */ 10585 if (old_other_state->src_w != new_other_state->src_w || 10586 old_other_state->src_h != new_other_state->src_h || 10587 old_other_state->crtc_w != new_other_state->crtc_w || 10588 old_other_state->crtc_h != new_other_state->crtc_h) 10589 return true; 10590 10591 /* Rotation / mirroring updates. */ 10592 if (old_other_state->rotation != new_other_state->rotation) 10593 return true; 10594 10595 /* Blending updates. */ 10596 if (old_other_state->pixel_blend_mode != 10597 new_other_state->pixel_blend_mode) 10598 return true; 10599 10600 /* Alpha updates. */ 10601 if (old_other_state->alpha != new_other_state->alpha) 10602 return true; 10603 10604 /* Colorspace changes. */ 10605 if (old_other_state->color_range != new_other_state->color_range || 10606 old_other_state->color_encoding != new_other_state->color_encoding) 10607 return true; 10608 10609 /* HDR/Transfer Function changes. */ 10610 if (dm_old_other_state->degamma_tf != dm_new_other_state->degamma_tf || 10611 dm_old_other_state->degamma_lut != dm_new_other_state->degamma_lut || 10612 dm_old_other_state->hdr_mult != dm_new_other_state->hdr_mult || 10613 dm_old_other_state->ctm != dm_new_other_state->ctm || 10614 dm_old_other_state->shaper_lut != dm_new_other_state->shaper_lut || 10615 dm_old_other_state->shaper_tf != dm_new_other_state->shaper_tf || 10616 dm_old_other_state->lut3d != dm_new_other_state->lut3d || 10617 dm_old_other_state->blend_lut != dm_new_other_state->blend_lut || 10618 dm_old_other_state->blend_tf != dm_new_other_state->blend_tf) 10619 return true; 10620 10621 /* Framebuffer checks fall at the end. */ 10622 if (!old_other_state->fb || !new_other_state->fb) 10623 continue; 10624 10625 /* Pixel format changes can require bandwidth updates. */ 10626 if (old_other_state->fb->format != new_other_state->fb->format) 10627 return true; 10628 10629 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; 10630 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb; 10631 10632 /* Tiling and DCC changes also require bandwidth updates. */ 10633 if (old_afb->tiling_flags != new_afb->tiling_flags || 10634 old_afb->base.modifier != new_afb->base.modifier) 10635 return true; 10636 } 10637 10638 return false; 10639 } 10640 10641 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, 10642 struct drm_plane_state *new_plane_state, 10643 struct drm_framebuffer *fb) 10644 { 10645 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev); 10646 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); 10647 unsigned int pitch; 10648 bool linear; 10649 10650 if (fb->width > new_acrtc->max_cursor_width || 10651 fb->height > new_acrtc->max_cursor_height) { 10652 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n", 10653 new_plane_state->fb->width, 10654 new_plane_state->fb->height); 10655 return -EINVAL; 10656 } 10657 if (new_plane_state->src_w != fb->width << 16 || 10658 new_plane_state->src_h != fb->height << 16) { 10659 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 10660 return -EINVAL; 10661 } 10662 10663 /* Pitch in pixels */ 10664 pitch = fb->pitches[0] / fb->format->cpp[0]; 10665 10666 if (fb->width != pitch) { 10667 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d", 10668 fb->width, pitch); 10669 return -EINVAL; 10670 } 10671 10672 switch (pitch) { 10673 case 64: 10674 case 128: 10675 case 256: 10676 /* FB pitch is supported by cursor plane */ 10677 break; 10678 default: 10679 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch); 10680 return -EINVAL; 10681 } 10682 10683 /* Core DRM takes care of checking FB modifiers, so we only need to 10684 * check tiling flags when the FB doesn't have a modifier. 10685 */ 10686 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { 10687 if (adev->family >= AMDGPU_FAMILY_GC_12_0_0) { 10688 linear = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE) == 0; 10689 } else if (adev->family >= AMDGPU_FAMILY_AI) { 10690 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; 10691 } else { 10692 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && 10693 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && 10694 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; 10695 } 10696 if (!linear) { 10697 DRM_DEBUG_ATOMIC("Cursor FB not linear"); 10698 return -EINVAL; 10699 } 10700 } 10701 10702 return 0; 10703 } 10704 10705 /* 10706 * Helper function for checking the cursor in native mode 10707 */ 10708 static int dm_check_native_cursor_state(struct drm_crtc *new_plane_crtc, 10709 struct drm_plane *plane, 10710 struct drm_plane_state *new_plane_state, 10711 bool enable) 10712 { 10713 10714 struct amdgpu_crtc *new_acrtc; 10715 int ret; 10716 10717 if (!enable || !new_plane_crtc || 10718 drm_atomic_plane_disabling(plane->state, new_plane_state)) 10719 return 0; 10720 10721 new_acrtc = to_amdgpu_crtc(new_plane_crtc); 10722 10723 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) { 10724 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 10725 return -EINVAL; 10726 } 10727 10728 if (new_plane_state->fb) { 10729 ret = dm_check_cursor_fb(new_acrtc, new_plane_state, 10730 new_plane_state->fb); 10731 if (ret) 10732 return ret; 10733 } 10734 10735 return 0; 10736 } 10737 10738 static bool dm_should_update_native_cursor(struct drm_atomic_state *state, 10739 struct drm_crtc *old_plane_crtc, 10740 struct drm_crtc *new_plane_crtc, 10741 bool enable) 10742 { 10743 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 10744 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 10745 10746 if (!enable) { 10747 if (old_plane_crtc == NULL) 10748 return true; 10749 10750 old_crtc_state = drm_atomic_get_old_crtc_state( 10751 state, old_plane_crtc); 10752 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 10753 10754 return dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE; 10755 } else { 10756 if (new_plane_crtc == NULL) 10757 return true; 10758 10759 new_crtc_state = drm_atomic_get_new_crtc_state( 10760 state, new_plane_crtc); 10761 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 10762 10763 return dm_new_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE; 10764 } 10765 } 10766 10767 static int dm_update_plane_state(struct dc *dc, 10768 struct drm_atomic_state *state, 10769 struct drm_plane *plane, 10770 struct drm_plane_state *old_plane_state, 10771 struct drm_plane_state *new_plane_state, 10772 bool enable, 10773 bool *lock_and_validation_needed, 10774 bool *is_top_most_overlay) 10775 { 10776 10777 struct dm_atomic_state *dm_state = NULL; 10778 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 10779 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 10780 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 10781 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 10782 bool needs_reset, update_native_cursor; 10783 int ret = 0; 10784 10785 10786 new_plane_crtc = new_plane_state->crtc; 10787 old_plane_crtc = old_plane_state->crtc; 10788 dm_new_plane_state = to_dm_plane_state(new_plane_state); 10789 dm_old_plane_state = to_dm_plane_state(old_plane_state); 10790 10791 update_native_cursor = dm_should_update_native_cursor(state, 10792 old_plane_crtc, 10793 new_plane_crtc, 10794 enable); 10795 10796 if (plane->type == DRM_PLANE_TYPE_CURSOR && update_native_cursor) { 10797 ret = dm_check_native_cursor_state(new_plane_crtc, plane, 10798 new_plane_state, enable); 10799 if (ret) 10800 return ret; 10801 10802 return 0; 10803 } 10804 10805 needs_reset = should_reset_plane(state, plane, old_plane_state, 10806 new_plane_state); 10807 10808 /* Remove any changed/removed planes */ 10809 if (!enable) { 10810 if (!needs_reset) 10811 return 0; 10812 10813 if (!old_plane_crtc) 10814 return 0; 10815 10816 old_crtc_state = drm_atomic_get_old_crtc_state( 10817 state, old_plane_crtc); 10818 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 10819 10820 if (!dm_old_crtc_state->stream) 10821 return 0; 10822 10823 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", 10824 plane->base.id, old_plane_crtc->base.id); 10825 10826 ret = dm_atomic_get_state(state, &dm_state); 10827 if (ret) 10828 return ret; 10829 10830 if (!dc_state_remove_plane( 10831 dc, 10832 dm_old_crtc_state->stream, 10833 dm_old_plane_state->dc_state, 10834 dm_state->context)) { 10835 10836 return -EINVAL; 10837 } 10838 10839 if (dm_old_plane_state->dc_state) 10840 dc_plane_state_release(dm_old_plane_state->dc_state); 10841 10842 dm_new_plane_state->dc_state = NULL; 10843 10844 *lock_and_validation_needed = true; 10845 10846 } else { /* Add new planes */ 10847 struct dc_plane_state *dc_new_plane_state; 10848 10849 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 10850 return 0; 10851 10852 if (!new_plane_crtc) 10853 return 0; 10854 10855 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 10856 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 10857 10858 if (!dm_new_crtc_state->stream) 10859 return 0; 10860 10861 if (!needs_reset) 10862 return 0; 10863 10864 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); 10865 if (ret) 10866 goto out; 10867 10868 WARN_ON(dm_new_plane_state->dc_state); 10869 10870 dc_new_plane_state = dc_create_plane_state(dc); 10871 if (!dc_new_plane_state) { 10872 ret = -ENOMEM; 10873 goto out; 10874 } 10875 10876 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n", 10877 plane->base.id, new_plane_crtc->base.id); 10878 10879 ret = fill_dc_plane_attributes( 10880 drm_to_adev(new_plane_crtc->dev), 10881 dc_new_plane_state, 10882 new_plane_state, 10883 new_crtc_state); 10884 if (ret) { 10885 dc_plane_state_release(dc_new_plane_state); 10886 goto out; 10887 } 10888 10889 ret = dm_atomic_get_state(state, &dm_state); 10890 if (ret) { 10891 dc_plane_state_release(dc_new_plane_state); 10892 goto out; 10893 } 10894 10895 /* 10896 * Any atomic check errors that occur after this will 10897 * not need a release. The plane state will be attached 10898 * to the stream, and therefore part of the atomic 10899 * state. It'll be released when the atomic state is 10900 * cleaned. 10901 */ 10902 if (!dc_state_add_plane( 10903 dc, 10904 dm_new_crtc_state->stream, 10905 dc_new_plane_state, 10906 dm_state->context)) { 10907 10908 dc_plane_state_release(dc_new_plane_state); 10909 ret = -EINVAL; 10910 goto out; 10911 } 10912 10913 dm_new_plane_state->dc_state = dc_new_plane_state; 10914 10915 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY); 10916 10917 /* Tell DC to do a full surface update every time there 10918 * is a plane change. Inefficient, but works for now. 10919 */ 10920 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; 10921 10922 *lock_and_validation_needed = true; 10923 } 10924 10925 out: 10926 /* If enabling cursor overlay failed, attempt fallback to native mode */ 10927 if (enable && ret == -EINVAL && plane->type == DRM_PLANE_TYPE_CURSOR) { 10928 ret = dm_check_native_cursor_state(new_plane_crtc, plane, 10929 new_plane_state, enable); 10930 if (ret) 10931 return ret; 10932 10933 dm_new_crtc_state->cursor_mode = DM_CURSOR_NATIVE_MODE; 10934 } 10935 10936 return ret; 10937 } 10938 10939 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state, 10940 int *src_w, int *src_h) 10941 { 10942 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 10943 case DRM_MODE_ROTATE_90: 10944 case DRM_MODE_ROTATE_270: 10945 *src_w = plane_state->src_h >> 16; 10946 *src_h = plane_state->src_w >> 16; 10947 break; 10948 case DRM_MODE_ROTATE_0: 10949 case DRM_MODE_ROTATE_180: 10950 default: 10951 *src_w = plane_state->src_w >> 16; 10952 *src_h = plane_state->src_h >> 16; 10953 break; 10954 } 10955 } 10956 10957 static void 10958 dm_get_plane_scale(struct drm_plane_state *plane_state, 10959 int *out_plane_scale_w, int *out_plane_scale_h) 10960 { 10961 int plane_src_w, plane_src_h; 10962 10963 dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h); 10964 *out_plane_scale_w = plane_state->crtc_w * 1000 / plane_src_w; 10965 *out_plane_scale_h = plane_state->crtc_h * 1000 / plane_src_h; 10966 } 10967 10968 /* 10969 * The normalized_zpos value cannot be used by this iterator directly. It's only 10970 * calculated for enabled planes, potentially causing normalized_zpos collisions 10971 * between enabled/disabled planes in the atomic state. We need a unique value 10972 * so that the iterator will not generate the same object twice, or loop 10973 * indefinitely. 10974 */ 10975 static inline struct __drm_planes_state *__get_next_zpos( 10976 struct drm_atomic_state *state, 10977 struct __drm_planes_state *prev) 10978 { 10979 unsigned int highest_zpos = 0, prev_zpos = 256; 10980 uint32_t highest_id = 0, prev_id = UINT_MAX; 10981 struct drm_plane_state *new_plane_state; 10982 struct drm_plane *plane; 10983 int i, highest_i = -1; 10984 10985 if (prev != NULL) { 10986 prev_zpos = prev->new_state->zpos; 10987 prev_id = prev->ptr->base.id; 10988 } 10989 10990 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 10991 /* Skip planes with higher zpos than the previously returned */ 10992 if (new_plane_state->zpos > prev_zpos || 10993 (new_plane_state->zpos == prev_zpos && 10994 plane->base.id >= prev_id)) 10995 continue; 10996 10997 /* Save the index of the plane with highest zpos */ 10998 if (new_plane_state->zpos > highest_zpos || 10999 (new_plane_state->zpos == highest_zpos && 11000 plane->base.id > highest_id)) { 11001 highest_zpos = new_plane_state->zpos; 11002 highest_id = plane->base.id; 11003 highest_i = i; 11004 } 11005 } 11006 11007 if (highest_i < 0) 11008 return NULL; 11009 11010 return &state->planes[highest_i]; 11011 } 11012 11013 /* 11014 * Use the uniqueness of the plane's (zpos, drm obj ID) combination to iterate 11015 * by descending zpos, as read from the new plane state. This is the same 11016 * ordering as defined by drm_atomic_normalize_zpos(). 11017 */ 11018 #define for_each_oldnew_plane_in_descending_zpos(__state, plane, old_plane_state, new_plane_state) \ 11019 for (struct __drm_planes_state *__i = __get_next_zpos((__state), NULL); \ 11020 __i != NULL; __i = __get_next_zpos((__state), __i)) \ 11021 for_each_if(((plane) = __i->ptr, \ 11022 (void)(plane) /* Only to avoid unused-but-set-variable warning */, \ 11023 (old_plane_state) = __i->old_state, \ 11024 (new_plane_state) = __i->new_state, 1)) 11025 11026 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) 11027 { 11028 struct drm_connector *connector; 11029 struct drm_connector_state *conn_state, *old_conn_state; 11030 struct amdgpu_dm_connector *aconnector = NULL; 11031 int i; 11032 11033 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) { 11034 if (!conn_state->crtc) 11035 conn_state = old_conn_state; 11036 11037 if (conn_state->crtc != crtc) 11038 continue; 11039 11040 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 11041 continue; 11042 11043 aconnector = to_amdgpu_dm_connector(connector); 11044 if (!aconnector->mst_output_port || !aconnector->mst_root) 11045 aconnector = NULL; 11046 else 11047 break; 11048 } 11049 11050 if (!aconnector) 11051 return 0; 11052 11053 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr); 11054 } 11055 11056 /** 11057 * DOC: Cursor Modes - Native vs Overlay 11058 * 11059 * In native mode, the cursor uses a integrated cursor pipe within each DCN hw 11060 * plane. It does not require a dedicated hw plane to enable, but it is 11061 * subjected to the same z-order and scaling as the hw plane. It also has format 11062 * restrictions, a RGB cursor in native mode cannot be enabled within a non-RGB 11063 * hw plane. 11064 * 11065 * In overlay mode, the cursor uses a separate DCN hw plane, and thus has its 11066 * own scaling and z-pos. It also has no blending restrictions. It lends to a 11067 * cursor behavior more akin to a DRM client's expectations. However, it does 11068 * occupy an extra DCN plane, and therefore will only be used if a DCN plane is 11069 * available. 11070 */ 11071 11072 /** 11073 * dm_crtc_get_cursor_mode() - Determine the required cursor mode on crtc 11074 * @adev: amdgpu device 11075 * @state: DRM atomic state 11076 * @dm_crtc_state: amdgpu state for the CRTC containing the cursor 11077 * @cursor_mode: Returns the required cursor mode on dm_crtc_state 11078 * 11079 * Get whether the cursor should be enabled in native mode, or overlay mode, on 11080 * the dm_crtc_state. 11081 * 11082 * The cursor should be enabled in overlay mode if there exists an underlying 11083 * plane - on which the cursor may be blended - that is either YUV formatted, or 11084 * scaled differently from the cursor. 11085 * 11086 * Since zpos info is required, drm_atomic_normalize_zpos must be called before 11087 * calling this function. 11088 * 11089 * Return: 0 on success, or an error code if getting the cursor plane state 11090 * failed. 11091 */ 11092 static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev, 11093 struct drm_atomic_state *state, 11094 struct dm_crtc_state *dm_crtc_state, 11095 enum amdgpu_dm_cursor_mode *cursor_mode) 11096 { 11097 struct drm_plane_state *old_plane_state, *plane_state, *cursor_state; 11098 struct drm_crtc_state *crtc_state = &dm_crtc_state->base; 11099 struct drm_plane *plane; 11100 bool consider_mode_change = false; 11101 bool entire_crtc_covered = false; 11102 bool cursor_changed = false; 11103 int underlying_scale_w, underlying_scale_h; 11104 int cursor_scale_w, cursor_scale_h; 11105 int i; 11106 11107 /* Overlay cursor not supported on HW before DCN 11108 * DCN401 does not have the cursor-on-scaled-plane or cursor-on-yuv-plane restrictions 11109 * as previous DCN generations, so enable native mode on DCN401 in addition to DCE 11110 */ 11111 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0 || 11112 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) { 11113 *cursor_mode = DM_CURSOR_NATIVE_MODE; 11114 return 0; 11115 } 11116 11117 /* Init cursor_mode to be the same as current */ 11118 *cursor_mode = dm_crtc_state->cursor_mode; 11119 11120 /* 11121 * Cursor mode can change if a plane's format changes, scale changes, is 11122 * enabled/disabled, or z-order changes. 11123 */ 11124 for_each_oldnew_plane_in_state(state, plane, old_plane_state, plane_state, i) { 11125 int new_scale_w, new_scale_h, old_scale_w, old_scale_h; 11126 11127 /* Only care about planes on this CRTC */ 11128 if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0) 11129 continue; 11130 11131 if (plane->type == DRM_PLANE_TYPE_CURSOR) 11132 cursor_changed = true; 11133 11134 if (drm_atomic_plane_enabling(old_plane_state, plane_state) || 11135 drm_atomic_plane_disabling(old_plane_state, plane_state) || 11136 old_plane_state->fb->format != plane_state->fb->format) { 11137 consider_mode_change = true; 11138 break; 11139 } 11140 11141 dm_get_plane_scale(plane_state, &new_scale_w, &new_scale_h); 11142 dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h); 11143 if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) { 11144 consider_mode_change = true; 11145 break; 11146 } 11147 } 11148 11149 if (!consider_mode_change && !crtc_state->zpos_changed) 11150 return 0; 11151 11152 /* 11153 * If no cursor change on this CRTC, and not enabled on this CRTC, then 11154 * no need to set cursor mode. This avoids needlessly locking the cursor 11155 * state. 11156 */ 11157 if (!cursor_changed && 11158 !(drm_plane_mask(crtc_state->crtc->cursor) & crtc_state->plane_mask)) { 11159 return 0; 11160 } 11161 11162 cursor_state = drm_atomic_get_plane_state(state, 11163 crtc_state->crtc->cursor); 11164 if (IS_ERR(cursor_state)) 11165 return PTR_ERR(cursor_state); 11166 11167 /* Cursor is disabled */ 11168 if (!cursor_state->fb) 11169 return 0; 11170 11171 /* For all planes in descending z-order (all of which are below cursor 11172 * as per zpos definitions), check their scaling and format 11173 */ 11174 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, plane_state) { 11175 11176 /* Only care about non-cursor planes on this CRTC */ 11177 if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0 || 11178 plane->type == DRM_PLANE_TYPE_CURSOR) 11179 continue; 11180 11181 /* Underlying plane is YUV format - use overlay cursor */ 11182 if (amdgpu_dm_plane_is_video_format(plane_state->fb->format->format)) { 11183 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 11184 return 0; 11185 } 11186 11187 dm_get_plane_scale(plane_state, 11188 &underlying_scale_w, &underlying_scale_h); 11189 dm_get_plane_scale(cursor_state, 11190 &cursor_scale_w, &cursor_scale_h); 11191 11192 /* Underlying plane has different scale - use overlay cursor */ 11193 if (cursor_scale_w != underlying_scale_w && 11194 cursor_scale_h != underlying_scale_h) { 11195 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 11196 return 0; 11197 } 11198 11199 /* If this plane covers the whole CRTC, no need to check planes underneath */ 11200 if (plane_state->crtc_x <= 0 && plane_state->crtc_y <= 0 && 11201 plane_state->crtc_x + plane_state->crtc_w >= crtc_state->mode.hdisplay && 11202 plane_state->crtc_y + plane_state->crtc_h >= crtc_state->mode.vdisplay) { 11203 entire_crtc_covered = true; 11204 break; 11205 } 11206 } 11207 11208 /* If planes do not cover the entire CRTC, use overlay mode to enable 11209 * cursor over holes 11210 */ 11211 if (entire_crtc_covered) 11212 *cursor_mode = DM_CURSOR_NATIVE_MODE; 11213 else 11214 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 11215 11216 return 0; 11217 } 11218 11219 /** 11220 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 11221 * 11222 * @dev: The DRM device 11223 * @state: The atomic state to commit 11224 * 11225 * Validate that the given atomic state is programmable by DC into hardware. 11226 * This involves constructing a &struct dc_state reflecting the new hardware 11227 * state we wish to commit, then querying DC to see if it is programmable. It's 11228 * important not to modify the existing DC state. Otherwise, atomic_check 11229 * may unexpectedly commit hardware changes. 11230 * 11231 * When validating the DC state, it's important that the right locks are 11232 * acquired. For full updates case which removes/adds/updates streams on one 11233 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 11234 * that any such full update commit will wait for completion of any outstanding 11235 * flip using DRMs synchronization events. 11236 * 11237 * Note that DM adds the affected connectors for all CRTCs in state, when that 11238 * might not seem necessary. This is because DC stream creation requires the 11239 * DC sink, which is tied to the DRM connector state. Cleaning this up should 11240 * be possible but non-trivial - a possible TODO item. 11241 * 11242 * Return: -Error code if validation failed. 11243 */ 11244 static int amdgpu_dm_atomic_check(struct drm_device *dev, 11245 struct drm_atomic_state *state) 11246 { 11247 struct amdgpu_device *adev = drm_to_adev(dev); 11248 struct dm_atomic_state *dm_state = NULL; 11249 struct dc *dc = adev->dm.dc; 11250 struct drm_connector *connector; 11251 struct drm_connector_state *old_con_state, *new_con_state; 11252 struct drm_crtc *crtc; 11253 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 11254 struct drm_plane *plane; 11255 struct drm_plane_state *old_plane_state, *new_plane_state, *new_cursor_state; 11256 enum dc_status status; 11257 int ret, i; 11258 bool lock_and_validation_needed = false; 11259 bool is_top_most_overlay = true; 11260 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 11261 struct drm_dp_mst_topology_mgr *mgr; 11262 struct drm_dp_mst_topology_state *mst_state; 11263 struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; 11264 11265 trace_amdgpu_dm_atomic_check_begin(state); 11266 11267 ret = drm_atomic_helper_check_modeset(dev, state); 11268 if (ret) { 11269 drm_dbg_atomic(dev, "drm_atomic_helper_check_modeset() failed\n"); 11270 goto fail; 11271 } 11272 11273 /* Check connector changes */ 11274 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 11275 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 11276 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 11277 11278 /* Skip connectors that are disabled or part of modeset already. */ 11279 if (!new_con_state->crtc) 11280 continue; 11281 11282 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc); 11283 if (IS_ERR(new_crtc_state)) { 11284 drm_dbg_atomic(dev, "drm_atomic_get_crtc_state() failed\n"); 11285 ret = PTR_ERR(new_crtc_state); 11286 goto fail; 11287 } 11288 11289 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level || 11290 dm_old_con_state->scaling != dm_new_con_state->scaling) 11291 new_crtc_state->connectors_changed = true; 11292 } 11293 11294 if (dc_resource_is_dsc_encoding_supported(dc)) { 11295 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 11296 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { 11297 ret = add_affected_mst_dsc_crtcs(state, crtc); 11298 if (ret) { 11299 drm_dbg_atomic(dev, "add_affected_mst_dsc_crtcs() failed\n"); 11300 goto fail; 11301 } 11302 } 11303 } 11304 } 11305 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 11306 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 11307 11308 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 11309 !new_crtc_state->color_mgmt_changed && 11310 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && 11311 dm_old_crtc_state->dsc_force_changed == false) 11312 continue; 11313 11314 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state); 11315 if (ret) { 11316 drm_dbg_atomic(dev, "amdgpu_dm_verify_lut_sizes() failed\n"); 11317 goto fail; 11318 } 11319 11320 if (!new_crtc_state->enable) 11321 continue; 11322 11323 ret = drm_atomic_add_affected_connectors(state, crtc); 11324 if (ret) { 11325 drm_dbg_atomic(dev, "drm_atomic_add_affected_connectors() failed\n"); 11326 goto fail; 11327 } 11328 11329 ret = drm_atomic_add_affected_planes(state, crtc); 11330 if (ret) { 11331 drm_dbg_atomic(dev, "drm_atomic_add_affected_planes() failed\n"); 11332 goto fail; 11333 } 11334 11335 if (dm_old_crtc_state->dsc_force_changed) 11336 new_crtc_state->mode_changed = true; 11337 } 11338 11339 /* 11340 * Add all primary and overlay planes on the CRTC to the state 11341 * whenever a plane is enabled to maintain correct z-ordering 11342 * and to enable fast surface updates. 11343 */ 11344 drm_for_each_crtc(crtc, dev) { 11345 bool modified = false; 11346 11347 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 11348 if (plane->type == DRM_PLANE_TYPE_CURSOR) 11349 continue; 11350 11351 if (new_plane_state->crtc == crtc || 11352 old_plane_state->crtc == crtc) { 11353 modified = true; 11354 break; 11355 } 11356 } 11357 11358 if (!modified) 11359 continue; 11360 11361 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 11362 if (plane->type == DRM_PLANE_TYPE_CURSOR) 11363 continue; 11364 11365 new_plane_state = 11366 drm_atomic_get_plane_state(state, plane); 11367 11368 if (IS_ERR(new_plane_state)) { 11369 ret = PTR_ERR(new_plane_state); 11370 drm_dbg_atomic(dev, "new_plane_state is BAD\n"); 11371 goto fail; 11372 } 11373 } 11374 } 11375 11376 /* 11377 * DC consults the zpos (layer_index in DC terminology) to determine the 11378 * hw plane on which to enable the hw cursor (see 11379 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in 11380 * atomic state, so call drm helper to normalize zpos. 11381 */ 11382 ret = drm_atomic_normalize_zpos(dev, state); 11383 if (ret) { 11384 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n"); 11385 goto fail; 11386 } 11387 11388 /* 11389 * Determine whether cursors on each CRTC should be enabled in native or 11390 * overlay mode. 11391 */ 11392 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 11393 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 11394 11395 ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state, 11396 &dm_new_crtc_state->cursor_mode); 11397 if (ret) { 11398 drm_dbg(dev, "Failed to determine cursor mode\n"); 11399 goto fail; 11400 } 11401 } 11402 11403 /* Remove exiting planes if they are modified */ 11404 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) { 11405 if (old_plane_state->fb && new_plane_state->fb && 11406 get_mem_type(old_plane_state->fb) != 11407 get_mem_type(new_plane_state->fb)) 11408 lock_and_validation_needed = true; 11409 11410 ret = dm_update_plane_state(dc, state, plane, 11411 old_plane_state, 11412 new_plane_state, 11413 false, 11414 &lock_and_validation_needed, 11415 &is_top_most_overlay); 11416 if (ret) { 11417 drm_dbg_atomic(dev, "dm_update_plane_state() failed\n"); 11418 goto fail; 11419 } 11420 } 11421 11422 /* Disable all crtcs which require disable */ 11423 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 11424 ret = dm_update_crtc_state(&adev->dm, state, crtc, 11425 old_crtc_state, 11426 new_crtc_state, 11427 false, 11428 &lock_and_validation_needed); 11429 if (ret) { 11430 drm_dbg_atomic(dev, "DISABLE: dm_update_crtc_state() failed\n"); 11431 goto fail; 11432 } 11433 } 11434 11435 /* Enable all crtcs which require enable */ 11436 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 11437 ret = dm_update_crtc_state(&adev->dm, state, crtc, 11438 old_crtc_state, 11439 new_crtc_state, 11440 true, 11441 &lock_and_validation_needed); 11442 if (ret) { 11443 drm_dbg_atomic(dev, "ENABLE: dm_update_crtc_state() failed\n"); 11444 goto fail; 11445 } 11446 } 11447 11448 /* Add new/modified planes */ 11449 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) { 11450 ret = dm_update_plane_state(dc, state, plane, 11451 old_plane_state, 11452 new_plane_state, 11453 true, 11454 &lock_and_validation_needed, 11455 &is_top_most_overlay); 11456 if (ret) { 11457 drm_dbg_atomic(dev, "dm_update_plane_state() failed\n"); 11458 goto fail; 11459 } 11460 } 11461 11462 #if defined(CONFIG_DRM_AMD_DC_FP) 11463 if (dc_resource_is_dsc_encoding_supported(dc)) { 11464 ret = pre_validate_dsc(state, &dm_state, vars); 11465 if (ret != 0) 11466 goto fail; 11467 } 11468 #endif 11469 11470 /* Run this here since we want to validate the streams we created */ 11471 ret = drm_atomic_helper_check_planes(dev, state); 11472 if (ret) { 11473 drm_dbg_atomic(dev, "drm_atomic_helper_check_planes() failed\n"); 11474 goto fail; 11475 } 11476 11477 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 11478 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 11479 if (dm_new_crtc_state->mpo_requested) 11480 drm_dbg_atomic(dev, "MPO enablement requested on crtc:[%p]\n", crtc); 11481 } 11482 11483 /* Check cursor restrictions */ 11484 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 11485 enum amdgpu_dm_cursor_mode required_cursor_mode; 11486 int is_rotated, is_scaled; 11487 11488 /* Overlay cusor not subject to native cursor restrictions */ 11489 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 11490 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) 11491 continue; 11492 11493 /* Check if rotation or scaling is enabled on DCN401 */ 11494 if ((drm_plane_mask(crtc->cursor) & new_crtc_state->plane_mask) && 11495 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) { 11496 new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor); 11497 11498 is_rotated = new_cursor_state && 11499 ((new_cursor_state->rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0); 11500 is_scaled = new_cursor_state && ((new_cursor_state->src_w >> 16 != new_cursor_state->crtc_w) || 11501 (new_cursor_state->src_h >> 16 != new_cursor_state->crtc_h)); 11502 11503 if (is_rotated || is_scaled) { 11504 drm_dbg_driver( 11505 crtc->dev, 11506 "[CRTC:%d:%s] cannot enable hardware cursor due to rotation/scaling\n", 11507 crtc->base.id, crtc->name); 11508 ret = -EINVAL; 11509 goto fail; 11510 } 11511 } 11512 11513 /* If HW can only do native cursor, check restrictions again */ 11514 ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state, 11515 &required_cursor_mode); 11516 if (ret) { 11517 drm_dbg_driver(crtc->dev, 11518 "[CRTC:%d:%s] Checking cursor mode failed\n", 11519 crtc->base.id, crtc->name); 11520 goto fail; 11521 } else if (required_cursor_mode == DM_CURSOR_OVERLAY_MODE) { 11522 drm_dbg_driver(crtc->dev, 11523 "[CRTC:%d:%s] Cannot enable native cursor due to scaling or YUV restrictions\n", 11524 crtc->base.id, crtc->name); 11525 ret = -EINVAL; 11526 goto fail; 11527 } 11528 } 11529 11530 if (state->legacy_cursor_update) { 11531 /* 11532 * This is a fast cursor update coming from the plane update 11533 * helper, check if it can be done asynchronously for better 11534 * performance. 11535 */ 11536 state->async_update = 11537 !drm_atomic_helper_async_check(dev, state); 11538 11539 /* 11540 * Skip the remaining global validation if this is an async 11541 * update. Cursor updates can be done without affecting 11542 * state or bandwidth calcs and this avoids the performance 11543 * penalty of locking the private state object and 11544 * allocating a new dc_state. 11545 */ 11546 if (state->async_update) 11547 return 0; 11548 } 11549 11550 /* Check scaling and underscan changes*/ 11551 /* TODO Removed scaling changes validation due to inability to commit 11552 * new stream into context w\o causing full reset. Need to 11553 * decide how to handle. 11554 */ 11555 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 11556 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 11557 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 11558 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 11559 11560 /* Skip any modesets/resets */ 11561 if (!acrtc || drm_atomic_crtc_needs_modeset( 11562 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 11563 continue; 11564 11565 /* Skip any thing not scale or underscan changes */ 11566 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 11567 continue; 11568 11569 lock_and_validation_needed = true; 11570 } 11571 11572 /* set the slot info for each mst_state based on the link encoding format */ 11573 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { 11574 struct amdgpu_dm_connector *aconnector; 11575 struct drm_connector *connector; 11576 struct drm_connector_list_iter iter; 11577 u8 link_coding_cap; 11578 11579 drm_connector_list_iter_begin(dev, &iter); 11580 drm_for_each_connector_iter(connector, &iter) { 11581 if (connector->index == mst_state->mgr->conn_base_id) { 11582 aconnector = to_amdgpu_dm_connector(connector); 11583 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); 11584 drm_dp_mst_update_slots(mst_state, link_coding_cap); 11585 11586 break; 11587 } 11588 } 11589 drm_connector_list_iter_end(&iter); 11590 } 11591 11592 /** 11593 * Streams and planes are reset when there are changes that affect 11594 * bandwidth. Anything that affects bandwidth needs to go through 11595 * DC global validation to ensure that the configuration can be applied 11596 * to hardware. 11597 * 11598 * We have to currently stall out here in atomic_check for outstanding 11599 * commits to finish in this case because our IRQ handlers reference 11600 * DRM state directly - we can end up disabling interrupts too early 11601 * if we don't. 11602 * 11603 * TODO: Remove this stall and drop DM state private objects. 11604 */ 11605 if (lock_and_validation_needed) { 11606 ret = dm_atomic_get_state(state, &dm_state); 11607 if (ret) { 11608 drm_dbg_atomic(dev, "dm_atomic_get_state() failed\n"); 11609 goto fail; 11610 } 11611 11612 ret = do_aquire_global_lock(dev, state); 11613 if (ret) { 11614 drm_dbg_atomic(dev, "do_aquire_global_lock() failed\n"); 11615 goto fail; 11616 } 11617 11618 #if defined(CONFIG_DRM_AMD_DC_FP) 11619 if (dc_resource_is_dsc_encoding_supported(dc)) { 11620 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); 11621 if (ret) { 11622 drm_dbg_atomic(dev, "compute_mst_dsc_configs_for_state() failed\n"); 11623 ret = -EINVAL; 11624 goto fail; 11625 } 11626 } 11627 #endif 11628 11629 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); 11630 if (ret) { 11631 drm_dbg_atomic(dev, "dm_update_mst_vcpi_slots_for_dsc() failed\n"); 11632 goto fail; 11633 } 11634 11635 /* 11636 * Perform validation of MST topology in the state: 11637 * We need to perform MST atomic check before calling 11638 * dc_validate_global_state(), or there is a chance 11639 * to get stuck in an infinite loop and hang eventually. 11640 */ 11641 ret = drm_dp_mst_atomic_check(state); 11642 if (ret) { 11643 drm_dbg_atomic(dev, "drm_dp_mst_atomic_check() failed\n"); 11644 goto fail; 11645 } 11646 status = dc_validate_global_state(dc, dm_state->context, true); 11647 if (status != DC_OK) { 11648 drm_dbg_atomic(dev, "DC global validation failure: %s (%d)", 11649 dc_status_to_str(status), status); 11650 ret = -EINVAL; 11651 goto fail; 11652 } 11653 } else { 11654 /* 11655 * The commit is a fast update. Fast updates shouldn't change 11656 * the DC context, affect global validation, and can have their 11657 * commit work done in parallel with other commits not touching 11658 * the same resource. If we have a new DC context as part of 11659 * the DM atomic state from validation we need to free it and 11660 * retain the existing one instead. 11661 * 11662 * Furthermore, since the DM atomic state only contains the DC 11663 * context and can safely be annulled, we can free the state 11664 * and clear the associated private object now to free 11665 * some memory and avoid a possible use-after-free later. 11666 */ 11667 11668 for (i = 0; i < state->num_private_objs; i++) { 11669 struct drm_private_obj *obj = state->private_objs[i].ptr; 11670 11671 if (obj->funcs == adev->dm.atomic_obj.funcs) { 11672 int j = state->num_private_objs-1; 11673 11674 dm_atomic_destroy_state(obj, 11675 state->private_objs[i].state); 11676 11677 /* If i is not at the end of the array then the 11678 * last element needs to be moved to where i was 11679 * before the array can safely be truncated. 11680 */ 11681 if (i != j) 11682 state->private_objs[i] = 11683 state->private_objs[j]; 11684 11685 state->private_objs[j].ptr = NULL; 11686 state->private_objs[j].state = NULL; 11687 state->private_objs[j].old_state = NULL; 11688 state->private_objs[j].new_state = NULL; 11689 11690 state->num_private_objs = j; 11691 break; 11692 } 11693 } 11694 } 11695 11696 /* Store the overall update type for use later in atomic check. */ 11697 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 11698 struct dm_crtc_state *dm_new_crtc_state = 11699 to_dm_crtc_state(new_crtc_state); 11700 11701 /* 11702 * Only allow async flips for fast updates that don't change 11703 * the FB pitch, the DCC state, rotation, etc. 11704 */ 11705 if (new_crtc_state->async_flip && lock_and_validation_needed) { 11706 drm_dbg_atomic(crtc->dev, 11707 "[CRTC:%d:%s] async flips are only supported for fast updates\n", 11708 crtc->base.id, crtc->name); 11709 ret = -EINVAL; 11710 goto fail; 11711 } 11712 11713 dm_new_crtc_state->update_type = lock_and_validation_needed ? 11714 UPDATE_TYPE_FULL : UPDATE_TYPE_FAST; 11715 } 11716 11717 /* Must be success */ 11718 WARN_ON(ret); 11719 11720 trace_amdgpu_dm_atomic_check_finish(state, ret); 11721 11722 return ret; 11723 11724 fail: 11725 if (ret == -EDEADLK) 11726 drm_dbg_atomic(dev, "Atomic check stopped to avoid deadlock.\n"); 11727 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 11728 drm_dbg_atomic(dev, "Atomic check stopped due to signal.\n"); 11729 else 11730 drm_dbg_atomic(dev, "Atomic check failed with err: %d\n", ret); 11731 11732 trace_amdgpu_dm_atomic_check_finish(state, ret); 11733 11734 return ret; 11735 } 11736 11737 static bool is_dp_capable_without_timing_msa(struct dc *dc, 11738 struct amdgpu_dm_connector *amdgpu_dm_connector) 11739 { 11740 u8 dpcd_data; 11741 bool capable = false; 11742 11743 if (amdgpu_dm_connector->dc_link && 11744 dm_helpers_dp_read_dpcd( 11745 NULL, 11746 amdgpu_dm_connector->dc_link, 11747 DP_DOWN_STREAM_PORT_COUNT, 11748 &dpcd_data, 11749 sizeof(dpcd_data))) { 11750 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; 11751 } 11752 11753 return capable; 11754 } 11755 11756 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm, 11757 unsigned int offset, 11758 unsigned int total_length, 11759 u8 *data, 11760 unsigned int length, 11761 struct amdgpu_hdmi_vsdb_info *vsdb) 11762 { 11763 bool res; 11764 union dmub_rb_cmd cmd; 11765 struct dmub_cmd_send_edid_cea *input; 11766 struct dmub_cmd_edid_cea_output *output; 11767 11768 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES) 11769 return false; 11770 11771 memset(&cmd, 0, sizeof(cmd)); 11772 11773 input = &cmd.edid_cea.data.input; 11774 11775 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA; 11776 cmd.edid_cea.header.sub_type = 0; 11777 cmd.edid_cea.header.payload_bytes = 11778 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header); 11779 input->offset = offset; 11780 input->length = length; 11781 input->cea_total_length = total_length; 11782 memcpy(input->payload, data, length); 11783 11784 res = dc_wake_and_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY); 11785 if (!res) { 11786 DRM_ERROR("EDID CEA parser failed\n"); 11787 return false; 11788 } 11789 11790 output = &cmd.edid_cea.data.output; 11791 11792 if (output->type == DMUB_CMD__EDID_CEA_ACK) { 11793 if (!output->ack.success) { 11794 DRM_ERROR("EDID CEA ack failed at offset %d\n", 11795 output->ack.offset); 11796 } 11797 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) { 11798 if (!output->amd_vsdb.vsdb_found) 11799 return false; 11800 11801 vsdb->freesync_supported = output->amd_vsdb.freesync_supported; 11802 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version; 11803 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate; 11804 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate; 11805 } else { 11806 DRM_WARN("Unknown EDID CEA parser results\n"); 11807 return false; 11808 } 11809 11810 return true; 11811 } 11812 11813 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm, 11814 u8 *edid_ext, int len, 11815 struct amdgpu_hdmi_vsdb_info *vsdb_info) 11816 { 11817 int i; 11818 11819 /* send extension block to DMCU for parsing */ 11820 for (i = 0; i < len; i += 8) { 11821 bool res; 11822 int offset; 11823 11824 /* send 8 bytes a time */ 11825 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8)) 11826 return false; 11827 11828 if (i+8 == len) { 11829 /* EDID block sent completed, expect result */ 11830 int version, min_rate, max_rate; 11831 11832 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate); 11833 if (res) { 11834 /* amd vsdb found */ 11835 vsdb_info->freesync_supported = 1; 11836 vsdb_info->amd_vsdb_version = version; 11837 vsdb_info->min_refresh_rate_hz = min_rate; 11838 vsdb_info->max_refresh_rate_hz = max_rate; 11839 return true; 11840 } 11841 /* not amd vsdb */ 11842 return false; 11843 } 11844 11845 /* check for ack*/ 11846 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset); 11847 if (!res) 11848 return false; 11849 } 11850 11851 return false; 11852 } 11853 11854 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm, 11855 u8 *edid_ext, int len, 11856 struct amdgpu_hdmi_vsdb_info *vsdb_info) 11857 { 11858 int i; 11859 11860 /* send extension block to DMCU for parsing */ 11861 for (i = 0; i < len; i += 8) { 11862 /* send 8 bytes a time */ 11863 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info)) 11864 return false; 11865 } 11866 11867 return vsdb_info->freesync_supported; 11868 } 11869 11870 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, 11871 u8 *edid_ext, int len, 11872 struct amdgpu_hdmi_vsdb_info *vsdb_info) 11873 { 11874 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); 11875 bool ret; 11876 11877 mutex_lock(&adev->dm.dc_lock); 11878 if (adev->dm.dmub_srv) 11879 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info); 11880 else 11881 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info); 11882 mutex_unlock(&adev->dm.dc_lock); 11883 return ret; 11884 } 11885 11886 static void parse_edid_displayid_vrr(struct drm_connector *connector, 11887 struct edid *edid) 11888 { 11889 u8 *edid_ext = NULL; 11890 int i; 11891 int j = 0; 11892 u16 min_vfreq; 11893 u16 max_vfreq; 11894 11895 if (edid == NULL || edid->extensions == 0) 11896 return; 11897 11898 /* Find DisplayID extension */ 11899 for (i = 0; i < edid->extensions; i++) { 11900 edid_ext = (void *)(edid + (i + 1)); 11901 if (edid_ext[0] == DISPLAYID_EXT) 11902 break; 11903 } 11904 11905 if (edid_ext == NULL) 11906 return; 11907 11908 while (j < EDID_LENGTH) { 11909 /* Get dynamic video timing range from DisplayID if available */ 11910 if (EDID_LENGTH - j > 13 && edid_ext[j] == 0x25 && 11911 (edid_ext[j+1] & 0xFE) == 0 && (edid_ext[j+2] == 9)) { 11912 min_vfreq = edid_ext[j+9]; 11913 if (edid_ext[j+1] & 7) 11914 max_vfreq = edid_ext[j+10] + ((edid_ext[j+11] & 3) << 8); 11915 else 11916 max_vfreq = edid_ext[j+10]; 11917 11918 if (max_vfreq && min_vfreq) { 11919 connector->display_info.monitor_range.max_vfreq = max_vfreq; 11920 connector->display_info.monitor_range.min_vfreq = min_vfreq; 11921 11922 return; 11923 } 11924 } 11925 j++; 11926 } 11927 } 11928 11929 static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector, 11930 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) 11931 { 11932 u8 *edid_ext = NULL; 11933 int i; 11934 int j = 0; 11935 11936 if (edid == NULL || edid->extensions == 0) 11937 return -ENODEV; 11938 11939 /* Find DisplayID extension */ 11940 for (i = 0; i < edid->extensions; i++) { 11941 edid_ext = (void *)(edid + (i + 1)); 11942 if (edid_ext[0] == DISPLAYID_EXT) 11943 break; 11944 } 11945 11946 while (j < EDID_LENGTH) { 11947 struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j]; 11948 unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]); 11949 11950 if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID && 11951 amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) { 11952 vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false; 11953 vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3; 11954 DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode); 11955 11956 return true; 11957 } 11958 j++; 11959 } 11960 11961 return false; 11962 } 11963 11964 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, 11965 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) 11966 { 11967 u8 *edid_ext = NULL; 11968 int i; 11969 bool valid_vsdb_found = false; 11970 11971 /*----- drm_find_cea_extension() -----*/ 11972 /* No EDID or EDID extensions */ 11973 if (edid == NULL || edid->extensions == 0) 11974 return -ENODEV; 11975 11976 /* Find CEA extension */ 11977 for (i = 0; i < edid->extensions; i++) { 11978 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1); 11979 if (edid_ext[0] == CEA_EXT) 11980 break; 11981 } 11982 11983 if (i == edid->extensions) 11984 return -ENODEV; 11985 11986 /*----- cea_db_offsets() -----*/ 11987 if (edid_ext[0] != CEA_EXT) 11988 return -ENODEV; 11989 11990 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info); 11991 11992 return valid_vsdb_found ? i : -ENODEV; 11993 } 11994 11995 /** 11996 * amdgpu_dm_update_freesync_caps - Update Freesync capabilities 11997 * 11998 * @connector: Connector to query. 11999 * @edid: EDID from monitor 12000 * 12001 * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep 12002 * track of some of the display information in the internal data struct used by 12003 * amdgpu_dm. This function checks which type of connector we need to set the 12004 * FreeSync parameters. 12005 */ 12006 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 12007 struct edid *edid) 12008 { 12009 int i = 0; 12010 struct detailed_timing *timing; 12011 struct detailed_non_pixel *data; 12012 struct detailed_data_monitor_range *range; 12013 struct amdgpu_dm_connector *amdgpu_dm_connector = 12014 to_amdgpu_dm_connector(connector); 12015 struct dm_connector_state *dm_con_state = NULL; 12016 struct dc_sink *sink; 12017 12018 struct amdgpu_device *adev = drm_to_adev(connector->dev); 12019 struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; 12020 bool freesync_capable = false; 12021 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; 12022 12023 if (!connector->state) { 12024 DRM_ERROR("%s - Connector has no state", __func__); 12025 goto update; 12026 } 12027 12028 sink = amdgpu_dm_connector->dc_sink ? 12029 amdgpu_dm_connector->dc_sink : 12030 amdgpu_dm_connector->dc_em_sink; 12031 12032 if (!edid || !sink) { 12033 dm_con_state = to_dm_connector_state(connector->state); 12034 12035 amdgpu_dm_connector->min_vfreq = 0; 12036 amdgpu_dm_connector->max_vfreq = 0; 12037 connector->display_info.monitor_range.min_vfreq = 0; 12038 connector->display_info.monitor_range.max_vfreq = 0; 12039 freesync_capable = false; 12040 12041 goto update; 12042 } 12043 12044 dm_con_state = to_dm_connector_state(connector->state); 12045 12046 if (!adev->dm.freesync_module) 12047 goto update; 12048 12049 /* Some eDP panels only have the refresh rate range info in DisplayID */ 12050 if ((connector->display_info.monitor_range.min_vfreq == 0 || 12051 connector->display_info.monitor_range.max_vfreq == 0)) 12052 parse_edid_displayid_vrr(connector, edid); 12053 12054 if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || 12055 sink->sink_signal == SIGNAL_TYPE_EDP)) { 12056 bool edid_check_required = false; 12057 12058 if (is_dp_capable_without_timing_msa(adev->dm.dc, 12059 amdgpu_dm_connector)) { 12060 if (edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) { 12061 amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq; 12062 amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq; 12063 if (amdgpu_dm_connector->max_vfreq - 12064 amdgpu_dm_connector->min_vfreq > 10) 12065 freesync_capable = true; 12066 } else { 12067 edid_check_required = edid->version > 1 || 12068 (edid->version == 1 && 12069 edid->revision > 1); 12070 } 12071 } 12072 12073 if (edid_check_required) { 12074 for (i = 0; i < 4; i++) { 12075 12076 timing = &edid->detailed_timings[i]; 12077 data = &timing->data.other_data; 12078 range = &data->data.range; 12079 /* 12080 * Check if monitor has continuous frequency mode 12081 */ 12082 if (data->type != EDID_DETAIL_MONITOR_RANGE) 12083 continue; 12084 /* 12085 * Check for flag range limits only. If flag == 1 then 12086 * no additional timing information provided. 12087 * Default GTF, GTF Secondary curve and CVT are not 12088 * supported 12089 */ 12090 if (range->flags != 1) 12091 continue; 12092 12093 connector->display_info.monitor_range.min_vfreq = range->min_vfreq; 12094 connector->display_info.monitor_range.max_vfreq = range->max_vfreq; 12095 12096 if (edid->revision >= 4) { 12097 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ) 12098 connector->display_info.monitor_range.min_vfreq += 255; 12099 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ) 12100 connector->display_info.monitor_range.max_vfreq += 255; 12101 } 12102 12103 amdgpu_dm_connector->min_vfreq = 12104 connector->display_info.monitor_range.min_vfreq; 12105 amdgpu_dm_connector->max_vfreq = 12106 connector->display_info.monitor_range.max_vfreq; 12107 12108 break; 12109 } 12110 12111 if (amdgpu_dm_connector->max_vfreq - 12112 amdgpu_dm_connector->min_vfreq > 10) { 12113 12114 freesync_capable = true; 12115 } 12116 } 12117 parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 12118 12119 if (vsdb_info.replay_mode) { 12120 amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode; 12121 amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version; 12122 amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP; 12123 } 12124 12125 } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { 12126 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 12127 if (i >= 0 && vsdb_info.freesync_supported) { 12128 timing = &edid->detailed_timings[i]; 12129 data = &timing->data.other_data; 12130 12131 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; 12132 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; 12133 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 12134 freesync_capable = true; 12135 12136 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; 12137 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; 12138 } 12139 } 12140 12141 as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link); 12142 12143 if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) { 12144 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 12145 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) { 12146 12147 amdgpu_dm_connector->pack_sdp_v1_3 = true; 12148 amdgpu_dm_connector->as_type = as_type; 12149 amdgpu_dm_connector->vsdb_info = vsdb_info; 12150 12151 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; 12152 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; 12153 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 12154 freesync_capable = true; 12155 12156 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; 12157 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; 12158 } 12159 } 12160 12161 update: 12162 if (dm_con_state) 12163 dm_con_state->freesync_capable = freesync_capable; 12164 12165 if (connector->vrr_capable_property) 12166 drm_connector_set_vrr_capable_property(connector, 12167 freesync_capable); 12168 } 12169 12170 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) 12171 { 12172 struct amdgpu_device *adev = drm_to_adev(dev); 12173 struct dc *dc = adev->dm.dc; 12174 int i; 12175 12176 mutex_lock(&adev->dm.dc_lock); 12177 if (dc->current_state) { 12178 for (i = 0; i < dc->current_state->stream_count; ++i) 12179 dc->current_state->streams[i] 12180 ->triggered_crtc_reset.enabled = 12181 adev->dm.force_timing_sync; 12182 12183 dm_enable_per_frame_crtc_master_sync(dc->current_state); 12184 dc_trigger_sync(dc, dc->current_state); 12185 } 12186 mutex_unlock(&adev->dm.dc_lock); 12187 } 12188 12189 static inline void amdgpu_dm_exit_ips_for_hw_access(struct dc *dc) 12190 { 12191 if (dc->ctx->dmub_srv && !dc->ctx->dmub_srv->idle_exit_counter) 12192 dc_exit_ips_for_hw_access(dc); 12193 } 12194 12195 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, 12196 u32 value, const char *func_name) 12197 { 12198 #ifdef DM_CHECK_ADDR_0 12199 if (address == 0) { 12200 drm_err(adev_to_drm(ctx->driver_context), 12201 "invalid register write. address = 0"); 12202 return; 12203 } 12204 #endif 12205 12206 amdgpu_dm_exit_ips_for_hw_access(ctx->dc); 12207 cgs_write_register(ctx->cgs_device, address, value); 12208 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value); 12209 } 12210 12211 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, 12212 const char *func_name) 12213 { 12214 u32 value; 12215 #ifdef DM_CHECK_ADDR_0 12216 if (address == 0) { 12217 drm_err(adev_to_drm(ctx->driver_context), 12218 "invalid register read; address = 0\n"); 12219 return 0; 12220 } 12221 #endif 12222 12223 if (ctx->dmub_srv && 12224 ctx->dmub_srv->reg_helper_offload.gather_in_progress && 12225 !ctx->dmub_srv->reg_helper_offload.should_burst_write) { 12226 ASSERT(false); 12227 return 0; 12228 } 12229 12230 amdgpu_dm_exit_ips_for_hw_access(ctx->dc); 12231 12232 value = cgs_read_register(ctx->cgs_device, address); 12233 12234 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); 12235 12236 return value; 12237 } 12238 12239 int amdgpu_dm_process_dmub_aux_transfer_sync( 12240 struct dc_context *ctx, 12241 unsigned int link_index, 12242 struct aux_payload *payload, 12243 enum aux_return_code_type *operation_result) 12244 { 12245 struct amdgpu_device *adev = ctx->driver_context; 12246 struct dmub_notification *p_notify = adev->dm.dmub_notify; 12247 int ret = -1; 12248 12249 mutex_lock(&adev->dm.dpia_aux_lock); 12250 if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) { 12251 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE; 12252 goto out; 12253 } 12254 12255 if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { 12256 DRM_ERROR("wait_for_completion_timeout timeout!"); 12257 *operation_result = AUX_RET_ERROR_TIMEOUT; 12258 goto out; 12259 } 12260 12261 if (p_notify->result != AUX_RET_SUCCESS) { 12262 /* 12263 * Transient states before tunneling is enabled could 12264 * lead to this error. We can ignore this for now. 12265 */ 12266 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) { 12267 DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n", 12268 payload->address, payload->length, 12269 p_notify->result); 12270 } 12271 *operation_result = AUX_RET_ERROR_INVALID_REPLY; 12272 goto out; 12273 } 12274 12275 12276 payload->reply[0] = adev->dm.dmub_notify->aux_reply.command; 12277 if (!payload->write && p_notify->aux_reply.length && 12278 (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) { 12279 12280 if (payload->length != p_notify->aux_reply.length) { 12281 DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n", 12282 p_notify->aux_reply.length, 12283 payload->address, payload->length); 12284 *operation_result = AUX_RET_ERROR_INVALID_REPLY; 12285 goto out; 12286 } 12287 12288 memcpy(payload->data, p_notify->aux_reply.data, 12289 p_notify->aux_reply.length); 12290 } 12291 12292 /* success */ 12293 ret = p_notify->aux_reply.length; 12294 *operation_result = p_notify->result; 12295 out: 12296 reinit_completion(&adev->dm.dmub_aux_transfer_done); 12297 mutex_unlock(&adev->dm.dpia_aux_lock); 12298 return ret; 12299 } 12300 12301 int amdgpu_dm_process_dmub_set_config_sync( 12302 struct dc_context *ctx, 12303 unsigned int link_index, 12304 struct set_config_cmd_payload *payload, 12305 enum set_config_status *operation_result) 12306 { 12307 struct amdgpu_device *adev = ctx->driver_context; 12308 bool is_cmd_complete; 12309 int ret; 12310 12311 mutex_lock(&adev->dm.dpia_aux_lock); 12312 is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc, 12313 link_index, payload, adev->dm.dmub_notify); 12314 12315 if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { 12316 ret = 0; 12317 *operation_result = adev->dm.dmub_notify->sc_status; 12318 } else { 12319 DRM_ERROR("wait_for_completion_timeout timeout!"); 12320 ret = -1; 12321 *operation_result = SET_CONFIG_UNKNOWN_ERROR; 12322 } 12323 12324 if (!is_cmd_complete) 12325 reinit_completion(&adev->dm.dmub_aux_transfer_done); 12326 mutex_unlock(&adev->dm.dpia_aux_lock); 12327 return ret; 12328 } 12329 12330 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) 12331 { 12332 return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type); 12333 } 12334 12335 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) 12336 { 12337 return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type); 12338 } 12339