1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2016-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include "kfd_device_queue_manager.h" 26 #include "vega10_enum.h" 27 #include "gc/gc_9_4_3_sh_mask.h" 28 29 static int update_qpd_v9(struct device_queue_manager *dqm, 30 struct qcm_process_device *qpd); 31 static void init_sdma_vm_v9(struct device_queue_manager *dqm, struct queue *q, 32 struct qcm_process_device *qpd); 33 34 void device_queue_manager_init_v9( 35 struct device_queue_manager_asic_ops *asic_ops) 36 { 37 asic_ops->update_qpd = update_qpd_v9; 38 asic_ops->init_sdma_vm = init_sdma_vm_v9; 39 asic_ops->mqd_manager_init = mqd_manager_init_v9; 40 } 41 42 static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd) 43 { 44 uint32_t shared_base = pdd->lds_base >> 48; 45 uint32_t private_base = pdd->scratch_base >> 48; 46 47 return (shared_base << SH_MEM_BASES__SHARED_BASE__SHIFT) | 48 private_base; 49 } 50 51 static int update_qpd_v9(struct device_queue_manager *dqm, 52 struct qcm_process_device *qpd) 53 { 54 struct kfd_process_device *pdd; 55 56 pdd = qpd_to_pdd(qpd); 57 58 /* check if sh_mem_config register already configured */ 59 if (qpd->sh_mem_config == 0) { 60 qpd->sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED << 61 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 62 63 if (dqm->dev->kfd->noretry) 64 qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT; 65 66 if (KFD_GC_VERSION(dqm->dev->kfd) == IP_VERSION(9, 4, 3) || 67 KFD_GC_VERSION(dqm->dev->kfd) == IP_VERSION(9, 4, 4)) 68 qpd->sh_mem_config |= 69 (1 << SH_MEM_CONFIG__F8_MODE__SHIFT); 70 71 qpd->sh_mem_ape1_limit = 0; 72 qpd->sh_mem_ape1_base = 0; 73 } 74 75 if (KFD_SUPPORT_XNACK_PER_PROCESS(dqm->dev)) { 76 if (!pdd->process->xnack_enabled) 77 qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT; 78 else 79 qpd->sh_mem_config &= ~(1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT); 80 } 81 82 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd); 83 84 pr_debug("sh_mem_bases 0x%X sh_mem_config 0x%X\n", qpd->sh_mem_bases, 85 qpd->sh_mem_config); 86 87 return 0; 88 } 89 90 static void init_sdma_vm_v9(struct device_queue_manager *dqm, struct queue *q, 91 struct qcm_process_device *qpd) 92 { 93 /* Not needed on SDMAv4 any more */ 94 q->properties.sdma_vm_addr = 0; 95 } 96