1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include "kfd_device_queue_manager.h"
25 #include "cik_regs.h"
26 #include "oss/oss_2_4_sh_mask.h"
27 #include "gca/gfx_7_2_sh_mask.h"
28 
29 static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm,
30 				   struct qcm_process_device *qpd,
31 				   enum cache_policy default_policy,
32 				   enum cache_policy alternate_policy,
33 				   void __user *alternate_aperture_base,
34 				   uint64_t alternate_aperture_size);
35 static int register_process_cik(struct device_queue_manager *dqm,
36 					struct qcm_process_device *qpd);
37 static int initialize_cpsch_cik(struct device_queue_manager *dqm);
38 static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
39 				struct qcm_process_device *qpd);
40 
41 void device_queue_manager_init_cik(struct device_queue_manager_asic_ops *ops)
42 {
43 	ops->set_cache_memory_policy = set_cache_memory_policy_cik;
44 	ops->register_process = register_process_cik;
45 	ops->initialize = initialize_cpsch_cik;
46 	ops->init_sdma_vm = init_sdma_vm;
47 }
48 
49 static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble)
50 {
51 	/* In 64-bit mode, we can only control the top 3 bits of the LDS,
52 	 * scratch and GPUVM apertures.
53 	 * The hardware fills in the remaining 59 bits according to the
54 	 * following pattern:
55 	 * LDS:		X0000000'00000000 - X0000001'00000000 (4GB)
56 	 * Scratch:	X0000001'00000000 - X0000002'00000000 (4GB)
57 	 * GPUVM:	Y0010000'00000000 - Y0020000'00000000 (1TB)
58 	 *
59 	 * (where X/Y is the configurable nybble with the low-bit 0)
60 	 *
61 	 * LDS and scratch will have the same top nybble programmed in the
62 	 * top 3 bits of SH_MEM_BASES.PRIVATE_BASE.
63 	 * GPUVM can have a different top nybble programmed in the
64 	 * top 3 bits of SH_MEM_BASES.SHARED_BASE.
65 	 * We don't bother to support different top nybbles
66 	 * for LDS/Scratch and GPUVM.
67 	 */
68 
69 	WARN_ON((top_address_nybble & 1) || top_address_nybble > 0xE ||
70 		top_address_nybble == 0);
71 
72 	return PRIVATE_BASE(top_address_nybble << 12) |
73 			SHARED_BASE(top_address_nybble << 12);
74 }
75 
76 static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm,
77 				   struct qcm_process_device *qpd,
78 				   enum cache_policy default_policy,
79 				   enum cache_policy alternate_policy,
80 				   void __user *alternate_aperture_base,
81 				   uint64_t alternate_aperture_size)
82 {
83 	uint32_t default_mtype;
84 	uint32_t ape1_mtype;
85 
86 	default_mtype = (default_policy == cache_policy_coherent) ?
87 			MTYPE_NONCACHED :
88 			MTYPE_CACHED;
89 
90 	ape1_mtype = (alternate_policy == cache_policy_coherent) ?
91 			MTYPE_NONCACHED :
92 			MTYPE_CACHED;
93 
94 	qpd->sh_mem_config = (qpd->sh_mem_config & PTR32)
95 			| ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED)
96 			| DEFAULT_MTYPE(default_mtype)
97 			| APE1_MTYPE(ape1_mtype);
98 
99 	return true;
100 }
101 
102 static int register_process_cik(struct device_queue_manager *dqm,
103 		struct qcm_process_device *qpd)
104 {
105 	struct kfd_process_device *pdd;
106 	unsigned int temp;
107 
108 	pdd = qpd_to_pdd(qpd);
109 
110 	/* check if sh_mem_config register already configured */
111 	if (qpd->sh_mem_config == 0) {
112 		qpd->sh_mem_config =
113 			ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED) |
114 			DEFAULT_MTYPE(MTYPE_NONCACHED) |
115 			APE1_MTYPE(MTYPE_NONCACHED);
116 		qpd->sh_mem_ape1_limit = 0;
117 		qpd->sh_mem_ape1_base = 0;
118 	}
119 
120 	if (qpd->pqm->process->is_32bit_user_mode) {
121 		temp = get_sh_mem_bases_32(pdd);
122 		qpd->sh_mem_bases = SHARED_BASE(temp);
123 		qpd->sh_mem_config |= PTR32;
124 	} else {
125 		temp = get_sh_mem_bases_nybble_64(pdd);
126 		qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp);
127 		qpd->sh_mem_config |= 1  << SH_MEM_CONFIG__PRIVATE_ATC__SHIFT;
128 	}
129 
130 	pr_debug("is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n",
131 		qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases);
132 
133 	return 0;
134 }
135 
136 static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
137 				struct qcm_process_device *qpd)
138 {
139 	uint32_t value = (1 << SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT);
140 
141 	if (q->process->is_32bit_user_mode)
142 		value |= (1 << SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT) |
143 				get_sh_mem_bases_32(qpd_to_pdd(qpd));
144 	else
145 		value |= ((get_sh_mem_bases_nybble_64(qpd_to_pdd(qpd))) <<
146 				SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT) &
147 				SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK;
148 
149 	q->properties.sdma_vm_addr = value;
150 }
151 
152 static int initialize_cpsch_cik(struct device_queue_manager *dqm)
153 {
154 	return 0;
155 }
156