1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include "kfd_device_queue_manager.h" 26 #include "cik_regs.h" 27 #include "oss/oss_2_4_sh_mask.h" 28 #include "gca/gfx_7_2_sh_mask.h" 29 30 /* 31 * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to 32 * stay in user mode. 33 */ 34 #define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL 35 /* APE1 limit is inclusive and 64K aligned. */ 36 #define APE1_LIMIT_ALIGNMENT 0xFFFF 37 38 static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm, 39 struct qcm_process_device *qpd, 40 enum cache_policy default_policy, 41 enum cache_policy alternate_policy, 42 void __user *alternate_aperture_base, 43 uint64_t alternate_aperture_size); 44 static int update_qpd_cik(struct device_queue_manager *dqm, 45 struct qcm_process_device *qpd); 46 static void init_sdma_vm(struct device_queue_manager *dqm, 47 struct queue *q, 48 struct qcm_process_device *qpd); 49 50 void device_queue_manager_init_cik( 51 struct device_queue_manager_asic_ops *asic_ops) 52 { 53 asic_ops->set_cache_memory_policy = set_cache_memory_policy_cik; 54 asic_ops->update_qpd = update_qpd_cik; 55 asic_ops->init_sdma_vm = init_sdma_vm; 56 asic_ops->mqd_manager_init = mqd_manager_init_cik; 57 } 58 59 static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble) 60 { 61 /* In 64-bit mode, we can only control the top 3 bits of the LDS, 62 * scratch and GPUVM apertures. 63 * The hardware fills in the remaining 59 bits according to the 64 * following pattern: 65 * LDS: X0000000'00000000 - X0000001'00000000 (4GB) 66 * Scratch: X0000001'00000000 - X0000002'00000000 (4GB) 67 * GPUVM: Y0010000'00000000 - Y0020000'00000000 (1TB) 68 * 69 * (where X/Y is the configurable nybble with the low-bit 0) 70 * 71 * LDS and scratch will have the same top nybble programmed in the 72 * top 3 bits of SH_MEM_BASES.PRIVATE_BASE. 73 * GPUVM can have a different top nybble programmed in the 74 * top 3 bits of SH_MEM_BASES.SHARED_BASE. 75 * We don't bother to support different top nybbles 76 * for LDS/Scratch and GPUVM. 77 */ 78 79 WARN_ON((top_address_nybble & 1) || top_address_nybble > 0xE || 80 top_address_nybble == 0); 81 82 return PRIVATE_BASE(top_address_nybble << 12) | 83 SHARED_BASE(top_address_nybble << 12); 84 } 85 86 static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm, 87 struct qcm_process_device *qpd, 88 enum cache_policy default_policy, 89 enum cache_policy alternate_policy, 90 void __user *alternate_aperture_base, 91 uint64_t alternate_aperture_size) 92 { 93 uint32_t default_mtype; 94 uint32_t ape1_mtype; 95 unsigned int temp; 96 bool retval = true; 97 98 if (alternate_aperture_size == 0) { 99 /* base > limit disables APE1 */ 100 qpd->sh_mem_ape1_base = 1; 101 qpd->sh_mem_ape1_limit = 0; 102 } else { 103 /* 104 * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]}, 105 * SH_MEM_APE1_BASE[31:0], 0x0000 } 106 * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]}, 107 * SH_MEM_APE1_LIMIT[31:0], 0xFFFF } 108 * Verify that the base and size parameters can be 109 * represented in this format and convert them. 110 * Additionally restrict APE1 to user-mode addresses. 111 */ 112 113 uint64_t base = (uintptr_t)alternate_aperture_base; 114 uint64_t limit = base + alternate_aperture_size - 1; 115 116 if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 || 117 (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) { 118 retval = false; 119 goto out; 120 } 121 122 qpd->sh_mem_ape1_base = base >> 16; 123 qpd->sh_mem_ape1_limit = limit >> 16; 124 } 125 126 default_mtype = (default_policy == cache_policy_coherent) ? 127 MTYPE_NONCACHED : 128 MTYPE_CACHED; 129 130 ape1_mtype = (alternate_policy == cache_policy_coherent) ? 131 MTYPE_NONCACHED : 132 MTYPE_CACHED; 133 134 qpd->sh_mem_config = (qpd->sh_mem_config & PTR32) 135 | ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED) 136 | DEFAULT_MTYPE(default_mtype) 137 | APE1_MTYPE(ape1_mtype); 138 /* On dGPU we're always in GPUVM64 addressing mode with 64-bit 139 * aperture addresses. 140 */ 141 temp = get_sh_mem_bases_nybble_64(qpd_to_pdd(qpd)); 142 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); 143 144 pr_debug("is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n", 145 qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases); 146 147 out: 148 return retval; 149 } 150 151 static int update_qpd_cik(struct device_queue_manager *dqm, 152 struct qcm_process_device *qpd) 153 { 154 return 0; 155 } 156 157 static void init_sdma_vm(struct device_queue_manager *dqm, 158 struct queue *q, 159 struct qcm_process_device *qpd) 160 { 161 /* On dGPU we're always in GPUVM64 addressing mode with 64-bit 162 * aperture addresses. 163 */ 164 q->properties.sdma_vm_addr = 165 ((get_sh_mem_bases_nybble_64(qpd_to_pdd(qpd))) << 166 SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT) & 167 SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK; 168 } 169