1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/ratelimit.h> 26 #include <linux/printk.h> 27 #include <linux/slab.h> 28 #include <linux/list.h> 29 #include <linux/types.h> 30 #include <linux/bitops.h> 31 #include <linux/sched.h> 32 #include "kfd_priv.h" 33 #include "kfd_device_queue_manager.h" 34 #include "kfd_mqd_manager.h" 35 #include "cik_regs.h" 36 #include "kfd_kernel_queue.h" 37 #include "amdgpu_amdkfd.h" 38 #include "amdgpu_reset.h" 39 #include "mes_v11_api_def.h" 40 #include "kfd_debug.h" 41 42 /* Size of the per-pipe EOP queue */ 43 #define CIK_HPD_EOP_BYTES_LOG2 11 44 #define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2) 45 46 static int set_pasid_vmid_mapping(struct device_queue_manager *dqm, 47 u32 pasid, unsigned int vmid); 48 49 static int execute_queues_cpsch(struct device_queue_manager *dqm, 50 enum kfd_unmap_queues_filter filter, 51 uint32_t filter_param, 52 uint32_t grace_period); 53 static int unmap_queues_cpsch(struct device_queue_manager *dqm, 54 enum kfd_unmap_queues_filter filter, 55 uint32_t filter_param, 56 uint32_t grace_period, 57 bool reset); 58 59 static int map_queues_cpsch(struct device_queue_manager *dqm); 60 61 static void deallocate_sdma_queue(struct device_queue_manager *dqm, 62 struct queue *q); 63 64 static inline void deallocate_hqd(struct device_queue_manager *dqm, 65 struct queue *q); 66 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q); 67 static int allocate_sdma_queue(struct device_queue_manager *dqm, 68 struct queue *q, const uint32_t *restore_sdma_id); 69 static void kfd_process_hw_exception(struct work_struct *work); 70 71 static inline 72 enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type) 73 { 74 if (type == KFD_QUEUE_TYPE_SDMA || type == KFD_QUEUE_TYPE_SDMA_XGMI) 75 return KFD_MQD_TYPE_SDMA; 76 return KFD_MQD_TYPE_CP; 77 } 78 79 static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe) 80 { 81 int i; 82 int pipe_offset = (mec * dqm->dev->kfd->shared_resources.num_pipe_per_mec 83 + pipe) * dqm->dev->kfd->shared_resources.num_queue_per_pipe; 84 85 /* queue is available for KFD usage if bit is 1 */ 86 for (i = 0; i < dqm->dev->kfd->shared_resources.num_queue_per_pipe; ++i) 87 if (test_bit(pipe_offset + i, 88 dqm->dev->kfd->shared_resources.cp_queue_bitmap)) 89 return true; 90 return false; 91 } 92 93 unsigned int get_cp_queues_num(struct device_queue_manager *dqm) 94 { 95 return bitmap_weight(dqm->dev->kfd->shared_resources.cp_queue_bitmap, 96 AMDGPU_MAX_QUEUES); 97 } 98 99 unsigned int get_queues_per_pipe(struct device_queue_manager *dqm) 100 { 101 return dqm->dev->kfd->shared_resources.num_queue_per_pipe; 102 } 103 104 unsigned int get_pipes_per_mec(struct device_queue_manager *dqm) 105 { 106 return dqm->dev->kfd->shared_resources.num_pipe_per_mec; 107 } 108 109 static unsigned int get_num_all_sdma_engines(struct device_queue_manager *dqm) 110 { 111 return kfd_get_num_sdma_engines(dqm->dev) + 112 kfd_get_num_xgmi_sdma_engines(dqm->dev); 113 } 114 115 unsigned int get_num_sdma_queues(struct device_queue_manager *dqm) 116 { 117 return kfd_get_num_sdma_engines(dqm->dev) * 118 dqm->dev->kfd->device_info.num_sdma_queues_per_engine; 119 } 120 121 unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm) 122 { 123 return kfd_get_num_xgmi_sdma_engines(dqm->dev) * 124 dqm->dev->kfd->device_info.num_sdma_queues_per_engine; 125 } 126 127 static void init_sdma_bitmaps(struct device_queue_manager *dqm) 128 { 129 bitmap_zero(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES); 130 bitmap_set(dqm->sdma_bitmap, 0, get_num_sdma_queues(dqm)); 131 132 bitmap_zero(dqm->xgmi_sdma_bitmap, KFD_MAX_SDMA_QUEUES); 133 bitmap_set(dqm->xgmi_sdma_bitmap, 0, get_num_xgmi_sdma_queues(dqm)); 134 135 /* Mask out the reserved queues */ 136 bitmap_andnot(dqm->sdma_bitmap, dqm->sdma_bitmap, 137 dqm->dev->kfd->device_info.reserved_sdma_queues_bitmap, 138 KFD_MAX_SDMA_QUEUES); 139 } 140 141 void program_sh_mem_settings(struct device_queue_manager *dqm, 142 struct qcm_process_device *qpd) 143 { 144 uint32_t xcc_mask = dqm->dev->xcc_mask; 145 int xcc_id; 146 147 for_each_inst(xcc_id, xcc_mask) 148 dqm->dev->kfd2kgd->program_sh_mem_settings( 149 dqm->dev->adev, qpd->vmid, qpd->sh_mem_config, 150 qpd->sh_mem_ape1_base, qpd->sh_mem_ape1_limit, 151 qpd->sh_mem_bases, xcc_id); 152 } 153 154 static void kfd_hws_hang(struct device_queue_manager *dqm) 155 { 156 /* 157 * Issue a GPU reset if HWS is unresponsive 158 */ 159 schedule_work(&dqm->hw_exception_work); 160 } 161 162 static int convert_to_mes_queue_type(int queue_type) 163 { 164 int mes_queue_type; 165 166 switch (queue_type) { 167 case KFD_QUEUE_TYPE_COMPUTE: 168 mes_queue_type = MES_QUEUE_TYPE_COMPUTE; 169 break; 170 case KFD_QUEUE_TYPE_SDMA: 171 mes_queue_type = MES_QUEUE_TYPE_SDMA; 172 break; 173 default: 174 WARN(1, "Invalid queue type %d", queue_type); 175 mes_queue_type = -EINVAL; 176 break; 177 } 178 179 return mes_queue_type; 180 } 181 182 static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q, 183 struct qcm_process_device *qpd) 184 { 185 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; 186 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 187 struct mes_add_queue_input queue_input; 188 int r, queue_type; 189 uint64_t wptr_addr_off; 190 191 if (!down_read_trylock(&adev->reset_domain->sem)) 192 return -EIO; 193 194 memset(&queue_input, 0x0, sizeof(struct mes_add_queue_input)); 195 queue_input.process_id = qpd->pqm->process->pasid; 196 queue_input.page_table_base_addr = qpd->page_table_base; 197 queue_input.process_va_start = 0; 198 queue_input.process_va_end = adev->vm_manager.max_pfn - 1; 199 /* MES unit for quantum is 100ns */ 200 queue_input.process_quantum = KFD_MES_PROCESS_QUANTUM; /* Equivalent to 10ms. */ 201 queue_input.process_context_addr = pdd->proc_ctx_gpu_addr; 202 queue_input.gang_quantum = KFD_MES_GANG_QUANTUM; /* Equivalent to 1ms */ 203 queue_input.gang_context_addr = q->gang_ctx_gpu_addr; 204 queue_input.inprocess_gang_priority = q->properties.priority; 205 queue_input.gang_global_priority_level = 206 AMDGPU_MES_PRIORITY_LEVEL_NORMAL; 207 queue_input.doorbell_offset = q->properties.doorbell_off; 208 queue_input.mqd_addr = q->gart_mqd_addr; 209 queue_input.wptr_addr = (uint64_t)q->properties.write_ptr; 210 211 wptr_addr_off = (uint64_t)q->properties.write_ptr & (PAGE_SIZE - 1); 212 queue_input.wptr_mc_addr = amdgpu_bo_gpu_offset(q->properties.wptr_bo) + wptr_addr_off; 213 214 queue_input.is_kfd_process = 1; 215 queue_input.is_aql_queue = (q->properties.format == KFD_QUEUE_FORMAT_AQL); 216 queue_input.queue_size = q->properties.queue_size >> 2; 217 218 queue_input.paging = false; 219 queue_input.tba_addr = qpd->tba_addr; 220 queue_input.tma_addr = qpd->tma_addr; 221 queue_input.trap_en = !kfd_dbg_has_cwsr_workaround(q->device); 222 queue_input.skip_process_ctx_clear = 223 qpd->pqm->process->runtime_info.runtime_state == DEBUG_RUNTIME_STATE_ENABLED && 224 (qpd->pqm->process->debug_trap_enabled || 225 kfd_dbg_has_ttmps_always_setup(q->device)); 226 227 queue_type = convert_to_mes_queue_type(q->properties.type); 228 if (queue_type < 0) { 229 dev_err(adev->dev, "Queue type not supported with MES, queue:%d\n", 230 q->properties.type); 231 up_read(&adev->reset_domain->sem); 232 return -EINVAL; 233 } 234 queue_input.queue_type = (uint32_t)queue_type; 235 236 queue_input.exclusively_scheduled = q->properties.is_gws; 237 238 amdgpu_mes_lock(&adev->mes); 239 r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input); 240 amdgpu_mes_unlock(&adev->mes); 241 up_read(&adev->reset_domain->sem); 242 if (r) { 243 dev_err(adev->dev, "failed to add hardware queue to MES, doorbell=0x%x\n", 244 q->properties.doorbell_off); 245 dev_err(adev->dev, "MES might be in unrecoverable state, issue a GPU reset\n"); 246 kfd_hws_hang(dqm); 247 } 248 249 return r; 250 } 251 252 static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q, 253 struct qcm_process_device *qpd) 254 { 255 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; 256 int r; 257 struct mes_remove_queue_input queue_input; 258 259 if (!down_read_trylock(&adev->reset_domain->sem)) 260 return -EIO; 261 262 memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input)); 263 queue_input.doorbell_offset = q->properties.doorbell_off; 264 queue_input.gang_context_addr = q->gang_ctx_gpu_addr; 265 266 amdgpu_mes_lock(&adev->mes); 267 r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input); 268 amdgpu_mes_unlock(&adev->mes); 269 up_read(&adev->reset_domain->sem); 270 271 if (r) { 272 dev_err(adev->dev, "failed to remove hardware queue from MES, doorbell=0x%x\n", 273 q->properties.doorbell_off); 274 dev_err(adev->dev, "MES might be in unrecoverable state, issue a GPU reset\n"); 275 kfd_hws_hang(dqm); 276 } 277 278 return r; 279 } 280 281 static int remove_all_queues_mes(struct device_queue_manager *dqm) 282 { 283 struct device_process_node *cur; 284 struct device *dev = dqm->dev->adev->dev; 285 struct qcm_process_device *qpd; 286 struct queue *q; 287 int retval = 0; 288 289 list_for_each_entry(cur, &dqm->queues, list) { 290 qpd = cur->qpd; 291 list_for_each_entry(q, &qpd->queues_list, list) { 292 if (q->properties.is_active) { 293 retval = remove_queue_mes(dqm, q, qpd); 294 if (retval) { 295 dev_err(dev, "%s: Failed to remove queue %d for dev %d", 296 __func__, 297 q->properties.queue_id, 298 dqm->dev->id); 299 return retval; 300 } 301 } 302 } 303 } 304 305 return retval; 306 } 307 308 static void increment_queue_count(struct device_queue_manager *dqm, 309 struct qcm_process_device *qpd, 310 struct queue *q) 311 { 312 dqm->active_queue_count++; 313 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 314 q->properties.type == KFD_QUEUE_TYPE_DIQ) 315 dqm->active_cp_queue_count++; 316 317 if (q->properties.is_gws) { 318 dqm->gws_queue_count++; 319 qpd->mapped_gws_queue = true; 320 } 321 } 322 323 static void decrement_queue_count(struct device_queue_manager *dqm, 324 struct qcm_process_device *qpd, 325 struct queue *q) 326 { 327 dqm->active_queue_count--; 328 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 329 q->properties.type == KFD_QUEUE_TYPE_DIQ) 330 dqm->active_cp_queue_count--; 331 332 if (q->properties.is_gws) { 333 dqm->gws_queue_count--; 334 qpd->mapped_gws_queue = false; 335 } 336 } 337 338 /* 339 * Allocate a doorbell ID to this queue. 340 * If doorbell_id is passed in, make sure requested ID is valid then allocate it. 341 */ 342 static int allocate_doorbell(struct qcm_process_device *qpd, 343 struct queue *q, 344 uint32_t const *restore_id) 345 { 346 struct kfd_node *dev = qpd->dqm->dev; 347 348 if (!KFD_IS_SOC15(dev)) { 349 /* On pre-SOC15 chips we need to use the queue ID to 350 * preserve the user mode ABI. 351 */ 352 353 if (restore_id && *restore_id != q->properties.queue_id) 354 return -EINVAL; 355 356 q->doorbell_id = q->properties.queue_id; 357 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 358 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 359 /* For SDMA queues on SOC15 with 8-byte doorbell, use static 360 * doorbell assignments based on the engine and queue id. 361 * The doobell index distance between RLC (2*i) and (2*i+1) 362 * for a SDMA engine is 512. 363 */ 364 365 uint32_t *idx_offset = dev->kfd->shared_resources.sdma_doorbell_idx; 366 367 /* 368 * q->properties.sdma_engine_id corresponds to the virtual 369 * sdma engine number. However, for doorbell allocation, 370 * we need the physical sdma engine id in order to get the 371 * correct doorbell offset. 372 */ 373 uint32_t valid_id = idx_offset[qpd->dqm->dev->node_id * 374 get_num_all_sdma_engines(qpd->dqm) + 375 q->properties.sdma_engine_id] 376 + (q->properties.sdma_queue_id & 1) 377 * KFD_QUEUE_DOORBELL_MIRROR_OFFSET 378 + (q->properties.sdma_queue_id >> 1); 379 380 if (restore_id && *restore_id != valid_id) 381 return -EINVAL; 382 q->doorbell_id = valid_id; 383 } else { 384 /* For CP queues on SOC15 */ 385 if (restore_id) { 386 /* make sure that ID is free */ 387 if (__test_and_set_bit(*restore_id, qpd->doorbell_bitmap)) 388 return -EINVAL; 389 390 q->doorbell_id = *restore_id; 391 } else { 392 /* or reserve a free doorbell ID */ 393 unsigned int found; 394 395 found = find_first_zero_bit(qpd->doorbell_bitmap, 396 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); 397 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) { 398 pr_debug("No doorbells available"); 399 return -EBUSY; 400 } 401 set_bit(found, qpd->doorbell_bitmap); 402 q->doorbell_id = found; 403 } 404 } 405 406 q->properties.doorbell_off = amdgpu_doorbell_index_on_bar(dev->adev, 407 qpd->proc_doorbells, 408 q->doorbell_id, 409 dev->kfd->device_info.doorbell_size); 410 return 0; 411 } 412 413 static void deallocate_doorbell(struct qcm_process_device *qpd, 414 struct queue *q) 415 { 416 unsigned int old; 417 struct kfd_node *dev = qpd->dqm->dev; 418 419 if (!KFD_IS_SOC15(dev) || 420 q->properties.type == KFD_QUEUE_TYPE_SDMA || 421 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 422 return; 423 424 old = test_and_clear_bit(q->doorbell_id, qpd->doorbell_bitmap); 425 WARN_ON(!old); 426 } 427 428 static void program_trap_handler_settings(struct device_queue_manager *dqm, 429 struct qcm_process_device *qpd) 430 { 431 uint32_t xcc_mask = dqm->dev->xcc_mask; 432 int xcc_id; 433 434 if (dqm->dev->kfd2kgd->program_trap_handler_settings) 435 for_each_inst(xcc_id, xcc_mask) 436 dqm->dev->kfd2kgd->program_trap_handler_settings( 437 dqm->dev->adev, qpd->vmid, qpd->tba_addr, 438 qpd->tma_addr, xcc_id); 439 } 440 441 static int allocate_vmid(struct device_queue_manager *dqm, 442 struct qcm_process_device *qpd, 443 struct queue *q) 444 { 445 struct device *dev = dqm->dev->adev->dev; 446 int allocated_vmid = -1, i; 447 448 for (i = dqm->dev->vm_info.first_vmid_kfd; 449 i <= dqm->dev->vm_info.last_vmid_kfd; i++) { 450 if (!dqm->vmid_pasid[i]) { 451 allocated_vmid = i; 452 break; 453 } 454 } 455 456 if (allocated_vmid < 0) { 457 dev_err(dev, "no more vmid to allocate\n"); 458 return -ENOSPC; 459 } 460 461 pr_debug("vmid allocated: %d\n", allocated_vmid); 462 463 dqm->vmid_pasid[allocated_vmid] = q->process->pasid; 464 465 set_pasid_vmid_mapping(dqm, q->process->pasid, allocated_vmid); 466 467 qpd->vmid = allocated_vmid; 468 q->properties.vmid = allocated_vmid; 469 470 program_sh_mem_settings(dqm, qpd); 471 472 if (KFD_IS_SOC15(dqm->dev) && dqm->dev->kfd->cwsr_enabled) 473 program_trap_handler_settings(dqm, qpd); 474 475 /* qpd->page_table_base is set earlier when register_process() 476 * is called, i.e. when the first queue is created. 477 */ 478 dqm->dev->kfd2kgd->set_vm_context_page_table_base(dqm->dev->adev, 479 qpd->vmid, 480 qpd->page_table_base); 481 /* invalidate the VM context after pasid and vmid mapping is set up */ 482 kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY); 483 484 if (dqm->dev->kfd2kgd->set_scratch_backing_va) 485 dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->adev, 486 qpd->sh_hidden_private_base, qpd->vmid); 487 488 return 0; 489 } 490 491 static int flush_texture_cache_nocpsch(struct kfd_node *kdev, 492 struct qcm_process_device *qpd) 493 { 494 const struct packet_manager_funcs *pmf = qpd->dqm->packet_mgr.pmf; 495 int ret; 496 497 if (!qpd->ib_kaddr) 498 return -ENOMEM; 499 500 ret = pmf->release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr); 501 if (ret) 502 return ret; 503 504 return amdgpu_amdkfd_submit_ib(kdev->adev, KGD_ENGINE_MEC1, qpd->vmid, 505 qpd->ib_base, (uint32_t *)qpd->ib_kaddr, 506 pmf->release_mem_size / sizeof(uint32_t)); 507 } 508 509 static void deallocate_vmid(struct device_queue_manager *dqm, 510 struct qcm_process_device *qpd, 511 struct queue *q) 512 { 513 struct device *dev = dqm->dev->adev->dev; 514 515 /* On GFX v7, CP doesn't flush TC at dequeue */ 516 if (q->device->adev->asic_type == CHIP_HAWAII) 517 if (flush_texture_cache_nocpsch(q->device, qpd)) 518 dev_err(dev, "Failed to flush TC\n"); 519 520 kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY); 521 522 /* Release the vmid mapping */ 523 set_pasid_vmid_mapping(dqm, 0, qpd->vmid); 524 dqm->vmid_pasid[qpd->vmid] = 0; 525 526 qpd->vmid = 0; 527 q->properties.vmid = 0; 528 } 529 530 static int create_queue_nocpsch(struct device_queue_manager *dqm, 531 struct queue *q, 532 struct qcm_process_device *qpd, 533 const struct kfd_criu_queue_priv_data *qd, 534 const void *restore_mqd, const void *restore_ctl_stack) 535 { 536 struct mqd_manager *mqd_mgr; 537 int retval; 538 539 dqm_lock(dqm); 540 541 if (dqm->total_queue_count >= max_num_of_queues_per_device) { 542 pr_warn("Can't create new usermode queue because %d queues were already created\n", 543 dqm->total_queue_count); 544 retval = -EPERM; 545 goto out_unlock; 546 } 547 548 if (list_empty(&qpd->queues_list)) { 549 retval = allocate_vmid(dqm, qpd, q); 550 if (retval) 551 goto out_unlock; 552 } 553 q->properties.vmid = qpd->vmid; 554 /* 555 * Eviction state logic: mark all queues as evicted, even ones 556 * not currently active. Restoring inactive queues later only 557 * updates the is_evicted flag but is a no-op otherwise. 558 */ 559 q->properties.is_evicted = !!qpd->evicted; 560 561 q->properties.tba_addr = qpd->tba_addr; 562 q->properties.tma_addr = qpd->tma_addr; 563 564 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 565 q->properties.type)]; 566 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) { 567 retval = allocate_hqd(dqm, q); 568 if (retval) 569 goto deallocate_vmid; 570 pr_debug("Loading mqd to hqd on pipe %d, queue %d\n", 571 q->pipe, q->queue); 572 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 573 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 574 retval = allocate_sdma_queue(dqm, q, qd ? &qd->sdma_id : NULL); 575 if (retval) 576 goto deallocate_vmid; 577 dqm->asic_ops.init_sdma_vm(dqm, q, qpd); 578 } 579 580 retval = allocate_doorbell(qpd, q, qd ? &qd->doorbell_id : NULL); 581 if (retval) 582 goto out_deallocate_hqd; 583 584 /* Temporarily release dqm lock to avoid a circular lock dependency */ 585 dqm_unlock(dqm); 586 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties); 587 dqm_lock(dqm); 588 589 if (!q->mqd_mem_obj) { 590 retval = -ENOMEM; 591 goto out_deallocate_doorbell; 592 } 593 594 if (qd) 595 mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr, 596 &q->properties, restore_mqd, restore_ctl_stack, 597 qd->ctl_stack_size); 598 else 599 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, 600 &q->gart_mqd_addr, &q->properties); 601 602 if (q->properties.is_active) { 603 if (!dqm->sched_running) { 604 WARN_ONCE(1, "Load non-HWS mqd while stopped\n"); 605 goto add_queue_to_list; 606 } 607 608 if (WARN(q->process->mm != current->mm, 609 "should only run in user thread")) 610 retval = -EFAULT; 611 else 612 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe, 613 q->queue, &q->properties, current->mm); 614 if (retval) 615 goto out_free_mqd; 616 } 617 618 add_queue_to_list: 619 list_add(&q->list, &qpd->queues_list); 620 qpd->queue_count++; 621 if (q->properties.is_active) 622 increment_queue_count(dqm, qpd, q); 623 624 /* 625 * Unconditionally increment this counter, regardless of the queue's 626 * type or whether the queue is active. 627 */ 628 dqm->total_queue_count++; 629 pr_debug("Total of %d queues are accountable so far\n", 630 dqm->total_queue_count); 631 goto out_unlock; 632 633 out_free_mqd: 634 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 635 out_deallocate_doorbell: 636 deallocate_doorbell(qpd, q); 637 out_deallocate_hqd: 638 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) 639 deallocate_hqd(dqm, q); 640 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 641 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 642 deallocate_sdma_queue(dqm, q); 643 deallocate_vmid: 644 if (list_empty(&qpd->queues_list)) 645 deallocate_vmid(dqm, qpd, q); 646 out_unlock: 647 dqm_unlock(dqm); 648 return retval; 649 } 650 651 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q) 652 { 653 bool set; 654 int pipe, bit, i; 655 656 set = false; 657 658 for (pipe = dqm->next_pipe_to_allocate, i = 0; 659 i < get_pipes_per_mec(dqm); 660 pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) { 661 662 if (!is_pipe_enabled(dqm, 0, pipe)) 663 continue; 664 665 if (dqm->allocated_queues[pipe] != 0) { 666 bit = ffs(dqm->allocated_queues[pipe]) - 1; 667 dqm->allocated_queues[pipe] &= ~(1 << bit); 668 q->pipe = pipe; 669 q->queue = bit; 670 set = true; 671 break; 672 } 673 } 674 675 if (!set) 676 return -EBUSY; 677 678 pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue); 679 /* horizontal hqd allocation */ 680 dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm); 681 682 return 0; 683 } 684 685 static inline void deallocate_hqd(struct device_queue_manager *dqm, 686 struct queue *q) 687 { 688 dqm->allocated_queues[q->pipe] |= (1 << q->queue); 689 } 690 691 #define SQ_IND_CMD_CMD_KILL 0x00000003 692 #define SQ_IND_CMD_MODE_BROADCAST 0x00000001 693 694 static int dbgdev_wave_reset_wavefronts(struct kfd_node *dev, struct kfd_process *p) 695 { 696 int status = 0; 697 unsigned int vmid; 698 uint16_t queried_pasid; 699 union SQ_CMD_BITS reg_sq_cmd; 700 union GRBM_GFX_INDEX_BITS reg_gfx_index; 701 struct kfd_process_device *pdd; 702 int first_vmid_to_scan = dev->vm_info.first_vmid_kfd; 703 int last_vmid_to_scan = dev->vm_info.last_vmid_kfd; 704 uint32_t xcc_mask = dev->xcc_mask; 705 int xcc_id; 706 707 reg_sq_cmd.u32All = 0; 708 reg_gfx_index.u32All = 0; 709 710 pr_debug("Killing all process wavefronts\n"); 711 712 if (!dev->kfd2kgd->get_atc_vmid_pasid_mapping_info) { 713 dev_err(dev->adev->dev, "no vmid pasid mapping supported\n"); 714 return -EOPNOTSUPP; 715 } 716 717 /* Scan all registers in the range ATC_VMID8_PASID_MAPPING .. 718 * ATC_VMID15_PASID_MAPPING 719 * to check which VMID the current process is mapped to. 720 */ 721 722 for (vmid = first_vmid_to_scan; vmid <= last_vmid_to_scan; vmid++) { 723 status = dev->kfd2kgd->get_atc_vmid_pasid_mapping_info 724 (dev->adev, vmid, &queried_pasid); 725 726 if (status && queried_pasid == p->pasid) { 727 pr_debug("Killing wave fronts of vmid %d and pasid 0x%x\n", 728 vmid, p->pasid); 729 break; 730 } 731 } 732 733 if (vmid > last_vmid_to_scan) { 734 dev_err(dev->adev->dev, "Didn't find vmid for pasid 0x%x\n", p->pasid); 735 return -EFAULT; 736 } 737 738 /* taking the VMID for that process on the safe way using PDD */ 739 pdd = kfd_get_process_device_data(dev, p); 740 if (!pdd) 741 return -EFAULT; 742 743 reg_gfx_index.bits.sh_broadcast_writes = 1; 744 reg_gfx_index.bits.se_broadcast_writes = 1; 745 reg_gfx_index.bits.instance_broadcast_writes = 1; 746 reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST; 747 reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_KILL; 748 reg_sq_cmd.bits.vm_id = vmid; 749 750 for_each_inst(xcc_id, xcc_mask) 751 dev->kfd2kgd->wave_control_execute( 752 dev->adev, reg_gfx_index.u32All, 753 reg_sq_cmd.u32All, xcc_id); 754 755 return 0; 756 } 757 758 /* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked 759 * to avoid asynchronized access 760 */ 761 static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm, 762 struct qcm_process_device *qpd, 763 struct queue *q) 764 { 765 int retval; 766 struct mqd_manager *mqd_mgr; 767 768 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 769 q->properties.type)]; 770 771 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) 772 deallocate_hqd(dqm, q); 773 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) 774 deallocate_sdma_queue(dqm, q); 775 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 776 deallocate_sdma_queue(dqm, q); 777 else { 778 pr_debug("q->properties.type %d is invalid\n", 779 q->properties.type); 780 return -EINVAL; 781 } 782 dqm->total_queue_count--; 783 784 deallocate_doorbell(qpd, q); 785 786 if (!dqm->sched_running) { 787 WARN_ONCE(1, "Destroy non-HWS queue while stopped\n"); 788 return 0; 789 } 790 791 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, 792 KFD_PREEMPT_TYPE_WAVEFRONT_RESET, 793 KFD_UNMAP_LATENCY_MS, 794 q->pipe, q->queue); 795 if (retval == -ETIME) 796 qpd->reset_wavefronts = true; 797 798 list_del(&q->list); 799 if (list_empty(&qpd->queues_list)) { 800 if (qpd->reset_wavefronts) { 801 pr_warn("Resetting wave fronts (nocpsch) on dev %p\n", 802 dqm->dev); 803 /* dbgdev_wave_reset_wavefronts has to be called before 804 * deallocate_vmid(), i.e. when vmid is still in use. 805 */ 806 dbgdev_wave_reset_wavefronts(dqm->dev, 807 qpd->pqm->process); 808 qpd->reset_wavefronts = false; 809 } 810 811 deallocate_vmid(dqm, qpd, q); 812 } 813 qpd->queue_count--; 814 if (q->properties.is_active) 815 decrement_queue_count(dqm, qpd, q); 816 817 return retval; 818 } 819 820 static int destroy_queue_nocpsch(struct device_queue_manager *dqm, 821 struct qcm_process_device *qpd, 822 struct queue *q) 823 { 824 int retval; 825 uint64_t sdma_val = 0; 826 struct device *dev = dqm->dev->adev->dev; 827 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 828 struct mqd_manager *mqd_mgr = 829 dqm->mqd_mgrs[get_mqd_type_from_queue_type(q->properties.type)]; 830 831 /* Get the SDMA queue stats */ 832 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || 833 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 834 retval = read_sdma_queue_counter((uint64_t __user *)q->properties.read_ptr, 835 &sdma_val); 836 if (retval) 837 dev_err(dev, "Failed to read SDMA queue counter for queue: %d\n", 838 q->properties.queue_id); 839 } 840 841 dqm_lock(dqm); 842 retval = destroy_queue_nocpsch_locked(dqm, qpd, q); 843 if (!retval) 844 pdd->sdma_past_activity_counter += sdma_val; 845 dqm_unlock(dqm); 846 847 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 848 849 return retval; 850 } 851 852 static int update_queue(struct device_queue_manager *dqm, struct queue *q, 853 struct mqd_update_info *minfo) 854 { 855 int retval = 0; 856 struct device *dev = dqm->dev->adev->dev; 857 struct mqd_manager *mqd_mgr; 858 struct kfd_process_device *pdd; 859 bool prev_active = false; 860 861 dqm_lock(dqm); 862 pdd = kfd_get_process_device_data(q->device, q->process); 863 if (!pdd) { 864 retval = -ENODEV; 865 goto out_unlock; 866 } 867 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 868 q->properties.type)]; 869 870 /* Save previous activity state for counters */ 871 prev_active = q->properties.is_active; 872 873 /* Make sure the queue is unmapped before updating the MQD */ 874 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) { 875 if (!dqm->dev->kfd->shared_resources.enable_mes) 876 retval = unmap_queues_cpsch(dqm, 877 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD, false); 878 else if (prev_active) 879 retval = remove_queue_mes(dqm, q, &pdd->qpd); 880 881 if (retval) { 882 dev_err(dev, "unmap queue failed\n"); 883 goto out_unlock; 884 } 885 } else if (prev_active && 886 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 887 q->properties.type == KFD_QUEUE_TYPE_SDMA || 888 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 889 890 if (!dqm->sched_running) { 891 WARN_ONCE(1, "Update non-HWS queue while stopped\n"); 892 goto out_unlock; 893 } 894 895 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, 896 (dqm->dev->kfd->cwsr_enabled ? 897 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE : 898 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN), 899 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue); 900 if (retval) { 901 dev_err(dev, "destroy mqd failed\n"); 902 goto out_unlock; 903 } 904 } 905 906 mqd_mgr->update_mqd(mqd_mgr, q->mqd, &q->properties, minfo); 907 908 /* 909 * check active state vs. the previous state and modify 910 * counter accordingly. map_queues_cpsch uses the 911 * dqm->active_queue_count to determine whether a new runlist must be 912 * uploaded. 913 */ 914 if (q->properties.is_active && !prev_active) { 915 increment_queue_count(dqm, &pdd->qpd, q); 916 } else if (!q->properties.is_active && prev_active) { 917 decrement_queue_count(dqm, &pdd->qpd, q); 918 } else if (q->gws && !q->properties.is_gws) { 919 if (q->properties.is_active) { 920 dqm->gws_queue_count++; 921 pdd->qpd.mapped_gws_queue = true; 922 } 923 q->properties.is_gws = true; 924 } else if (!q->gws && q->properties.is_gws) { 925 if (q->properties.is_active) { 926 dqm->gws_queue_count--; 927 pdd->qpd.mapped_gws_queue = false; 928 } 929 q->properties.is_gws = false; 930 } 931 932 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) { 933 if (!dqm->dev->kfd->shared_resources.enable_mes) 934 retval = map_queues_cpsch(dqm); 935 else if (q->properties.is_active) 936 retval = add_queue_mes(dqm, q, &pdd->qpd); 937 } else if (q->properties.is_active && 938 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 939 q->properties.type == KFD_QUEUE_TYPE_SDMA || 940 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 941 if (WARN(q->process->mm != current->mm, 942 "should only run in user thread")) 943 retval = -EFAULT; 944 else 945 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, 946 q->pipe, q->queue, 947 &q->properties, current->mm); 948 } 949 950 out_unlock: 951 dqm_unlock(dqm); 952 return retval; 953 } 954 955 /* suspend_single_queue does not lock the dqm like the 956 * evict_process_queues_cpsch or evict_process_queues_nocpsch. You should 957 * lock the dqm before calling, and unlock after calling. 958 * 959 * The reason we don't lock the dqm is because this function may be 960 * called on multiple queues in a loop, so rather than locking/unlocking 961 * multiple times, we will just keep the dqm locked for all of the calls. 962 */ 963 static int suspend_single_queue(struct device_queue_manager *dqm, 964 struct kfd_process_device *pdd, 965 struct queue *q) 966 { 967 bool is_new; 968 969 if (q->properties.is_suspended) 970 return 0; 971 972 pr_debug("Suspending PASID %u queue [%i]\n", 973 pdd->process->pasid, 974 q->properties.queue_id); 975 976 is_new = q->properties.exception_status & KFD_EC_MASK(EC_QUEUE_NEW); 977 978 if (is_new || q->properties.is_being_destroyed) { 979 pr_debug("Suspend: skip %s queue id %i\n", 980 is_new ? "new" : "destroyed", 981 q->properties.queue_id); 982 return -EBUSY; 983 } 984 985 q->properties.is_suspended = true; 986 if (q->properties.is_active) { 987 if (dqm->dev->kfd->shared_resources.enable_mes) { 988 int r = remove_queue_mes(dqm, q, &pdd->qpd); 989 990 if (r) 991 return r; 992 } 993 994 decrement_queue_count(dqm, &pdd->qpd, q); 995 q->properties.is_active = false; 996 } 997 998 return 0; 999 } 1000 1001 /* resume_single_queue does not lock the dqm like the functions 1002 * restore_process_queues_cpsch or restore_process_queues_nocpsch. You should 1003 * lock the dqm before calling, and unlock after calling. 1004 * 1005 * The reason we don't lock the dqm is because this function may be 1006 * called on multiple queues in a loop, so rather than locking/unlocking 1007 * multiple times, we will just keep the dqm locked for all of the calls. 1008 */ 1009 static int resume_single_queue(struct device_queue_manager *dqm, 1010 struct qcm_process_device *qpd, 1011 struct queue *q) 1012 { 1013 struct kfd_process_device *pdd; 1014 1015 if (!q->properties.is_suspended) 1016 return 0; 1017 1018 pdd = qpd_to_pdd(qpd); 1019 1020 pr_debug("Restoring from suspend PASID %u queue [%i]\n", 1021 pdd->process->pasid, 1022 q->properties.queue_id); 1023 1024 q->properties.is_suspended = false; 1025 1026 if (QUEUE_IS_ACTIVE(q->properties)) { 1027 if (dqm->dev->kfd->shared_resources.enable_mes) { 1028 int r = add_queue_mes(dqm, q, &pdd->qpd); 1029 1030 if (r) 1031 return r; 1032 } 1033 1034 q->properties.is_active = true; 1035 increment_queue_count(dqm, qpd, q); 1036 } 1037 1038 return 0; 1039 } 1040 1041 static int evict_process_queues_nocpsch(struct device_queue_manager *dqm, 1042 struct qcm_process_device *qpd) 1043 { 1044 struct queue *q; 1045 struct mqd_manager *mqd_mgr; 1046 struct kfd_process_device *pdd; 1047 int retval, ret = 0; 1048 1049 dqm_lock(dqm); 1050 if (qpd->evicted++ > 0) /* already evicted, do nothing */ 1051 goto out; 1052 1053 pdd = qpd_to_pdd(qpd); 1054 pr_debug_ratelimited("Evicting PASID 0x%x queues\n", 1055 pdd->process->pasid); 1056 1057 pdd->last_evict_timestamp = get_jiffies_64(); 1058 /* Mark all queues as evicted. Deactivate all active queues on 1059 * the qpd. 1060 */ 1061 list_for_each_entry(q, &qpd->queues_list, list) { 1062 q->properties.is_evicted = true; 1063 if (!q->properties.is_active) 1064 continue; 1065 1066 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1067 q->properties.type)]; 1068 q->properties.is_active = false; 1069 decrement_queue_count(dqm, qpd, q); 1070 1071 if (WARN_ONCE(!dqm->sched_running, "Evict when stopped\n")) 1072 continue; 1073 1074 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, 1075 (dqm->dev->kfd->cwsr_enabled ? 1076 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE : 1077 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN), 1078 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue); 1079 if (retval && !ret) 1080 /* Return the first error, but keep going to 1081 * maintain a consistent eviction state 1082 */ 1083 ret = retval; 1084 } 1085 1086 out: 1087 dqm_unlock(dqm); 1088 return ret; 1089 } 1090 1091 static int evict_process_queues_cpsch(struct device_queue_manager *dqm, 1092 struct qcm_process_device *qpd) 1093 { 1094 struct queue *q; 1095 struct device *dev = dqm->dev->adev->dev; 1096 struct kfd_process_device *pdd; 1097 int retval = 0; 1098 1099 dqm_lock(dqm); 1100 if (qpd->evicted++ > 0) /* already evicted, do nothing */ 1101 goto out; 1102 1103 pdd = qpd_to_pdd(qpd); 1104 1105 /* The debugger creates processes that temporarily have not acquired 1106 * all VMs for all devices and has no VMs itself. 1107 * Skip queue eviction on process eviction. 1108 */ 1109 if (!pdd->drm_priv) 1110 goto out; 1111 1112 pr_debug_ratelimited("Evicting PASID 0x%x queues\n", 1113 pdd->process->pasid); 1114 1115 /* Mark all queues as evicted. Deactivate all active queues on 1116 * the qpd. 1117 */ 1118 list_for_each_entry(q, &qpd->queues_list, list) { 1119 q->properties.is_evicted = true; 1120 if (!q->properties.is_active) 1121 continue; 1122 1123 q->properties.is_active = false; 1124 decrement_queue_count(dqm, qpd, q); 1125 1126 if (dqm->dev->kfd->shared_resources.enable_mes) { 1127 retval = remove_queue_mes(dqm, q, qpd); 1128 if (retval) { 1129 dev_err(dev, "Failed to evict queue %d\n", 1130 q->properties.queue_id); 1131 goto out; 1132 } 1133 } 1134 } 1135 pdd->last_evict_timestamp = get_jiffies_64(); 1136 if (!dqm->dev->kfd->shared_resources.enable_mes) 1137 retval = execute_queues_cpsch(dqm, 1138 qpd->is_debug ? 1139 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES : 1140 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, 1141 USE_DEFAULT_GRACE_PERIOD); 1142 1143 out: 1144 dqm_unlock(dqm); 1145 return retval; 1146 } 1147 1148 static int restore_process_queues_nocpsch(struct device_queue_manager *dqm, 1149 struct qcm_process_device *qpd) 1150 { 1151 struct mm_struct *mm = NULL; 1152 struct queue *q; 1153 struct mqd_manager *mqd_mgr; 1154 struct kfd_process_device *pdd; 1155 uint64_t pd_base; 1156 uint64_t eviction_duration; 1157 int retval, ret = 0; 1158 1159 pdd = qpd_to_pdd(qpd); 1160 /* Retrieve PD base */ 1161 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); 1162 1163 dqm_lock(dqm); 1164 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */ 1165 goto out; 1166 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */ 1167 qpd->evicted--; 1168 goto out; 1169 } 1170 1171 pr_debug_ratelimited("Restoring PASID 0x%x queues\n", 1172 pdd->process->pasid); 1173 1174 /* Update PD Base in QPD */ 1175 qpd->page_table_base = pd_base; 1176 pr_debug("Updated PD address to 0x%llx\n", pd_base); 1177 1178 if (!list_empty(&qpd->queues_list)) { 1179 dqm->dev->kfd2kgd->set_vm_context_page_table_base( 1180 dqm->dev->adev, 1181 qpd->vmid, 1182 qpd->page_table_base); 1183 kfd_flush_tlb(pdd, TLB_FLUSH_LEGACY); 1184 } 1185 1186 /* Take a safe reference to the mm_struct, which may otherwise 1187 * disappear even while the kfd_process is still referenced. 1188 */ 1189 mm = get_task_mm(pdd->process->lead_thread); 1190 if (!mm) { 1191 ret = -EFAULT; 1192 goto out; 1193 } 1194 1195 /* Remove the eviction flags. Activate queues that are not 1196 * inactive for other reasons. 1197 */ 1198 list_for_each_entry(q, &qpd->queues_list, list) { 1199 q->properties.is_evicted = false; 1200 if (!QUEUE_IS_ACTIVE(q->properties)) 1201 continue; 1202 1203 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1204 q->properties.type)]; 1205 q->properties.is_active = true; 1206 increment_queue_count(dqm, qpd, q); 1207 1208 if (WARN_ONCE(!dqm->sched_running, "Restore when stopped\n")) 1209 continue; 1210 1211 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe, 1212 q->queue, &q->properties, mm); 1213 if (retval && !ret) 1214 /* Return the first error, but keep going to 1215 * maintain a consistent eviction state 1216 */ 1217 ret = retval; 1218 } 1219 qpd->evicted = 0; 1220 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp; 1221 atomic64_add(eviction_duration, &pdd->evict_duration_counter); 1222 out: 1223 if (mm) 1224 mmput(mm); 1225 dqm_unlock(dqm); 1226 return ret; 1227 } 1228 1229 static int restore_process_queues_cpsch(struct device_queue_manager *dqm, 1230 struct qcm_process_device *qpd) 1231 { 1232 struct queue *q; 1233 struct device *dev = dqm->dev->adev->dev; 1234 struct kfd_process_device *pdd; 1235 uint64_t eviction_duration; 1236 int retval = 0; 1237 1238 pdd = qpd_to_pdd(qpd); 1239 1240 dqm_lock(dqm); 1241 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */ 1242 goto out; 1243 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */ 1244 qpd->evicted--; 1245 goto out; 1246 } 1247 1248 /* The debugger creates processes that temporarily have not acquired 1249 * all VMs for all devices and has no VMs itself. 1250 * Skip queue restore on process restore. 1251 */ 1252 if (!pdd->drm_priv) 1253 goto vm_not_acquired; 1254 1255 pr_debug_ratelimited("Restoring PASID 0x%x queues\n", 1256 pdd->process->pasid); 1257 1258 /* Update PD Base in QPD */ 1259 qpd->page_table_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); 1260 pr_debug("Updated PD address to 0x%llx\n", qpd->page_table_base); 1261 1262 /* activate all active queues on the qpd */ 1263 list_for_each_entry(q, &qpd->queues_list, list) { 1264 q->properties.is_evicted = false; 1265 if (!QUEUE_IS_ACTIVE(q->properties)) 1266 continue; 1267 1268 q->properties.is_active = true; 1269 increment_queue_count(dqm, &pdd->qpd, q); 1270 1271 if (dqm->dev->kfd->shared_resources.enable_mes) { 1272 retval = add_queue_mes(dqm, q, qpd); 1273 if (retval) { 1274 dev_err(dev, "Failed to restore queue %d\n", 1275 q->properties.queue_id); 1276 goto out; 1277 } 1278 } 1279 } 1280 if (!dqm->dev->kfd->shared_resources.enable_mes) 1281 retval = execute_queues_cpsch(dqm, 1282 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); 1283 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp; 1284 atomic64_add(eviction_duration, &pdd->evict_duration_counter); 1285 vm_not_acquired: 1286 qpd->evicted = 0; 1287 out: 1288 dqm_unlock(dqm); 1289 return retval; 1290 } 1291 1292 static int register_process(struct device_queue_manager *dqm, 1293 struct qcm_process_device *qpd) 1294 { 1295 struct device_process_node *n; 1296 struct kfd_process_device *pdd; 1297 uint64_t pd_base; 1298 int retval; 1299 1300 n = kzalloc(sizeof(*n), GFP_KERNEL); 1301 if (!n) 1302 return -ENOMEM; 1303 1304 n->qpd = qpd; 1305 1306 pdd = qpd_to_pdd(qpd); 1307 /* Retrieve PD base */ 1308 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); 1309 1310 dqm_lock(dqm); 1311 list_add(&n->list, &dqm->queues); 1312 1313 /* Update PD Base in QPD */ 1314 qpd->page_table_base = pd_base; 1315 pr_debug("Updated PD address to 0x%llx\n", pd_base); 1316 1317 retval = dqm->asic_ops.update_qpd(dqm, qpd); 1318 1319 dqm->processes_count++; 1320 1321 dqm_unlock(dqm); 1322 1323 /* Outside the DQM lock because under the DQM lock we can't do 1324 * reclaim or take other locks that others hold while reclaiming. 1325 */ 1326 kfd_inc_compute_active(dqm->dev); 1327 1328 return retval; 1329 } 1330 1331 static int unregister_process(struct device_queue_manager *dqm, 1332 struct qcm_process_device *qpd) 1333 { 1334 int retval; 1335 struct device_process_node *cur, *next; 1336 1337 pr_debug("qpd->queues_list is %s\n", 1338 list_empty(&qpd->queues_list) ? "empty" : "not empty"); 1339 1340 retval = 0; 1341 dqm_lock(dqm); 1342 1343 list_for_each_entry_safe(cur, next, &dqm->queues, list) { 1344 if (qpd == cur->qpd) { 1345 list_del(&cur->list); 1346 kfree(cur); 1347 dqm->processes_count--; 1348 goto out; 1349 } 1350 } 1351 /* qpd not found in dqm list */ 1352 retval = 1; 1353 out: 1354 dqm_unlock(dqm); 1355 1356 /* Outside the DQM lock because under the DQM lock we can't do 1357 * reclaim or take other locks that others hold while reclaiming. 1358 */ 1359 if (!retval) 1360 kfd_dec_compute_active(dqm->dev); 1361 1362 return retval; 1363 } 1364 1365 static int 1366 set_pasid_vmid_mapping(struct device_queue_manager *dqm, u32 pasid, 1367 unsigned int vmid) 1368 { 1369 uint32_t xcc_mask = dqm->dev->xcc_mask; 1370 int xcc_id, ret; 1371 1372 for_each_inst(xcc_id, xcc_mask) { 1373 ret = dqm->dev->kfd2kgd->set_pasid_vmid_mapping( 1374 dqm->dev->adev, pasid, vmid, xcc_id); 1375 if (ret) 1376 break; 1377 } 1378 1379 return ret; 1380 } 1381 1382 static void init_interrupts(struct device_queue_manager *dqm) 1383 { 1384 uint32_t xcc_mask = dqm->dev->xcc_mask; 1385 unsigned int i, xcc_id; 1386 1387 for_each_inst(xcc_id, xcc_mask) { 1388 for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++) { 1389 if (is_pipe_enabled(dqm, 0, i)) { 1390 dqm->dev->kfd2kgd->init_interrupts( 1391 dqm->dev->adev, i, xcc_id); 1392 } 1393 } 1394 } 1395 } 1396 1397 static int initialize_nocpsch(struct device_queue_manager *dqm) 1398 { 1399 int pipe, queue; 1400 1401 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm)); 1402 1403 dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm), 1404 sizeof(unsigned int), GFP_KERNEL); 1405 if (!dqm->allocated_queues) 1406 return -ENOMEM; 1407 1408 mutex_init(&dqm->lock_hidden); 1409 INIT_LIST_HEAD(&dqm->queues); 1410 dqm->active_queue_count = dqm->next_pipe_to_allocate = 0; 1411 dqm->active_cp_queue_count = 0; 1412 dqm->gws_queue_count = 0; 1413 1414 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) { 1415 int pipe_offset = pipe * get_queues_per_pipe(dqm); 1416 1417 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) 1418 if (test_bit(pipe_offset + queue, 1419 dqm->dev->kfd->shared_resources.cp_queue_bitmap)) 1420 dqm->allocated_queues[pipe] |= 1 << queue; 1421 } 1422 1423 memset(dqm->vmid_pasid, 0, sizeof(dqm->vmid_pasid)); 1424 1425 init_sdma_bitmaps(dqm); 1426 1427 return 0; 1428 } 1429 1430 static void uninitialize(struct device_queue_manager *dqm) 1431 { 1432 int i; 1433 1434 WARN_ON(dqm->active_queue_count > 0 || dqm->processes_count > 0); 1435 1436 kfree(dqm->allocated_queues); 1437 for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++) 1438 kfree(dqm->mqd_mgrs[i]); 1439 mutex_destroy(&dqm->lock_hidden); 1440 } 1441 1442 static int start_nocpsch(struct device_queue_manager *dqm) 1443 { 1444 int r = 0; 1445 1446 pr_info("SW scheduler is used"); 1447 init_interrupts(dqm); 1448 1449 if (dqm->dev->adev->asic_type == CHIP_HAWAII) 1450 r = pm_init(&dqm->packet_mgr, dqm); 1451 if (!r) 1452 dqm->sched_running = true; 1453 1454 return r; 1455 } 1456 1457 static int stop_nocpsch(struct device_queue_manager *dqm) 1458 { 1459 dqm_lock(dqm); 1460 if (!dqm->sched_running) { 1461 dqm_unlock(dqm); 1462 return 0; 1463 } 1464 1465 if (dqm->dev->adev->asic_type == CHIP_HAWAII) 1466 pm_uninit(&dqm->packet_mgr); 1467 dqm->sched_running = false; 1468 dqm_unlock(dqm); 1469 1470 return 0; 1471 } 1472 1473 static int allocate_sdma_queue(struct device_queue_manager *dqm, 1474 struct queue *q, const uint32_t *restore_sdma_id) 1475 { 1476 struct device *dev = dqm->dev->adev->dev; 1477 int bit; 1478 1479 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) { 1480 if (bitmap_empty(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES)) { 1481 dev_err(dev, "No more SDMA queue to allocate\n"); 1482 return -ENOMEM; 1483 } 1484 1485 if (restore_sdma_id) { 1486 /* Re-use existing sdma_id */ 1487 if (!test_bit(*restore_sdma_id, dqm->sdma_bitmap)) { 1488 dev_err(dev, "SDMA queue already in use\n"); 1489 return -EBUSY; 1490 } 1491 clear_bit(*restore_sdma_id, dqm->sdma_bitmap); 1492 q->sdma_id = *restore_sdma_id; 1493 } else { 1494 /* Find first available sdma_id */ 1495 bit = find_first_bit(dqm->sdma_bitmap, 1496 get_num_sdma_queues(dqm)); 1497 clear_bit(bit, dqm->sdma_bitmap); 1498 q->sdma_id = bit; 1499 } 1500 1501 q->properties.sdma_engine_id = 1502 q->sdma_id % kfd_get_num_sdma_engines(dqm->dev); 1503 q->properties.sdma_queue_id = q->sdma_id / 1504 kfd_get_num_sdma_engines(dqm->dev); 1505 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1506 if (bitmap_empty(dqm->xgmi_sdma_bitmap, KFD_MAX_SDMA_QUEUES)) { 1507 dev_err(dev, "No more XGMI SDMA queue to allocate\n"); 1508 return -ENOMEM; 1509 } 1510 if (restore_sdma_id) { 1511 /* Re-use existing sdma_id */ 1512 if (!test_bit(*restore_sdma_id, dqm->xgmi_sdma_bitmap)) { 1513 dev_err(dev, "SDMA queue already in use\n"); 1514 return -EBUSY; 1515 } 1516 clear_bit(*restore_sdma_id, dqm->xgmi_sdma_bitmap); 1517 q->sdma_id = *restore_sdma_id; 1518 } else { 1519 bit = find_first_bit(dqm->xgmi_sdma_bitmap, 1520 get_num_xgmi_sdma_queues(dqm)); 1521 clear_bit(bit, dqm->xgmi_sdma_bitmap); 1522 q->sdma_id = bit; 1523 } 1524 /* sdma_engine_id is sdma id including 1525 * both PCIe-optimized SDMAs and XGMI- 1526 * optimized SDMAs. The calculation below 1527 * assumes the first N engines are always 1528 * PCIe-optimized ones 1529 */ 1530 q->properties.sdma_engine_id = 1531 kfd_get_num_sdma_engines(dqm->dev) + 1532 q->sdma_id % kfd_get_num_xgmi_sdma_engines(dqm->dev); 1533 q->properties.sdma_queue_id = q->sdma_id / 1534 kfd_get_num_xgmi_sdma_engines(dqm->dev); 1535 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) { 1536 int i, num_queues, num_engines, eng_offset = 0, start_engine; 1537 bool free_bit_found = false, is_xgmi = false; 1538 1539 if (q->properties.sdma_engine_id < kfd_get_num_sdma_engines(dqm->dev)) { 1540 num_queues = get_num_sdma_queues(dqm); 1541 num_engines = kfd_get_num_sdma_engines(dqm->dev); 1542 q->properties.type = KFD_QUEUE_TYPE_SDMA; 1543 } else { 1544 num_queues = get_num_xgmi_sdma_queues(dqm); 1545 num_engines = kfd_get_num_xgmi_sdma_engines(dqm->dev); 1546 eng_offset = kfd_get_num_sdma_engines(dqm->dev); 1547 q->properties.type = KFD_QUEUE_TYPE_SDMA_XGMI; 1548 is_xgmi = true; 1549 } 1550 1551 /* Scan available bit based on target engine ID. */ 1552 start_engine = q->properties.sdma_engine_id - eng_offset; 1553 for (i = start_engine; i < num_queues; i += num_engines) { 1554 1555 if (!test_bit(i, is_xgmi ? dqm->xgmi_sdma_bitmap : dqm->sdma_bitmap)) 1556 continue; 1557 1558 clear_bit(i, is_xgmi ? dqm->xgmi_sdma_bitmap : dqm->sdma_bitmap); 1559 q->sdma_id = i; 1560 q->properties.sdma_queue_id = q->sdma_id / num_engines; 1561 free_bit_found = true; 1562 break; 1563 } 1564 1565 if (!free_bit_found) { 1566 dev_err(dev, "No more SDMA queue to allocate for target ID %i\n", 1567 q->properties.sdma_engine_id); 1568 return -ENOMEM; 1569 } 1570 } 1571 1572 pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id); 1573 pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id); 1574 1575 return 0; 1576 } 1577 1578 static void deallocate_sdma_queue(struct device_queue_manager *dqm, 1579 struct queue *q) 1580 { 1581 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) { 1582 if (q->sdma_id >= get_num_sdma_queues(dqm)) 1583 return; 1584 set_bit(q->sdma_id, dqm->sdma_bitmap); 1585 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1586 if (q->sdma_id >= get_num_xgmi_sdma_queues(dqm)) 1587 return; 1588 set_bit(q->sdma_id, dqm->xgmi_sdma_bitmap); 1589 } 1590 } 1591 1592 /* 1593 * Device Queue Manager implementation for cp scheduler 1594 */ 1595 1596 static int set_sched_resources(struct device_queue_manager *dqm) 1597 { 1598 int i, mec; 1599 struct scheduling_resources res; 1600 struct device *dev = dqm->dev->adev->dev; 1601 1602 res.vmid_mask = dqm->dev->compute_vmid_bitmap; 1603 1604 res.queue_mask = 0; 1605 for (i = 0; i < AMDGPU_MAX_QUEUES; ++i) { 1606 mec = (i / dqm->dev->kfd->shared_resources.num_queue_per_pipe) 1607 / dqm->dev->kfd->shared_resources.num_pipe_per_mec; 1608 1609 if (!test_bit(i, dqm->dev->kfd->shared_resources.cp_queue_bitmap)) 1610 continue; 1611 1612 /* only acquire queues from the first MEC */ 1613 if (mec > 0) 1614 continue; 1615 1616 /* This situation may be hit in the future if a new HW 1617 * generation exposes more than 64 queues. If so, the 1618 * definition of res.queue_mask needs updating 1619 */ 1620 if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) { 1621 dev_err(dev, "Invalid queue enabled by amdgpu: %d\n", i); 1622 break; 1623 } 1624 1625 res.queue_mask |= 1ull 1626 << amdgpu_queue_mask_bit_to_set_resource_bit( 1627 dqm->dev->adev, i); 1628 } 1629 res.gws_mask = ~0ull; 1630 res.oac_mask = res.gds_heap_base = res.gds_heap_size = 0; 1631 1632 pr_debug("Scheduling resources:\n" 1633 "vmid mask: 0x%8X\n" 1634 "queue mask: 0x%8llX\n", 1635 res.vmid_mask, res.queue_mask); 1636 1637 return pm_send_set_resources(&dqm->packet_mgr, &res); 1638 } 1639 1640 static int initialize_cpsch(struct device_queue_manager *dqm) 1641 { 1642 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm)); 1643 1644 mutex_init(&dqm->lock_hidden); 1645 INIT_LIST_HEAD(&dqm->queues); 1646 dqm->active_queue_count = dqm->processes_count = 0; 1647 dqm->active_cp_queue_count = 0; 1648 dqm->gws_queue_count = 0; 1649 dqm->active_runlist = false; 1650 INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception); 1651 dqm->trap_debug_vmid = 0; 1652 1653 init_sdma_bitmaps(dqm); 1654 1655 if (dqm->dev->kfd2kgd->get_iq_wait_times) 1656 dqm->dev->kfd2kgd->get_iq_wait_times(dqm->dev->adev, 1657 &dqm->wait_times, 1658 ffs(dqm->dev->xcc_mask) - 1); 1659 return 0; 1660 } 1661 1662 static int start_cpsch(struct device_queue_manager *dqm) 1663 { 1664 struct device *dev = dqm->dev->adev->dev; 1665 int retval; 1666 1667 retval = 0; 1668 1669 dqm_lock(dqm); 1670 1671 if (!dqm->dev->kfd->shared_resources.enable_mes) { 1672 retval = pm_init(&dqm->packet_mgr, dqm); 1673 if (retval) 1674 goto fail_packet_manager_init; 1675 1676 retval = set_sched_resources(dqm); 1677 if (retval) 1678 goto fail_set_sched_resources; 1679 } 1680 pr_debug("Allocating fence memory\n"); 1681 1682 /* allocate fence memory on the gart */ 1683 retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr), 1684 &dqm->fence_mem); 1685 1686 if (retval) 1687 goto fail_allocate_vidmem; 1688 1689 dqm->fence_addr = (uint64_t *)dqm->fence_mem->cpu_ptr; 1690 dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr; 1691 1692 init_interrupts(dqm); 1693 1694 /* clear hang status when driver try to start the hw scheduler */ 1695 dqm->sched_running = true; 1696 1697 if (!dqm->dev->kfd->shared_resources.enable_mes) 1698 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); 1699 1700 /* Set CWSR grace period to 1x1000 cycle for GFX9.4.3 APU */ 1701 if (amdgpu_emu_mode == 0 && dqm->dev->adev->gmc.is_app_apu && 1702 (KFD_GC_VERSION(dqm->dev) == IP_VERSION(9, 4, 3))) { 1703 uint32_t reg_offset = 0; 1704 uint32_t grace_period = 1; 1705 1706 retval = pm_update_grace_period(&dqm->packet_mgr, 1707 grace_period); 1708 if (retval) 1709 dev_err(dev, "Setting grace timeout failed\n"); 1710 else if (dqm->dev->kfd2kgd->build_grace_period_packet_info) 1711 /* Update dqm->wait_times maintained in software */ 1712 dqm->dev->kfd2kgd->build_grace_period_packet_info( 1713 dqm->dev->adev, dqm->wait_times, 1714 grace_period, ®_offset, 1715 &dqm->wait_times); 1716 } 1717 1718 dqm_unlock(dqm); 1719 1720 return 0; 1721 fail_allocate_vidmem: 1722 fail_set_sched_resources: 1723 if (!dqm->dev->kfd->shared_resources.enable_mes) 1724 pm_uninit(&dqm->packet_mgr); 1725 fail_packet_manager_init: 1726 dqm_unlock(dqm); 1727 return retval; 1728 } 1729 1730 static int stop_cpsch(struct device_queue_manager *dqm) 1731 { 1732 dqm_lock(dqm); 1733 if (!dqm->sched_running) { 1734 dqm_unlock(dqm); 1735 return 0; 1736 } 1737 1738 if (!dqm->dev->kfd->shared_resources.enable_mes) 1739 unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD, false); 1740 else 1741 remove_all_queues_mes(dqm); 1742 1743 dqm->sched_running = false; 1744 1745 if (!dqm->dev->kfd->shared_resources.enable_mes) 1746 pm_release_ib(&dqm->packet_mgr); 1747 1748 kfd_gtt_sa_free(dqm->dev, dqm->fence_mem); 1749 if (!dqm->dev->kfd->shared_resources.enable_mes) 1750 pm_uninit(&dqm->packet_mgr); 1751 dqm_unlock(dqm); 1752 1753 return 0; 1754 } 1755 1756 static int create_kernel_queue_cpsch(struct device_queue_manager *dqm, 1757 struct kernel_queue *kq, 1758 struct qcm_process_device *qpd) 1759 { 1760 dqm_lock(dqm); 1761 if (dqm->total_queue_count >= max_num_of_queues_per_device) { 1762 pr_warn("Can't create new kernel queue because %d queues were already created\n", 1763 dqm->total_queue_count); 1764 dqm_unlock(dqm); 1765 return -EPERM; 1766 } 1767 1768 /* 1769 * Unconditionally increment this counter, regardless of the queue's 1770 * type or whether the queue is active. 1771 */ 1772 dqm->total_queue_count++; 1773 pr_debug("Total of %d queues are accountable so far\n", 1774 dqm->total_queue_count); 1775 1776 list_add(&kq->list, &qpd->priv_queue_list); 1777 increment_queue_count(dqm, qpd, kq->queue); 1778 qpd->is_debug = true; 1779 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, 1780 USE_DEFAULT_GRACE_PERIOD); 1781 dqm_unlock(dqm); 1782 1783 return 0; 1784 } 1785 1786 static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm, 1787 struct kernel_queue *kq, 1788 struct qcm_process_device *qpd) 1789 { 1790 dqm_lock(dqm); 1791 list_del(&kq->list); 1792 decrement_queue_count(dqm, qpd, kq->queue); 1793 qpd->is_debug = false; 1794 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 1795 USE_DEFAULT_GRACE_PERIOD); 1796 /* 1797 * Unconditionally decrement this counter, regardless of the queue's 1798 * type. 1799 */ 1800 dqm->total_queue_count--; 1801 pr_debug("Total of %d queues are accountable so far\n", 1802 dqm->total_queue_count); 1803 dqm_unlock(dqm); 1804 } 1805 1806 static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, 1807 struct qcm_process_device *qpd, 1808 const struct kfd_criu_queue_priv_data *qd, 1809 const void *restore_mqd, const void *restore_ctl_stack) 1810 { 1811 int retval; 1812 struct mqd_manager *mqd_mgr; 1813 1814 if (dqm->total_queue_count >= max_num_of_queues_per_device) { 1815 pr_warn("Can't create new usermode queue because %d queues were already created\n", 1816 dqm->total_queue_count); 1817 retval = -EPERM; 1818 goto out; 1819 } 1820 1821 if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 1822 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI || 1823 q->properties.type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) { 1824 dqm_lock(dqm); 1825 retval = allocate_sdma_queue(dqm, q, qd ? &qd->sdma_id : NULL); 1826 dqm_unlock(dqm); 1827 if (retval) 1828 goto out; 1829 } 1830 1831 retval = allocate_doorbell(qpd, q, qd ? &qd->doorbell_id : NULL); 1832 if (retval) 1833 goto out_deallocate_sdma_queue; 1834 1835 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1836 q->properties.type)]; 1837 1838 if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 1839 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 1840 dqm->asic_ops.init_sdma_vm(dqm, q, qpd); 1841 q->properties.tba_addr = qpd->tba_addr; 1842 q->properties.tma_addr = qpd->tma_addr; 1843 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties); 1844 if (!q->mqd_mem_obj) { 1845 retval = -ENOMEM; 1846 goto out_deallocate_doorbell; 1847 } 1848 1849 dqm_lock(dqm); 1850 /* 1851 * Eviction state logic: mark all queues as evicted, even ones 1852 * not currently active. Restoring inactive queues later only 1853 * updates the is_evicted flag but is a no-op otherwise. 1854 */ 1855 q->properties.is_evicted = !!qpd->evicted; 1856 q->properties.is_dbg_wa = qpd->pqm->process->debug_trap_enabled && 1857 kfd_dbg_has_cwsr_workaround(q->device); 1858 1859 if (qd) 1860 mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr, 1861 &q->properties, restore_mqd, restore_ctl_stack, 1862 qd->ctl_stack_size); 1863 else 1864 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, 1865 &q->gart_mqd_addr, &q->properties); 1866 1867 list_add(&q->list, &qpd->queues_list); 1868 qpd->queue_count++; 1869 1870 if (q->properties.is_active) { 1871 increment_queue_count(dqm, qpd, q); 1872 1873 if (!dqm->dev->kfd->shared_resources.enable_mes) 1874 retval = execute_queues_cpsch(dqm, 1875 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); 1876 else 1877 retval = add_queue_mes(dqm, q, qpd); 1878 if (retval) 1879 goto cleanup_queue; 1880 } 1881 1882 /* 1883 * Unconditionally increment this counter, regardless of the queue's 1884 * type or whether the queue is active. 1885 */ 1886 dqm->total_queue_count++; 1887 1888 pr_debug("Total of %d queues are accountable so far\n", 1889 dqm->total_queue_count); 1890 1891 dqm_unlock(dqm); 1892 return retval; 1893 1894 cleanup_queue: 1895 qpd->queue_count--; 1896 list_del(&q->list); 1897 if (q->properties.is_active) 1898 decrement_queue_count(dqm, qpd, q); 1899 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 1900 dqm_unlock(dqm); 1901 out_deallocate_doorbell: 1902 deallocate_doorbell(qpd, q); 1903 out_deallocate_sdma_queue: 1904 if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 1905 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1906 dqm_lock(dqm); 1907 deallocate_sdma_queue(dqm, q); 1908 dqm_unlock(dqm); 1909 } 1910 out: 1911 return retval; 1912 } 1913 1914 int amdkfd_fence_wait_timeout(struct device_queue_manager *dqm, 1915 uint64_t fence_value, 1916 unsigned int timeout_ms) 1917 { 1918 unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies; 1919 struct device *dev = dqm->dev->adev->dev; 1920 uint64_t *fence_addr = dqm->fence_addr; 1921 1922 while (*fence_addr != fence_value) { 1923 /* Fatal err detected, this response won't come */ 1924 if (amdgpu_amdkfd_is_fed(dqm->dev->adev)) 1925 return -EIO; 1926 1927 if (time_after(jiffies, end_jiffies)) { 1928 dev_err(dev, "qcm fence wait loop timeout expired\n"); 1929 /* In HWS case, this is used to halt the driver thread 1930 * in order not to mess up CP states before doing 1931 * scandumps for FW debugging. 1932 */ 1933 while (halt_if_hws_hang) 1934 schedule(); 1935 1936 return -ETIME; 1937 } 1938 schedule(); 1939 } 1940 1941 return 0; 1942 } 1943 1944 /* dqm->lock mutex has to be locked before calling this function */ 1945 static int map_queues_cpsch(struct device_queue_manager *dqm) 1946 { 1947 struct device *dev = dqm->dev->adev->dev; 1948 int retval; 1949 1950 if (!dqm->sched_running) 1951 return 0; 1952 if (dqm->active_queue_count <= 0 || dqm->processes_count <= 0) 1953 return 0; 1954 if (dqm->active_runlist) 1955 return 0; 1956 1957 retval = pm_send_runlist(&dqm->packet_mgr, &dqm->queues); 1958 pr_debug("%s sent runlist\n", __func__); 1959 if (retval) { 1960 dev_err(dev, "failed to execute runlist\n"); 1961 return retval; 1962 } 1963 dqm->active_runlist = true; 1964 1965 return retval; 1966 } 1967 1968 /* dqm->lock mutex has to be locked before calling this function */ 1969 static int unmap_queues_cpsch(struct device_queue_manager *dqm, 1970 enum kfd_unmap_queues_filter filter, 1971 uint32_t filter_param, 1972 uint32_t grace_period, 1973 bool reset) 1974 { 1975 struct device *dev = dqm->dev->adev->dev; 1976 struct mqd_manager *mqd_mgr; 1977 int retval; 1978 1979 if (!dqm->sched_running) 1980 return 0; 1981 if (!dqm->active_runlist) 1982 return 0; 1983 if (!down_read_trylock(&dqm->dev->adev->reset_domain->sem)) 1984 return -EIO; 1985 1986 if (grace_period != USE_DEFAULT_GRACE_PERIOD) { 1987 retval = pm_update_grace_period(&dqm->packet_mgr, grace_period); 1988 if (retval) 1989 goto out; 1990 } 1991 1992 retval = pm_send_unmap_queue(&dqm->packet_mgr, filter, filter_param, reset); 1993 if (retval) 1994 goto out; 1995 1996 *dqm->fence_addr = KFD_FENCE_INIT; 1997 pm_send_query_status(&dqm->packet_mgr, dqm->fence_gpu_addr, 1998 KFD_FENCE_COMPLETED); 1999 /* should be timed out */ 2000 retval = amdkfd_fence_wait_timeout(dqm, KFD_FENCE_COMPLETED, 2001 queue_preemption_timeout_ms); 2002 if (retval) { 2003 dev_err(dev, "The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n"); 2004 kfd_hws_hang(dqm); 2005 goto out; 2006 } 2007 2008 /* In the current MEC firmware implementation, if compute queue 2009 * doesn't response to the preemption request in time, HIQ will 2010 * abandon the unmap request without returning any timeout error 2011 * to driver. Instead, MEC firmware will log the doorbell of the 2012 * unresponding compute queue to HIQ.MQD.queue_doorbell_id fields. 2013 * To make sure the queue unmap was successful, driver need to 2014 * check those fields 2015 */ 2016 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]; 2017 if (mqd_mgr->check_preemption_failed(mqd_mgr, dqm->packet_mgr.priv_queue->queue->mqd)) { 2018 while (halt_if_hws_hang) 2019 schedule(); 2020 kfd_hws_hang(dqm); 2021 retval = -ETIME; 2022 goto out; 2023 } 2024 2025 /* We need to reset the grace period value for this device */ 2026 if (grace_period != USE_DEFAULT_GRACE_PERIOD) { 2027 if (pm_update_grace_period(&dqm->packet_mgr, 2028 USE_DEFAULT_GRACE_PERIOD)) 2029 dev_err(dev, "Failed to reset grace period\n"); 2030 } 2031 2032 pm_release_ib(&dqm->packet_mgr); 2033 dqm->active_runlist = false; 2034 2035 out: 2036 up_read(&dqm->dev->adev->reset_domain->sem); 2037 return retval; 2038 } 2039 2040 /* only for compute queue */ 2041 static int reset_queues_cpsch(struct device_queue_manager *dqm, 2042 uint16_t pasid) 2043 { 2044 int retval; 2045 2046 dqm_lock(dqm); 2047 2048 retval = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_BY_PASID, 2049 pasid, USE_DEFAULT_GRACE_PERIOD, true); 2050 2051 dqm_unlock(dqm); 2052 return retval; 2053 } 2054 2055 /* dqm->lock mutex has to be locked before calling this function */ 2056 static int execute_queues_cpsch(struct device_queue_manager *dqm, 2057 enum kfd_unmap_queues_filter filter, 2058 uint32_t filter_param, 2059 uint32_t grace_period) 2060 { 2061 int retval; 2062 2063 if (!down_read_trylock(&dqm->dev->adev->reset_domain->sem)) 2064 return -EIO; 2065 retval = unmap_queues_cpsch(dqm, filter, filter_param, grace_period, false); 2066 if (!retval) 2067 retval = map_queues_cpsch(dqm); 2068 up_read(&dqm->dev->adev->reset_domain->sem); 2069 return retval; 2070 } 2071 2072 static int wait_on_destroy_queue(struct device_queue_manager *dqm, 2073 struct queue *q) 2074 { 2075 struct kfd_process_device *pdd = kfd_get_process_device_data(q->device, 2076 q->process); 2077 int ret = 0; 2078 2079 if (pdd->qpd.is_debug) 2080 return ret; 2081 2082 q->properties.is_being_destroyed = true; 2083 2084 if (pdd->process->debug_trap_enabled && q->properties.is_suspended) { 2085 dqm_unlock(dqm); 2086 mutex_unlock(&q->process->mutex); 2087 ret = wait_event_interruptible(dqm->destroy_wait, 2088 !q->properties.is_suspended); 2089 2090 mutex_lock(&q->process->mutex); 2091 dqm_lock(dqm); 2092 } 2093 2094 return ret; 2095 } 2096 2097 static int destroy_queue_cpsch(struct device_queue_manager *dqm, 2098 struct qcm_process_device *qpd, 2099 struct queue *q) 2100 { 2101 int retval; 2102 struct mqd_manager *mqd_mgr; 2103 uint64_t sdma_val = 0; 2104 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 2105 struct device *dev = dqm->dev->adev->dev; 2106 2107 /* Get the SDMA queue stats */ 2108 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || 2109 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 2110 retval = read_sdma_queue_counter((uint64_t __user *)q->properties.read_ptr, 2111 &sdma_val); 2112 if (retval) 2113 dev_err(dev, "Failed to read SDMA queue counter for queue: %d\n", 2114 q->properties.queue_id); 2115 } 2116 2117 /* remove queue from list to prevent rescheduling after preemption */ 2118 dqm_lock(dqm); 2119 2120 retval = wait_on_destroy_queue(dqm, q); 2121 2122 if (retval) { 2123 dqm_unlock(dqm); 2124 return retval; 2125 } 2126 2127 if (qpd->is_debug) { 2128 /* 2129 * error, currently we do not allow to destroy a queue 2130 * of a currently debugged process 2131 */ 2132 retval = -EBUSY; 2133 goto failed_try_destroy_debugged_queue; 2134 2135 } 2136 2137 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 2138 q->properties.type)]; 2139 2140 deallocate_doorbell(qpd, q); 2141 2142 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || 2143 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 2144 deallocate_sdma_queue(dqm, q); 2145 pdd->sdma_past_activity_counter += sdma_val; 2146 } 2147 2148 list_del(&q->list); 2149 qpd->queue_count--; 2150 if (q->properties.is_active) { 2151 decrement_queue_count(dqm, qpd, q); 2152 if (!dqm->dev->kfd->shared_resources.enable_mes) { 2153 retval = execute_queues_cpsch(dqm, 2154 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, 2155 USE_DEFAULT_GRACE_PERIOD); 2156 if (retval == -ETIME) 2157 qpd->reset_wavefronts = true; 2158 } else { 2159 retval = remove_queue_mes(dqm, q, qpd); 2160 } 2161 } 2162 2163 /* 2164 * Unconditionally decrement this counter, regardless of the queue's 2165 * type 2166 */ 2167 dqm->total_queue_count--; 2168 pr_debug("Total of %d queues are accountable so far\n", 2169 dqm->total_queue_count); 2170 2171 dqm_unlock(dqm); 2172 2173 /* 2174 * Do free_mqd and raise delete event after dqm_unlock(dqm) to avoid 2175 * circular locking 2176 */ 2177 kfd_dbg_ev_raise(KFD_EC_MASK(EC_DEVICE_QUEUE_DELETE), 2178 qpd->pqm->process, q->device, 2179 -1, false, NULL, 0); 2180 2181 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 2182 2183 return retval; 2184 2185 failed_try_destroy_debugged_queue: 2186 2187 dqm_unlock(dqm); 2188 return retval; 2189 } 2190 2191 /* 2192 * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to 2193 * stay in user mode. 2194 */ 2195 #define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL 2196 /* APE1 limit is inclusive and 64K aligned. */ 2197 #define APE1_LIMIT_ALIGNMENT 0xFFFF 2198 2199 static bool set_cache_memory_policy(struct device_queue_manager *dqm, 2200 struct qcm_process_device *qpd, 2201 enum cache_policy default_policy, 2202 enum cache_policy alternate_policy, 2203 void __user *alternate_aperture_base, 2204 uint64_t alternate_aperture_size) 2205 { 2206 bool retval = true; 2207 2208 if (!dqm->asic_ops.set_cache_memory_policy) 2209 return retval; 2210 2211 dqm_lock(dqm); 2212 2213 if (alternate_aperture_size == 0) { 2214 /* base > limit disables APE1 */ 2215 qpd->sh_mem_ape1_base = 1; 2216 qpd->sh_mem_ape1_limit = 0; 2217 } else { 2218 /* 2219 * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]}, 2220 * SH_MEM_APE1_BASE[31:0], 0x0000 } 2221 * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]}, 2222 * SH_MEM_APE1_LIMIT[31:0], 0xFFFF } 2223 * Verify that the base and size parameters can be 2224 * represented in this format and convert them. 2225 * Additionally restrict APE1 to user-mode addresses. 2226 */ 2227 2228 uint64_t base = (uintptr_t)alternate_aperture_base; 2229 uint64_t limit = base + alternate_aperture_size - 1; 2230 2231 if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 || 2232 (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) { 2233 retval = false; 2234 goto out; 2235 } 2236 2237 qpd->sh_mem_ape1_base = base >> 16; 2238 qpd->sh_mem_ape1_limit = limit >> 16; 2239 } 2240 2241 retval = dqm->asic_ops.set_cache_memory_policy( 2242 dqm, 2243 qpd, 2244 default_policy, 2245 alternate_policy, 2246 alternate_aperture_base, 2247 alternate_aperture_size); 2248 2249 if ((dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0)) 2250 program_sh_mem_settings(dqm, qpd); 2251 2252 pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n", 2253 qpd->sh_mem_config, qpd->sh_mem_ape1_base, 2254 qpd->sh_mem_ape1_limit); 2255 2256 out: 2257 dqm_unlock(dqm); 2258 return retval; 2259 } 2260 2261 static int process_termination_nocpsch(struct device_queue_manager *dqm, 2262 struct qcm_process_device *qpd) 2263 { 2264 struct queue *q; 2265 struct device_process_node *cur, *next_dpn; 2266 int retval = 0; 2267 bool found = false; 2268 2269 dqm_lock(dqm); 2270 2271 /* Clear all user mode queues */ 2272 while (!list_empty(&qpd->queues_list)) { 2273 struct mqd_manager *mqd_mgr; 2274 int ret; 2275 2276 q = list_first_entry(&qpd->queues_list, struct queue, list); 2277 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 2278 q->properties.type)]; 2279 ret = destroy_queue_nocpsch_locked(dqm, qpd, q); 2280 if (ret) 2281 retval = ret; 2282 dqm_unlock(dqm); 2283 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 2284 dqm_lock(dqm); 2285 } 2286 2287 /* Unregister process */ 2288 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) { 2289 if (qpd == cur->qpd) { 2290 list_del(&cur->list); 2291 kfree(cur); 2292 dqm->processes_count--; 2293 found = true; 2294 break; 2295 } 2296 } 2297 2298 dqm_unlock(dqm); 2299 2300 /* Outside the DQM lock because under the DQM lock we can't do 2301 * reclaim or take other locks that others hold while reclaiming. 2302 */ 2303 if (found) 2304 kfd_dec_compute_active(dqm->dev); 2305 2306 return retval; 2307 } 2308 2309 static int get_wave_state(struct device_queue_manager *dqm, 2310 struct queue *q, 2311 void __user *ctl_stack, 2312 u32 *ctl_stack_used_size, 2313 u32 *save_area_used_size) 2314 { 2315 struct mqd_manager *mqd_mgr; 2316 2317 dqm_lock(dqm); 2318 2319 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP]; 2320 2321 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE || 2322 q->properties.is_active || !q->device->kfd->cwsr_enabled || 2323 !mqd_mgr->get_wave_state) { 2324 dqm_unlock(dqm); 2325 return -EINVAL; 2326 } 2327 2328 dqm_unlock(dqm); 2329 2330 /* 2331 * get_wave_state is outside the dqm lock to prevent circular locking 2332 * and the queue should be protected against destruction by the process 2333 * lock. 2334 */ 2335 return mqd_mgr->get_wave_state(mqd_mgr, q->mqd, &q->properties, 2336 ctl_stack, ctl_stack_used_size, save_area_used_size); 2337 } 2338 2339 static void get_queue_checkpoint_info(struct device_queue_manager *dqm, 2340 const struct queue *q, 2341 u32 *mqd_size, 2342 u32 *ctl_stack_size) 2343 { 2344 struct mqd_manager *mqd_mgr; 2345 enum KFD_MQD_TYPE mqd_type = 2346 get_mqd_type_from_queue_type(q->properties.type); 2347 2348 dqm_lock(dqm); 2349 mqd_mgr = dqm->mqd_mgrs[mqd_type]; 2350 *mqd_size = mqd_mgr->mqd_size; 2351 *ctl_stack_size = 0; 2352 2353 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE && mqd_mgr->get_checkpoint_info) 2354 mqd_mgr->get_checkpoint_info(mqd_mgr, q->mqd, ctl_stack_size); 2355 2356 dqm_unlock(dqm); 2357 } 2358 2359 static int checkpoint_mqd(struct device_queue_manager *dqm, 2360 const struct queue *q, 2361 void *mqd, 2362 void *ctl_stack) 2363 { 2364 struct mqd_manager *mqd_mgr; 2365 int r = 0; 2366 enum KFD_MQD_TYPE mqd_type = 2367 get_mqd_type_from_queue_type(q->properties.type); 2368 2369 dqm_lock(dqm); 2370 2371 if (q->properties.is_active || !q->device->kfd->cwsr_enabled) { 2372 r = -EINVAL; 2373 goto dqm_unlock; 2374 } 2375 2376 mqd_mgr = dqm->mqd_mgrs[mqd_type]; 2377 if (!mqd_mgr->checkpoint_mqd) { 2378 r = -EOPNOTSUPP; 2379 goto dqm_unlock; 2380 } 2381 2382 mqd_mgr->checkpoint_mqd(mqd_mgr, q->mqd, mqd, ctl_stack); 2383 2384 dqm_unlock: 2385 dqm_unlock(dqm); 2386 return r; 2387 } 2388 2389 static int process_termination_cpsch(struct device_queue_manager *dqm, 2390 struct qcm_process_device *qpd) 2391 { 2392 int retval; 2393 struct queue *q; 2394 struct device *dev = dqm->dev->adev->dev; 2395 struct kernel_queue *kq, *kq_next; 2396 struct mqd_manager *mqd_mgr; 2397 struct device_process_node *cur, *next_dpn; 2398 enum kfd_unmap_queues_filter filter = 2399 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES; 2400 bool found = false; 2401 2402 retval = 0; 2403 2404 dqm_lock(dqm); 2405 2406 /* Clean all kernel queues */ 2407 list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) { 2408 list_del(&kq->list); 2409 decrement_queue_count(dqm, qpd, kq->queue); 2410 qpd->is_debug = false; 2411 dqm->total_queue_count--; 2412 filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES; 2413 } 2414 2415 /* Clear all user mode queues */ 2416 list_for_each_entry(q, &qpd->queues_list, list) { 2417 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) 2418 deallocate_sdma_queue(dqm, q); 2419 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 2420 deallocate_sdma_queue(dqm, q); 2421 2422 if (q->properties.is_active) { 2423 decrement_queue_count(dqm, qpd, q); 2424 2425 if (dqm->dev->kfd->shared_resources.enable_mes) { 2426 retval = remove_queue_mes(dqm, q, qpd); 2427 if (retval) 2428 dev_err(dev, "Failed to remove queue %d\n", 2429 q->properties.queue_id); 2430 } 2431 } 2432 2433 dqm->total_queue_count--; 2434 } 2435 2436 /* Unregister process */ 2437 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) { 2438 if (qpd == cur->qpd) { 2439 list_del(&cur->list); 2440 kfree(cur); 2441 dqm->processes_count--; 2442 found = true; 2443 break; 2444 } 2445 } 2446 2447 if (!dqm->dev->kfd->shared_resources.enable_mes) 2448 retval = execute_queues_cpsch(dqm, filter, 0, USE_DEFAULT_GRACE_PERIOD); 2449 2450 if ((retval || qpd->reset_wavefronts) && 2451 down_read_trylock(&dqm->dev->adev->reset_domain->sem)) { 2452 pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm->dev); 2453 dbgdev_wave_reset_wavefronts(dqm->dev, qpd->pqm->process); 2454 qpd->reset_wavefronts = false; 2455 up_read(&dqm->dev->adev->reset_domain->sem); 2456 } 2457 2458 /* Lastly, free mqd resources. 2459 * Do free_mqd() after dqm_unlock to avoid circular locking. 2460 */ 2461 while (!list_empty(&qpd->queues_list)) { 2462 q = list_first_entry(&qpd->queues_list, struct queue, list); 2463 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 2464 q->properties.type)]; 2465 list_del(&q->list); 2466 qpd->queue_count--; 2467 dqm_unlock(dqm); 2468 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 2469 dqm_lock(dqm); 2470 } 2471 dqm_unlock(dqm); 2472 2473 /* Outside the DQM lock because under the DQM lock we can't do 2474 * reclaim or take other locks that others hold while reclaiming. 2475 */ 2476 if (found) 2477 kfd_dec_compute_active(dqm->dev); 2478 2479 return retval; 2480 } 2481 2482 static int init_mqd_managers(struct device_queue_manager *dqm) 2483 { 2484 int i, j; 2485 struct device *dev = dqm->dev->adev->dev; 2486 struct mqd_manager *mqd_mgr; 2487 2488 for (i = 0; i < KFD_MQD_TYPE_MAX; i++) { 2489 mqd_mgr = dqm->asic_ops.mqd_manager_init(i, dqm->dev); 2490 if (!mqd_mgr) { 2491 dev_err(dev, "mqd manager [%d] initialization failed\n", i); 2492 goto out_free; 2493 } 2494 dqm->mqd_mgrs[i] = mqd_mgr; 2495 } 2496 2497 return 0; 2498 2499 out_free: 2500 for (j = 0; j < i; j++) { 2501 kfree(dqm->mqd_mgrs[j]); 2502 dqm->mqd_mgrs[j] = NULL; 2503 } 2504 2505 return -ENOMEM; 2506 } 2507 2508 /* Allocate one hiq mqd (HWS) and all SDMA mqd in a continuous trunk*/ 2509 static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm) 2510 { 2511 int retval; 2512 struct kfd_node *dev = dqm->dev; 2513 struct kfd_mem_obj *mem_obj = &dqm->hiq_sdma_mqd; 2514 uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size * 2515 get_num_all_sdma_engines(dqm) * 2516 dev->kfd->device_info.num_sdma_queues_per_engine + 2517 (dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size * 2518 NUM_XCC(dqm->dev->xcc_mask)); 2519 2520 retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, size, 2521 &(mem_obj->gtt_mem), &(mem_obj->gpu_addr), 2522 (void *)&(mem_obj->cpu_ptr), false); 2523 2524 return retval; 2525 } 2526 2527 struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev) 2528 { 2529 struct device_queue_manager *dqm; 2530 2531 pr_debug("Loading device queue manager\n"); 2532 2533 dqm = kzalloc(sizeof(*dqm), GFP_KERNEL); 2534 if (!dqm) 2535 return NULL; 2536 2537 switch (dev->adev->asic_type) { 2538 /* HWS is not available on Hawaii. */ 2539 case CHIP_HAWAII: 2540 /* HWS depends on CWSR for timely dequeue. CWSR is not 2541 * available on Tonga. 2542 * 2543 * FIXME: This argument also applies to Kaveri. 2544 */ 2545 case CHIP_TONGA: 2546 dqm->sched_policy = KFD_SCHED_POLICY_NO_HWS; 2547 break; 2548 default: 2549 dqm->sched_policy = sched_policy; 2550 break; 2551 } 2552 2553 dqm->dev = dev; 2554 switch (dqm->sched_policy) { 2555 case KFD_SCHED_POLICY_HWS: 2556 case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION: 2557 /* initialize dqm for cp scheduling */ 2558 dqm->ops.create_queue = create_queue_cpsch; 2559 dqm->ops.initialize = initialize_cpsch; 2560 dqm->ops.start = start_cpsch; 2561 dqm->ops.stop = stop_cpsch; 2562 dqm->ops.destroy_queue = destroy_queue_cpsch; 2563 dqm->ops.update_queue = update_queue; 2564 dqm->ops.register_process = register_process; 2565 dqm->ops.unregister_process = unregister_process; 2566 dqm->ops.uninitialize = uninitialize; 2567 dqm->ops.create_kernel_queue = create_kernel_queue_cpsch; 2568 dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch; 2569 dqm->ops.set_cache_memory_policy = set_cache_memory_policy; 2570 dqm->ops.process_termination = process_termination_cpsch; 2571 dqm->ops.evict_process_queues = evict_process_queues_cpsch; 2572 dqm->ops.restore_process_queues = restore_process_queues_cpsch; 2573 dqm->ops.get_wave_state = get_wave_state; 2574 dqm->ops.reset_queues = reset_queues_cpsch; 2575 dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; 2576 dqm->ops.checkpoint_mqd = checkpoint_mqd; 2577 break; 2578 case KFD_SCHED_POLICY_NO_HWS: 2579 /* initialize dqm for no cp scheduling */ 2580 dqm->ops.start = start_nocpsch; 2581 dqm->ops.stop = stop_nocpsch; 2582 dqm->ops.create_queue = create_queue_nocpsch; 2583 dqm->ops.destroy_queue = destroy_queue_nocpsch; 2584 dqm->ops.update_queue = update_queue; 2585 dqm->ops.register_process = register_process; 2586 dqm->ops.unregister_process = unregister_process; 2587 dqm->ops.initialize = initialize_nocpsch; 2588 dqm->ops.uninitialize = uninitialize; 2589 dqm->ops.set_cache_memory_policy = set_cache_memory_policy; 2590 dqm->ops.process_termination = process_termination_nocpsch; 2591 dqm->ops.evict_process_queues = evict_process_queues_nocpsch; 2592 dqm->ops.restore_process_queues = 2593 restore_process_queues_nocpsch; 2594 dqm->ops.get_wave_state = get_wave_state; 2595 dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; 2596 dqm->ops.checkpoint_mqd = checkpoint_mqd; 2597 break; 2598 default: 2599 dev_err(dev->adev->dev, "Invalid scheduling policy %d\n", dqm->sched_policy); 2600 goto out_free; 2601 } 2602 2603 switch (dev->adev->asic_type) { 2604 case CHIP_KAVERI: 2605 case CHIP_HAWAII: 2606 device_queue_manager_init_cik(&dqm->asic_ops); 2607 break; 2608 2609 case CHIP_CARRIZO: 2610 case CHIP_TONGA: 2611 case CHIP_FIJI: 2612 case CHIP_POLARIS10: 2613 case CHIP_POLARIS11: 2614 case CHIP_POLARIS12: 2615 case CHIP_VEGAM: 2616 device_queue_manager_init_vi(&dqm->asic_ops); 2617 break; 2618 2619 default: 2620 if (KFD_GC_VERSION(dev) >= IP_VERSION(12, 0, 0)) 2621 device_queue_manager_init_v12(&dqm->asic_ops); 2622 else if (KFD_GC_VERSION(dev) >= IP_VERSION(11, 0, 0)) 2623 device_queue_manager_init_v11(&dqm->asic_ops); 2624 else if (KFD_GC_VERSION(dev) >= IP_VERSION(10, 1, 1)) 2625 device_queue_manager_init_v10(&dqm->asic_ops); 2626 else if (KFD_GC_VERSION(dev) >= IP_VERSION(9, 0, 1)) 2627 device_queue_manager_init_v9(&dqm->asic_ops); 2628 else { 2629 WARN(1, "Unexpected ASIC family %u", 2630 dev->adev->asic_type); 2631 goto out_free; 2632 } 2633 } 2634 2635 if (init_mqd_managers(dqm)) 2636 goto out_free; 2637 2638 if (!dev->kfd->shared_resources.enable_mes && allocate_hiq_sdma_mqd(dqm)) { 2639 dev_err(dev->adev->dev, "Failed to allocate hiq sdma mqd trunk buffer\n"); 2640 goto out_free; 2641 } 2642 2643 if (!dqm->ops.initialize(dqm)) { 2644 init_waitqueue_head(&dqm->destroy_wait); 2645 return dqm; 2646 } 2647 2648 out_free: 2649 kfree(dqm); 2650 return NULL; 2651 } 2652 2653 static void deallocate_hiq_sdma_mqd(struct kfd_node *dev, 2654 struct kfd_mem_obj *mqd) 2655 { 2656 WARN(!mqd, "No hiq sdma mqd trunk to free"); 2657 2658 amdgpu_amdkfd_free_gtt_mem(dev->adev, &mqd->gtt_mem); 2659 } 2660 2661 void device_queue_manager_uninit(struct device_queue_manager *dqm) 2662 { 2663 dqm->ops.stop(dqm); 2664 dqm->ops.uninitialize(dqm); 2665 if (!dqm->dev->kfd->shared_resources.enable_mes) 2666 deallocate_hiq_sdma_mqd(dqm->dev, &dqm->hiq_sdma_mqd); 2667 kfree(dqm); 2668 } 2669 2670 int kfd_dqm_evict_pasid(struct device_queue_manager *dqm, u32 pasid) 2671 { 2672 struct kfd_process_device *pdd; 2673 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); 2674 int ret = 0; 2675 2676 if (!p) 2677 return -EINVAL; 2678 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 2679 pdd = kfd_get_process_device_data(dqm->dev, p); 2680 if (pdd) 2681 ret = dqm->ops.evict_process_queues(dqm, &pdd->qpd); 2682 kfd_unref_process(p); 2683 2684 return ret; 2685 } 2686 2687 static void kfd_process_hw_exception(struct work_struct *work) 2688 { 2689 struct device_queue_manager *dqm = container_of(work, 2690 struct device_queue_manager, hw_exception_work); 2691 amdgpu_amdkfd_gpu_reset(dqm->dev->adev); 2692 } 2693 2694 int reserve_debug_trap_vmid(struct device_queue_manager *dqm, 2695 struct qcm_process_device *qpd) 2696 { 2697 int r; 2698 struct device *dev = dqm->dev->adev->dev; 2699 int updated_vmid_mask; 2700 2701 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 2702 dev_err(dev, "Unsupported on sched_policy: %i\n", dqm->sched_policy); 2703 return -EINVAL; 2704 } 2705 2706 dqm_lock(dqm); 2707 2708 if (dqm->trap_debug_vmid != 0) { 2709 dev_err(dev, "Trap debug id already reserved\n"); 2710 r = -EBUSY; 2711 goto out_unlock; 2712 } 2713 2714 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 2715 USE_DEFAULT_GRACE_PERIOD, false); 2716 if (r) 2717 goto out_unlock; 2718 2719 updated_vmid_mask = dqm->dev->kfd->shared_resources.compute_vmid_bitmap; 2720 updated_vmid_mask &= ~(1 << dqm->dev->vm_info.last_vmid_kfd); 2721 2722 dqm->dev->kfd->shared_resources.compute_vmid_bitmap = updated_vmid_mask; 2723 dqm->trap_debug_vmid = dqm->dev->vm_info.last_vmid_kfd; 2724 r = set_sched_resources(dqm); 2725 if (r) 2726 goto out_unlock; 2727 2728 r = map_queues_cpsch(dqm); 2729 if (r) 2730 goto out_unlock; 2731 2732 pr_debug("Reserved VMID for trap debug: %i\n", dqm->trap_debug_vmid); 2733 2734 out_unlock: 2735 dqm_unlock(dqm); 2736 return r; 2737 } 2738 2739 /* 2740 * Releases vmid for the trap debugger 2741 */ 2742 int release_debug_trap_vmid(struct device_queue_manager *dqm, 2743 struct qcm_process_device *qpd) 2744 { 2745 struct device *dev = dqm->dev->adev->dev; 2746 int r; 2747 int updated_vmid_mask; 2748 uint32_t trap_debug_vmid; 2749 2750 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 2751 dev_err(dev, "Unsupported on sched_policy: %i\n", dqm->sched_policy); 2752 return -EINVAL; 2753 } 2754 2755 dqm_lock(dqm); 2756 trap_debug_vmid = dqm->trap_debug_vmid; 2757 if (dqm->trap_debug_vmid == 0) { 2758 dev_err(dev, "Trap debug id is not reserved\n"); 2759 r = -EINVAL; 2760 goto out_unlock; 2761 } 2762 2763 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 2764 USE_DEFAULT_GRACE_PERIOD, false); 2765 if (r) 2766 goto out_unlock; 2767 2768 updated_vmid_mask = dqm->dev->kfd->shared_resources.compute_vmid_bitmap; 2769 updated_vmid_mask |= (1 << dqm->dev->vm_info.last_vmid_kfd); 2770 2771 dqm->dev->kfd->shared_resources.compute_vmid_bitmap = updated_vmid_mask; 2772 dqm->trap_debug_vmid = 0; 2773 r = set_sched_resources(dqm); 2774 if (r) 2775 goto out_unlock; 2776 2777 r = map_queues_cpsch(dqm); 2778 if (r) 2779 goto out_unlock; 2780 2781 pr_debug("Released VMID for trap debug: %i\n", trap_debug_vmid); 2782 2783 out_unlock: 2784 dqm_unlock(dqm); 2785 return r; 2786 } 2787 2788 #define QUEUE_NOT_FOUND -1 2789 /* invalidate queue operation in array */ 2790 static void q_array_invalidate(uint32_t num_queues, uint32_t *queue_ids) 2791 { 2792 int i; 2793 2794 for (i = 0; i < num_queues; i++) 2795 queue_ids[i] |= KFD_DBG_QUEUE_INVALID_MASK; 2796 } 2797 2798 /* find queue index in array */ 2799 static int q_array_get_index(unsigned int queue_id, 2800 uint32_t num_queues, 2801 uint32_t *queue_ids) 2802 { 2803 int i; 2804 2805 for (i = 0; i < num_queues; i++) 2806 if (queue_id == (queue_ids[i] & ~KFD_DBG_QUEUE_INVALID_MASK)) 2807 return i; 2808 2809 return QUEUE_NOT_FOUND; 2810 } 2811 2812 struct copy_context_work_handler_workarea { 2813 struct work_struct copy_context_work; 2814 struct kfd_process *p; 2815 }; 2816 2817 static void copy_context_work_handler (struct work_struct *work) 2818 { 2819 struct copy_context_work_handler_workarea *workarea; 2820 struct mqd_manager *mqd_mgr; 2821 struct queue *q; 2822 struct mm_struct *mm; 2823 struct kfd_process *p; 2824 uint32_t tmp_ctl_stack_used_size, tmp_save_area_used_size; 2825 int i; 2826 2827 workarea = container_of(work, 2828 struct copy_context_work_handler_workarea, 2829 copy_context_work); 2830 2831 p = workarea->p; 2832 mm = get_task_mm(p->lead_thread); 2833 2834 if (!mm) 2835 return; 2836 2837 kthread_use_mm(mm); 2838 for (i = 0; i < p->n_pdds; i++) { 2839 struct kfd_process_device *pdd = p->pdds[i]; 2840 struct device_queue_manager *dqm = pdd->dev->dqm; 2841 struct qcm_process_device *qpd = &pdd->qpd; 2842 2843 list_for_each_entry(q, &qpd->queues_list, list) { 2844 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP]; 2845 2846 /* We ignore the return value from get_wave_state 2847 * because 2848 * i) right now, it always returns 0, and 2849 * ii) if we hit an error, we would continue to the 2850 * next queue anyway. 2851 */ 2852 mqd_mgr->get_wave_state(mqd_mgr, 2853 q->mqd, 2854 &q->properties, 2855 (void __user *) q->properties.ctx_save_restore_area_address, 2856 &tmp_ctl_stack_used_size, 2857 &tmp_save_area_used_size); 2858 } 2859 } 2860 kthread_unuse_mm(mm); 2861 mmput(mm); 2862 } 2863 2864 static uint32_t *get_queue_ids(uint32_t num_queues, uint32_t *usr_queue_id_array) 2865 { 2866 size_t array_size = num_queues * sizeof(uint32_t); 2867 2868 if (!usr_queue_id_array) 2869 return NULL; 2870 2871 return memdup_user(usr_queue_id_array, array_size); 2872 } 2873 2874 int resume_queues(struct kfd_process *p, 2875 uint32_t num_queues, 2876 uint32_t *usr_queue_id_array) 2877 { 2878 uint32_t *queue_ids = NULL; 2879 int total_resumed = 0; 2880 int i; 2881 2882 if (usr_queue_id_array) { 2883 queue_ids = get_queue_ids(num_queues, usr_queue_id_array); 2884 2885 if (IS_ERR(queue_ids)) 2886 return PTR_ERR(queue_ids); 2887 2888 /* mask all queues as invalid. unmask per successful request */ 2889 q_array_invalidate(num_queues, queue_ids); 2890 } 2891 2892 for (i = 0; i < p->n_pdds; i++) { 2893 struct kfd_process_device *pdd = p->pdds[i]; 2894 struct device_queue_manager *dqm = pdd->dev->dqm; 2895 struct device *dev = dqm->dev->adev->dev; 2896 struct qcm_process_device *qpd = &pdd->qpd; 2897 struct queue *q; 2898 int r, per_device_resumed = 0; 2899 2900 dqm_lock(dqm); 2901 2902 /* unmask queues that resume or already resumed as valid */ 2903 list_for_each_entry(q, &qpd->queues_list, list) { 2904 int q_idx = QUEUE_NOT_FOUND; 2905 2906 if (queue_ids) 2907 q_idx = q_array_get_index( 2908 q->properties.queue_id, 2909 num_queues, 2910 queue_ids); 2911 2912 if (!queue_ids || q_idx != QUEUE_NOT_FOUND) { 2913 int err = resume_single_queue(dqm, &pdd->qpd, q); 2914 2915 if (queue_ids) { 2916 if (!err) { 2917 queue_ids[q_idx] &= 2918 ~KFD_DBG_QUEUE_INVALID_MASK; 2919 } else { 2920 queue_ids[q_idx] |= 2921 KFD_DBG_QUEUE_ERROR_MASK; 2922 break; 2923 } 2924 } 2925 2926 if (dqm->dev->kfd->shared_resources.enable_mes) { 2927 wake_up_all(&dqm->destroy_wait); 2928 if (!err) 2929 total_resumed++; 2930 } else { 2931 per_device_resumed++; 2932 } 2933 } 2934 } 2935 2936 if (!per_device_resumed) { 2937 dqm_unlock(dqm); 2938 continue; 2939 } 2940 2941 r = execute_queues_cpsch(dqm, 2942 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 2943 0, 2944 USE_DEFAULT_GRACE_PERIOD); 2945 if (r) { 2946 dev_err(dev, "Failed to resume process queues\n"); 2947 if (queue_ids) { 2948 list_for_each_entry(q, &qpd->queues_list, list) { 2949 int q_idx = q_array_get_index( 2950 q->properties.queue_id, 2951 num_queues, 2952 queue_ids); 2953 2954 /* mask queue as error on resume fail */ 2955 if (q_idx != QUEUE_NOT_FOUND) 2956 queue_ids[q_idx] |= 2957 KFD_DBG_QUEUE_ERROR_MASK; 2958 } 2959 } 2960 } else { 2961 wake_up_all(&dqm->destroy_wait); 2962 total_resumed += per_device_resumed; 2963 } 2964 2965 dqm_unlock(dqm); 2966 } 2967 2968 if (queue_ids) { 2969 if (copy_to_user((void __user *)usr_queue_id_array, queue_ids, 2970 num_queues * sizeof(uint32_t))) 2971 pr_err("copy_to_user failed on queue resume\n"); 2972 2973 kfree(queue_ids); 2974 } 2975 2976 return total_resumed; 2977 } 2978 2979 int suspend_queues(struct kfd_process *p, 2980 uint32_t num_queues, 2981 uint32_t grace_period, 2982 uint64_t exception_clear_mask, 2983 uint32_t *usr_queue_id_array) 2984 { 2985 uint32_t *queue_ids = get_queue_ids(num_queues, usr_queue_id_array); 2986 int total_suspended = 0; 2987 int i; 2988 2989 if (IS_ERR(queue_ids)) 2990 return PTR_ERR(queue_ids); 2991 2992 /* mask all queues as invalid. umask on successful request */ 2993 q_array_invalidate(num_queues, queue_ids); 2994 2995 for (i = 0; i < p->n_pdds; i++) { 2996 struct kfd_process_device *pdd = p->pdds[i]; 2997 struct device_queue_manager *dqm = pdd->dev->dqm; 2998 struct device *dev = dqm->dev->adev->dev; 2999 struct qcm_process_device *qpd = &pdd->qpd; 3000 struct queue *q; 3001 int r, per_device_suspended = 0; 3002 3003 mutex_lock(&p->event_mutex); 3004 dqm_lock(dqm); 3005 3006 /* unmask queues that suspend or already suspended */ 3007 list_for_each_entry(q, &qpd->queues_list, list) { 3008 int q_idx = q_array_get_index(q->properties.queue_id, 3009 num_queues, 3010 queue_ids); 3011 3012 if (q_idx != QUEUE_NOT_FOUND) { 3013 int err = suspend_single_queue(dqm, pdd, q); 3014 bool is_mes = dqm->dev->kfd->shared_resources.enable_mes; 3015 3016 if (!err) { 3017 queue_ids[q_idx] &= ~KFD_DBG_QUEUE_INVALID_MASK; 3018 if (exception_clear_mask && is_mes) 3019 q->properties.exception_status &= 3020 ~exception_clear_mask; 3021 3022 if (is_mes) 3023 total_suspended++; 3024 else 3025 per_device_suspended++; 3026 } else if (err != -EBUSY) { 3027 r = err; 3028 queue_ids[q_idx] |= KFD_DBG_QUEUE_ERROR_MASK; 3029 break; 3030 } 3031 } 3032 } 3033 3034 if (!per_device_suspended) { 3035 dqm_unlock(dqm); 3036 mutex_unlock(&p->event_mutex); 3037 if (total_suspended) 3038 amdgpu_amdkfd_debug_mem_fence(dqm->dev->adev); 3039 continue; 3040 } 3041 3042 r = execute_queues_cpsch(dqm, 3043 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, 3044 grace_period); 3045 3046 if (r) 3047 dev_err(dev, "Failed to suspend process queues.\n"); 3048 else 3049 total_suspended += per_device_suspended; 3050 3051 list_for_each_entry(q, &qpd->queues_list, list) { 3052 int q_idx = q_array_get_index(q->properties.queue_id, 3053 num_queues, queue_ids); 3054 3055 if (q_idx == QUEUE_NOT_FOUND) 3056 continue; 3057 3058 /* mask queue as error on suspend fail */ 3059 if (r) 3060 queue_ids[q_idx] |= KFD_DBG_QUEUE_ERROR_MASK; 3061 else if (exception_clear_mask) 3062 q->properties.exception_status &= 3063 ~exception_clear_mask; 3064 } 3065 3066 dqm_unlock(dqm); 3067 mutex_unlock(&p->event_mutex); 3068 amdgpu_device_flush_hdp(dqm->dev->adev, NULL); 3069 } 3070 3071 if (total_suspended) { 3072 struct copy_context_work_handler_workarea copy_context_worker; 3073 3074 INIT_WORK_ONSTACK( 3075 ©_context_worker.copy_context_work, 3076 copy_context_work_handler); 3077 3078 copy_context_worker.p = p; 3079 3080 schedule_work(©_context_worker.copy_context_work); 3081 3082 3083 flush_work(©_context_worker.copy_context_work); 3084 destroy_work_on_stack(©_context_worker.copy_context_work); 3085 } 3086 3087 if (copy_to_user((void __user *)usr_queue_id_array, queue_ids, 3088 num_queues * sizeof(uint32_t))) 3089 pr_err("copy_to_user failed on queue suspend\n"); 3090 3091 kfree(queue_ids); 3092 3093 return total_suspended; 3094 } 3095 3096 static uint32_t set_queue_type_for_user(struct queue_properties *q_props) 3097 { 3098 switch (q_props->type) { 3099 case KFD_QUEUE_TYPE_COMPUTE: 3100 return q_props->format == KFD_QUEUE_FORMAT_PM4 3101 ? KFD_IOC_QUEUE_TYPE_COMPUTE 3102 : KFD_IOC_QUEUE_TYPE_COMPUTE_AQL; 3103 case KFD_QUEUE_TYPE_SDMA: 3104 return KFD_IOC_QUEUE_TYPE_SDMA; 3105 case KFD_QUEUE_TYPE_SDMA_XGMI: 3106 return KFD_IOC_QUEUE_TYPE_SDMA_XGMI; 3107 default: 3108 WARN_ONCE(true, "queue type not recognized!"); 3109 return 0xffffffff; 3110 }; 3111 } 3112 3113 void set_queue_snapshot_entry(struct queue *q, 3114 uint64_t exception_clear_mask, 3115 struct kfd_queue_snapshot_entry *qss_entry) 3116 { 3117 qss_entry->ring_base_address = q->properties.queue_address; 3118 qss_entry->write_pointer_address = (uint64_t)q->properties.write_ptr; 3119 qss_entry->read_pointer_address = (uint64_t)q->properties.read_ptr; 3120 qss_entry->ctx_save_restore_address = 3121 q->properties.ctx_save_restore_area_address; 3122 qss_entry->ctx_save_restore_area_size = 3123 q->properties.ctx_save_restore_area_size; 3124 qss_entry->exception_status = q->properties.exception_status; 3125 qss_entry->queue_id = q->properties.queue_id; 3126 qss_entry->gpu_id = q->device->id; 3127 qss_entry->ring_size = (uint32_t)q->properties.queue_size; 3128 qss_entry->queue_type = set_queue_type_for_user(&q->properties); 3129 q->properties.exception_status &= ~exception_clear_mask; 3130 } 3131 3132 int debug_lock_and_unmap(struct device_queue_manager *dqm) 3133 { 3134 struct device *dev = dqm->dev->adev->dev; 3135 int r; 3136 3137 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 3138 dev_err(dev, "Unsupported on sched_policy: %i\n", dqm->sched_policy); 3139 return -EINVAL; 3140 } 3141 3142 if (!kfd_dbg_is_per_vmid_supported(dqm->dev)) 3143 return 0; 3144 3145 dqm_lock(dqm); 3146 3147 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 0, false); 3148 if (r) 3149 dqm_unlock(dqm); 3150 3151 return r; 3152 } 3153 3154 int debug_map_and_unlock(struct device_queue_manager *dqm) 3155 { 3156 struct device *dev = dqm->dev->adev->dev; 3157 int r; 3158 3159 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 3160 dev_err(dev, "Unsupported on sched_policy: %i\n", dqm->sched_policy); 3161 return -EINVAL; 3162 } 3163 3164 if (!kfd_dbg_is_per_vmid_supported(dqm->dev)) 3165 return 0; 3166 3167 r = map_queues_cpsch(dqm); 3168 3169 dqm_unlock(dqm); 3170 3171 return r; 3172 } 3173 3174 int debug_refresh_runlist(struct device_queue_manager *dqm) 3175 { 3176 int r = debug_lock_and_unmap(dqm); 3177 3178 if (r) 3179 return r; 3180 3181 return debug_map_and_unlock(dqm); 3182 } 3183 3184 #if defined(CONFIG_DEBUG_FS) 3185 3186 static void seq_reg_dump(struct seq_file *m, 3187 uint32_t (*dump)[2], uint32_t n_regs) 3188 { 3189 uint32_t i, count; 3190 3191 for (i = 0, count = 0; i < n_regs; i++) { 3192 if (count == 0 || 3193 dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) { 3194 seq_printf(m, "%s %08x: %08x", 3195 i ? "\n" : "", 3196 dump[i][0], dump[i][1]); 3197 count = 7; 3198 } else { 3199 seq_printf(m, " %08x", dump[i][1]); 3200 count--; 3201 } 3202 } 3203 3204 seq_puts(m, "\n"); 3205 } 3206 3207 int dqm_debugfs_hqds(struct seq_file *m, void *data) 3208 { 3209 struct device_queue_manager *dqm = data; 3210 uint32_t xcc_mask = dqm->dev->xcc_mask; 3211 uint32_t (*dump)[2], n_regs; 3212 int pipe, queue; 3213 int r = 0, xcc_id; 3214 uint32_t sdma_engine_start; 3215 3216 if (!dqm->sched_running) { 3217 seq_puts(m, " Device is stopped\n"); 3218 return 0; 3219 } 3220 3221 for_each_inst(xcc_id, xcc_mask) { 3222 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->adev, 3223 KFD_CIK_HIQ_PIPE, 3224 KFD_CIK_HIQ_QUEUE, &dump, 3225 &n_regs, xcc_id); 3226 if (!r) { 3227 seq_printf( 3228 m, 3229 " Inst %d, HIQ on MEC %d Pipe %d Queue %d\n", 3230 xcc_id, 3231 KFD_CIK_HIQ_PIPE / get_pipes_per_mec(dqm) + 1, 3232 KFD_CIK_HIQ_PIPE % get_pipes_per_mec(dqm), 3233 KFD_CIK_HIQ_QUEUE); 3234 seq_reg_dump(m, dump, n_regs); 3235 3236 kfree(dump); 3237 } 3238 3239 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) { 3240 int pipe_offset = pipe * get_queues_per_pipe(dqm); 3241 3242 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) { 3243 if (!test_bit(pipe_offset + queue, 3244 dqm->dev->kfd->shared_resources.cp_queue_bitmap)) 3245 continue; 3246 3247 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->adev, 3248 pipe, queue, 3249 &dump, &n_regs, 3250 xcc_id); 3251 if (r) 3252 break; 3253 3254 seq_printf(m, 3255 " Inst %d, CP Pipe %d, Queue %d\n", 3256 xcc_id, pipe, queue); 3257 seq_reg_dump(m, dump, n_regs); 3258 3259 kfree(dump); 3260 } 3261 } 3262 } 3263 3264 sdma_engine_start = dqm->dev->node_id * get_num_all_sdma_engines(dqm); 3265 for (pipe = sdma_engine_start; 3266 pipe < (sdma_engine_start + get_num_all_sdma_engines(dqm)); 3267 pipe++) { 3268 for (queue = 0; 3269 queue < dqm->dev->kfd->device_info.num_sdma_queues_per_engine; 3270 queue++) { 3271 r = dqm->dev->kfd2kgd->hqd_sdma_dump( 3272 dqm->dev->adev, pipe, queue, &dump, &n_regs); 3273 if (r) 3274 break; 3275 3276 seq_printf(m, " SDMA Engine %d, RLC %d\n", 3277 pipe, queue); 3278 seq_reg_dump(m, dump, n_regs); 3279 3280 kfree(dump); 3281 } 3282 } 3283 3284 return r; 3285 } 3286 3287 int dqm_debugfs_hang_hws(struct device_queue_manager *dqm) 3288 { 3289 int r = 0; 3290 3291 dqm_lock(dqm); 3292 r = pm_debugfs_hang_hws(&dqm->packet_mgr); 3293 if (r) { 3294 dqm_unlock(dqm); 3295 return r; 3296 } 3297 dqm->active_runlist = true; 3298 r = execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 3299 0, USE_DEFAULT_GRACE_PERIOD); 3300 dqm_unlock(dqm); 3301 3302 return r; 3303 } 3304 3305 #endif 3306