1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_11_0_0_offset.h" 34 #include "gc/gc_11_0_0_sh_mask.h" 35 #include "gc/gc_11_0_0_default.h" 36 #include "hdp/hdp_6_0_0_offset.h" 37 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 38 39 #include "soc15_common.h" 40 #include "soc15.h" 41 #include "sdma_v6_0_0_pkt_open.h" 42 #include "nbio_v4_3.h" 43 #include "sdma_common.h" 44 #include "sdma_v6_0.h" 45 #include "v11_structs.h" 46 47 MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin"); 48 MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin"); 49 MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin"); 50 MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin"); 51 MODULE_FIRMWARE("amdgpu/sdma_6_1_0.bin"); 52 53 #define SDMA1_REG_OFFSET 0x600 54 #define SDMA0_HYP_DEC_REG_START 0x5880 55 #define SDMA0_HYP_DEC_REG_END 0x589a 56 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 57 58 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev); 59 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev); 60 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev); 61 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev); 62 static int sdma_v6_0_start(struct amdgpu_device *adev); 63 64 static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 65 { 66 u32 base; 67 68 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 69 internal_offset <= SDMA0_HYP_DEC_REG_END) { 70 base = adev->reg_offset[GC_HWIP][0][1]; 71 if (instance != 0) 72 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 73 } else { 74 base = adev->reg_offset[GC_HWIP][0][0]; 75 if (instance == 1) 76 internal_offset += SDMA1_REG_OFFSET; 77 } 78 79 return base + internal_offset; 80 } 81 82 static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring) 83 { 84 unsigned ret; 85 86 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE)); 87 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 88 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 89 amdgpu_ring_write(ring, 1); 90 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ 91 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 92 93 return ret; 94 } 95 96 static void sdma_v6_0_ring_patch_cond_exec(struct amdgpu_ring *ring, 97 unsigned offset) 98 { 99 unsigned cur; 100 101 BUG_ON(offset > ring->buf_mask); 102 BUG_ON(ring->ring[offset] != 0x55aa55aa); 103 104 cur = (ring->wptr - 1) & ring->buf_mask; 105 if (cur > offset) 106 ring->ring[offset] = cur - offset; 107 else 108 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 109 } 110 111 /** 112 * sdma_v6_0_ring_get_rptr - get the current read pointer 113 * 114 * @ring: amdgpu ring pointer 115 * 116 * Get the current rptr from the hardware. 117 */ 118 static uint64_t sdma_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 119 { 120 u64 *rptr; 121 122 /* XXX check if swapping is necessary on BE */ 123 rptr = (u64 *)ring->rptr_cpu_addr; 124 125 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 126 return ((*rptr) >> 2); 127 } 128 129 /** 130 * sdma_v6_0_ring_get_wptr - get the current write pointer 131 * 132 * @ring: amdgpu ring pointer 133 * 134 * Get the current wptr from the hardware. 135 */ 136 static uint64_t sdma_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 137 { 138 u64 wptr = 0; 139 140 if (ring->use_doorbell) { 141 /* XXX check if swapping is necessary on BE */ 142 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 143 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 144 } 145 146 return wptr >> 2; 147 } 148 149 /** 150 * sdma_v6_0_ring_set_wptr - commit the write pointer 151 * 152 * @ring: amdgpu ring pointer 153 * 154 * Write the wptr back to the hardware. 155 */ 156 static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring) 157 { 158 struct amdgpu_device *adev = ring->adev; 159 160 if (ring->use_doorbell) { 161 DRM_DEBUG("Using doorbell -- " 162 "wptr_offs == 0x%08x " 163 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 164 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 165 ring->wptr_offs, 166 lower_32_bits(ring->wptr << 2), 167 upper_32_bits(ring->wptr << 2)); 168 /* XXX check if swapping is necessary on BE */ 169 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 170 ring->wptr << 2); 171 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 172 ring->doorbell_index, ring->wptr << 2); 173 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 174 } else { 175 DRM_DEBUG("Not using doorbell -- " 176 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 177 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 178 ring->me, 179 lower_32_bits(ring->wptr << 2), 180 ring->me, 181 upper_32_bits(ring->wptr << 2)); 182 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 183 ring->me, regSDMA0_QUEUE0_RB_WPTR), 184 lower_32_bits(ring->wptr << 2)); 185 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 186 ring->me, regSDMA0_QUEUE0_RB_WPTR_HI), 187 upper_32_bits(ring->wptr << 2)); 188 } 189 } 190 191 static void sdma_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 192 { 193 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 194 int i; 195 196 for (i = 0; i < count; i++) 197 if (sdma && sdma->burst_nop && (i == 0)) 198 amdgpu_ring_write(ring, ring->funcs->nop | 199 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 200 else 201 amdgpu_ring_write(ring, ring->funcs->nop); 202 } 203 204 /* 205 * sdma_v6_0_ring_emit_ib - Schedule an IB on the DMA engine 206 * 207 * @ring: amdgpu ring pointer 208 * @ib: IB object to schedule 209 * @flags: unused 210 * @job: job to retrieve vmid from 211 * 212 * Schedule an IB in the DMA ring. 213 */ 214 static void sdma_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 215 struct amdgpu_job *job, 216 struct amdgpu_ib *ib, 217 uint32_t flags) 218 { 219 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 220 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 221 222 /* An IB packet must end on a 8 DW boundary--the next dword 223 * must be on a 8-dword boundary. Our IB packet below is 6 224 * dwords long, thus add x number of NOPs, such that, in 225 * modular arithmetic, 226 * wptr + 6 + x = 8k, k >= 0, which in C is, 227 * (wptr + 6 + x) % 8 = 0. 228 * The expression below, is a solution of x. 229 */ 230 sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 231 232 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) | 233 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 234 /* base must be 32 byte aligned */ 235 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 236 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 237 amdgpu_ring_write(ring, ib->length_dw); 238 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 239 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 240 } 241 242 /** 243 * sdma_v6_0_ring_emit_mem_sync - flush the IB by graphics cache rinse 244 * 245 * @ring: amdgpu ring pointer 246 * 247 * flush the IB by graphics cache rinse. 248 */ 249 static void sdma_v6_0_ring_emit_mem_sync(struct amdgpu_ring *ring) 250 { 251 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | 252 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 253 SDMA_GCR_GLI_INV(1); 254 255 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 256 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ)); 257 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 258 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 259 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 260 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 261 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 262 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 263 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 264 } 265 266 267 /** 268 * sdma_v6_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 269 * 270 * @ring: amdgpu ring pointer 271 * 272 * Emit an hdp flush packet on the requested DMA ring. 273 */ 274 static void sdma_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 275 { 276 struct amdgpu_device *adev = ring->adev; 277 u32 ref_and_mask = 0; 278 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 279 280 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 281 282 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 283 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 284 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 285 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 286 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 287 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 288 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 289 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 290 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 291 } 292 293 /** 294 * sdma_v6_0_ring_emit_fence - emit a fence on the DMA ring 295 * 296 * @ring: amdgpu ring pointer 297 * @addr: address 298 * @seq: fence seq number 299 * @flags: fence flags 300 * 301 * Add a DMA fence packet to the ring to write 302 * the fence seq number and DMA trap packet to generate 303 * an interrupt if needed. 304 */ 305 static void sdma_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 306 unsigned flags) 307 { 308 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 309 /* write the fence */ 310 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 311 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 312 /* zero in first two bits */ 313 BUG_ON(addr & 0x3); 314 amdgpu_ring_write(ring, lower_32_bits(addr)); 315 amdgpu_ring_write(ring, upper_32_bits(addr)); 316 amdgpu_ring_write(ring, lower_32_bits(seq)); 317 318 /* optionally write high bits as well */ 319 if (write64bit) { 320 addr += 4; 321 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 322 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 323 /* zero in first two bits */ 324 BUG_ON(addr & 0x3); 325 amdgpu_ring_write(ring, lower_32_bits(addr)); 326 amdgpu_ring_write(ring, upper_32_bits(addr)); 327 amdgpu_ring_write(ring, upper_32_bits(seq)); 328 } 329 330 if (flags & AMDGPU_FENCE_FLAG_INT) { 331 uint32_t ctx = ring->is_mes_queue ? 332 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0; 333 /* generate an interrupt */ 334 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP)); 335 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx)); 336 } 337 } 338 339 /** 340 * sdma_v6_0_gfx_stop - stop the gfx async dma engines 341 * 342 * @adev: amdgpu_device pointer 343 * 344 * Stop the gfx async dma ring buffers. 345 */ 346 static void sdma_v6_0_gfx_stop(struct amdgpu_device *adev) 347 { 348 u32 rb_cntl, ib_cntl; 349 int i; 350 351 amdgpu_sdma_unset_buffer_funcs_helper(adev); 352 353 for (i = 0; i < adev->sdma.num_instances; i++) { 354 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 355 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0); 356 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 357 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 358 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0); 359 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 360 } 361 } 362 363 /** 364 * sdma_v6_0_rlc_stop - stop the compute async dma engines 365 * 366 * @adev: amdgpu_device pointer 367 * 368 * Stop the compute async dma queues. 369 */ 370 static void sdma_v6_0_rlc_stop(struct amdgpu_device *adev) 371 { 372 /* XXX todo */ 373 } 374 375 /** 376 * sdma_v6_0_ctxempty_int_enable - enable or disable context empty interrupts 377 * 378 * @adev: amdgpu_device pointer 379 * @enable: enable/disable context switching due to queue empty conditions 380 * 381 * Enable or disable the async dma engines queue empty context switch. 382 */ 383 static void sdma_v6_0_ctxempty_int_enable(struct amdgpu_device *adev, bool enable) 384 { 385 u32 f32_cntl; 386 int i; 387 388 if (!amdgpu_sriov_vf(adev)) { 389 for (i = 0; i < adev->sdma.num_instances; i++) { 390 f32_cntl = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL)); 391 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 392 CTXEMPTY_INT_ENABLE, enable ? 1 : 0); 393 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL), f32_cntl); 394 } 395 } 396 } 397 398 /** 399 * sdma_v6_0_enable - stop the async dma engines 400 * 401 * @adev: amdgpu_device pointer 402 * @enable: enable/disable the DMA MEs. 403 * 404 * Halt or unhalt the async dma engines. 405 */ 406 static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable) 407 { 408 u32 f32_cntl; 409 int i; 410 411 if (!enable) { 412 sdma_v6_0_gfx_stop(adev); 413 sdma_v6_0_rlc_stop(adev); 414 } 415 416 if (amdgpu_sriov_vf(adev)) 417 return; 418 419 for (i = 0; i < adev->sdma.num_instances; i++) { 420 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 421 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 422 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl); 423 } 424 } 425 426 /** 427 * sdma_v6_0_gfx_resume - setup and start the async dma engines 428 * 429 * @adev: amdgpu_device pointer 430 * 431 * Set up the gfx DMA ring buffers and enable them. 432 * Returns 0 for success, error for failure. 433 */ 434 static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev) 435 { 436 struct amdgpu_ring *ring; 437 u32 rb_cntl, ib_cntl; 438 u32 rb_bufsz; 439 u32 doorbell; 440 u32 doorbell_offset; 441 u32 temp; 442 u64 wptr_gpu_addr; 443 int i, r; 444 445 for (i = 0; i < adev->sdma.num_instances; i++) { 446 ring = &adev->sdma.instance[i].ring; 447 448 if (!amdgpu_sriov_vf(adev)) 449 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 450 451 /* Set ring buffer size in dwords */ 452 rb_bufsz = order_base_2(ring->ring_size / 4); 453 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 454 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); 455 #ifdef __BIG_ENDIAN 456 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1); 457 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, 458 RPTR_WRITEBACK_SWAP_ENABLE, 1); 459 #endif 460 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1); 461 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 462 463 /* Initialize the ring buffer's read and write pointers */ 464 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); 465 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0); 466 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0); 467 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0); 468 469 /* setup the wptr shadow polling */ 470 wptr_gpu_addr = ring->wptr_gpu_addr; 471 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO), 472 lower_32_bits(wptr_gpu_addr)); 473 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI), 474 upper_32_bits(wptr_gpu_addr)); 475 476 /* set the wb address whether it's enabled or not */ 477 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI), 478 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 479 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO), 480 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 481 482 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 483 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); 484 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1); 485 486 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8); 487 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40); 488 489 ring->wptr = 0; 490 491 /* before programing wptr to a less value, need set minor_ptr_update first */ 492 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1); 493 494 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 495 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2); 496 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 497 } 498 499 doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL)); 500 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET)); 501 502 if (ring->use_doorbell) { 503 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 504 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET, 505 OFFSET, ring->doorbell_index); 506 } else { 507 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0); 508 } 509 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell); 510 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset); 511 512 if (i == 0) 513 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 514 ring->doorbell_index, 515 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); 516 517 if (amdgpu_sriov_vf(adev)) 518 sdma_v6_0_ring_set_wptr(ring); 519 520 /* set minor_ptr_update to 0 after wptr programed */ 521 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0); 522 523 /* Set up RESP_MODE to non-copy addresses */ 524 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL)); 525 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 526 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 527 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp); 528 529 /* program default cache read and write policy */ 530 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE)); 531 /* clean read policy and write policy bits */ 532 temp &= 0xFF0FFF; 533 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 534 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | 535 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); 536 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp); 537 538 if (!amdgpu_sriov_vf(adev)) { 539 /* unhalt engine */ 540 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 541 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 542 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0); 543 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp); 544 } 545 546 /* enable DMA RB */ 547 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1); 548 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 549 550 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 551 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1); 552 #ifdef __BIG_ENDIAN 553 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1); 554 #endif 555 /* enable DMA IBs */ 556 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 557 558 if (amdgpu_sriov_vf(adev)) 559 sdma_v6_0_enable(adev, true); 560 561 r = amdgpu_ring_test_helper(ring); 562 if (r) 563 return r; 564 565 if (adev->mman.buffer_funcs_ring == ring) 566 amdgpu_ttm_set_buffer_funcs_status(adev, true); 567 } 568 569 return 0; 570 } 571 572 /** 573 * sdma_v6_0_rlc_resume - setup and start the async dma engines 574 * 575 * @adev: amdgpu_device pointer 576 * 577 * Set up the compute DMA queues and enable them. 578 * Returns 0 for success, error for failure. 579 */ 580 static int sdma_v6_0_rlc_resume(struct amdgpu_device *adev) 581 { 582 return 0; 583 } 584 585 /** 586 * sdma_v6_0_load_microcode - load the sDMA ME ucode 587 * 588 * @adev: amdgpu_device pointer 589 * 590 * Loads the sDMA0/1 ucode. 591 * Returns 0 for success, -EINVAL if the ucode is not available. 592 */ 593 static int sdma_v6_0_load_microcode(struct amdgpu_device *adev) 594 { 595 const struct sdma_firmware_header_v2_0 *hdr; 596 const __le32 *fw_data; 597 u32 fw_size; 598 int i, j; 599 bool use_broadcast; 600 601 /* halt the MEs */ 602 sdma_v6_0_enable(adev, false); 603 604 if (!adev->sdma.instance[0].fw) 605 return -EINVAL; 606 607 /* use broadcast mode to load SDMA microcode by default */ 608 use_broadcast = true; 609 610 if (use_broadcast) { 611 dev_info(adev->dev, "Use broadcast method to load SDMA firmware\n"); 612 /* load Control Thread microcode */ 613 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; 614 amdgpu_ucode_print_sdma_hdr(&hdr->header); 615 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4; 616 617 fw_data = (const __le32 *) 618 (adev->sdma.instance[0].fw->data + 619 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 620 621 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0); 622 623 for (j = 0; j < fw_size; j++) { 624 if (amdgpu_emu_mode == 1 && j % 500 == 0) 625 msleep(1); 626 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++)); 627 } 628 629 /* load Context Switch microcode */ 630 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4; 631 632 fw_data = (const __le32 *) 633 (adev->sdma.instance[0].fw->data + 634 le32_to_cpu(hdr->ctl_ucode_offset)); 635 636 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0x8000); 637 638 for (j = 0; j < fw_size; j++) { 639 if (amdgpu_emu_mode == 1 && j % 500 == 0) 640 msleep(1); 641 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++)); 642 } 643 } else { 644 dev_info(adev->dev, "Use legacy method to load SDMA firmware\n"); 645 for (i = 0; i < adev->sdma.num_instances; i++) { 646 /* load Control Thread microcode */ 647 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; 648 amdgpu_ucode_print_sdma_hdr(&hdr->header); 649 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4; 650 651 fw_data = (const __le32 *) 652 (adev->sdma.instance[0].fw->data + 653 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 654 655 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0); 656 657 for (j = 0; j < fw_size; j++) { 658 if (amdgpu_emu_mode == 1 && j % 500 == 0) 659 msleep(1); 660 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 661 } 662 663 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version); 664 665 /* load Context Switch microcode */ 666 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4; 667 668 fw_data = (const __le32 *) 669 (adev->sdma.instance[0].fw->data + 670 le32_to_cpu(hdr->ctl_ucode_offset)); 671 672 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0x8000); 673 674 for (j = 0; j < fw_size; j++) { 675 if (amdgpu_emu_mode == 1 && j % 500 == 0) 676 msleep(1); 677 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 678 } 679 680 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version); 681 } 682 } 683 684 return 0; 685 } 686 687 static int sdma_v6_0_soft_reset(void *handle) 688 { 689 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 690 u32 tmp; 691 int i; 692 693 sdma_v6_0_gfx_stop(adev); 694 695 for (i = 0; i < adev->sdma.num_instances; i++) { 696 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE)); 697 tmp |= SDMA0_FREEZE__FREEZE_MASK; 698 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp); 699 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 700 tmp |= SDMA0_F32_CNTL__HALT_MASK; 701 tmp |= SDMA0_F32_CNTL__TH1_RESET_MASK; 702 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp); 703 704 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0); 705 706 udelay(100); 707 708 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i; 709 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 710 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 711 712 udelay(100); 713 714 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0); 715 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 716 717 udelay(100); 718 } 719 720 return sdma_v6_0_start(adev); 721 } 722 723 static bool sdma_v6_0_check_soft_reset(void *handle) 724 { 725 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 726 struct amdgpu_ring *ring; 727 int i, r; 728 long tmo = msecs_to_jiffies(1000); 729 730 for (i = 0; i < adev->sdma.num_instances; i++) { 731 ring = &adev->sdma.instance[i].ring; 732 r = amdgpu_ring_test_ib(ring, tmo); 733 if (r) 734 return true; 735 } 736 737 return false; 738 } 739 740 /** 741 * sdma_v6_0_start - setup and start the async dma engines 742 * 743 * @adev: amdgpu_device pointer 744 * 745 * Set up the DMA engines and enable them. 746 * Returns 0 for success, error for failure. 747 */ 748 static int sdma_v6_0_start(struct amdgpu_device *adev) 749 { 750 int r = 0; 751 752 if (amdgpu_sriov_vf(adev)) { 753 sdma_v6_0_enable(adev, false); 754 755 /* set RB registers */ 756 r = sdma_v6_0_gfx_resume(adev); 757 return r; 758 } 759 760 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 761 r = sdma_v6_0_load_microcode(adev); 762 if (r) 763 return r; 764 765 /* The value of regSDMA_F32_CNTL is invalid the moment after loading fw */ 766 if (amdgpu_emu_mode == 1) 767 msleep(1000); 768 } 769 770 /* unhalt the MEs */ 771 sdma_v6_0_enable(adev, true); 772 /* enable sdma ring preemption */ 773 sdma_v6_0_ctxempty_int_enable(adev, true); 774 775 /* start the gfx rings and rlc compute queues */ 776 r = sdma_v6_0_gfx_resume(adev); 777 if (r) 778 return r; 779 r = sdma_v6_0_rlc_resume(adev); 780 781 return r; 782 } 783 784 static int sdma_v6_0_mqd_init(struct amdgpu_device *adev, void *mqd, 785 struct amdgpu_mqd_prop *prop) 786 { 787 struct v11_sdma_mqd *m = mqd; 788 uint64_t wb_gpu_addr; 789 790 m->sdmax_rlcx_rb_cntl = 791 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | 792 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 793 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 794 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT; 795 796 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); 797 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); 798 799 wb_gpu_addr = prop->wptr_gpu_addr; 800 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); 801 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); 802 803 wb_gpu_addr = prop->rptr_gpu_addr; 804 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); 805 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); 806 807 m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0, 808 regSDMA0_QUEUE0_IB_CNTL)); 809 810 m->sdmax_rlcx_doorbell_offset = 811 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 812 813 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 814 815 m->sdmax_rlcx_skip_cntl = 0; 816 m->sdmax_rlcx_context_status = 0; 817 m->sdmax_rlcx_doorbell_log = 0; 818 819 m->sdmax_rlcx_rb_aql_cntl = regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT; 820 m->sdmax_rlcx_dummy_reg = regSDMA0_QUEUE0_DUMMY_REG_DEFAULT; 821 822 return 0; 823 } 824 825 static void sdma_v6_0_set_mqd_funcs(struct amdgpu_device *adev) 826 { 827 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v11_sdma_mqd); 828 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v6_0_mqd_init; 829 } 830 831 /** 832 * sdma_v6_0_ring_test_ring - simple async dma engine test 833 * 834 * @ring: amdgpu_ring structure holding ring information 835 * 836 * Test the DMA engine by writing using it to write an 837 * value to memory. 838 * Returns 0 for success, error for failure. 839 */ 840 static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring) 841 { 842 struct amdgpu_device *adev = ring->adev; 843 unsigned i; 844 unsigned index; 845 int r; 846 u32 tmp; 847 u64 gpu_addr; 848 volatile uint32_t *cpu_ptr = NULL; 849 850 tmp = 0xCAFEDEAD; 851 852 if (ring->is_mes_queue) { 853 uint32_t offset = 0; 854 offset = amdgpu_mes_ctx_get_offs(ring, 855 AMDGPU_MES_CTX_PADDING_OFFS); 856 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 857 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 858 *cpu_ptr = tmp; 859 } else { 860 r = amdgpu_device_wb_get(adev, &index); 861 if (r) { 862 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 863 return r; 864 } 865 866 gpu_addr = adev->wb.gpu_addr + (index * 4); 867 adev->wb.wb[index] = cpu_to_le32(tmp); 868 } 869 870 r = amdgpu_ring_alloc(ring, 5); 871 if (r) { 872 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 873 amdgpu_device_wb_free(adev, index); 874 return r; 875 } 876 877 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 878 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 879 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 880 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 881 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 882 amdgpu_ring_write(ring, 0xDEADBEEF); 883 amdgpu_ring_commit(ring); 884 885 for (i = 0; i < adev->usec_timeout; i++) { 886 if (ring->is_mes_queue) 887 tmp = le32_to_cpu(*cpu_ptr); 888 else 889 tmp = le32_to_cpu(adev->wb.wb[index]); 890 if (tmp == 0xDEADBEEF) 891 break; 892 if (amdgpu_emu_mode == 1) 893 msleep(1); 894 else 895 udelay(1); 896 } 897 898 if (i >= adev->usec_timeout) 899 r = -ETIMEDOUT; 900 901 if (!ring->is_mes_queue) 902 amdgpu_device_wb_free(adev, index); 903 904 return r; 905 } 906 907 /* 908 * sdma_v6_0_ring_test_ib - test an IB on the DMA engine 909 * 910 * @ring: amdgpu_ring structure holding ring information 911 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 912 * 913 * Test a simple IB in the DMA ring. 914 * Returns 0 on success, error on failure. 915 */ 916 static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 917 { 918 struct amdgpu_device *adev = ring->adev; 919 struct amdgpu_ib ib; 920 struct dma_fence *f = NULL; 921 unsigned index; 922 long r; 923 u32 tmp = 0; 924 u64 gpu_addr; 925 volatile uint32_t *cpu_ptr = NULL; 926 927 tmp = 0xCAFEDEAD; 928 memset(&ib, 0, sizeof(ib)); 929 930 if (ring->is_mes_queue) { 931 uint32_t offset = 0; 932 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 933 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 934 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 935 936 offset = amdgpu_mes_ctx_get_offs(ring, 937 AMDGPU_MES_CTX_PADDING_OFFS); 938 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 939 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 940 *cpu_ptr = tmp; 941 } else { 942 r = amdgpu_device_wb_get(adev, &index); 943 if (r) { 944 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 945 return r; 946 } 947 948 gpu_addr = adev->wb.gpu_addr + (index * 4); 949 adev->wb.wb[index] = cpu_to_le32(tmp); 950 951 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 952 if (r) { 953 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 954 goto err0; 955 } 956 } 957 958 ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 959 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 960 ib.ptr[1] = lower_32_bits(gpu_addr); 961 ib.ptr[2] = upper_32_bits(gpu_addr); 962 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 963 ib.ptr[4] = 0xDEADBEEF; 964 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 965 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 966 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 967 ib.length_dw = 8; 968 969 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 970 if (r) 971 goto err1; 972 973 r = dma_fence_wait_timeout(f, false, timeout); 974 if (r == 0) { 975 DRM_ERROR("amdgpu: IB test timed out\n"); 976 r = -ETIMEDOUT; 977 goto err1; 978 } else if (r < 0) { 979 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 980 goto err1; 981 } 982 983 if (ring->is_mes_queue) 984 tmp = le32_to_cpu(*cpu_ptr); 985 else 986 tmp = le32_to_cpu(adev->wb.wb[index]); 987 988 if (tmp == 0xDEADBEEF) 989 r = 0; 990 else 991 r = -EINVAL; 992 993 err1: 994 amdgpu_ib_free(adev, &ib, NULL); 995 dma_fence_put(f); 996 err0: 997 if (!ring->is_mes_queue) 998 amdgpu_device_wb_free(adev, index); 999 return r; 1000 } 1001 1002 1003 /** 1004 * sdma_v6_0_vm_copy_pte - update PTEs by copying them from the GART 1005 * 1006 * @ib: indirect buffer to fill with commands 1007 * @pe: addr of the page entry 1008 * @src: src addr to copy from 1009 * @count: number of page entries to update 1010 * 1011 * Update PTEs by copying them from the GART using sDMA. 1012 */ 1013 static void sdma_v6_0_vm_copy_pte(struct amdgpu_ib *ib, 1014 uint64_t pe, uint64_t src, 1015 unsigned count) 1016 { 1017 unsigned bytes = count * 8; 1018 1019 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1020 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1021 ib->ptr[ib->length_dw++] = bytes - 1; 1022 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1023 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1024 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1025 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1026 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1027 1028 } 1029 1030 /** 1031 * sdma_v6_0_vm_write_pte - update PTEs by writing them manually 1032 * 1033 * @ib: indirect buffer to fill with commands 1034 * @pe: addr of the page entry 1035 * @value: dst addr to write into pe 1036 * @count: number of page entries to update 1037 * @incr: increase next addr by incr bytes 1038 * 1039 * Update PTEs by writing them manually using sDMA. 1040 */ 1041 static void sdma_v6_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1042 uint64_t value, unsigned count, 1043 uint32_t incr) 1044 { 1045 unsigned ndw = count * 2; 1046 1047 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 1048 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1049 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1050 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1051 ib->ptr[ib->length_dw++] = ndw - 1; 1052 for (; ndw > 0; ndw -= 2) { 1053 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1054 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1055 value += incr; 1056 } 1057 } 1058 1059 /** 1060 * sdma_v6_0_vm_set_pte_pde - update the page tables using sDMA 1061 * 1062 * @ib: indirect buffer to fill with commands 1063 * @pe: addr of the page entry 1064 * @addr: dst addr to write into pe 1065 * @count: number of page entries to update 1066 * @incr: increase next addr by incr bytes 1067 * @flags: access flags 1068 * 1069 * Update the page tables using sDMA. 1070 */ 1071 static void sdma_v6_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1072 uint64_t pe, 1073 uint64_t addr, unsigned count, 1074 uint32_t incr, uint64_t flags) 1075 { 1076 /* for physically contiguous pages (vram) */ 1077 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE); 1078 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1079 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1080 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1081 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1082 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1083 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1084 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1085 ib->ptr[ib->length_dw++] = 0; 1086 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1087 } 1088 1089 /* 1090 * sdma_v6_0_ring_pad_ib - pad the IB 1091 * @ib: indirect buffer to fill with padding 1092 * @ring: amdgpu ring pointer 1093 * 1094 * Pad the IB with NOPs to a boundary multiple of 8. 1095 */ 1096 static void sdma_v6_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1097 { 1098 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1099 u32 pad_count; 1100 int i; 1101 1102 pad_count = (-ib->length_dw) & 0x7; 1103 for (i = 0; i < pad_count; i++) 1104 if (sdma && sdma->burst_nop && (i == 0)) 1105 ib->ptr[ib->length_dw++] = 1106 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) | 1107 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1108 else 1109 ib->ptr[ib->length_dw++] = 1110 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP); 1111 } 1112 1113 /** 1114 * sdma_v6_0_ring_emit_pipeline_sync - sync the pipeline 1115 * 1116 * @ring: amdgpu_ring pointer 1117 * 1118 * Make sure all previous operations are completed (CIK). 1119 */ 1120 static void sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1121 { 1122 uint32_t seq = ring->fence_drv.sync_seq; 1123 uint64_t addr = ring->fence_drv.gpu_addr; 1124 1125 /* wait for idle */ 1126 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1127 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1128 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1129 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1130 amdgpu_ring_write(ring, addr & 0xfffffffc); 1131 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1132 amdgpu_ring_write(ring, seq); /* reference */ 1133 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1134 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1135 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1136 } 1137 1138 /* 1139 * sdma_v6_0_ring_emit_vm_flush - vm flush using sDMA 1140 * 1141 * @ring: amdgpu_ring pointer 1142 * @vmid: vmid number to use 1143 * @pd_addr: address 1144 * 1145 * Update the page table base and flush the VM TLB 1146 * using sDMA. 1147 */ 1148 static void sdma_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1149 unsigned vmid, uint64_t pd_addr) 1150 { 1151 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1152 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 1153 1154 /* Update the PD address for this VMID. */ 1155 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 1156 (hub->ctx_addr_distance * vmid), 1157 lower_32_bits(pd_addr)); 1158 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1159 (hub->ctx_addr_distance * vmid), 1160 upper_32_bits(pd_addr)); 1161 1162 /* Trigger invalidation. */ 1163 amdgpu_ring_write(ring, 1164 SDMA_PKT_VM_INVALIDATION_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1165 SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(SDMA_SUBOP_VM_INVALIDATION) | 1166 SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(ring->vm_inv_eng) | 1167 SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(0x1f)); 1168 amdgpu_ring_write(ring, req); 1169 amdgpu_ring_write(ring, 0xFFFFFFFF); 1170 amdgpu_ring_write(ring, 1171 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(1 << vmid) | 1172 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(0x1F)); 1173 } 1174 1175 static void sdma_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, 1176 uint32_t reg, uint32_t val) 1177 { 1178 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1179 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1180 amdgpu_ring_write(ring, reg); 1181 amdgpu_ring_write(ring, val); 1182 } 1183 1184 static void sdma_v6_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1185 uint32_t val, uint32_t mask) 1186 { 1187 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1188 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1189 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1190 amdgpu_ring_write(ring, reg << 2); 1191 amdgpu_ring_write(ring, 0); 1192 amdgpu_ring_write(ring, val); /* reference */ 1193 amdgpu_ring_write(ring, mask); /* mask */ 1194 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1195 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1196 } 1197 1198 static void sdma_v6_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1199 uint32_t reg0, uint32_t reg1, 1200 uint32_t ref, uint32_t mask) 1201 { 1202 amdgpu_ring_emit_wreg(ring, reg0, ref); 1203 /* wait for a cycle to reset vm_inv_eng*_ack */ 1204 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1205 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1206 } 1207 1208 static struct amdgpu_sdma_ras sdma_v6_0_3_ras = { 1209 .ras_block = { 1210 .ras_late_init = amdgpu_ras_block_late_init, 1211 }, 1212 }; 1213 1214 static void sdma_v6_0_set_ras_funcs(struct amdgpu_device *adev) 1215 { 1216 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1217 case IP_VERSION(6, 0, 3): 1218 adev->sdma.ras = &sdma_v6_0_3_ras; 1219 break; 1220 default: 1221 break; 1222 } 1223 } 1224 1225 static int sdma_v6_0_early_init(void *handle) 1226 { 1227 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1228 int r; 1229 1230 r = amdgpu_sdma_init_microcode(adev, 0, true); 1231 if (r) 1232 return r; 1233 1234 sdma_v6_0_set_ring_funcs(adev); 1235 sdma_v6_0_set_buffer_funcs(adev); 1236 sdma_v6_0_set_vm_pte_funcs(adev); 1237 sdma_v6_0_set_irq_funcs(adev); 1238 sdma_v6_0_set_mqd_funcs(adev); 1239 sdma_v6_0_set_ras_funcs(adev); 1240 1241 return 0; 1242 } 1243 1244 static int sdma_v6_0_sw_init(void *handle) 1245 { 1246 struct amdgpu_ring *ring; 1247 int r, i; 1248 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1249 1250 /* SDMA trap event */ 1251 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1252 GFX_11_0_0__SRCID__SDMA_TRAP, 1253 &adev->sdma.trap_irq); 1254 if (r) 1255 return r; 1256 1257 for (i = 0; i < adev->sdma.num_instances; i++) { 1258 ring = &adev->sdma.instance[i].ring; 1259 ring->ring_obj = NULL; 1260 ring->use_doorbell = true; 1261 ring->me = i; 1262 1263 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1264 ring->use_doorbell?"true":"false"); 1265 1266 ring->doorbell_index = 1267 (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset 1268 1269 ring->vm_hub = AMDGPU_GFXHUB(0); 1270 sprintf(ring->name, "sdma%d", i); 1271 r = amdgpu_ring_init(adev, ring, 1024, 1272 &adev->sdma.trap_irq, 1273 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1274 AMDGPU_RING_PRIO_DEFAULT, NULL); 1275 if (r) 1276 return r; 1277 } 1278 1279 if (amdgpu_sdma_ras_sw_init(adev)) { 1280 dev_err(adev->dev, "Failed to initialize sdma ras block!\n"); 1281 return -EINVAL; 1282 } 1283 1284 return r; 1285 } 1286 1287 static int sdma_v6_0_sw_fini(void *handle) 1288 { 1289 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1290 int i; 1291 1292 for (i = 0; i < adev->sdma.num_instances; i++) 1293 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1294 1295 amdgpu_sdma_destroy_inst_ctx(adev, true); 1296 1297 return 0; 1298 } 1299 1300 static int sdma_v6_0_hw_init(void *handle) 1301 { 1302 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1303 1304 return sdma_v6_0_start(adev); 1305 } 1306 1307 static int sdma_v6_0_hw_fini(void *handle) 1308 { 1309 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1310 1311 if (amdgpu_sriov_vf(adev)) { 1312 /* disable the scheduler for SDMA */ 1313 amdgpu_sdma_unset_buffer_funcs_helper(adev); 1314 return 0; 1315 } 1316 1317 sdma_v6_0_ctxempty_int_enable(adev, false); 1318 sdma_v6_0_enable(adev, false); 1319 1320 return 0; 1321 } 1322 1323 static int sdma_v6_0_suspend(void *handle) 1324 { 1325 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1326 1327 return sdma_v6_0_hw_fini(adev); 1328 } 1329 1330 static int sdma_v6_0_resume(void *handle) 1331 { 1332 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1333 1334 return sdma_v6_0_hw_init(adev); 1335 } 1336 1337 static bool sdma_v6_0_is_idle(void *handle) 1338 { 1339 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1340 u32 i; 1341 1342 for (i = 0; i < adev->sdma.num_instances; i++) { 1343 u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG)); 1344 1345 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1346 return false; 1347 } 1348 1349 return true; 1350 } 1351 1352 static int sdma_v6_0_wait_for_idle(void *handle) 1353 { 1354 unsigned i; 1355 u32 sdma0, sdma1; 1356 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1357 1358 for (i = 0; i < adev->usec_timeout; i++) { 1359 sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG)); 1360 sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG)); 1361 1362 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1363 return 0; 1364 udelay(1); 1365 } 1366 return -ETIMEDOUT; 1367 } 1368 1369 static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring) 1370 { 1371 int i, r = 0; 1372 struct amdgpu_device *adev = ring->adev; 1373 u32 index = 0; 1374 u64 sdma_gfx_preempt; 1375 1376 amdgpu_sdma_get_index_from_ring(ring, &index); 1377 sdma_gfx_preempt = 1378 sdma_v6_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT); 1379 1380 /* assert preemption condition */ 1381 amdgpu_ring_set_preempt_cond_exec(ring, false); 1382 1383 /* emit the trailing fence */ 1384 ring->trail_seq += 1; 1385 amdgpu_ring_alloc(ring, 10); 1386 sdma_v6_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1387 ring->trail_seq, 0); 1388 amdgpu_ring_commit(ring); 1389 1390 /* assert IB preemption */ 1391 WREG32(sdma_gfx_preempt, 1); 1392 1393 /* poll the trailing fence */ 1394 for (i = 0; i < adev->usec_timeout; i++) { 1395 if (ring->trail_seq == 1396 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1397 break; 1398 udelay(1); 1399 } 1400 1401 if (i >= adev->usec_timeout) { 1402 r = -EINVAL; 1403 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1404 } 1405 1406 /* deassert IB preemption */ 1407 WREG32(sdma_gfx_preempt, 0); 1408 1409 /* deassert the preemption condition */ 1410 amdgpu_ring_set_preempt_cond_exec(ring, true); 1411 return r; 1412 } 1413 1414 static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev, 1415 struct amdgpu_irq_src *source, 1416 unsigned type, 1417 enum amdgpu_interrupt_state state) 1418 { 1419 u32 sdma_cntl; 1420 1421 u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL); 1422 1423 if (!amdgpu_sriov_vf(adev)) { 1424 sdma_cntl = RREG32(reg_offset); 1425 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1426 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1427 WREG32(reg_offset, sdma_cntl); 1428 } 1429 1430 return 0; 1431 } 1432 1433 static int sdma_v6_0_process_trap_irq(struct amdgpu_device *adev, 1434 struct amdgpu_irq_src *source, 1435 struct amdgpu_iv_entry *entry) 1436 { 1437 int instances, queue; 1438 uint32_t mes_queue_id = entry->src_data[0]; 1439 1440 DRM_DEBUG("IH: SDMA trap\n"); 1441 1442 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 1443 struct amdgpu_mes_queue *queue; 1444 1445 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 1446 1447 spin_lock(&adev->mes.queue_id_lock); 1448 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 1449 if (queue) { 1450 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); 1451 amdgpu_fence_process(queue->ring); 1452 } 1453 spin_unlock(&adev->mes.queue_id_lock); 1454 return 0; 1455 } 1456 1457 queue = entry->ring_id & 0xf; 1458 instances = (entry->ring_id & 0xf0) >> 4; 1459 if (instances > 1) { 1460 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n"); 1461 return -EINVAL; 1462 } 1463 1464 switch (entry->client_id) { 1465 case SOC21_IH_CLIENTID_GFX: 1466 switch (queue) { 1467 case 0: 1468 amdgpu_fence_process(&adev->sdma.instance[instances].ring); 1469 break; 1470 default: 1471 break; 1472 } 1473 break; 1474 } 1475 return 0; 1476 } 1477 1478 static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1479 struct amdgpu_irq_src *source, 1480 struct amdgpu_iv_entry *entry) 1481 { 1482 return 0; 1483 } 1484 1485 static int sdma_v6_0_set_clockgating_state(void *handle, 1486 enum amd_clockgating_state state) 1487 { 1488 return 0; 1489 } 1490 1491 static int sdma_v6_0_set_powergating_state(void *handle, 1492 enum amd_powergating_state state) 1493 { 1494 return 0; 1495 } 1496 1497 static void sdma_v6_0_get_clockgating_state(void *handle, u64 *flags) 1498 { 1499 } 1500 1501 const struct amd_ip_funcs sdma_v6_0_ip_funcs = { 1502 .name = "sdma_v6_0", 1503 .early_init = sdma_v6_0_early_init, 1504 .late_init = NULL, 1505 .sw_init = sdma_v6_0_sw_init, 1506 .sw_fini = sdma_v6_0_sw_fini, 1507 .hw_init = sdma_v6_0_hw_init, 1508 .hw_fini = sdma_v6_0_hw_fini, 1509 .suspend = sdma_v6_0_suspend, 1510 .resume = sdma_v6_0_resume, 1511 .is_idle = sdma_v6_0_is_idle, 1512 .wait_for_idle = sdma_v6_0_wait_for_idle, 1513 .soft_reset = sdma_v6_0_soft_reset, 1514 .check_soft_reset = sdma_v6_0_check_soft_reset, 1515 .set_clockgating_state = sdma_v6_0_set_clockgating_state, 1516 .set_powergating_state = sdma_v6_0_set_powergating_state, 1517 .get_clockgating_state = sdma_v6_0_get_clockgating_state, 1518 }; 1519 1520 static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = { 1521 .type = AMDGPU_RING_TYPE_SDMA, 1522 .align_mask = 0xf, 1523 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1524 .support_64bit_ptrs = true, 1525 .secure_submission_supported = true, 1526 .get_rptr = sdma_v6_0_ring_get_rptr, 1527 .get_wptr = sdma_v6_0_ring_get_wptr, 1528 .set_wptr = sdma_v6_0_ring_set_wptr, 1529 .emit_frame_size = 1530 5 + /* sdma_v6_0_ring_init_cond_exec */ 1531 6 + /* sdma_v6_0_ring_emit_hdp_flush */ 1532 6 + /* sdma_v6_0_ring_emit_pipeline_sync */ 1533 /* sdma_v6_0_ring_emit_vm_flush */ 1534 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1535 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1536 10 + 10 + 10, /* sdma_v6_0_ring_emit_fence x3 for user fence, vm fence */ 1537 .emit_ib_size = 5 + 7 + 6, /* sdma_v6_0_ring_emit_ib */ 1538 .emit_ib = sdma_v6_0_ring_emit_ib, 1539 .emit_mem_sync = sdma_v6_0_ring_emit_mem_sync, 1540 .emit_fence = sdma_v6_0_ring_emit_fence, 1541 .emit_pipeline_sync = sdma_v6_0_ring_emit_pipeline_sync, 1542 .emit_vm_flush = sdma_v6_0_ring_emit_vm_flush, 1543 .emit_hdp_flush = sdma_v6_0_ring_emit_hdp_flush, 1544 .test_ring = sdma_v6_0_ring_test_ring, 1545 .test_ib = sdma_v6_0_ring_test_ib, 1546 .insert_nop = sdma_v6_0_ring_insert_nop, 1547 .pad_ib = sdma_v6_0_ring_pad_ib, 1548 .emit_wreg = sdma_v6_0_ring_emit_wreg, 1549 .emit_reg_wait = sdma_v6_0_ring_emit_reg_wait, 1550 .emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait, 1551 .init_cond_exec = sdma_v6_0_ring_init_cond_exec, 1552 .patch_cond_exec = sdma_v6_0_ring_patch_cond_exec, 1553 .preempt_ib = sdma_v6_0_ring_preempt_ib, 1554 }; 1555 1556 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev) 1557 { 1558 int i; 1559 1560 for (i = 0; i < adev->sdma.num_instances; i++) { 1561 adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs; 1562 adev->sdma.instance[i].ring.me = i; 1563 } 1564 } 1565 1566 static const struct amdgpu_irq_src_funcs sdma_v6_0_trap_irq_funcs = { 1567 .set = sdma_v6_0_set_trap_irq_state, 1568 .process = sdma_v6_0_process_trap_irq, 1569 }; 1570 1571 static const struct amdgpu_irq_src_funcs sdma_v6_0_illegal_inst_irq_funcs = { 1572 .process = sdma_v6_0_process_illegal_inst_irq, 1573 }; 1574 1575 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev) 1576 { 1577 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1578 adev->sdma.num_instances; 1579 adev->sdma.trap_irq.funcs = &sdma_v6_0_trap_irq_funcs; 1580 adev->sdma.illegal_inst_irq.funcs = &sdma_v6_0_illegal_inst_irq_funcs; 1581 } 1582 1583 /** 1584 * sdma_v6_0_emit_copy_buffer - copy buffer using the sDMA engine 1585 * 1586 * @ib: indirect buffer to fill with commands 1587 * @src_offset: src GPU address 1588 * @dst_offset: dst GPU address 1589 * @byte_count: number of bytes to xfer 1590 * @tmz: if a secure copy should be used 1591 * 1592 * Copy GPU buffers using the DMA engine. 1593 * Used by the amdgpu ttm implementation to move pages if 1594 * registered as the asic copy callback. 1595 */ 1596 static void sdma_v6_0_emit_copy_buffer(struct amdgpu_ib *ib, 1597 uint64_t src_offset, 1598 uint64_t dst_offset, 1599 uint32_t byte_count, 1600 bool tmz) 1601 { 1602 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1603 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1604 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 1605 ib->ptr[ib->length_dw++] = byte_count - 1; 1606 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1607 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1608 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1609 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1610 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1611 } 1612 1613 /** 1614 * sdma_v6_0_emit_fill_buffer - fill buffer using the sDMA engine 1615 * 1616 * @ib: indirect buffer to fill 1617 * @src_data: value to write to buffer 1618 * @dst_offset: dst GPU address 1619 * @byte_count: number of bytes to xfer 1620 * 1621 * Fill GPU buffers using the DMA engine. 1622 */ 1623 static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib, 1624 uint32_t src_data, 1625 uint64_t dst_offset, 1626 uint32_t byte_count) 1627 { 1628 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_CONST_FILL); 1629 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1630 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1631 ib->ptr[ib->length_dw++] = src_data; 1632 ib->ptr[ib->length_dw++] = byte_count - 1; 1633 } 1634 1635 static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = { 1636 .copy_max_bytes = 0x400000, 1637 .copy_num_dw = 7, 1638 .emit_copy_buffer = sdma_v6_0_emit_copy_buffer, 1639 1640 .fill_max_bytes = 0x400000, 1641 .fill_num_dw = 5, 1642 .emit_fill_buffer = sdma_v6_0_emit_fill_buffer, 1643 }; 1644 1645 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev) 1646 { 1647 adev->mman.buffer_funcs = &sdma_v6_0_buffer_funcs; 1648 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1649 } 1650 1651 static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = { 1652 .copy_pte_num_dw = 7, 1653 .copy_pte = sdma_v6_0_vm_copy_pte, 1654 .write_pte = sdma_v6_0_vm_write_pte, 1655 .set_pte_pde = sdma_v6_0_vm_set_pte_pde, 1656 }; 1657 1658 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1659 { 1660 unsigned i; 1661 1662 adev->vm_manager.vm_pte_funcs = &sdma_v6_0_vm_pte_funcs; 1663 for (i = 0; i < adev->sdma.num_instances; i++) { 1664 adev->vm_manager.vm_pte_scheds[i] = 1665 &adev->sdma.instance[i].ring.sched; 1666 } 1667 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1668 } 1669 1670 const struct amdgpu_ip_block_version sdma_v6_0_ip_block = { 1671 .type = AMD_IP_BLOCK_TYPE_SDMA, 1672 .major = 6, 1673 .minor = 0, 1674 .rev = 0, 1675 .funcs = &sdma_v6_0_ip_funcs, 1676 }; 1677