1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_atombios.h" 25 #include "nbio_v7_9.h" 26 #include "amdgpu_ras.h" 27 28 #include "nbio/nbio_7_9_0_offset.h" 29 #include "nbio/nbio_7_9_0_sh_mask.h" 30 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" 31 #include <uapi/linux/kfd_ioctl.h> 32 33 #define NPS_MODE_MASK 0x000000FFL 34 35 /* Core 0 Port 0 counter */ 36 #define smnPCIEP_NAK_COUNTER 0x1A340218 37 38 #define smnPCIE_PERF_CNTL_TXCLK3 0x1A38021c 39 #define smnPCIE_PERF_CNTL_TXCLK7 0x1A380888 40 #define smnPCIE_PERF_COUNT_CNTL 0x1A380200 41 #define smnPCIE_PERF_COUNT0_TXCLK3 0x1A380220 42 #define smnPCIE_PERF_COUNT0_TXCLK7 0x1A38088C 43 #define smnPCIE_PERF_COUNT0_UPVAL_TXCLK3 0x1A3808F8 44 #define smnPCIE_PERF_COUNT0_UPVAL_TXCLK7 0x1A380918 45 46 47 static void nbio_v7_9_remap_hdp_registers(struct amdgpu_device *adev) 48 { 49 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, 50 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 51 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL, 52 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 53 } 54 55 static u32 nbio_v7_9_get_rev_id(struct amdgpu_device *adev) 56 { 57 u32 tmp; 58 59 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); 60 tmp = REG_GET_FIELD(tmp, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0, STRAP_ATI_REV_ID_DEV0_F0); 61 62 return tmp; 63 } 64 65 static void nbio_v7_9_mc_access_enable(struct amdgpu_device *adev, bool enable) 66 { 67 if (enable) 68 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 69 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); 70 else 71 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0); 72 } 73 74 static u32 nbio_v7_9_get_memsize(struct amdgpu_device *adev) 75 { 76 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); 77 } 78 79 static void nbio_v7_9_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 80 bool use_doorbell, int doorbell_index, int doorbell_size) 81 { 82 u32 doorbell_range = 0, doorbell_ctrl = 0; 83 int aid_id, dev_inst; 84 85 dev_inst = GET_INST(SDMA0, instance); 86 aid_id = adev->sdma.instance[instance].aid_id; 87 88 if (use_doorbell == false) 89 return; 90 91 doorbell_range = 92 REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0, 93 BIF_DOORBELL0_RANGE_OFFSET_ENTRY, doorbell_index); 94 doorbell_range = 95 REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0, 96 BIF_DOORBELL0_RANGE_SIZE_ENTRY, doorbell_size); 97 doorbell_ctrl = 98 REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL, 99 S2A_DOORBELL_PORT1_ENABLE, 1); 100 doorbell_ctrl = 101 REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL, 102 S2A_DOORBELL_PORT1_RANGE_SIZE, doorbell_size); 103 104 switch (dev_inst % adev->sdma.num_inst_per_aid) { 105 case 0: 106 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_1, 107 4 * aid_id, doorbell_range); 108 109 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 110 S2A_DOORBELL_ENTRY_1_CTRL, 111 S2A_DOORBELL_PORT1_AWID, 0xe); 112 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 113 S2A_DOORBELL_ENTRY_1_CTRL, 114 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xe); 115 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 116 S2A_DOORBELL_ENTRY_1_CTRL, 117 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 118 0x1); 119 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_1_CTRL, 120 aid_id, doorbell_ctrl); 121 break; 122 case 1: 123 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_2, 124 4 * aid_id, doorbell_range); 125 126 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 127 S2A_DOORBELL_ENTRY_1_CTRL, 128 S2A_DOORBELL_PORT1_AWID, 0x8); 129 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 130 S2A_DOORBELL_ENTRY_1_CTRL, 131 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x8); 132 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 133 S2A_DOORBELL_ENTRY_1_CTRL, 134 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 135 0x2); 136 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_2_CTRL, 137 aid_id, doorbell_ctrl); 138 break; 139 case 2: 140 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_3, 141 4 * aid_id, doorbell_range); 142 143 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 144 S2A_DOORBELL_ENTRY_1_CTRL, 145 S2A_DOORBELL_PORT1_AWID, 0x9); 146 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 147 S2A_DOORBELL_ENTRY_1_CTRL, 148 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x9); 149 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 150 S2A_DOORBELL_ENTRY_1_CTRL, 151 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 152 0x8); 153 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_5_CTRL, 154 aid_id, doorbell_ctrl); 155 break; 156 case 3: 157 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_4, 158 4 * aid_id, doorbell_range); 159 160 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 161 S2A_DOORBELL_ENTRY_1_CTRL, 162 S2A_DOORBELL_PORT1_AWID, 0xa); 163 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 164 S2A_DOORBELL_ENTRY_1_CTRL, 165 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xa); 166 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 167 S2A_DOORBELL_ENTRY_1_CTRL, 168 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 169 0x9); 170 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_6_CTRL, 171 aid_id, doorbell_ctrl); 172 break; 173 default: 174 break; 175 } 176 } 177 178 static void nbio_v7_9_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, 179 int doorbell_index, int instance) 180 { 181 u32 doorbell_range = 0, doorbell_ctrl = 0; 182 u32 aid_id = instance; 183 184 if (use_doorbell) { 185 doorbell_range = REG_SET_FIELD(doorbell_range, 186 DOORBELL0_CTRL_ENTRY_0, 187 BIF_DOORBELL0_RANGE_OFFSET_ENTRY, 188 doorbell_index); 189 doorbell_range = REG_SET_FIELD(doorbell_range, 190 DOORBELL0_CTRL_ENTRY_0, 191 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 192 0x9); 193 if (aid_id) 194 doorbell_range = REG_SET_FIELD(doorbell_range, 195 DOORBELL0_CTRL_ENTRY_0, 196 DOORBELL0_FENCE_ENABLE_ENTRY, 197 0x4); 198 199 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 200 S2A_DOORBELL_ENTRY_1_CTRL, 201 S2A_DOORBELL_PORT1_ENABLE, 1); 202 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 203 S2A_DOORBELL_ENTRY_1_CTRL, 204 S2A_DOORBELL_PORT1_AWID, 0x4); 205 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 206 S2A_DOORBELL_ENTRY_1_CTRL, 207 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x4); 208 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 209 S2A_DOORBELL_ENTRY_1_CTRL, 210 S2A_DOORBELL_PORT1_RANGE_SIZE, 0x9); 211 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 212 S2A_DOORBELL_ENTRY_1_CTRL, 213 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0x4); 214 215 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17, 216 aid_id, doorbell_range); 217 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_4_CTRL, 218 aid_id, doorbell_ctrl); 219 } else { 220 doorbell_range = REG_SET_FIELD(doorbell_range, 221 DOORBELL0_CTRL_ENTRY_0, 222 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0); 223 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 224 S2A_DOORBELL_ENTRY_1_CTRL, 225 S2A_DOORBELL_PORT1_RANGE_SIZE, 0); 226 227 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17, 228 aid_id, doorbell_range); 229 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_4_CTRL, 230 aid_id, doorbell_ctrl); 231 } 232 } 233 234 static void nbio_v7_9_enable_doorbell_aperture(struct amdgpu_device *adev, 235 bool enable) 236 { 237 /* Enable to allow doorbell pass thru on pre-silicon bare-metal */ 238 WREG32_SOC15(NBIO, 0, regBIFC_DOORBELL_ACCESS_EN_PF, 0xfffff); 239 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, 240 BIF_DOORBELL_APER_EN, enable ? 1 : 0); 241 } 242 243 static void nbio_v7_9_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 244 bool enable) 245 { 246 u32 tmp = 0; 247 248 if (enable) { 249 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 250 DOORBELL_SELFRING_GPA_APER_EN, 1) | 251 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 252 DOORBELL_SELFRING_GPA_APER_MODE, 1) | 253 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 254 DOORBELL_SELFRING_GPA_APER_SIZE, 0); 255 256 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 257 lower_32_bits(adev->doorbell.base)); 258 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 259 upper_32_bits(adev->doorbell.base)); 260 } 261 262 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp); 263 } 264 265 static void nbio_v7_9_ih_doorbell_range(struct amdgpu_device *adev, 266 bool use_doorbell, int doorbell_index) 267 { 268 u32 ih_doorbell_range = 0, ih_doorbell_ctrl = 0; 269 270 if (use_doorbell) { 271 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 272 DOORBELL0_CTRL_ENTRY_0, 273 BIF_DOORBELL0_RANGE_OFFSET_ENTRY, 274 doorbell_index); 275 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 276 DOORBELL0_CTRL_ENTRY_0, 277 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 278 0x8); 279 280 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 281 S2A_DOORBELL_ENTRY_1_CTRL, 282 S2A_DOORBELL_PORT1_ENABLE, 1); 283 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 284 S2A_DOORBELL_ENTRY_1_CTRL, 285 S2A_DOORBELL_PORT1_AWID, 0); 286 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 287 S2A_DOORBELL_ENTRY_1_CTRL, 288 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0); 289 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 290 S2A_DOORBELL_ENTRY_1_CTRL, 291 S2A_DOORBELL_PORT1_RANGE_SIZE, 0x8); 292 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 293 S2A_DOORBELL_ENTRY_1_CTRL, 294 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0); 295 } else { 296 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 297 DOORBELL0_CTRL_ENTRY_0, 298 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0); 299 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 300 S2A_DOORBELL_ENTRY_1_CTRL, 301 S2A_DOORBELL_PORT1_RANGE_SIZE, 0); 302 } 303 304 WREG32_SOC15(NBIO, 0, regDOORBELL0_CTRL_ENTRY_0, ih_doorbell_range); 305 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_3_CTRL, ih_doorbell_ctrl); 306 } 307 308 309 static void nbio_v7_9_update_medium_grain_clock_gating(struct amdgpu_device *adev, 310 bool enable) 311 { 312 } 313 314 static void nbio_v7_9_update_medium_grain_light_sleep(struct amdgpu_device *adev, 315 bool enable) 316 { 317 } 318 319 static void nbio_v7_9_get_clockgating_state(struct amdgpu_device *adev, 320 u64 *flags) 321 { 322 } 323 324 static void nbio_v7_9_ih_control(struct amdgpu_device *adev) 325 { 326 u32 interrupt_cntl; 327 328 /* setup interrupt control */ 329 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 330 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL); 331 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 332 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 333 */ 334 interrupt_cntl = 335 REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 336 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 337 interrupt_cntl = 338 REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 339 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl); 340 } 341 342 static u32 nbio_v7_9_get_hdp_flush_req_offset(struct amdgpu_device *adev) 343 { 344 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ); 345 } 346 347 static u32 nbio_v7_9_get_hdp_flush_done_offset(struct amdgpu_device *adev) 348 { 349 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE); 350 } 351 352 static u32 nbio_v7_9_get_pcie_index_offset(struct amdgpu_device *adev) 353 { 354 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2); 355 } 356 357 static u32 nbio_v7_9_get_pcie_data_offset(struct amdgpu_device *adev) 358 { 359 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2); 360 } 361 362 static u32 nbio_v7_9_get_pcie_index_hi_offset(struct amdgpu_device *adev) 363 { 364 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2_HI); 365 } 366 367 const struct nbio_hdp_flush_reg nbio_v7_9_hdp_flush_reg = { 368 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK, 369 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK, 370 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK, 371 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK, 372 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK, 373 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK, 374 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK, 375 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK, 376 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK, 377 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK, 378 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 379 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK, 380 .ref_and_mask_sdma2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK, 381 .ref_and_mask_sdma3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK, 382 .ref_and_mask_sdma4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK, 383 .ref_and_mask_sdma5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK, 384 .ref_and_mask_sdma6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK, 385 .ref_and_mask_sdma7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK, 386 }; 387 388 static void nbio_v7_9_enable_doorbell_interrupt(struct amdgpu_device *adev, 389 bool enable) 390 { 391 WREG32_FIELD15_PREREG(NBIO, 0, BIF_BX0_BIF_DOORBELL_INT_CNTL, 392 DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1); 393 } 394 395 static int nbio_v7_9_get_compute_partition_mode(struct amdgpu_device *adev) 396 { 397 u32 tmp, px; 398 399 tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS); 400 px = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_STATUS, 401 PARTITION_MODE); 402 403 return px; 404 } 405 406 static u32 nbio_v7_9_get_memory_partition_mode(struct amdgpu_device *adev, 407 u32 *supp_modes) 408 { 409 u32 tmp; 410 411 tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS); 412 tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS, NPS_MODE); 413 414 if (supp_modes) { 415 *supp_modes = 416 RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_CAP); 417 } 418 419 return ffs(tmp); 420 } 421 422 static void nbio_v7_9_init_registers(struct amdgpu_device *adev) 423 { 424 u32 inst_mask; 425 int i; 426 427 WREG32_SOC15(NBIO, 0, regXCC_DOORBELL_FENCE, 428 0xff & ~(adev->gfx.xcc_mask)); 429 430 WREG32_SOC15(NBIO, 0, regBIFC_GFX_INT_MONITOR_MASK, 0x7ff); 431 432 inst_mask = adev->aid_mask & ~1U; 433 for_each_inst(i, inst_mask) { 434 WREG32_SOC15_EXT(NBIO, i, regXCC_DOORBELL_FENCE, i, 435 XCC_DOORBELL_FENCE__SHUB_SLV_MODE_MASK); 436 437 } 438 439 if (!amdgpu_sriov_vf(adev)) { 440 u32 baco_cntl; 441 for_each_inst(i, adev->aid_mask) { 442 baco_cntl = RREG32_SOC15(NBIO, i, regBIF_BX0_BACO_CNTL); 443 if (baco_cntl & (BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK | 444 BIF_BX0_BACO_CNTL__BACO_EN_MASK)) { 445 baco_cntl &= ~( 446 BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK | 447 BIF_BX0_BACO_CNTL__BACO_EN_MASK); 448 dev_dbg(adev->dev, 449 "Unsetting baco dummy mode %x", 450 baco_cntl); 451 WREG32_SOC15(NBIO, i, regBIF_BX0_BACO_CNTL, 452 baco_cntl); 453 } 454 } 455 } 456 } 457 458 static u64 nbio_v7_9_get_pcie_replay_count(struct amdgpu_device *adev) 459 { 460 u32 val, nak_r, nak_g; 461 462 if (adev->flags & AMD_IS_APU) 463 return 0; 464 465 /* Get the number of NAKs received and generated */ 466 val = RREG32_PCIE(smnPCIEP_NAK_COUNTER); 467 nak_r = val & 0xFFFF; 468 nak_g = val >> 16; 469 470 /* Add the total number of NAKs, i.e the number of replays */ 471 return (nak_r + nak_g); 472 } 473 474 static void nbio_v7_9_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 475 uint64_t *count1) 476 { 477 uint32_t perfctrrx = 0; 478 uint32_t perfctrtx = 0; 479 480 /* This reports 0 on APUs, so return to avoid writing/reading registers 481 * that may or may not be different from their GPU counterparts 482 */ 483 if (adev->flags & AMD_IS_APU) 484 return; 485 486 /* Use TXCLK3 counter group for rx event */ 487 /* Use TXCLK7 counter group for tx event */ 488 /* Set the 2 events that we wish to watch, defined above */ 489 /* 40 is event# for received msgs */ 490 /* 2 is event# of posted requests sent */ 491 perfctrrx = REG_SET_FIELD(perfctrrx, PCIE_PERF_CNTL_TXCLK3, EVENT0_SEL, 40); 492 perfctrtx = REG_SET_FIELD(perfctrtx, PCIE_PERF_CNTL_TXCLK7, EVENT0_SEL, 2); 493 494 /* Write to enable desired perf counters */ 495 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctrrx); 496 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK7, perfctrtx); 497 498 /* Zero out and enable SHADOW_WR 499 * Write 0x6: 500 * Bit 1 = Global Shadow wr(1) 501 * Bit 2 = Global counter reset enable(1) 502 */ 503 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000006); 504 505 /* Enable Gloabl Counter 506 * Write 0x1: 507 * Bit 0 = Global Counter Enable(1) 508 */ 509 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000001); 510 511 msleep(1000); 512 513 /* Disable Global Counter, Reset and enable SHADOW_WR 514 * Write 0x6: 515 * Bit 1 = Global Shadow wr(1) 516 * Bit 2 = Global counter reset enable(1) 517 */ 518 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000006); 519 520 /* Get the upper and lower count */ 521 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | 522 ((uint64_t)RREG32_PCIE(smnPCIE_PERF_COUNT0_UPVAL_TXCLK3) << 32); 523 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK7) | 524 ((uint64_t)RREG32_PCIE(smnPCIE_PERF_COUNT0_UPVAL_TXCLK7) << 32); 525 } 526 527 const struct amdgpu_nbio_funcs nbio_v7_9_funcs = { 528 .get_hdp_flush_req_offset = nbio_v7_9_get_hdp_flush_req_offset, 529 .get_hdp_flush_done_offset = nbio_v7_9_get_hdp_flush_done_offset, 530 .get_pcie_index_offset = nbio_v7_9_get_pcie_index_offset, 531 .get_pcie_data_offset = nbio_v7_9_get_pcie_data_offset, 532 .get_pcie_index_hi_offset = nbio_v7_9_get_pcie_index_hi_offset, 533 .get_rev_id = nbio_v7_9_get_rev_id, 534 .mc_access_enable = nbio_v7_9_mc_access_enable, 535 .get_memsize = nbio_v7_9_get_memsize, 536 .sdma_doorbell_range = nbio_v7_9_sdma_doorbell_range, 537 .vcn_doorbell_range = nbio_v7_9_vcn_doorbell_range, 538 .enable_doorbell_aperture = nbio_v7_9_enable_doorbell_aperture, 539 .enable_doorbell_selfring_aperture = nbio_v7_9_enable_doorbell_selfring_aperture, 540 .ih_doorbell_range = nbio_v7_9_ih_doorbell_range, 541 .enable_doorbell_interrupt = nbio_v7_9_enable_doorbell_interrupt, 542 .update_medium_grain_clock_gating = nbio_v7_9_update_medium_grain_clock_gating, 543 .update_medium_grain_light_sleep = nbio_v7_9_update_medium_grain_light_sleep, 544 .get_clockgating_state = nbio_v7_9_get_clockgating_state, 545 .ih_control = nbio_v7_9_ih_control, 546 .remap_hdp_registers = nbio_v7_9_remap_hdp_registers, 547 .get_compute_partition_mode = nbio_v7_9_get_compute_partition_mode, 548 .get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode, 549 .init_registers = nbio_v7_9_init_registers, 550 .get_pcie_replay_count = nbio_v7_9_get_pcie_replay_count, 551 .get_pcie_usage = nbio_v7_9_get_pcie_usage, 552 }; 553 554 static void nbio_v7_9_query_ras_error_count(struct amdgpu_device *adev, 555 void *ras_error_status) 556 { 557 } 558 559 static void nbio_v7_9_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev) 560 { 561 uint32_t bif_doorbell_intr_cntl; 562 struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if); 563 struct ras_err_data err_data; 564 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 565 566 if (amdgpu_ras_error_data_init(&err_data)) 567 return; 568 569 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL); 570 571 if (REG_GET_FIELD(bif_doorbell_intr_cntl, 572 BIF_BX0_BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) { 573 /* driver has to clear the interrupt status when bif ring is disabled */ 574 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl, 575 BIF_BX0_BIF_DOORBELL_INT_CNTL, 576 RAS_CNTLR_INTERRUPT_CLEAR, 1); 577 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); 578 579 if (!ras->disable_ras_err_cnt_harvest) { 580 /* 581 * clear error status after ras_controller_intr 582 * according to hw team and count ue number 583 * for query 584 */ 585 nbio_v7_9_query_ras_error_count(adev, &err_data); 586 587 /* logging on error cnt and printing for awareness */ 588 obj->err_data.ue_count += err_data.ue_count; 589 obj->err_data.ce_count += err_data.ce_count; 590 591 if (err_data.ce_count) 592 dev_info(adev->dev, "%ld correctable hardware " 593 "errors detected in %s block, " 594 "no user action is needed.\n", 595 obj->err_data.ce_count, 596 get_ras_block_str(adev->nbio.ras_if)); 597 598 if (err_data.ue_count) 599 dev_info(adev->dev, "%ld uncorrectable hardware " 600 "errors detected in %s block\n", 601 obj->err_data.ue_count, 602 get_ras_block_str(adev->nbio.ras_if)); 603 } 604 605 dev_info(adev->dev, "RAS controller interrupt triggered " 606 "by NBIF error\n"); 607 608 /* ras_controller_int is dedicated for nbif ras error, 609 * not the global interrupt for sync flood 610 */ 611 amdgpu_ras_reset_gpu(adev); 612 } 613 614 amdgpu_ras_error_data_fini(&err_data); 615 } 616 617 static void nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev) 618 { 619 uint32_t bif_doorbell_intr_cntl; 620 621 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL); 622 623 if (REG_GET_FIELD(bif_doorbell_intr_cntl, 624 BIF_BX0_BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) { 625 /* driver has to clear the interrupt status when bif ring is disabled */ 626 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl, 627 BIF_BX0_BIF_DOORBELL_INT_CNTL, 628 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1); 629 630 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); 631 632 amdgpu_ras_global_ras_isr(adev); 633 } 634 } 635 636 static int nbio_v7_9_set_ras_controller_irq_state(struct amdgpu_device *adev, 637 struct amdgpu_irq_src *src, 638 unsigned type, 639 enum amdgpu_interrupt_state state) 640 { 641 /* Dummy function, there is no initialization operation in driver */ 642 643 return 0; 644 } 645 646 static int nbio_v7_9_process_ras_controller_irq(struct amdgpu_device *adev, 647 struct amdgpu_irq_src *source, 648 struct amdgpu_iv_entry *entry) 649 { 650 /* By design, the ih cookie for ras_controller_irq should be written 651 * to BIFring instead of general iv ring. However, due to known bif ring 652 * hw bug, it has to be disabled. There is no chance the process function 653 * will be involked. Just left it as a dummy one. 654 */ 655 return 0; 656 } 657 658 static int nbio_v7_9_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev, 659 struct amdgpu_irq_src *src, 660 unsigned type, 661 enum amdgpu_interrupt_state state) 662 { 663 /* Dummy function, there is no initialization operation in driver */ 664 665 return 0; 666 } 667 668 static int nbio_v7_9_process_err_event_athub_irq(struct amdgpu_device *adev, 669 struct amdgpu_irq_src *source, 670 struct amdgpu_iv_entry *entry) 671 { 672 /* By design, the ih cookie for err_event_athub_irq should be written 673 * to BIFring instead of general iv ring. However, due to known bif ring 674 * hw bug, it has to be disabled. There is no chance the process function 675 * will be involked. Just left it as a dummy one. 676 */ 677 return 0; 678 } 679 680 static const struct amdgpu_irq_src_funcs nbio_v7_9_ras_controller_irq_funcs = { 681 .set = nbio_v7_9_set_ras_controller_irq_state, 682 .process = nbio_v7_9_process_ras_controller_irq, 683 }; 684 685 static const struct amdgpu_irq_src_funcs nbio_v7_9_ras_err_event_athub_irq_funcs = { 686 .set = nbio_v7_9_set_ras_err_event_athub_irq_state, 687 .process = nbio_v7_9_process_err_event_athub_irq, 688 }; 689 690 static int nbio_v7_9_init_ras_controller_interrupt (struct amdgpu_device *adev) 691 { 692 int r; 693 694 /* init the irq funcs */ 695 adev->nbio.ras_controller_irq.funcs = 696 &nbio_v7_9_ras_controller_irq_funcs; 697 adev->nbio.ras_controller_irq.num_types = 1; 698 699 /* register ras controller interrupt */ 700 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 701 NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT, 702 &adev->nbio.ras_controller_irq); 703 704 return r; 705 } 706 707 static int nbio_v7_9_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev) 708 { 709 710 int r; 711 712 /* init the irq funcs */ 713 adev->nbio.ras_err_event_athub_irq.funcs = 714 &nbio_v7_9_ras_err_event_athub_irq_funcs; 715 adev->nbio.ras_err_event_athub_irq.num_types = 1; 716 717 /* register ras err event athub interrupt */ 718 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 719 NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT, 720 &adev->nbio.ras_err_event_athub_irq); 721 722 return r; 723 } 724 725 const struct amdgpu_ras_block_hw_ops nbio_v7_9_ras_hw_ops = { 726 .query_ras_error_count = nbio_v7_9_query_ras_error_count, 727 }; 728 729 struct amdgpu_nbio_ras nbio_v7_9_ras = { 730 .ras_block = { 731 .ras_comm = { 732 .name = "pcie_bif", 733 .block = AMDGPU_RAS_BLOCK__PCIE_BIF, 734 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 735 }, 736 .hw_ops = &nbio_v7_9_ras_hw_ops, 737 .ras_late_init = amdgpu_nbio_ras_late_init, 738 }, 739 .handle_ras_controller_intr_no_bifring = nbio_v7_9_handle_ras_controller_intr_no_bifring, 740 .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring, 741 .init_ras_controller_interrupt = nbio_v7_9_init_ras_controller_interrupt, 742 .init_ras_err_event_athub_interrupt = nbio_v7_9_init_ras_err_event_athub_interrupt, 743 }; 744