1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu_ras.h" 24 #include "amdgpu.h" 25 #include "amdgpu_mca.h" 26 27 #define smnMCMP0_STATUST0 0x03830408 28 #define smnMCMP1_STATUST0 0x03b30408 29 #define smnMCMPIO_STATUST0 0x0c930408 30 31 32 static void mca_v3_0_mp0_query_ras_error_count(struct amdgpu_device *adev, 33 void *ras_error_status) 34 { 35 amdgpu_mca_query_ras_error_count(adev, 36 smnMCMP0_STATUST0, 37 ras_error_status); 38 } 39 40 static int mca_v3_0_mp0_ras_late_init(struct amdgpu_device *adev, void *ras_info) 41 { 42 return amdgpu_mca_ras_late_init(adev, &adev->mca.mp0); 43 } 44 45 static void mca_v3_0_mp0_ras_fini(struct amdgpu_device *adev) 46 { 47 amdgpu_mca_ras_fini(adev, &adev->mca.mp0); 48 } 49 50 static int mca_v3_0_ras_block_match(struct amdgpu_ras_block_object *block_obj, 51 enum amdgpu_ras_block block, uint32_t sub_block_index) 52 { 53 if (!block_obj) 54 return -EINVAL; 55 56 if ((block_obj->ras_comm.block == block) && 57 (block_obj->ras_comm.sub_block_index == sub_block_index)) { 58 return 0; 59 } 60 61 return -EINVAL; 62 } 63 64 const struct amdgpu_ras_block_hw_ops mca_v3_0_mp0_hw_ops = { 65 .query_ras_error_count = mca_v3_0_mp0_query_ras_error_count, 66 .query_ras_error_address = NULL, 67 }; 68 69 struct amdgpu_mca_ras_block mca_v3_0_mp0_ras = { 70 .ras_block = { 71 .ras_comm = { 72 .block = AMDGPU_RAS_BLOCK__MCA, 73 .sub_block_index = AMDGPU_RAS_MCA_BLOCK__MP0, 74 .name = "mp0", 75 }, 76 .hw_ops = &mca_v3_0_mp0_hw_ops, 77 .ras_block_match = mca_v3_0_ras_block_match, 78 .ras_late_init = mca_v3_0_mp0_ras_late_init, 79 .ras_fini = mca_v3_0_mp0_ras_fini, 80 }, 81 }; 82 83 static void mca_v3_0_mp1_query_ras_error_count(struct amdgpu_device *adev, 84 void *ras_error_status) 85 { 86 amdgpu_mca_query_ras_error_count(adev, 87 smnMCMP1_STATUST0, 88 ras_error_status); 89 } 90 91 static int mca_v3_0_mp1_ras_late_init(struct amdgpu_device *adev, void *ras_info) 92 { 93 return amdgpu_mca_ras_late_init(adev, &adev->mca.mp1); 94 } 95 96 static void mca_v3_0_mp1_ras_fini(struct amdgpu_device *adev) 97 { 98 amdgpu_mca_ras_fini(adev, &adev->mca.mp1); 99 } 100 101 const struct amdgpu_ras_block_hw_ops mca_v3_0_mp1_hw_ops = { 102 .query_ras_error_count = mca_v3_0_mp1_query_ras_error_count, 103 .query_ras_error_address = NULL, 104 }; 105 106 struct amdgpu_mca_ras_block mca_v3_0_mp1_ras = { 107 .ras_block = { 108 .ras_comm = { 109 .block = AMDGPU_RAS_BLOCK__MCA, 110 .sub_block_index = AMDGPU_RAS_MCA_BLOCK__MP1, 111 .name = "mp1", 112 }, 113 .hw_ops = &mca_v3_0_mp1_hw_ops, 114 .ras_block_match = mca_v3_0_ras_block_match, 115 .ras_late_init = mca_v3_0_mp1_ras_late_init, 116 .ras_fini = mca_v3_0_mp1_ras_fini, 117 }, 118 }; 119 120 static void mca_v3_0_mpio_query_ras_error_count(struct amdgpu_device *adev, 121 void *ras_error_status) 122 { 123 amdgpu_mca_query_ras_error_count(adev, 124 smnMCMPIO_STATUST0, 125 ras_error_status); 126 } 127 128 static int mca_v3_0_mpio_ras_late_init(struct amdgpu_device *adev, void *ras_info) 129 { 130 return amdgpu_mca_ras_late_init(adev, &adev->mca.mpio); 131 } 132 133 static void mca_v3_0_mpio_ras_fini(struct amdgpu_device *adev) 134 { 135 amdgpu_mca_ras_fini(adev, &adev->mca.mpio); 136 } 137 138 const struct amdgpu_ras_block_hw_ops mca_v3_0_mpio_hw_ops = { 139 .query_ras_error_count = mca_v3_0_mpio_query_ras_error_count, 140 .query_ras_error_address = NULL, 141 }; 142 143 struct amdgpu_mca_ras_block mca_v3_0_mpio_ras = { 144 .ras_block = { 145 .ras_comm = { 146 .block = AMDGPU_RAS_BLOCK__MCA, 147 .sub_block_index = AMDGPU_RAS_MCA_BLOCK__MPIO, 148 .name = "mpio", 149 }, 150 .hw_ops = &mca_v3_0_mpio_hw_ops, 151 .ras_block_match = mca_v3_0_ras_block_match, 152 .ras_late_init = mca_v3_0_mpio_ras_late_init, 153 .ras_fini = mca_v3_0_mpio_ras_fini, 154 }, 155 }; 156 157 158 static void mca_v3_0_init(struct amdgpu_device *adev) 159 { 160 struct amdgpu_mca *mca = &adev->mca; 161 162 mca->mp0.ras = &mca_v3_0_mp0_ras; 163 mca->mp1.ras = &mca_v3_0_mp1_ras; 164 mca->mpio.ras = &mca_v3_0_mpio_ras; 165 amdgpu_ras_register_ras_block(adev, &mca->mp0.ras->ras_block); 166 amdgpu_ras_register_ras_block(adev, &mca->mp1.ras->ras_block); 167 amdgpu_ras_register_ras_block(adev, &mca->mpio.ras->ras_block); 168 } 169 170 const struct amdgpu_mca_funcs mca_v3_0_funcs = { 171 .init = mca_v3_0_init, 172 };