1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2024 Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "amdgpu_pm.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "jpeg_v4_0_3.h" 30 #include "jpeg_v5_0_1.h" 31 32 #include "vcn/vcn_5_0_0_offset.h" 33 #include "vcn/vcn_5_0_0_sh_mask.h" 34 #include "ivsrcid/vcn/irqsrcs_vcn_5_0.h" 35 36 static void jpeg_v5_0_1_set_dec_ring_funcs(struct amdgpu_device *adev); 37 static void jpeg_v5_0_1_set_irq_funcs(struct amdgpu_device *adev); 38 static int jpeg_v5_0_1_set_powergating_state(struct amdgpu_ip_block *ip_block, 39 enum amd_powergating_state state); 40 static void jpeg_v5_0_1_dec_ring_set_wptr(struct amdgpu_ring *ring); 41 42 static int amdgpu_ih_srcid_jpeg[] = { 43 VCN_5_0__SRCID__JPEG_DECODE, 44 VCN_5_0__SRCID__JPEG1_DECODE, 45 VCN_5_0__SRCID__JPEG2_DECODE, 46 VCN_5_0__SRCID__JPEG3_DECODE, 47 VCN_5_0__SRCID__JPEG4_DECODE, 48 VCN_5_0__SRCID__JPEG5_DECODE, 49 VCN_5_0__SRCID__JPEG6_DECODE, 50 VCN_5_0__SRCID__JPEG7_DECODE, 51 VCN_5_0__SRCID__JPEG8_DECODE, 52 VCN_5_0__SRCID__JPEG9_DECODE, 53 }; 54 55 static const struct amdgpu_hwip_reg_entry jpeg_reg_list_5_0_1[] = { 56 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS), 57 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT), 58 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR), 59 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR), 60 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS), 61 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE), 62 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG), 63 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE), 64 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE), 65 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH), 66 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH), 67 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_RPTR), 68 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_WPTR), 69 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_STATUS), 70 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_RPTR), 71 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_WPTR), 72 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_STATUS), 73 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_RPTR), 74 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_WPTR), 75 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_STATUS), 76 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_RPTR), 77 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_WPTR), 78 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_STATUS), 79 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_RPTR), 80 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_WPTR), 81 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_STATUS), 82 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_RPTR), 83 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_WPTR), 84 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_STATUS), 85 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_RPTR), 86 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_WPTR), 87 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_STATUS), 88 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_RB_RPTR), 89 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_RB_WPTR), 90 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_STATUS), 91 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_RB_RPTR), 92 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_RB_WPTR), 93 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_STATUS), 94 }; 95 96 static int jpeg_v5_0_1_core_reg_offset(u32 pipe) 97 { 98 if (pipe <= AMDGPU_MAX_JPEG_RINGS_4_0_3) 99 return ((0x40 * pipe) - 0xc80); 100 else 101 return ((0x40 * pipe) - 0x440); 102 } 103 104 /** 105 * jpeg_v5_0_1_early_init - set function pointers 106 * 107 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 108 * 109 * Set ring and irq function pointers 110 */ 111 static int jpeg_v5_0_1_early_init(struct amdgpu_ip_block *ip_block) 112 { 113 struct amdgpu_device *adev = ip_block->adev; 114 115 if (!adev->jpeg.num_jpeg_inst || adev->jpeg.num_jpeg_inst > AMDGPU_MAX_JPEG_INSTANCES) 116 return -ENOENT; 117 118 adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS; 119 jpeg_v5_0_1_set_dec_ring_funcs(adev); 120 jpeg_v5_0_1_set_irq_funcs(adev); 121 122 return 0; 123 } 124 125 /** 126 * jpeg_v5_0_1_sw_init - sw init for JPEG block 127 * 128 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 129 * 130 * Load firmware and sw initialization 131 */ 132 static int jpeg_v5_0_1_sw_init(struct amdgpu_ip_block *ip_block) 133 { 134 struct amdgpu_device *adev = ip_block->adev; 135 struct amdgpu_ring *ring; 136 int i, j, r, jpeg_inst; 137 138 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 139 /* JPEG TRAP */ 140 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 141 amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq); 142 if (r) 143 return r; 144 } 145 146 r = amdgpu_jpeg_sw_init(adev); 147 if (r) 148 return r; 149 150 r = amdgpu_jpeg_resume(adev); 151 if (r) 152 return r; 153 154 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 155 jpeg_inst = GET_INST(JPEG, i); 156 157 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 158 ring = &adev->jpeg.inst[i].ring_dec[j]; 159 ring->use_doorbell = false; 160 ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id); 161 if (!amdgpu_sriov_vf(adev)) { 162 ring->doorbell_index = 163 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 164 1 + j + 11 * jpeg_inst; 165 } else { 166 if (j < 4) 167 ring->doorbell_index = 168 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 169 4 + j + 32 * jpeg_inst; 170 else 171 ring->doorbell_index = 172 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 173 8 + j + 32 * jpeg_inst; 174 } 175 sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j); 176 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, 177 AMDGPU_RING_PRIO_DEFAULT, NULL); 178 if (r) 179 return r; 180 181 adev->jpeg.internal.jpeg_pitch[j] = 182 regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET; 183 adev->jpeg.inst[i].external.jpeg_pitch[j] = 184 SOC15_REG_OFFSET1(JPEG, jpeg_inst, regUVD_JRBC_SCRATCH0, 185 (j ? jpeg_v5_0_1_core_reg_offset(j) : 0)); 186 } 187 } 188 189 r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_5_0_1, ARRAY_SIZE(jpeg_reg_list_5_0_1)); 190 if (r) 191 return r; 192 193 if (!amdgpu_sriov_vf(adev)) { 194 adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE; 195 r = amdgpu_jpeg_sysfs_reset_mask_init(adev); 196 if (r) 197 return r; 198 } 199 200 return 0; 201 } 202 203 /** 204 * jpeg_v5_0_1_sw_fini - sw fini for JPEG block 205 * 206 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 207 * 208 * JPEG suspend and free up sw allocation 209 */ 210 static int jpeg_v5_0_1_sw_fini(struct amdgpu_ip_block *ip_block) 211 { 212 struct amdgpu_device *adev = ip_block->adev; 213 int r; 214 215 r = amdgpu_jpeg_suspend(adev); 216 if (r) 217 return r; 218 219 if (!amdgpu_sriov_vf(adev)) 220 amdgpu_jpeg_sysfs_reset_mask_fini(adev); 221 222 r = amdgpu_jpeg_sw_fini(adev); 223 224 return r; 225 } 226 227 /** 228 * jpeg_v5_0_1_hw_init - start and test JPEG block 229 * 230 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 231 * 232 */ 233 static int jpeg_v5_0_1_hw_init(struct amdgpu_ip_block *ip_block) 234 { 235 struct amdgpu_device *adev = ip_block->adev; 236 struct amdgpu_ring *ring; 237 int i, j, r, jpeg_inst; 238 239 if (amdgpu_sriov_vf(adev)) { 240 /* jpeg_v5_0_1_start_sriov(adev); */ 241 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 242 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 243 ring = &adev->jpeg.inst[i].ring_dec[j]; 244 ring->wptr = 0; 245 ring->wptr_old = 0; 246 jpeg_v5_0_1_dec_ring_set_wptr(ring); 247 ring->sched.ready = true; 248 } 249 } 250 return 0; 251 } 252 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 253 jpeg_inst = GET_INST(JPEG, i); 254 ring = adev->jpeg.inst[i].ring_dec; 255 if (ring->use_doorbell) 256 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 257 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 11 * jpeg_inst, 258 adev->jpeg.inst[i].aid_id); 259 260 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 261 ring = &adev->jpeg.inst[i].ring_dec[j]; 262 if (ring->use_doorbell) 263 WREG32_SOC15_OFFSET(VCN, GET_INST(VCN, i), regVCN_JPEG_DB_CTRL, 264 (ring->pipe ? (ring->pipe - 0x15) : 0), 265 ring->doorbell_index << 266 VCN_JPEG_DB_CTRL__OFFSET__SHIFT | 267 VCN_JPEG_DB_CTRL__EN_MASK); 268 r = amdgpu_ring_test_helper(ring); 269 if (r) 270 return r; 271 } 272 } 273 274 return 0; 275 } 276 277 /** 278 * jpeg_v5_0_1_hw_fini - stop the hardware block 279 * 280 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 281 * 282 * Stop the JPEG block, mark ring as not ready any more 283 */ 284 static int jpeg_v5_0_1_hw_fini(struct amdgpu_ip_block *ip_block) 285 { 286 struct amdgpu_device *adev = ip_block->adev; 287 int ret = 0; 288 289 cancel_delayed_work_sync(&adev->jpeg.idle_work); 290 291 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE) 292 ret = jpeg_v5_0_1_set_powergating_state(ip_block, AMD_PG_STATE_GATE); 293 294 return ret; 295 } 296 297 /** 298 * jpeg_v5_0_1_suspend - suspend JPEG block 299 * 300 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 301 * 302 * HW fini and suspend JPEG block 303 */ 304 static int jpeg_v5_0_1_suspend(struct amdgpu_ip_block *ip_block) 305 { 306 struct amdgpu_device *adev = ip_block->adev; 307 int r; 308 309 r = jpeg_v5_0_1_hw_fini(ip_block); 310 if (r) 311 return r; 312 313 r = amdgpu_jpeg_suspend(adev); 314 315 return r; 316 } 317 318 /** 319 * jpeg_v5_0_1_resume - resume JPEG block 320 * 321 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 322 * 323 * Resume firmware and hw init JPEG block 324 */ 325 static int jpeg_v5_0_1_resume(struct amdgpu_ip_block *ip_block) 326 { 327 struct amdgpu_device *adev = ip_block->adev; 328 int r; 329 330 r = amdgpu_jpeg_resume(adev); 331 if (r) 332 return r; 333 334 r = jpeg_v5_0_1_hw_init(ip_block); 335 336 return r; 337 } 338 339 static void jpeg_v5_0_1_init_inst(struct amdgpu_device *adev, int i) 340 { 341 int jpeg_inst = GET_INST(JPEG, i); 342 343 /* disable anti hang mechanism */ 344 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 0, 345 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 346 347 /* keep the JPEG in static PG mode */ 348 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 0, 349 ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK); 350 351 /* MJPEG global tiling registers */ 352 WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG, 353 adev->gfx.config.gb_addr_config); 354 355 /* enable JMI channel */ 356 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0, 357 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 358 } 359 360 static void jpeg_v5_0_1_deinit_inst(struct amdgpu_device *adev, int i) 361 { 362 int jpeg_inst = GET_INST(JPEG, i); 363 /* reset JMI */ 364 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 365 UVD_JMI_CNTL__SOFT_RESET_MASK, 366 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 367 368 /* enable anti hang mechanism */ 369 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 370 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 371 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 372 } 373 374 static void jpeg_v5_0_1_init_jrbc(struct amdgpu_ring *ring) 375 { 376 struct amdgpu_device *adev = ring->adev; 377 u32 reg, data, mask; 378 int jpeg_inst = GET_INST(JPEG, ring->me); 379 int reg_offset = ring->pipe ? jpeg_v5_0_1_core_reg_offset(ring->pipe) : 0; 380 381 /* enable System Interrupt for JRBC */ 382 reg = SOC15_REG_OFFSET(JPEG, jpeg_inst, regJPEG_SYS_INT_EN); 383 if (ring->pipe < AMDGPU_MAX_JPEG_RINGS_4_0_3) { 384 data = JPEG_SYS_INT_EN__DJRBC0_MASK << ring->pipe; 385 mask = ~(JPEG_SYS_INT_EN__DJRBC0_MASK << ring->pipe); 386 WREG32_P(reg, data, mask); 387 } else { 388 data = JPEG_SYS_INT_EN__DJRBC0_MASK << (ring->pipe+12); 389 mask = ~(JPEG_SYS_INT_EN__DJRBC0_MASK << (ring->pipe+12)); 390 WREG32_P(reg, data, mask); 391 } 392 393 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 394 regUVD_LMI_JRBC_RB_VMID, 395 reg_offset, 0); 396 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 397 regUVD_JRBC_RB_CNTL, 398 reg_offset, 399 (0x00000001L | 0x00000002L)); 400 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 401 regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 402 reg_offset, lower_32_bits(ring->gpu_addr)); 403 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 404 regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 405 reg_offset, upper_32_bits(ring->gpu_addr)); 406 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 407 regUVD_JRBC_RB_RPTR, 408 reg_offset, 0); 409 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 410 regUVD_JRBC_RB_WPTR, 411 reg_offset, 0); 412 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 413 regUVD_JRBC_RB_CNTL, 414 reg_offset, 0x00000002L); 415 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 416 regUVD_JRBC_RB_SIZE, 417 reg_offset, ring->ring_size / 4); 418 ring->wptr = RREG32_SOC15_OFFSET(JPEG, jpeg_inst, regUVD_JRBC_RB_WPTR, 419 reg_offset); 420 } 421 422 /** 423 * jpeg_v5_0_1_start - start JPEG block 424 * 425 * @adev: amdgpu_device pointer 426 * 427 * Setup and start the JPEG block 428 */ 429 static int jpeg_v5_0_1_start(struct amdgpu_device *adev) 430 { 431 struct amdgpu_ring *ring; 432 int i, j; 433 434 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 435 jpeg_v5_0_1_init_inst(adev, i); 436 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 437 ring = &adev->jpeg.inst[i].ring_dec[j]; 438 jpeg_v5_0_1_init_jrbc(ring); 439 } 440 } 441 442 return 0; 443 } 444 445 /** 446 * jpeg_v5_0_1_stop - stop JPEG block 447 * 448 * @adev: amdgpu_device pointer 449 * 450 * stop the JPEG block 451 */ 452 static int jpeg_v5_0_1_stop(struct amdgpu_device *adev) 453 { 454 int i; 455 456 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) 457 jpeg_v5_0_1_deinit_inst(adev, i); 458 459 return 0; 460 } 461 462 /** 463 * jpeg_v5_0_1_dec_ring_get_rptr - get read pointer 464 * 465 * @ring: amdgpu_ring pointer 466 * 467 * Returns the current hardware read pointer 468 */ 469 static uint64_t jpeg_v5_0_1_dec_ring_get_rptr(struct amdgpu_ring *ring) 470 { 471 struct amdgpu_device *adev = ring->adev; 472 473 return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC_RB_RPTR, 474 ring->pipe ? jpeg_v5_0_1_core_reg_offset(ring->pipe) : 0); 475 } 476 477 /** 478 * jpeg_v5_0_1_dec_ring_get_wptr - get write pointer 479 * 480 * @ring: amdgpu_ring pointer 481 * 482 * Returns the current hardware write pointer 483 */ 484 static uint64_t jpeg_v5_0_1_dec_ring_get_wptr(struct amdgpu_ring *ring) 485 { 486 struct amdgpu_device *adev = ring->adev; 487 488 if (ring->use_doorbell) 489 return adev->wb.wb[ring->wptr_offs]; 490 491 return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC_RB_WPTR, 492 ring->pipe ? jpeg_v5_0_1_core_reg_offset(ring->pipe) : 0); 493 } 494 495 /** 496 * jpeg_v5_0_1_dec_ring_set_wptr - set write pointer 497 * 498 * @ring: amdgpu_ring pointer 499 * 500 * Commits the write pointer to the hardware 501 */ 502 static void jpeg_v5_0_1_dec_ring_set_wptr(struct amdgpu_ring *ring) 503 { 504 struct amdgpu_device *adev = ring->adev; 505 506 if (ring->use_doorbell) { 507 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 508 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 509 } else { 510 WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), 511 regUVD_JRBC_RB_WPTR, 512 (ring->pipe ? jpeg_v5_0_1_core_reg_offset(ring->pipe) : 0), 513 lower_32_bits(ring->wptr)); 514 } 515 } 516 517 static bool jpeg_v5_0_1_is_idle(struct amdgpu_ip_block *ip_block) 518 { 519 struct amdgpu_device *adev = ip_block->adev; 520 bool ret = false; 521 int i, j; 522 523 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 524 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 525 int reg_offset = (j ? jpeg_v5_0_1_core_reg_offset(j) : 0); 526 527 ret &= ((RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, i), 528 regUVD_JRBC_STATUS, reg_offset) & 529 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 530 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 531 } 532 } 533 534 return ret; 535 } 536 537 static int jpeg_v5_0_1_wait_for_idle(struct amdgpu_ip_block *ip_block) 538 { 539 struct amdgpu_device *adev = ip_block->adev; 540 int ret = 0; 541 int i, j; 542 543 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 544 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 545 int reg_offset = (j ? jpeg_v5_0_1_core_reg_offset(j) : 0); 546 547 ret &= SOC15_WAIT_ON_RREG_OFFSET(JPEG, GET_INST(JPEG, i), 548 regUVD_JRBC_STATUS, reg_offset, 549 UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 550 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 551 } 552 } 553 return ret; 554 } 555 556 static int jpeg_v5_0_1_set_clockgating_state(struct amdgpu_ip_block *ip_block, 557 enum amd_clockgating_state state) 558 { 559 struct amdgpu_device *adev = ip_block->adev; 560 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 561 562 int i; 563 564 if (!enable) 565 return 0; 566 567 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 568 if (!jpeg_v5_0_1_is_idle(ip_block)) 569 return -EBUSY; 570 } 571 572 return 0; 573 } 574 575 static int jpeg_v5_0_1_set_powergating_state(struct amdgpu_ip_block *ip_block, 576 enum amd_powergating_state state) 577 { 578 struct amdgpu_device *adev = ip_block->adev; 579 int ret; 580 581 if (state == adev->jpeg.cur_state) 582 return 0; 583 584 if (state == AMD_PG_STATE_GATE) 585 ret = jpeg_v5_0_1_stop(adev); 586 else 587 ret = jpeg_v5_0_1_start(adev); 588 589 if (!ret) 590 adev->jpeg.cur_state = state; 591 592 return ret; 593 } 594 595 static int jpeg_v5_0_1_set_interrupt_state(struct amdgpu_device *adev, 596 struct amdgpu_irq_src *source, 597 unsigned int type, 598 enum amdgpu_interrupt_state state) 599 { 600 return 0; 601 } 602 603 static int jpeg_v5_0_1_process_interrupt(struct amdgpu_device *adev, 604 struct amdgpu_irq_src *source, 605 struct amdgpu_iv_entry *entry) 606 { 607 u32 i, inst; 608 609 i = node_id_to_phys_map[entry->node_id]; 610 DRM_DEV_DEBUG(adev->dev, "IH: JPEG TRAP\n"); 611 612 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst) 613 if (adev->jpeg.inst[inst].aid_id == i) 614 break; 615 616 if (inst >= adev->jpeg.num_jpeg_inst) { 617 dev_WARN_ONCE(adev->dev, 1, 618 "Interrupt received for unknown JPEG instance %d", 619 entry->node_id); 620 return 0; 621 } 622 623 switch (entry->src_id) { 624 case VCN_5_0__SRCID__JPEG_DECODE: 625 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]); 626 break; 627 case VCN_5_0__SRCID__JPEG1_DECODE: 628 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[1]); 629 break; 630 case VCN_5_0__SRCID__JPEG2_DECODE: 631 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[2]); 632 break; 633 case VCN_5_0__SRCID__JPEG3_DECODE: 634 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[3]); 635 break; 636 case VCN_5_0__SRCID__JPEG4_DECODE: 637 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[4]); 638 break; 639 case VCN_5_0__SRCID__JPEG5_DECODE: 640 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[5]); 641 break; 642 case VCN_5_0__SRCID__JPEG6_DECODE: 643 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[6]); 644 break; 645 case VCN_5_0__SRCID__JPEG7_DECODE: 646 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[7]); 647 break; 648 case VCN_5_0__SRCID__JPEG8_DECODE: 649 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[8]); 650 break; 651 case VCN_5_0__SRCID__JPEG9_DECODE: 652 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[9]); 653 break; 654 default: 655 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 656 entry->src_id, entry->src_data[0]); 657 break; 658 } 659 660 return 0; 661 } 662 663 static void jpeg_v5_0_1_core_stall_reset(struct amdgpu_ring *ring) 664 { 665 struct amdgpu_device *adev = ring->adev; 666 int jpeg_inst = GET_INST(JPEG, ring->me); 667 int reg_offset = ring->pipe ? jpeg_v5_0_1_core_reg_offset(ring->pipe) : 0; 668 669 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 670 regUVD_JMI0_UVD_JMI_CLIENT_STALL, 671 reg_offset, 0x1F); 672 SOC15_WAIT_ON_RREG(JPEG, jpeg_inst, 673 regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS, 674 0x1F, 0x1F); 675 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 676 regUVD_JMI0_JPEG_LMI_DROP, 677 reg_offset, 0x1F); 678 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 679 regJPEG_CORE_RST_CTRL, 680 reg_offset, 1 << ring->pipe); 681 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 682 regUVD_JMI0_UVD_JMI_CLIENT_STALL, 683 reg_offset, 0x00); 684 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 685 regUVD_JMI0_JPEG_LMI_DROP, 686 reg_offset, 0x00); 687 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 688 regJPEG_CORE_RST_CTRL, 689 reg_offset, 0x00); 690 } 691 692 static int jpeg_v5_0_1_ring_reset(struct amdgpu_ring *ring, unsigned int vmid) 693 { 694 if (amdgpu_sriov_vf(ring->adev)) 695 return -EOPNOTSUPP; 696 697 jpeg_v5_0_1_core_stall_reset(ring); 698 jpeg_v5_0_1_init_jrbc(ring); 699 return amdgpu_ring_test_helper(ring); 700 } 701 702 static const struct amd_ip_funcs jpeg_v5_0_1_ip_funcs = { 703 .name = "jpeg_v5_0_1", 704 .early_init = jpeg_v5_0_1_early_init, 705 .late_init = NULL, 706 .sw_init = jpeg_v5_0_1_sw_init, 707 .sw_fini = jpeg_v5_0_1_sw_fini, 708 .hw_init = jpeg_v5_0_1_hw_init, 709 .hw_fini = jpeg_v5_0_1_hw_fini, 710 .suspend = jpeg_v5_0_1_suspend, 711 .resume = jpeg_v5_0_1_resume, 712 .is_idle = jpeg_v5_0_1_is_idle, 713 .wait_for_idle = jpeg_v5_0_1_wait_for_idle, 714 .check_soft_reset = NULL, 715 .pre_soft_reset = NULL, 716 .soft_reset = NULL, 717 .post_soft_reset = NULL, 718 .set_clockgating_state = jpeg_v5_0_1_set_clockgating_state, 719 .set_powergating_state = jpeg_v5_0_1_set_powergating_state, 720 .dump_ip_state = amdgpu_jpeg_dump_ip_state, 721 .print_ip_state = amdgpu_jpeg_print_ip_state, 722 }; 723 724 static const struct amdgpu_ring_funcs jpeg_v5_0_1_dec_ring_vm_funcs = { 725 .type = AMDGPU_RING_TYPE_VCN_JPEG, 726 .align_mask = 0xf, 727 .get_rptr = jpeg_v5_0_1_dec_ring_get_rptr, 728 .get_wptr = jpeg_v5_0_1_dec_ring_get_wptr, 729 .set_wptr = jpeg_v5_0_1_dec_ring_set_wptr, 730 .emit_frame_size = 731 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 732 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 733 8 + /* jpeg_v5_0_1_dec_ring_emit_vm_flush */ 734 22 + 22 + /* jpeg_v5_0_1_dec_ring_emit_fence x2 vm fence */ 735 8 + 16, 736 .emit_ib_size = 22, /* jpeg_v5_0_1_dec_ring_emit_ib */ 737 .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib, 738 .emit_fence = jpeg_v4_0_3_dec_ring_emit_fence, 739 .emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush, 740 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 741 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 742 .insert_nop = jpeg_v4_0_3_dec_ring_nop, 743 .insert_start = jpeg_v4_0_3_dec_ring_insert_start, 744 .insert_end = jpeg_v4_0_3_dec_ring_insert_end, 745 .pad_ib = amdgpu_ring_generic_pad_ib, 746 .begin_use = amdgpu_jpeg_ring_begin_use, 747 .end_use = amdgpu_jpeg_ring_end_use, 748 .emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg, 749 .emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait, 750 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 751 .reset = jpeg_v5_0_1_ring_reset, 752 }; 753 754 static void jpeg_v5_0_1_set_dec_ring_funcs(struct amdgpu_device *adev) 755 { 756 int i, j, jpeg_inst; 757 758 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 759 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 760 adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v5_0_1_dec_ring_vm_funcs; 761 adev->jpeg.inst[i].ring_dec[j].me = i; 762 adev->jpeg.inst[i].ring_dec[j].pipe = j; 763 } 764 jpeg_inst = GET_INST(JPEG, i); 765 adev->jpeg.inst[i].aid_id = 766 jpeg_inst / adev->jpeg.num_inst_per_aid; 767 } 768 } 769 770 static const struct amdgpu_irq_src_funcs jpeg_v5_0_1_irq_funcs = { 771 .set = jpeg_v5_0_1_set_interrupt_state, 772 .process = jpeg_v5_0_1_process_interrupt, 773 }; 774 775 static void jpeg_v5_0_1_set_irq_funcs(struct amdgpu_device *adev) 776 { 777 int i; 778 779 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) 780 adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings; 781 782 adev->jpeg.inst->irq.funcs = &jpeg_v5_0_1_irq_funcs; 783 } 784 785 const struct amdgpu_ip_block_version jpeg_v5_0_1_ip_block = { 786 .type = AMD_IP_BLOCK_TYPE_JPEG, 787 .major = 5, 788 .minor = 0, 789 .rev = 1, 790 .funcs = &jpeg_v5_0_1_ip_funcs, 791 }; 792