1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "soc15.h" 27 #include "soc15d.h" 28 #include "jpeg_v2_0.h" 29 #include "jpeg_v2_5.h" 30 31 #include "vcn/vcn_2_5_offset.h" 32 #include "vcn/vcn_2_5_sh_mask.h" 33 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 34 35 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f 36 37 #define JPEG25_MAX_HW_INSTANCES_ARCTURUS 2 38 39 static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev); 40 static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev); 41 static int jpeg_v2_5_set_powergating_state(void *handle, 42 enum amd_powergating_state state); 43 static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev); 44 45 static int amdgpu_ih_clientid_jpeg[] = { 46 SOC15_IH_CLIENTID_VCN, 47 SOC15_IH_CLIENTID_VCN1 48 }; 49 50 /** 51 * jpeg_v2_5_early_init - set function pointers 52 * 53 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 54 * 55 * Set ring and irq function pointers 56 */ 57 static int jpeg_v2_5_early_init(struct amdgpu_ip_block *ip_block) 58 { 59 struct amdgpu_device *adev = ip_block->adev; 60 u32 harvest; 61 int i; 62 63 adev->jpeg.num_jpeg_rings = 1; 64 adev->jpeg.num_jpeg_inst = JPEG25_MAX_HW_INSTANCES_ARCTURUS; 65 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 66 harvest = RREG32_SOC15(JPEG, i, mmCC_UVD_HARVESTING); 67 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) 68 adev->jpeg.harvest_config |= 1 << i; 69 } 70 if (adev->jpeg.harvest_config == (AMDGPU_JPEG_HARVEST_JPEG0 | 71 AMDGPU_JPEG_HARVEST_JPEG1)) 72 return -ENOENT; 73 74 jpeg_v2_5_set_dec_ring_funcs(adev); 75 jpeg_v2_5_set_irq_funcs(adev); 76 jpeg_v2_5_set_ras_funcs(adev); 77 78 return 0; 79 } 80 81 /** 82 * jpeg_v2_5_sw_init - sw init for JPEG block 83 * 84 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 85 * 86 * Load firmware and sw initialization 87 */ 88 static int jpeg_v2_5_sw_init(struct amdgpu_ip_block *ip_block) 89 { 90 struct amdgpu_ring *ring; 91 int i, r; 92 struct amdgpu_device *adev = ip_block->adev; 93 94 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 95 if (adev->jpeg.harvest_config & (1 << i)) 96 continue; 97 98 /* JPEG TRAP */ 99 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i], 100 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq); 101 if (r) 102 return r; 103 104 /* JPEG DJPEG POISON EVENT */ 105 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i], 106 VCN_2_6__SRCID_DJPEG0_POISON, &adev->jpeg.inst[i].ras_poison_irq); 107 if (r) 108 return r; 109 110 /* JPEG EJPEG POISON EVENT */ 111 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i], 112 VCN_2_6__SRCID_EJPEG0_POISON, &adev->jpeg.inst[i].ras_poison_irq); 113 if (r) 114 return r; 115 } 116 117 r = amdgpu_jpeg_sw_init(adev); 118 if (r) 119 return r; 120 121 r = amdgpu_jpeg_resume(adev); 122 if (r) 123 return r; 124 125 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 126 if (adev->jpeg.harvest_config & (1 << i)) 127 continue; 128 129 ring = adev->jpeg.inst[i].ring_dec; 130 ring->use_doorbell = true; 131 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(2, 5, 0)) 132 ring->vm_hub = AMDGPU_MMHUB1(0); 133 else 134 ring->vm_hub = AMDGPU_MMHUB0(0); 135 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8 * i; 136 sprintf(ring->name, "jpeg_dec_%d", i); 137 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq, 138 0, AMDGPU_RING_PRIO_DEFAULT, NULL); 139 if (r) 140 return r; 141 142 adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; 143 adev->jpeg.inst[i].external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_PITCH); 144 } 145 146 r = amdgpu_jpeg_ras_sw_init(adev); 147 if (r) 148 return r; 149 150 return 0; 151 } 152 153 /** 154 * jpeg_v2_5_sw_fini - sw fini for JPEG block 155 * 156 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 157 * 158 * JPEG suspend and free up sw allocation 159 */ 160 static int jpeg_v2_5_sw_fini(struct amdgpu_ip_block *ip_block) 161 { 162 int r; 163 struct amdgpu_device *adev = ip_block->adev; 164 165 r = amdgpu_jpeg_suspend(adev); 166 if (r) 167 return r; 168 169 r = amdgpu_jpeg_sw_fini(adev); 170 171 return r; 172 } 173 174 /** 175 * jpeg_v2_5_hw_init - start and test JPEG block 176 * 177 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 178 * 179 */ 180 static int jpeg_v2_5_hw_init(struct amdgpu_ip_block *ip_block) 181 { 182 struct amdgpu_device *adev = ip_block->adev; 183 struct amdgpu_ring *ring; 184 int i, r; 185 186 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 187 if (adev->jpeg.harvest_config & (1 << i)) 188 continue; 189 190 ring = adev->jpeg.inst[i].ring_dec; 191 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 192 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i, i); 193 194 r = amdgpu_ring_test_helper(ring); 195 if (r) 196 return r; 197 } 198 199 return 0; 200 } 201 202 /** 203 * jpeg_v2_5_hw_fini - stop the hardware block 204 * 205 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 206 * 207 * Stop the JPEG block, mark ring as not ready any more 208 */ 209 static int jpeg_v2_5_hw_fini(struct amdgpu_ip_block *ip_block) 210 { 211 struct amdgpu_device *adev = ip_block->adev; 212 int i; 213 214 cancel_delayed_work_sync(&adev->vcn.idle_work); 215 216 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 217 if (adev->jpeg.harvest_config & (1 << i)) 218 continue; 219 220 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && 221 RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS)) 222 jpeg_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE); 223 224 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) 225 amdgpu_irq_put(adev, &adev->jpeg.inst[i].ras_poison_irq, 0); 226 } 227 228 return 0; 229 } 230 231 /** 232 * jpeg_v2_5_suspend - suspend JPEG block 233 * 234 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 235 * 236 * HW fini and suspend JPEG block 237 */ 238 static int jpeg_v2_5_suspend(struct amdgpu_ip_block *ip_block) 239 { 240 int r; 241 242 r = jpeg_v2_5_hw_fini(ip_block); 243 if (r) 244 return r; 245 246 r = amdgpu_jpeg_suspend(ip_block->adev); 247 248 return r; 249 } 250 251 /** 252 * jpeg_v2_5_resume - resume JPEG block 253 * 254 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 255 * 256 * Resume firmware and hw init JPEG block 257 */ 258 static int jpeg_v2_5_resume(struct amdgpu_ip_block *ip_block) 259 { 260 int r; 261 262 r = amdgpu_jpeg_resume(ip_block->adev); 263 if (r) 264 return r; 265 266 r = jpeg_v2_5_hw_init(ip_block); 267 268 return r; 269 } 270 271 static void jpeg_v2_5_disable_clock_gating(struct amdgpu_device *adev, int inst) 272 { 273 uint32_t data; 274 275 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL); 276 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) 277 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 278 else 279 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 280 281 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 282 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 283 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data); 284 285 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE); 286 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK 287 | JPEG_CGC_GATE__JPEG2_DEC_MASK 288 | JPEG_CGC_GATE__JMCIF_MASK 289 | JPEG_CGC_GATE__JRBBM_MASK); 290 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data); 291 292 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL); 293 data &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK 294 | JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK 295 | JPEG_CGC_CTRL__JMCIF_MODE_MASK 296 | JPEG_CGC_CTRL__JRBBM_MODE_MASK); 297 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data); 298 } 299 300 static void jpeg_v2_5_enable_clock_gating(struct amdgpu_device *adev, int inst) 301 { 302 uint32_t data; 303 304 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE); 305 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK 306 |JPEG_CGC_GATE__JPEG2_DEC_MASK 307 |JPEG_CGC_GATE__JPEG_ENC_MASK 308 |JPEG_CGC_GATE__JMCIF_MASK 309 |JPEG_CGC_GATE__JRBBM_MASK); 310 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data); 311 } 312 313 /** 314 * jpeg_v2_5_start - start JPEG block 315 * 316 * @adev: amdgpu_device pointer 317 * 318 * Setup and start the JPEG block 319 */ 320 static int jpeg_v2_5_start(struct amdgpu_device *adev) 321 { 322 struct amdgpu_ring *ring; 323 int i; 324 325 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 326 if (adev->jpeg.harvest_config & (1 << i)) 327 continue; 328 329 ring = adev->jpeg.inst[i].ring_dec; 330 /* disable anti hang mechanism */ 331 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 0, 332 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 333 334 /* JPEG disable CGC */ 335 jpeg_v2_5_disable_clock_gating(adev, i); 336 337 /* MJPEG global tiling registers */ 338 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX8_ADDR_CONFIG, 339 adev->gfx.config.gb_addr_config); 340 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX10_ADDR_CONFIG, 341 adev->gfx.config.gb_addr_config); 342 343 /* enable JMI channel */ 344 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 0, 345 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 346 347 /* enable System Interrupt for JRBC */ 348 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmJPEG_SYS_INT_EN), 349 JPEG_SYS_INT_EN__DJRBC_MASK, 350 ~JPEG_SYS_INT_EN__DJRBC_MASK); 351 352 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_VMID, 0); 353 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 354 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 355 lower_32_bits(ring->gpu_addr)); 356 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 357 upper_32_bits(ring->gpu_addr)); 358 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_RPTR, 0); 359 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR, 0); 360 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, 0x00000002L); 361 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); 362 ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR); 363 } 364 365 return 0; 366 } 367 368 /** 369 * jpeg_v2_5_stop - stop JPEG block 370 * 371 * @adev: amdgpu_device pointer 372 * 373 * stop the JPEG block 374 */ 375 static int jpeg_v2_5_stop(struct amdgpu_device *adev) 376 { 377 int i; 378 379 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 380 if (adev->jpeg.harvest_config & (1 << i)) 381 continue; 382 383 /* reset JMI */ 384 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 385 UVD_JMI_CNTL__SOFT_RESET_MASK, 386 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 387 388 jpeg_v2_5_enable_clock_gating(adev, i); 389 390 /* enable anti hang mechanism */ 391 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 392 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 393 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 394 } 395 396 return 0; 397 } 398 399 /** 400 * jpeg_v2_5_dec_ring_get_rptr - get read pointer 401 * 402 * @ring: amdgpu_ring pointer 403 * 404 * Returns the current hardware read pointer 405 */ 406 static uint64_t jpeg_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring) 407 { 408 struct amdgpu_device *adev = ring->adev; 409 410 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_RPTR); 411 } 412 413 /** 414 * jpeg_v2_5_dec_ring_get_wptr - get write pointer 415 * 416 * @ring: amdgpu_ring pointer 417 * 418 * Returns the current hardware write pointer 419 */ 420 static uint64_t jpeg_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring) 421 { 422 struct amdgpu_device *adev = ring->adev; 423 424 if (ring->use_doorbell) 425 return *ring->wptr_cpu_addr; 426 else 427 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR); 428 } 429 430 /** 431 * jpeg_v2_5_dec_ring_set_wptr - set write pointer 432 * 433 * @ring: amdgpu_ring pointer 434 * 435 * Commits the write pointer to the hardware 436 */ 437 static void jpeg_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring) 438 { 439 struct amdgpu_device *adev = ring->adev; 440 441 if (ring->use_doorbell) { 442 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 443 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 444 } else { 445 WREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 446 } 447 } 448 449 /** 450 * jpeg_v2_6_dec_ring_insert_start - insert a start command 451 * 452 * @ring: amdgpu_ring pointer 453 * 454 * Write a start command to the ring. 455 */ 456 static void jpeg_v2_6_dec_ring_insert_start(struct amdgpu_ring *ring) 457 { 458 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 459 0, 0, PACKETJ_TYPE0)); 460 amdgpu_ring_write(ring, 0x6aa04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ 461 462 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 463 0, 0, PACKETJ_TYPE0)); 464 amdgpu_ring_write(ring, 0x80000000 | (1 << (ring->me * 2 + 14))); 465 } 466 467 /** 468 * jpeg_v2_6_dec_ring_insert_end - insert a end command 469 * 470 * @ring: amdgpu_ring pointer 471 * 472 * Write a end command to the ring. 473 */ 474 static void jpeg_v2_6_dec_ring_insert_end(struct amdgpu_ring *ring) 475 { 476 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 477 0, 0, PACKETJ_TYPE0)); 478 amdgpu_ring_write(ring, 0x6aa04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ 479 480 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 481 0, 0, PACKETJ_TYPE0)); 482 amdgpu_ring_write(ring, (1 << (ring->me * 2 + 14))); 483 } 484 485 static bool jpeg_v2_5_is_idle(void *handle) 486 { 487 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 488 int i, ret = 1; 489 490 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 491 if (adev->jpeg.harvest_config & (1 << i)) 492 continue; 493 494 ret &= (((RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS) & 495 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 496 UVD_JRBC_STATUS__RB_JOB_DONE_MASK)); 497 } 498 499 return ret; 500 } 501 502 static int jpeg_v2_5_wait_for_idle(struct amdgpu_ip_block *ip_block) 503 { 504 struct amdgpu_device *adev = ip_block->adev; 505 int i, ret; 506 507 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 508 if (adev->jpeg.harvest_config & (1 << i)) 509 continue; 510 511 ret = SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS, 512 UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 513 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 514 if (ret) 515 return ret; 516 } 517 518 return 0; 519 } 520 521 static int jpeg_v2_5_set_clockgating_state(void *handle, 522 enum amd_clockgating_state state) 523 { 524 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 525 bool enable = (state == AMD_CG_STATE_GATE); 526 int i; 527 528 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 529 if (adev->jpeg.harvest_config & (1 << i)) 530 continue; 531 532 if (enable) { 533 if (!jpeg_v2_5_is_idle(handle)) 534 return -EBUSY; 535 jpeg_v2_5_enable_clock_gating(adev, i); 536 } else { 537 jpeg_v2_5_disable_clock_gating(adev, i); 538 } 539 } 540 541 return 0; 542 } 543 544 static int jpeg_v2_5_set_powergating_state(void *handle, 545 enum amd_powergating_state state) 546 { 547 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 548 int ret; 549 550 if (state == adev->jpeg.cur_state) 551 return 0; 552 553 if (state == AMD_PG_STATE_GATE) 554 ret = jpeg_v2_5_stop(adev); 555 else 556 ret = jpeg_v2_5_start(adev); 557 558 if (!ret) 559 adev->jpeg.cur_state = state; 560 561 return ret; 562 } 563 564 static int jpeg_v2_5_set_interrupt_state(struct amdgpu_device *adev, 565 struct amdgpu_irq_src *source, 566 unsigned type, 567 enum amdgpu_interrupt_state state) 568 { 569 return 0; 570 } 571 572 static int jpeg_v2_6_set_ras_interrupt_state(struct amdgpu_device *adev, 573 struct amdgpu_irq_src *source, 574 unsigned int type, 575 enum amdgpu_interrupt_state state) 576 { 577 return 0; 578 } 579 580 static int jpeg_v2_5_process_interrupt(struct amdgpu_device *adev, 581 struct amdgpu_irq_src *source, 582 struct amdgpu_iv_entry *entry) 583 { 584 uint32_t ip_instance; 585 586 switch (entry->client_id) { 587 case SOC15_IH_CLIENTID_VCN: 588 ip_instance = 0; 589 break; 590 case SOC15_IH_CLIENTID_VCN1: 591 ip_instance = 1; 592 break; 593 default: 594 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 595 return 0; 596 } 597 598 DRM_DEBUG("IH: JPEG TRAP\n"); 599 600 switch (entry->src_id) { 601 case VCN_2_0__SRCID__JPEG_DECODE: 602 amdgpu_fence_process(adev->jpeg.inst[ip_instance].ring_dec); 603 break; 604 default: 605 DRM_ERROR("Unhandled interrupt: %d %d\n", 606 entry->src_id, entry->src_data[0]); 607 break; 608 } 609 610 return 0; 611 } 612 613 static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = { 614 .name = "jpeg_v2_5", 615 .early_init = jpeg_v2_5_early_init, 616 .late_init = NULL, 617 .sw_init = jpeg_v2_5_sw_init, 618 .sw_fini = jpeg_v2_5_sw_fini, 619 .hw_init = jpeg_v2_5_hw_init, 620 .hw_fini = jpeg_v2_5_hw_fini, 621 .suspend = jpeg_v2_5_suspend, 622 .resume = jpeg_v2_5_resume, 623 .is_idle = jpeg_v2_5_is_idle, 624 .wait_for_idle = jpeg_v2_5_wait_for_idle, 625 .check_soft_reset = NULL, 626 .pre_soft_reset = NULL, 627 .soft_reset = NULL, 628 .post_soft_reset = NULL, 629 .set_clockgating_state = jpeg_v2_5_set_clockgating_state, 630 .set_powergating_state = jpeg_v2_5_set_powergating_state, 631 .dump_ip_state = NULL, 632 .print_ip_state = NULL, 633 }; 634 635 static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = { 636 .name = "jpeg_v2_6", 637 .early_init = jpeg_v2_5_early_init, 638 .late_init = NULL, 639 .sw_init = jpeg_v2_5_sw_init, 640 .sw_fini = jpeg_v2_5_sw_fini, 641 .hw_init = jpeg_v2_5_hw_init, 642 .hw_fini = jpeg_v2_5_hw_fini, 643 .suspend = jpeg_v2_5_suspend, 644 .resume = jpeg_v2_5_resume, 645 .is_idle = jpeg_v2_5_is_idle, 646 .wait_for_idle = jpeg_v2_5_wait_for_idle, 647 .check_soft_reset = NULL, 648 .pre_soft_reset = NULL, 649 .soft_reset = NULL, 650 .post_soft_reset = NULL, 651 .set_clockgating_state = jpeg_v2_5_set_clockgating_state, 652 .set_powergating_state = jpeg_v2_5_set_powergating_state, 653 .dump_ip_state = NULL, 654 .print_ip_state = NULL, 655 }; 656 657 static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = { 658 .type = AMDGPU_RING_TYPE_VCN_JPEG, 659 .align_mask = 0xf, 660 .get_rptr = jpeg_v2_5_dec_ring_get_rptr, 661 .get_wptr = jpeg_v2_5_dec_ring_get_wptr, 662 .set_wptr = jpeg_v2_5_dec_ring_set_wptr, 663 .parse_cs = jpeg_v2_dec_ring_parse_cs, 664 .emit_frame_size = 665 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 666 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 667 8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */ 668 18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */ 669 8 + 16, 670 .emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */ 671 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 672 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 673 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 674 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 675 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 676 .insert_nop = jpeg_v2_0_dec_ring_nop, 677 .insert_start = jpeg_v2_0_dec_ring_insert_start, 678 .insert_end = jpeg_v2_0_dec_ring_insert_end, 679 .pad_ib = amdgpu_ring_generic_pad_ib, 680 .begin_use = amdgpu_jpeg_ring_begin_use, 681 .end_use = amdgpu_jpeg_ring_end_use, 682 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 683 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 684 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 685 }; 686 687 static const struct amdgpu_ring_funcs jpeg_v2_6_dec_ring_vm_funcs = { 688 .type = AMDGPU_RING_TYPE_VCN_JPEG, 689 .align_mask = 0xf, 690 .get_rptr = jpeg_v2_5_dec_ring_get_rptr, 691 .get_wptr = jpeg_v2_5_dec_ring_get_wptr, 692 .set_wptr = jpeg_v2_5_dec_ring_set_wptr, 693 .parse_cs = jpeg_v2_dec_ring_parse_cs, 694 .emit_frame_size = 695 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 696 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 697 8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */ 698 18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */ 699 8 + 16, 700 .emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */ 701 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 702 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 703 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 704 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 705 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 706 .insert_nop = jpeg_v2_0_dec_ring_nop, 707 .insert_start = jpeg_v2_6_dec_ring_insert_start, 708 .insert_end = jpeg_v2_6_dec_ring_insert_end, 709 .pad_ib = amdgpu_ring_generic_pad_ib, 710 .begin_use = amdgpu_jpeg_ring_begin_use, 711 .end_use = amdgpu_jpeg_ring_end_use, 712 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 713 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 714 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 715 }; 716 717 static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev) 718 { 719 int i; 720 721 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 722 if (adev->jpeg.harvest_config & (1 << i)) 723 continue; 724 if (adev->asic_type == CHIP_ARCTURUS) 725 adev->jpeg.inst[i].ring_dec->funcs = &jpeg_v2_5_dec_ring_vm_funcs; 726 else /* CHIP_ALDEBARAN */ 727 adev->jpeg.inst[i].ring_dec->funcs = &jpeg_v2_6_dec_ring_vm_funcs; 728 adev->jpeg.inst[i].ring_dec->me = i; 729 } 730 } 731 732 static const struct amdgpu_irq_src_funcs jpeg_v2_5_irq_funcs = { 733 .set = jpeg_v2_5_set_interrupt_state, 734 .process = jpeg_v2_5_process_interrupt, 735 }; 736 737 static const struct amdgpu_irq_src_funcs jpeg_v2_6_ras_irq_funcs = { 738 .set = jpeg_v2_6_set_ras_interrupt_state, 739 .process = amdgpu_jpeg_process_poison_irq, 740 }; 741 742 static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev) 743 { 744 int i; 745 746 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 747 if (adev->jpeg.harvest_config & (1 << i)) 748 continue; 749 750 adev->jpeg.inst[i].irq.num_types = 1; 751 adev->jpeg.inst[i].irq.funcs = &jpeg_v2_5_irq_funcs; 752 753 adev->jpeg.inst[i].ras_poison_irq.num_types = 1; 754 adev->jpeg.inst[i].ras_poison_irq.funcs = &jpeg_v2_6_ras_irq_funcs; 755 } 756 } 757 758 const struct amdgpu_ip_block_version jpeg_v2_5_ip_block = { 759 .type = AMD_IP_BLOCK_TYPE_JPEG, 760 .major = 2, 761 .minor = 5, 762 .rev = 0, 763 .funcs = &jpeg_v2_5_ip_funcs, 764 }; 765 766 const struct amdgpu_ip_block_version jpeg_v2_6_ip_block = { 767 .type = AMD_IP_BLOCK_TYPE_JPEG, 768 .major = 2, 769 .minor = 6, 770 .rev = 0, 771 .funcs = &jpeg_v2_6_ip_funcs, 772 }; 773 774 static uint32_t jpeg_v2_6_query_poison_by_instance(struct amdgpu_device *adev, 775 uint32_t instance, uint32_t sub_block) 776 { 777 uint32_t poison_stat = 0, reg_value = 0; 778 779 switch (sub_block) { 780 case AMDGPU_JPEG_V2_6_JPEG0: 781 reg_value = RREG32_SOC15(JPEG, instance, mmUVD_RAS_JPEG0_STATUS); 782 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF); 783 break; 784 case AMDGPU_JPEG_V2_6_JPEG1: 785 reg_value = RREG32_SOC15(JPEG, instance, mmUVD_RAS_JPEG1_STATUS); 786 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF); 787 break; 788 default: 789 break; 790 } 791 792 if (poison_stat) 793 dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n", 794 instance, sub_block); 795 796 return poison_stat; 797 } 798 799 static bool jpeg_v2_6_query_ras_poison_status(struct amdgpu_device *adev) 800 { 801 uint32_t inst = 0, sub = 0, poison_stat = 0; 802 803 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++) 804 for (sub = 0; sub < AMDGPU_JPEG_V2_6_MAX_SUB_BLOCK; sub++) 805 poison_stat += 806 jpeg_v2_6_query_poison_by_instance(adev, inst, sub); 807 808 return !!poison_stat; 809 } 810 811 const struct amdgpu_ras_block_hw_ops jpeg_v2_6_ras_hw_ops = { 812 .query_poison_status = jpeg_v2_6_query_ras_poison_status, 813 }; 814 815 static struct amdgpu_jpeg_ras jpeg_v2_6_ras = { 816 .ras_block = { 817 .hw_ops = &jpeg_v2_6_ras_hw_ops, 818 .ras_late_init = amdgpu_jpeg_ras_late_init, 819 }, 820 }; 821 822 static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev) 823 { 824 switch (amdgpu_ip_version(adev, JPEG_HWIP, 0)) { 825 case IP_VERSION(2, 6, 0): 826 adev->jpeg.ras = &jpeg_v2_6_ras; 827 break; 828 default: 829 break; 830 } 831 } 832