1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "gc/gc_9_0_sh_mask.h" 35 #include "dce/dce_12_0_offset.h" 36 #include "dce/dce_12_0_sh_mask.h" 37 #include "vega10_enum.h" 38 #include "mmhub/mmhub_1_0_offset.h" 39 #include "athub/athub_1_0_sh_mask.h" 40 #include "athub/athub_1_0_offset.h" 41 #include "oss/osssys_4_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15d.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "gfxhub_v1_2.h" 53 #include "mmhub_v9_4.h" 54 #include "mmhub_v1_7.h" 55 #include "mmhub_v1_8.h" 56 #include "umc_v6_1.h" 57 #include "umc_v6_0.h" 58 #include "umc_v6_7.h" 59 #include "umc_v12_0.h" 60 #include "hdp_v4_0.h" 61 #include "mca_v3_0.h" 62 63 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 64 65 #include "amdgpu_ras.h" 66 #include "amdgpu_xgmi.h" 67 68 /* add these here since we already include dce12 headers and these are for DCN */ 69 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 70 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 71 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 74 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 75 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d 76 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 77 78 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea 79 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2 80 81 #define MAX_MEM_RANGES 8 82 83 static const char * const gfxhub_client_ids[] = { 84 "CB", 85 "DB", 86 "IA", 87 "WD", 88 "CPF", 89 "CPC", 90 "CPG", 91 "RLC", 92 "TCP", 93 "SQC (inst)", 94 "SQC (data)", 95 "SQG", 96 "PA", 97 }; 98 99 static const char *mmhub_client_ids_raven[][2] = { 100 [0][0] = "MP1", 101 [1][0] = "MP0", 102 [2][0] = "VCN", 103 [3][0] = "VCNU", 104 [4][0] = "HDP", 105 [5][0] = "DCE", 106 [13][0] = "UTCL2", 107 [19][0] = "TLS", 108 [26][0] = "OSS", 109 [27][0] = "SDMA0", 110 [0][1] = "MP1", 111 [1][1] = "MP0", 112 [2][1] = "VCN", 113 [3][1] = "VCNU", 114 [4][1] = "HDP", 115 [5][1] = "XDP", 116 [6][1] = "DBGU0", 117 [7][1] = "DCE", 118 [8][1] = "DCEDWB0", 119 [9][1] = "DCEDWB1", 120 [26][1] = "OSS", 121 [27][1] = "SDMA0", 122 }; 123 124 static const char *mmhub_client_ids_renoir[][2] = { 125 [0][0] = "MP1", 126 [1][0] = "MP0", 127 [2][0] = "HDP", 128 [4][0] = "DCEDMC", 129 [5][0] = "DCEVGA", 130 [13][0] = "UTCL2", 131 [19][0] = "TLS", 132 [26][0] = "OSS", 133 [27][0] = "SDMA0", 134 [28][0] = "VCN", 135 [29][0] = "VCNU", 136 [30][0] = "JPEG", 137 [0][1] = "MP1", 138 [1][1] = "MP0", 139 [2][1] = "HDP", 140 [3][1] = "XDP", 141 [6][1] = "DBGU0", 142 [7][1] = "DCEDMC", 143 [8][1] = "DCEVGA", 144 [9][1] = "DCEDWB", 145 [26][1] = "OSS", 146 [27][1] = "SDMA0", 147 [28][1] = "VCN", 148 [29][1] = "VCNU", 149 [30][1] = "JPEG", 150 }; 151 152 static const char *mmhub_client_ids_vega10[][2] = { 153 [0][0] = "MP0", 154 [1][0] = "UVD", 155 [2][0] = "UVDU", 156 [3][0] = "HDP", 157 [13][0] = "UTCL2", 158 [14][0] = "OSS", 159 [15][0] = "SDMA1", 160 [32+0][0] = "VCE0", 161 [32+1][0] = "VCE0U", 162 [32+2][0] = "XDMA", 163 [32+3][0] = "DCE", 164 [32+4][0] = "MP1", 165 [32+14][0] = "SDMA0", 166 [0][1] = "MP0", 167 [1][1] = "UVD", 168 [2][1] = "UVDU", 169 [3][1] = "DBGU0", 170 [4][1] = "HDP", 171 [5][1] = "XDP", 172 [14][1] = "OSS", 173 [15][1] = "SDMA0", 174 [32+0][1] = "VCE0", 175 [32+1][1] = "VCE0U", 176 [32+2][1] = "XDMA", 177 [32+3][1] = "DCE", 178 [32+4][1] = "DCEDWB", 179 [32+5][1] = "MP1", 180 [32+6][1] = "DBGU1", 181 [32+14][1] = "SDMA1", 182 }; 183 184 static const char *mmhub_client_ids_vega12[][2] = { 185 [0][0] = "MP0", 186 [1][0] = "VCE0", 187 [2][0] = "VCE0U", 188 [3][0] = "HDP", 189 [13][0] = "UTCL2", 190 [14][0] = "OSS", 191 [15][0] = "SDMA1", 192 [32+0][0] = "DCE", 193 [32+1][0] = "XDMA", 194 [32+2][0] = "UVD", 195 [32+3][0] = "UVDU", 196 [32+4][0] = "MP1", 197 [32+15][0] = "SDMA0", 198 [0][1] = "MP0", 199 [1][1] = "VCE0", 200 [2][1] = "VCE0U", 201 [3][1] = "DBGU0", 202 [4][1] = "HDP", 203 [5][1] = "XDP", 204 [14][1] = "OSS", 205 [15][1] = "SDMA0", 206 [32+0][1] = "DCE", 207 [32+1][1] = "DCEDWB", 208 [32+2][1] = "XDMA", 209 [32+3][1] = "UVD", 210 [32+4][1] = "UVDU", 211 [32+5][1] = "MP1", 212 [32+6][1] = "DBGU1", 213 [32+15][1] = "SDMA1", 214 }; 215 216 static const char *mmhub_client_ids_vega20[][2] = { 217 [0][0] = "XDMA", 218 [1][0] = "DCE", 219 [2][0] = "VCE0", 220 [3][0] = "VCE0U", 221 [4][0] = "UVD", 222 [5][0] = "UVD1U", 223 [13][0] = "OSS", 224 [14][0] = "HDP", 225 [15][0] = "SDMA0", 226 [32+0][0] = "UVD", 227 [32+1][0] = "UVDU", 228 [32+2][0] = "MP1", 229 [32+3][0] = "MP0", 230 [32+12][0] = "UTCL2", 231 [32+14][0] = "SDMA1", 232 [0][1] = "XDMA", 233 [1][1] = "DCE", 234 [2][1] = "DCEDWB", 235 [3][1] = "VCE0", 236 [4][1] = "VCE0U", 237 [5][1] = "UVD1", 238 [6][1] = "UVD1U", 239 [7][1] = "DBGU0", 240 [8][1] = "XDP", 241 [13][1] = "OSS", 242 [14][1] = "HDP", 243 [15][1] = "SDMA0", 244 [32+0][1] = "UVD", 245 [32+1][1] = "UVDU", 246 [32+2][1] = "DBGU1", 247 [32+3][1] = "MP1", 248 [32+4][1] = "MP0", 249 [32+14][1] = "SDMA1", 250 }; 251 252 static const char *mmhub_client_ids_arcturus[][2] = { 253 [0][0] = "DBGU1", 254 [1][0] = "XDP", 255 [2][0] = "MP1", 256 [14][0] = "HDP", 257 [171][0] = "JPEG", 258 [172][0] = "VCN", 259 [173][0] = "VCNU", 260 [203][0] = "JPEG1", 261 [204][0] = "VCN1", 262 [205][0] = "VCN1U", 263 [256][0] = "SDMA0", 264 [257][0] = "SDMA1", 265 [258][0] = "SDMA2", 266 [259][0] = "SDMA3", 267 [260][0] = "SDMA4", 268 [261][0] = "SDMA5", 269 [262][0] = "SDMA6", 270 [263][0] = "SDMA7", 271 [384][0] = "OSS", 272 [0][1] = "DBGU1", 273 [1][1] = "XDP", 274 [2][1] = "MP1", 275 [14][1] = "HDP", 276 [171][1] = "JPEG", 277 [172][1] = "VCN", 278 [173][1] = "VCNU", 279 [203][1] = "JPEG1", 280 [204][1] = "VCN1", 281 [205][1] = "VCN1U", 282 [256][1] = "SDMA0", 283 [257][1] = "SDMA1", 284 [258][1] = "SDMA2", 285 [259][1] = "SDMA3", 286 [260][1] = "SDMA4", 287 [261][1] = "SDMA5", 288 [262][1] = "SDMA6", 289 [263][1] = "SDMA7", 290 [384][1] = "OSS", 291 }; 292 293 static const char *mmhub_client_ids_aldebaran[][2] = { 294 [2][0] = "MP1", 295 [3][0] = "MP0", 296 [32+1][0] = "DBGU_IO0", 297 [32+2][0] = "DBGU_IO2", 298 [32+4][0] = "MPIO", 299 [96+11][0] = "JPEG0", 300 [96+12][0] = "VCN0", 301 [96+13][0] = "VCNU0", 302 [128+11][0] = "JPEG1", 303 [128+12][0] = "VCN1", 304 [128+13][0] = "VCNU1", 305 [160+1][0] = "XDP", 306 [160+14][0] = "HDP", 307 [256+0][0] = "SDMA0", 308 [256+1][0] = "SDMA1", 309 [256+2][0] = "SDMA2", 310 [256+3][0] = "SDMA3", 311 [256+4][0] = "SDMA4", 312 [384+0][0] = "OSS", 313 [2][1] = "MP1", 314 [3][1] = "MP0", 315 [32+1][1] = "DBGU_IO0", 316 [32+2][1] = "DBGU_IO2", 317 [32+4][1] = "MPIO", 318 [96+11][1] = "JPEG0", 319 [96+12][1] = "VCN0", 320 [96+13][1] = "VCNU0", 321 [128+11][1] = "JPEG1", 322 [128+12][1] = "VCN1", 323 [128+13][1] = "VCNU1", 324 [160+1][1] = "XDP", 325 [160+14][1] = "HDP", 326 [256+0][1] = "SDMA0", 327 [256+1][1] = "SDMA1", 328 [256+2][1] = "SDMA2", 329 [256+3][1] = "SDMA3", 330 [256+4][1] = "SDMA4", 331 [384+0][1] = "OSS", 332 }; 333 334 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = { 335 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 336 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 337 }; 338 339 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = { 340 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 341 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 342 }; 343 344 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 345 (0x000143c0 + 0x00000000), 346 (0x000143c0 + 0x00000800), 347 (0x000143c0 + 0x00001000), 348 (0x000143c0 + 0x00001800), 349 (0x000543c0 + 0x00000000), 350 (0x000543c0 + 0x00000800), 351 (0x000543c0 + 0x00001000), 352 (0x000543c0 + 0x00001800), 353 (0x000943c0 + 0x00000000), 354 (0x000943c0 + 0x00000800), 355 (0x000943c0 + 0x00001000), 356 (0x000943c0 + 0x00001800), 357 (0x000d43c0 + 0x00000000), 358 (0x000d43c0 + 0x00000800), 359 (0x000d43c0 + 0x00001000), 360 (0x000d43c0 + 0x00001800), 361 (0x001143c0 + 0x00000000), 362 (0x001143c0 + 0x00000800), 363 (0x001143c0 + 0x00001000), 364 (0x001143c0 + 0x00001800), 365 (0x001543c0 + 0x00000000), 366 (0x001543c0 + 0x00000800), 367 (0x001543c0 + 0x00001000), 368 (0x001543c0 + 0x00001800), 369 (0x001943c0 + 0x00000000), 370 (0x001943c0 + 0x00000800), 371 (0x001943c0 + 0x00001000), 372 (0x001943c0 + 0x00001800), 373 (0x001d43c0 + 0x00000000), 374 (0x001d43c0 + 0x00000800), 375 (0x001d43c0 + 0x00001000), 376 (0x001d43c0 + 0x00001800), 377 }; 378 379 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 380 (0x000143e0 + 0x00000000), 381 (0x000143e0 + 0x00000800), 382 (0x000143e0 + 0x00001000), 383 (0x000143e0 + 0x00001800), 384 (0x000543e0 + 0x00000000), 385 (0x000543e0 + 0x00000800), 386 (0x000543e0 + 0x00001000), 387 (0x000543e0 + 0x00001800), 388 (0x000943e0 + 0x00000000), 389 (0x000943e0 + 0x00000800), 390 (0x000943e0 + 0x00001000), 391 (0x000943e0 + 0x00001800), 392 (0x000d43e0 + 0x00000000), 393 (0x000d43e0 + 0x00000800), 394 (0x000d43e0 + 0x00001000), 395 (0x000d43e0 + 0x00001800), 396 (0x001143e0 + 0x00000000), 397 (0x001143e0 + 0x00000800), 398 (0x001143e0 + 0x00001000), 399 (0x001143e0 + 0x00001800), 400 (0x001543e0 + 0x00000000), 401 (0x001543e0 + 0x00000800), 402 (0x001543e0 + 0x00001000), 403 (0x001543e0 + 0x00001800), 404 (0x001943e0 + 0x00000000), 405 (0x001943e0 + 0x00000800), 406 (0x001943e0 + 0x00001000), 407 (0x001943e0 + 0x00001800), 408 (0x001d43e0 + 0x00000000), 409 (0x001d43e0 + 0x00000800), 410 (0x001d43e0 + 0x00001000), 411 (0x001d43e0 + 0x00001800), 412 }; 413 414 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 415 struct amdgpu_irq_src *src, 416 unsigned int type, 417 enum amdgpu_interrupt_state state) 418 { 419 u32 bits, i, tmp, reg; 420 421 /* Devices newer then VEGA10/12 shall have these programming 422 * sequences performed by PSP BL 423 */ 424 if (adev->asic_type >= CHIP_VEGA20) 425 return 0; 426 427 bits = 0x7f; 428 429 switch (state) { 430 case AMDGPU_IRQ_STATE_DISABLE: 431 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 432 reg = ecc_umc_mcumc_ctrl_addrs[i]; 433 tmp = RREG32(reg); 434 tmp &= ~bits; 435 WREG32(reg, tmp); 436 } 437 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 438 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 439 tmp = RREG32(reg); 440 tmp &= ~bits; 441 WREG32(reg, tmp); 442 } 443 break; 444 case AMDGPU_IRQ_STATE_ENABLE: 445 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 446 reg = ecc_umc_mcumc_ctrl_addrs[i]; 447 tmp = RREG32(reg); 448 tmp |= bits; 449 WREG32(reg, tmp); 450 } 451 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 452 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 453 tmp = RREG32(reg); 454 tmp |= bits; 455 WREG32(reg, tmp); 456 } 457 break; 458 default: 459 break; 460 } 461 462 return 0; 463 } 464 465 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 466 struct amdgpu_irq_src *src, 467 unsigned int type, 468 enum amdgpu_interrupt_state state) 469 { 470 struct amdgpu_vmhub *hub; 471 u32 tmp, reg, bits, i, j; 472 473 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 474 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 475 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 476 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 477 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 478 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 479 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 480 481 switch (state) { 482 case AMDGPU_IRQ_STATE_DISABLE: 483 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 484 hub = &adev->vmhub[j]; 485 for (i = 0; i < 16; i++) { 486 reg = hub->vm_context0_cntl + i; 487 488 /* This works because this interrupt is only 489 * enabled at init/resume and disabled in 490 * fini/suspend, so the overall state doesn't 491 * change over the course of suspend/resume. 492 */ 493 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 494 continue; 495 496 if (j >= AMDGPU_MMHUB0(0)) 497 tmp = RREG32_SOC15_IP(MMHUB, reg); 498 else 499 tmp = RREG32_SOC15_IP(GC, reg); 500 501 tmp &= ~bits; 502 503 if (j >= AMDGPU_MMHUB0(0)) 504 WREG32_SOC15_IP(MMHUB, reg, tmp); 505 else 506 WREG32_SOC15_IP(GC, reg, tmp); 507 } 508 } 509 break; 510 case AMDGPU_IRQ_STATE_ENABLE: 511 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 512 hub = &adev->vmhub[j]; 513 for (i = 0; i < 16; i++) { 514 reg = hub->vm_context0_cntl + i; 515 516 /* This works because this interrupt is only 517 * enabled at init/resume and disabled in 518 * fini/suspend, so the overall state doesn't 519 * change over the course of suspend/resume. 520 */ 521 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 522 continue; 523 524 if (j >= AMDGPU_MMHUB0(0)) 525 tmp = RREG32_SOC15_IP(MMHUB, reg); 526 else 527 tmp = RREG32_SOC15_IP(GC, reg); 528 529 tmp |= bits; 530 531 if (j >= AMDGPU_MMHUB0(0)) 532 WREG32_SOC15_IP(MMHUB, reg, tmp); 533 else 534 WREG32_SOC15_IP(GC, reg, tmp); 535 } 536 } 537 break; 538 default: 539 break; 540 } 541 542 return 0; 543 } 544 545 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 546 struct amdgpu_irq_src *source, 547 struct amdgpu_iv_entry *entry) 548 { 549 bool retry_fault = !!(entry->src_data[1] & 0x80); 550 bool write_fault = !!(entry->src_data[1] & 0x20); 551 uint32_t status = 0, cid = 0, rw = 0; 552 struct amdgpu_task_info task_info; 553 struct amdgpu_vmhub *hub; 554 const char *mmhub_cid; 555 const char *hub_name; 556 unsigned int vmhub; 557 u64 addr; 558 uint32_t cam_index = 0; 559 int ret, xcc_id = 0; 560 uint32_t node_id; 561 562 node_id = entry->node_id; 563 564 addr = (u64)entry->src_data[0] << 12; 565 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 566 567 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 568 hub_name = "mmhub0"; 569 vmhub = AMDGPU_MMHUB0(node_id / 4); 570 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 571 hub_name = "mmhub1"; 572 vmhub = AMDGPU_MMHUB1(0); 573 } else { 574 hub_name = "gfxhub0"; 575 if (adev->gfx.funcs->ih_node_to_logical_xcc) { 576 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, 577 node_id); 578 if (xcc_id < 0) 579 xcc_id = 0; 580 } 581 vmhub = xcc_id; 582 } 583 hub = &adev->vmhub[vmhub]; 584 585 if (retry_fault) { 586 if (adev->irq.retry_cam_enabled) { 587 /* Delegate it to a different ring if the hardware hasn't 588 * already done it. 589 */ 590 if (entry->ih == &adev->irq.ih) { 591 amdgpu_irq_delegate(adev, entry, 8); 592 return 1; 593 } 594 595 cam_index = entry->src_data[2] & 0x3ff; 596 597 ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 598 addr, write_fault); 599 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 600 if (ret) 601 return 1; 602 } else { 603 /* Process it onyl if it's the first fault for this address */ 604 if (entry->ih != &adev->irq.ih_soft && 605 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 606 entry->timestamp)) 607 return 1; 608 609 /* Delegate it to a different ring if the hardware hasn't 610 * already done it. 611 */ 612 if (entry->ih == &adev->irq.ih) { 613 amdgpu_irq_delegate(adev, entry, 8); 614 return 1; 615 } 616 617 /* Try to handle the recoverable page faults by filling page 618 * tables 619 */ 620 if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 621 addr, write_fault)) 622 return 1; 623 } 624 } 625 626 if (!printk_ratelimit()) 627 return 0; 628 629 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 630 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 631 632 dev_err(adev->dev, 633 "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d)\n", 634 hub_name, retry_fault ? "retry" : "no-retry", 635 entry->src_id, entry->ring_id, entry->vmid, 636 entry->pasid, task_info.process_name, task_info.tgid, 637 task_info.task_name, task_info.pid); 638 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n", 639 addr, entry->client_id, 640 soc15_ih_clientid_name[entry->client_id]); 641 642 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 643 dev_err(adev->dev, " cookie node_id %d fault from die %s%d%s\n", 644 node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4, 645 node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : ""); 646 647 if (amdgpu_sriov_vf(adev)) 648 return 0; 649 650 /* 651 * Issue a dummy read to wait for the status register to 652 * be updated to avoid reading an incorrect value due to 653 * the new fast GRBM interface. 654 */ 655 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && 656 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 657 RREG32(hub->vm_l2_pro_fault_status); 658 659 status = RREG32(hub->vm_l2_pro_fault_status); 660 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); 661 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); 662 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 663 664 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, vmhub); 665 666 dev_err(adev->dev, 667 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 668 status); 669 if (entry->vmid_src == AMDGPU_GFXHUB(0)) { 670 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 671 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : 672 gfxhub_client_ids[cid], 673 cid); 674 } else { 675 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 676 case IP_VERSION(9, 0, 0): 677 mmhub_cid = mmhub_client_ids_vega10[cid][rw]; 678 break; 679 case IP_VERSION(9, 3, 0): 680 mmhub_cid = mmhub_client_ids_vega12[cid][rw]; 681 break; 682 case IP_VERSION(9, 4, 0): 683 mmhub_cid = mmhub_client_ids_vega20[cid][rw]; 684 break; 685 case IP_VERSION(9, 4, 1): 686 mmhub_cid = mmhub_client_ids_arcturus[cid][rw]; 687 break; 688 case IP_VERSION(9, 1, 0): 689 case IP_VERSION(9, 2, 0): 690 mmhub_cid = mmhub_client_ids_raven[cid][rw]; 691 break; 692 case IP_VERSION(1, 5, 0): 693 case IP_VERSION(2, 4, 0): 694 mmhub_cid = mmhub_client_ids_renoir[cid][rw]; 695 break; 696 case IP_VERSION(1, 8, 0): 697 case IP_VERSION(9, 4, 2): 698 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw]; 699 break; 700 default: 701 mmhub_cid = NULL; 702 break; 703 } 704 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 705 mmhub_cid ? mmhub_cid : "unknown", cid); 706 } 707 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 708 REG_GET_FIELD(status, 709 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 710 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 711 REG_GET_FIELD(status, 712 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 713 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 714 REG_GET_FIELD(status, 715 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 716 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 717 REG_GET_FIELD(status, 718 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 719 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 720 return 0; 721 } 722 723 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 724 .set = gmc_v9_0_vm_fault_interrupt_state, 725 .process = gmc_v9_0_process_interrupt, 726 }; 727 728 729 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 730 .set = gmc_v9_0_ecc_interrupt_state, 731 .process = amdgpu_umc_process_ecc_irq, 732 }; 733 734 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 735 { 736 adev->gmc.vm_fault.num_types = 1; 737 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 738 739 if (!amdgpu_sriov_vf(adev) && 740 !adev->gmc.xgmi.connected_to_cpu && 741 !adev->gmc.is_app_apu) { 742 adev->gmc.ecc_irq.num_types = 1; 743 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 744 } 745 } 746 747 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 748 uint32_t flush_type) 749 { 750 u32 req = 0; 751 752 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 753 PER_VMID_INVALIDATE_REQ, 1 << vmid); 754 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 755 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 756 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 757 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 758 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 759 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 760 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 761 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 762 763 return req; 764 } 765 766 /** 767 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 768 * 769 * @adev: amdgpu_device pointer 770 * @vmhub: vmhub type 771 * 772 */ 773 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 774 uint32_t vmhub) 775 { 776 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 777 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 778 return false; 779 780 return ((vmhub == AMDGPU_MMHUB0(0) || 781 vmhub == AMDGPU_MMHUB1(0)) && 782 (!amdgpu_sriov_vf(adev)) && 783 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) && 784 (adev->apu_flags & AMD_APU_IS_PICASSO)))); 785 } 786 787 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 788 uint8_t vmid, uint16_t *p_pasid) 789 { 790 uint32_t value; 791 792 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 793 + vmid); 794 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 795 796 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 797 } 798 799 /* 800 * GART 801 * VMID 0 is the physical GPU addresses as used by the kernel. 802 * VMIDs 1-15 are used for userspace clients and are handled 803 * by the amdgpu vm/hsa code. 804 */ 805 806 /** 807 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 808 * 809 * @adev: amdgpu_device pointer 810 * @vmid: vm instance to flush 811 * @vmhub: which hub to flush 812 * @flush_type: the flush type 813 * 814 * Flush the TLB for the requested page table using certain type. 815 */ 816 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 817 uint32_t vmhub, uint32_t flush_type) 818 { 819 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 820 u32 j, inv_req, tmp, sem, req, ack; 821 const unsigned int eng = 17; 822 struct amdgpu_vmhub *hub; 823 824 BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS); 825 826 hub = &adev->vmhub[vmhub]; 827 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 828 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; 829 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 830 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 831 832 /* This is necessary for a HW workaround under SRIOV as well 833 * as GFXOFF under bare metal 834 */ 835 if (adev->gfx.kiq[0].ring.sched.ready && 836 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 837 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 838 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 839 840 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 841 1 << vmid); 842 return; 843 } 844 845 spin_lock(&adev->gmc.invalidate_lock); 846 847 /* 848 * It may lose gpuvm invalidate acknowldege state across power-gating 849 * off cycle, add semaphore acquire before invalidation and semaphore 850 * release after invalidation to avoid entering power gated state 851 * to WA the Issue 852 */ 853 854 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 855 if (use_semaphore) { 856 for (j = 0; j < adev->usec_timeout; j++) { 857 /* a read return value of 1 means semaphore acquire */ 858 if (vmhub >= AMDGPU_MMHUB0(0)) 859 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem); 860 else 861 tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem); 862 if (tmp & 0x1) 863 break; 864 udelay(1); 865 } 866 867 if (j >= adev->usec_timeout) 868 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 869 } 870 871 if (vmhub >= AMDGPU_MMHUB0(0)) 872 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req); 873 else 874 WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req); 875 876 /* 877 * Issue a dummy read to wait for the ACK register to 878 * be cleared to avoid a false ACK due to the new fast 879 * GRBM interface. 880 */ 881 if ((vmhub == AMDGPU_GFXHUB(0)) && 882 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) 883 RREG32_NO_KIQ(req); 884 885 for (j = 0; j < adev->usec_timeout; j++) { 886 if (vmhub >= AMDGPU_MMHUB0(0)) 887 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack); 888 else 889 tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack); 890 if (tmp & (1 << vmid)) 891 break; 892 udelay(1); 893 } 894 895 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 896 if (use_semaphore) { 897 /* 898 * add semaphore release after invalidation, 899 * write with 0 means semaphore release 900 */ 901 if (vmhub >= AMDGPU_MMHUB0(0)) 902 WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0); 903 else 904 WREG32_SOC15_IP_NO_KIQ(GC, sem, 0); 905 } 906 907 spin_unlock(&adev->gmc.invalidate_lock); 908 909 if (j < adev->usec_timeout) 910 return; 911 912 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 913 } 914 915 /** 916 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 917 * 918 * @adev: amdgpu_device pointer 919 * @pasid: pasid to be flush 920 * @flush_type: the flush type 921 * @all_hub: flush all hubs 922 * @inst: is used to select which instance of KIQ to use for the invalidation 923 * 924 * Flush the TLB for the requested pasid. 925 */ 926 static void gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 927 uint16_t pasid, uint32_t flush_type, 928 bool all_hub, uint32_t inst) 929 { 930 uint16_t queried; 931 int i, vmid; 932 933 for (vmid = 1; vmid < 16; vmid++) { 934 bool valid; 935 936 valid = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 937 &queried); 938 if (!valid || queried != pasid) 939 continue; 940 941 if (all_hub) { 942 for_each_set_bit(i, adev->vmhubs_mask, 943 AMDGPU_MAX_VMHUBS) 944 gmc_v9_0_flush_gpu_tlb(adev, vmid, i, 945 flush_type); 946 } else { 947 gmc_v9_0_flush_gpu_tlb(adev, vmid, 948 AMDGPU_GFXHUB(0), 949 flush_type); 950 } 951 } 952 } 953 954 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 955 unsigned int vmid, uint64_t pd_addr) 956 { 957 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 958 struct amdgpu_device *adev = ring->adev; 959 struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub]; 960 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 961 unsigned int eng = ring->vm_inv_eng; 962 963 /* 964 * It may lose gpuvm invalidate acknowldege state across power-gating 965 * off cycle, add semaphore acquire before invalidation and semaphore 966 * release after invalidation to avoid entering power gated state 967 * to WA the Issue 968 */ 969 970 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 971 if (use_semaphore) 972 /* a read return value of 1 means semaphore acuqire */ 973 amdgpu_ring_emit_reg_wait(ring, 974 hub->vm_inv_eng0_sem + 975 hub->eng_distance * eng, 0x1, 0x1); 976 977 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 978 (hub->ctx_addr_distance * vmid), 979 lower_32_bits(pd_addr)); 980 981 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 982 (hub->ctx_addr_distance * vmid), 983 upper_32_bits(pd_addr)); 984 985 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 986 hub->eng_distance * eng, 987 hub->vm_inv_eng0_ack + 988 hub->eng_distance * eng, 989 req, 1 << vmid); 990 991 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 992 if (use_semaphore) 993 /* 994 * add semaphore release after invalidation, 995 * write with 0 means semaphore release 996 */ 997 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 998 hub->eng_distance * eng, 0); 999 1000 return pd_addr; 1001 } 1002 1003 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 1004 unsigned int pasid) 1005 { 1006 struct amdgpu_device *adev = ring->adev; 1007 uint32_t reg; 1008 1009 /* Do nothing because there's no lut register for mmhub1. */ 1010 if (ring->vm_hub == AMDGPU_MMHUB1(0)) 1011 return; 1012 1013 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 1014 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 1015 else 1016 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 1017 1018 amdgpu_ring_emit_wreg(ring, reg, pasid); 1019 } 1020 1021 /* 1022 * PTE format on VEGA 10: 1023 * 63:59 reserved 1024 * 58:57 mtype 1025 * 56 F 1026 * 55 L 1027 * 54 P 1028 * 53 SW 1029 * 52 T 1030 * 50:48 reserved 1031 * 47:12 4k physical page base address 1032 * 11:7 fragment 1033 * 6 write 1034 * 5 read 1035 * 4 exe 1036 * 3 Z 1037 * 2 snooped 1038 * 1 system 1039 * 0 valid 1040 * 1041 * PDE format on VEGA 10: 1042 * 63:59 block fragment size 1043 * 58:55 reserved 1044 * 54 P 1045 * 53:48 reserved 1046 * 47:6 physical base address of PD or PTE 1047 * 5:3 reserved 1048 * 2 C 1049 * 1 system 1050 * 0 valid 1051 */ 1052 1053 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 1054 1055 { 1056 switch (flags) { 1057 case AMDGPU_VM_MTYPE_DEFAULT: 1058 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1059 case AMDGPU_VM_MTYPE_NC: 1060 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1061 case AMDGPU_VM_MTYPE_WC: 1062 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); 1063 case AMDGPU_VM_MTYPE_RW: 1064 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW); 1065 case AMDGPU_VM_MTYPE_CC: 1066 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); 1067 case AMDGPU_VM_MTYPE_UC: 1068 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); 1069 default: 1070 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1071 } 1072 } 1073 1074 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 1075 uint64_t *addr, uint64_t *flags) 1076 { 1077 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 1078 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 1079 BUG_ON(*addr & 0xFFFF00000000003FULL); 1080 1081 if (!adev->gmc.translate_further) 1082 return; 1083 1084 if (level == AMDGPU_VM_PDB1) { 1085 /* Set the block fragment size */ 1086 if (!(*flags & AMDGPU_PDE_PTE)) 1087 *flags |= AMDGPU_PDE_BFS(0x9); 1088 1089 } else if (level == AMDGPU_VM_PDB0) { 1090 if (*flags & AMDGPU_PDE_PTE) { 1091 *flags &= ~AMDGPU_PDE_PTE; 1092 if (!(*flags & AMDGPU_PTE_VALID)) 1093 *addr |= 1 << PAGE_SHIFT; 1094 } else { 1095 *flags |= AMDGPU_PTE_TF; 1096 } 1097 } 1098 } 1099 1100 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, 1101 struct amdgpu_bo *bo, 1102 struct amdgpu_bo_va_mapping *mapping, 1103 uint64_t *flags) 1104 { 1105 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); 1106 bool is_vram = bo->tbo.resource->mem_type == TTM_PL_VRAM; 1107 bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT | AMDGPU_GEM_CREATE_EXT_COHERENT); 1108 bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT; 1109 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED; 1110 struct amdgpu_vm *vm = mapping->bo_va->base.vm; 1111 unsigned int mtype_local, mtype; 1112 bool snoop = false; 1113 bool is_local; 1114 1115 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1116 case IP_VERSION(9, 4, 1): 1117 case IP_VERSION(9, 4, 2): 1118 if (is_vram) { 1119 if (bo_adev == adev) { 1120 if (uncached) 1121 mtype = MTYPE_UC; 1122 else if (coherent) 1123 mtype = MTYPE_CC; 1124 else 1125 mtype = MTYPE_RW; 1126 /* FIXME: is this still needed? Or does 1127 * amdgpu_ttm_tt_pde_flags already handle this? 1128 */ 1129 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == 1130 IP_VERSION(9, 4, 2) || 1131 amdgpu_ip_version(adev, GC_HWIP, 0) == 1132 IP_VERSION(9, 4, 3)) && 1133 adev->gmc.xgmi.connected_to_cpu) 1134 snoop = true; 1135 } else { 1136 if (uncached || coherent) 1137 mtype = MTYPE_UC; 1138 else 1139 mtype = MTYPE_NC; 1140 if (mapping->bo_va->is_xgmi) 1141 snoop = true; 1142 } 1143 } else { 1144 if (uncached || coherent) 1145 mtype = MTYPE_UC; 1146 else 1147 mtype = MTYPE_NC; 1148 /* FIXME: is this still needed? Or does 1149 * amdgpu_ttm_tt_pde_flags already handle this? 1150 */ 1151 snoop = true; 1152 } 1153 break; 1154 case IP_VERSION(9, 4, 3): 1155 /* Only local VRAM BOs or system memory on non-NUMA APUs 1156 * can be assumed to be local in their entirety. Choose 1157 * MTYPE_NC as safe fallback for all system memory BOs on 1158 * NUMA systems. Their MTYPE can be overridden per-page in 1159 * gmc_v9_0_override_vm_pte_flags. 1160 */ 1161 mtype_local = MTYPE_RW; 1162 if (amdgpu_mtype_local == 1) { 1163 DRM_INFO_ONCE("Using MTYPE_NC for local memory\n"); 1164 mtype_local = MTYPE_NC; 1165 } else if (amdgpu_mtype_local == 2) { 1166 DRM_INFO_ONCE("Using MTYPE_CC for local memory\n"); 1167 mtype_local = MTYPE_CC; 1168 } else { 1169 DRM_INFO_ONCE("Using MTYPE_RW for local memory\n"); 1170 } 1171 is_local = (!is_vram && (adev->flags & AMD_IS_APU) && 1172 num_possible_nodes() <= 1) || 1173 (is_vram && adev == bo_adev && 1174 KFD_XCP_MEM_ID(adev, bo->xcp_id) == vm->mem_id); 1175 snoop = true; 1176 if (uncached) { 1177 mtype = MTYPE_UC; 1178 } else if (ext_coherent) { 1179 mtype = is_local ? MTYPE_CC : MTYPE_UC; 1180 } else if (adev->flags & AMD_IS_APU) { 1181 mtype = is_local ? mtype_local : MTYPE_NC; 1182 } else { 1183 /* dGPU */ 1184 if (is_local) 1185 mtype = mtype_local; 1186 else if (is_vram) 1187 mtype = MTYPE_NC; 1188 else 1189 mtype = MTYPE_UC; 1190 } 1191 1192 break; 1193 default: 1194 if (uncached || coherent) 1195 mtype = MTYPE_UC; 1196 else 1197 mtype = MTYPE_NC; 1198 1199 /* FIXME: is this still needed? Or does 1200 * amdgpu_ttm_tt_pde_flags already handle this? 1201 */ 1202 if (!is_vram) 1203 snoop = true; 1204 } 1205 1206 if (mtype != MTYPE_NC) 1207 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 1208 AMDGPU_PTE_MTYPE_VG10(mtype); 1209 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0; 1210 } 1211 1212 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 1213 struct amdgpu_bo_va_mapping *mapping, 1214 uint64_t *flags) 1215 { 1216 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 1217 1218 *flags &= ~AMDGPU_PTE_EXECUTABLE; 1219 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 1220 1221 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1222 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; 1223 1224 if (mapping->flags & AMDGPU_PTE_PRT) { 1225 *flags |= AMDGPU_PTE_PRT; 1226 *flags &= ~AMDGPU_PTE_VALID; 1227 } 1228 1229 if (bo && bo->tbo.resource) 1230 gmc_v9_0_get_coherence_flags(adev, mapping->bo_va->base.bo, 1231 mapping, flags); 1232 } 1233 1234 static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev, 1235 struct amdgpu_vm *vm, 1236 uint64_t addr, uint64_t *flags) 1237 { 1238 int local_node, nid; 1239 1240 /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes. Local system 1241 * memory can use more efficient MTYPEs. 1242 */ 1243 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3)) 1244 return; 1245 1246 /* Only direct-mapped memory allows us to determine the NUMA node from 1247 * the DMA address. 1248 */ 1249 if (!adev->ram_is_direct_mapped) { 1250 dev_dbg_ratelimited(adev->dev, "RAM is not direct mapped\n"); 1251 return; 1252 } 1253 1254 /* Only override mappings with MTYPE_NC, which is the safe default for 1255 * cacheable memory. 1256 */ 1257 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1258 AMDGPU_PTE_MTYPE_VG10(MTYPE_NC)) { 1259 dev_dbg_ratelimited(adev->dev, "MTYPE is not NC\n"); 1260 return; 1261 } 1262 1263 /* FIXME: Only supported on native mode for now. For carve-out, the 1264 * NUMA affinity of the GPU/VM needs to come from the PCI info because 1265 * memory partitions are not associated with different NUMA nodes. 1266 */ 1267 if (adev->gmc.is_app_apu && vm->mem_id >= 0) { 1268 local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node; 1269 } else { 1270 dev_dbg_ratelimited(adev->dev, "Only native mode APU is supported.\n"); 1271 return; 1272 } 1273 1274 /* Only handle real RAM. Mappings of PCIe resources don't have struct 1275 * page or NUMA nodes. 1276 */ 1277 if (!page_is_ram(addr >> PAGE_SHIFT)) { 1278 dev_dbg_ratelimited(adev->dev, "Page is not RAM.\n"); 1279 return; 1280 } 1281 nid = pfn_to_nid(addr >> PAGE_SHIFT); 1282 dev_dbg_ratelimited(adev->dev, "vm->mem_id=%d, local_node=%d, nid=%d\n", 1283 vm->mem_id, local_node, nid); 1284 if (nid == local_node) { 1285 uint64_t old_flags = *flags; 1286 unsigned int mtype_local = MTYPE_RW; 1287 1288 if (amdgpu_mtype_local == 1) 1289 mtype_local = MTYPE_NC; 1290 else if (amdgpu_mtype_local == 2) 1291 mtype_local = MTYPE_CC; 1292 1293 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 1294 AMDGPU_PTE_MTYPE_VG10(mtype_local); 1295 dev_dbg_ratelimited(adev->dev, "flags updated from %llx to %llx\n", 1296 old_flags, *flags); 1297 } 1298 } 1299 1300 static unsigned int gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1301 { 1302 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1303 unsigned int size; 1304 1305 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */ 1306 1307 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1308 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1309 } else { 1310 u32 viewport; 1311 1312 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1313 case IP_VERSION(1, 0, 0): 1314 case IP_VERSION(1, 0, 1): 1315 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1316 size = (REG_GET_FIELD(viewport, 1317 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1318 REG_GET_FIELD(viewport, 1319 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1320 4); 1321 break; 1322 case IP_VERSION(2, 1, 0): 1323 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2); 1324 size = (REG_GET_FIELD(viewport, 1325 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1326 REG_GET_FIELD(viewport, 1327 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1328 4); 1329 break; 1330 default: 1331 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1332 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1333 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1334 4); 1335 break; 1336 } 1337 } 1338 1339 return size; 1340 } 1341 1342 static enum amdgpu_memory_partition 1343 gmc_v9_0_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes) 1344 { 1345 enum amdgpu_memory_partition mode = UNKNOWN_MEMORY_PARTITION_MODE; 1346 1347 if (adev->nbio.funcs->get_memory_partition_mode) 1348 mode = adev->nbio.funcs->get_memory_partition_mode(adev, 1349 supp_modes); 1350 1351 return mode; 1352 } 1353 1354 static enum amdgpu_memory_partition 1355 gmc_v9_0_query_memory_partition(struct amdgpu_device *adev) 1356 { 1357 if (amdgpu_sriov_vf(adev)) 1358 return AMDGPU_NPS1_PARTITION_MODE; 1359 1360 return gmc_v9_0_get_memory_partition(adev, NULL); 1361 } 1362 1363 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 1364 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 1365 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 1366 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 1367 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 1368 .map_mtype = gmc_v9_0_map_mtype, 1369 .get_vm_pde = gmc_v9_0_get_vm_pde, 1370 .get_vm_pte = gmc_v9_0_get_vm_pte, 1371 .override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags, 1372 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size, 1373 .query_mem_partition_mode = &gmc_v9_0_query_memory_partition, 1374 }; 1375 1376 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 1377 { 1378 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 1379 } 1380 1381 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 1382 { 1383 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1384 case IP_VERSION(6, 0, 0): 1385 adev->umc.funcs = &umc_v6_0_funcs; 1386 break; 1387 case IP_VERSION(6, 1, 1): 1388 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1389 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1390 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1391 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 1392 adev->umc.retire_unit = 1; 1393 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1394 adev->umc.ras = &umc_v6_1_ras; 1395 break; 1396 case IP_VERSION(6, 1, 2): 1397 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1398 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1399 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1400 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 1401 adev->umc.retire_unit = 1; 1402 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1403 adev->umc.ras = &umc_v6_1_ras; 1404 break; 1405 case IP_VERSION(6, 7, 0): 1406 adev->umc.max_ras_err_cnt_per_query = 1407 UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL; 1408 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM; 1409 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM; 1410 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET; 1411 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2); 1412 if (!adev->gmc.xgmi.connected_to_cpu) 1413 adev->umc.ras = &umc_v6_7_ras; 1414 if (1 & adev->smuio.funcs->get_die_id(adev)) 1415 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0]; 1416 else 1417 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0]; 1418 break; 1419 case IP_VERSION(12, 0, 0): 1420 adev->umc.max_ras_err_cnt_per_query = 1421 UMC_V12_0_TOTAL_CHANNEL_NUM(adev) * UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL; 1422 adev->umc.channel_inst_num = UMC_V12_0_CHANNEL_INSTANCE_NUM; 1423 adev->umc.umc_inst_num = UMC_V12_0_UMC_INSTANCE_NUM; 1424 adev->umc.node_inst_num /= UMC_V12_0_UMC_INSTANCE_NUM; 1425 adev->umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET; 1426 adev->umc.active_mask = adev->aid_mask; 1427 adev->umc.retire_unit = UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL; 1428 adev->umc.channel_idx_tbl = &umc_v12_0_channel_idx_tbl[0][0][0]; 1429 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1430 adev->umc.ras = &umc_v12_0_ras; 1431 break; 1432 default: 1433 break; 1434 } 1435 } 1436 1437 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 1438 { 1439 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1440 case IP_VERSION(9, 4, 1): 1441 adev->mmhub.funcs = &mmhub_v9_4_funcs; 1442 break; 1443 case IP_VERSION(9, 4, 2): 1444 adev->mmhub.funcs = &mmhub_v1_7_funcs; 1445 break; 1446 case IP_VERSION(1, 8, 0): 1447 adev->mmhub.funcs = &mmhub_v1_8_funcs; 1448 break; 1449 default: 1450 adev->mmhub.funcs = &mmhub_v1_0_funcs; 1451 break; 1452 } 1453 } 1454 1455 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) 1456 { 1457 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1458 case IP_VERSION(9, 4, 0): 1459 adev->mmhub.ras = &mmhub_v1_0_ras; 1460 break; 1461 case IP_VERSION(9, 4, 1): 1462 adev->mmhub.ras = &mmhub_v9_4_ras; 1463 break; 1464 case IP_VERSION(9, 4, 2): 1465 adev->mmhub.ras = &mmhub_v1_7_ras; 1466 break; 1467 case IP_VERSION(1, 8, 0): 1468 adev->mmhub.ras = &mmhub_v1_8_ras; 1469 break; 1470 default: 1471 /* mmhub ras is not available */ 1472 break; 1473 } 1474 } 1475 1476 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) 1477 { 1478 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 1479 adev->gfxhub.funcs = &gfxhub_v1_2_funcs; 1480 else 1481 adev->gfxhub.funcs = &gfxhub_v1_0_funcs; 1482 } 1483 1484 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev) 1485 { 1486 adev->hdp.ras = &hdp_v4_0_ras; 1487 } 1488 1489 static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev) 1490 { 1491 struct amdgpu_mca *mca = &adev->mca; 1492 1493 /* is UMC the right IP to check for MCA? Maybe DF? */ 1494 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1495 case IP_VERSION(6, 7, 0): 1496 if (!adev->gmc.xgmi.connected_to_cpu) { 1497 mca->mp0.ras = &mca_v3_0_mp0_ras; 1498 mca->mp1.ras = &mca_v3_0_mp1_ras; 1499 mca->mpio.ras = &mca_v3_0_mpio_ras; 1500 } 1501 break; 1502 default: 1503 break; 1504 } 1505 } 1506 1507 static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev) 1508 { 1509 if (!adev->gmc.xgmi.connected_to_cpu) 1510 adev->gmc.xgmi.ras = &xgmi_ras; 1511 } 1512 1513 static int gmc_v9_0_early_init(void *handle) 1514 { 1515 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1516 1517 /* 1518 * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined 1519 * in their IP discovery tables 1520 */ 1521 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) || 1522 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 1523 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 1524 adev->gmc.xgmi.supported = true; 1525 1526 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(6, 1, 0)) { 1527 adev->gmc.xgmi.supported = true; 1528 adev->gmc.xgmi.connected_to_cpu = 1529 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); 1530 } 1531 1532 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { 1533 enum amdgpu_pkg_type pkg_type = 1534 adev->smuio.funcs->get_pkg_type(adev); 1535 /* On GFXIP 9.4.3. APU, there is no physical VRAM domain present 1536 * and the APU, can be in used two possible modes: 1537 * - carveout mode 1538 * - native APU mode 1539 * "is_app_apu" can be used to identify the APU in the native 1540 * mode. 1541 */ 1542 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU && 1543 !pci_resource_len(adev->pdev, 0)); 1544 } 1545 1546 gmc_v9_0_set_gmc_funcs(adev); 1547 gmc_v9_0_set_irq_funcs(adev); 1548 gmc_v9_0_set_umc_funcs(adev); 1549 gmc_v9_0_set_mmhub_funcs(adev); 1550 gmc_v9_0_set_mmhub_ras_funcs(adev); 1551 gmc_v9_0_set_gfxhub_funcs(adev); 1552 gmc_v9_0_set_hdp_ras_funcs(adev); 1553 gmc_v9_0_set_mca_ras_funcs(adev); 1554 gmc_v9_0_set_xgmi_ras_funcs(adev); 1555 1556 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1557 adev->gmc.shared_aperture_end = 1558 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1559 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 1560 adev->gmc.private_aperture_end = 1561 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1562 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 1563 1564 return 0; 1565 } 1566 1567 static int gmc_v9_0_late_init(void *handle) 1568 { 1569 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1570 int r; 1571 1572 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 1573 if (r) 1574 return r; 1575 1576 /* 1577 * Workaround performance drop issue with VBIOS enables partial 1578 * writes, while disables HBM ECC for vega10. 1579 */ 1580 if (!amdgpu_sriov_vf(adev) && 1581 (amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(6, 0, 0))) { 1582 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) { 1583 if (adev->df.funcs && 1584 adev->df.funcs->enable_ecc_force_par_wr_rmw) 1585 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 1586 } 1587 } 1588 1589 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1590 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB); 1591 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__HDP); 1592 } 1593 1594 r = amdgpu_gmc_ras_late_init(adev); 1595 if (r) 1596 return r; 1597 1598 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1599 } 1600 1601 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 1602 struct amdgpu_gmc *mc) 1603 { 1604 u64 base = adev->mmhub.funcs->get_fb_location(adev); 1605 1606 /* add the xgmi offset of the physical node */ 1607 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1608 if (adev->gmc.xgmi.connected_to_cpu) { 1609 amdgpu_gmc_sysvm_location(adev, mc); 1610 } else { 1611 amdgpu_gmc_vram_location(adev, mc, base); 1612 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 1613 if (!amdgpu_sriov_vf(adev)) 1614 amdgpu_gmc_agp_location(adev, mc); 1615 } 1616 /* base offset of vram pages */ 1617 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 1618 1619 /* XXX: add the xgmi offset of the physical node? */ 1620 adev->vm_manager.vram_base_offset += 1621 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1622 } 1623 1624 /** 1625 * gmc_v9_0_mc_init - initialize the memory controller driver params 1626 * 1627 * @adev: amdgpu_device pointer 1628 * 1629 * Look up the amount of vram, vram width, and decide how to place 1630 * vram and gart within the GPU's physical address space. 1631 * Returns 0 for success. 1632 */ 1633 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 1634 { 1635 int r; 1636 1637 /* size in MB on si */ 1638 if (!adev->gmc.is_app_apu) { 1639 adev->gmc.mc_vram_size = 1640 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 1641 } else { 1642 DRM_DEBUG("Set mc_vram_size = 0 for APP APU\n"); 1643 adev->gmc.mc_vram_size = 0; 1644 } 1645 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 1646 1647 if (!(adev->flags & AMD_IS_APU) && 1648 !adev->gmc.xgmi.connected_to_cpu) { 1649 r = amdgpu_device_resize_fb_bar(adev); 1650 if (r) 1651 return r; 1652 } 1653 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 1654 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 1655 1656 #ifdef CONFIG_X86_64 1657 /* 1658 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi 1659 * interface can use VRAM through here as it appears system reserved 1660 * memory in host address space. 1661 * 1662 * For APUs, VRAM is just the stolen system memory and can be accessed 1663 * directly. 1664 * 1665 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR. 1666 */ 1667 1668 /* check whether both host-gpu and gpu-gpu xgmi links exist */ 1669 if ((!amdgpu_sriov_vf(adev) && 1670 (adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) || 1671 (adev->gmc.xgmi.supported && 1672 adev->gmc.xgmi.connected_to_cpu)) { 1673 adev->gmc.aper_base = 1674 adev->gfxhub.funcs->get_mc_fb_offset(adev) + 1675 adev->gmc.xgmi.physical_node_id * 1676 adev->gmc.xgmi.node_segment_size; 1677 adev->gmc.aper_size = adev->gmc.real_vram_size; 1678 } 1679 1680 #endif 1681 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1682 1683 /* set the gart size */ 1684 if (amdgpu_gart_size == -1) { 1685 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1686 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ 1687 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ 1688 case IP_VERSION(9, 4, 0): 1689 case IP_VERSION(9, 4, 1): 1690 case IP_VERSION(9, 4, 2): 1691 case IP_VERSION(9, 4, 3): 1692 default: 1693 adev->gmc.gart_size = 512ULL << 20; 1694 break; 1695 case IP_VERSION(9, 1, 0): /* DCE SG support */ 1696 case IP_VERSION(9, 2, 2): /* DCE SG support */ 1697 case IP_VERSION(9, 3, 0): 1698 adev->gmc.gart_size = 1024ULL << 20; 1699 break; 1700 } 1701 } else { 1702 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 1703 } 1704 1705 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 1706 1707 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1708 1709 return 0; 1710 } 1711 1712 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1713 { 1714 int r; 1715 1716 if (adev->gart.bo) { 1717 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1718 return 0; 1719 } 1720 1721 if (adev->gmc.xgmi.connected_to_cpu) { 1722 adev->gmc.vmid0_page_table_depth = 1; 1723 adev->gmc.vmid0_page_table_block_size = 12; 1724 } else { 1725 adev->gmc.vmid0_page_table_depth = 0; 1726 adev->gmc.vmid0_page_table_block_size = 0; 1727 } 1728 1729 /* Initialize common gart structure */ 1730 r = amdgpu_gart_init(adev); 1731 if (r) 1732 return r; 1733 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1734 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | 1735 AMDGPU_PTE_EXECUTABLE; 1736 1737 if (!adev->gmc.real_vram_size) { 1738 dev_info(adev->dev, "Put GART in system memory for APU\n"); 1739 r = amdgpu_gart_table_ram_alloc(adev); 1740 if (r) 1741 dev_err(adev->dev, "Failed to allocate GART in system memory\n"); 1742 } else { 1743 r = amdgpu_gart_table_vram_alloc(adev); 1744 if (r) 1745 return r; 1746 1747 if (adev->gmc.xgmi.connected_to_cpu) 1748 r = amdgpu_gmc_pdb0_alloc(adev); 1749 } 1750 1751 return r; 1752 } 1753 1754 /** 1755 * gmc_v9_0_save_registers - saves regs 1756 * 1757 * @adev: amdgpu_device pointer 1758 * 1759 * This saves potential register values that should be 1760 * restored upon resume 1761 */ 1762 static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1763 { 1764 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 1765 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) 1766 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1767 } 1768 1769 static bool gmc_v9_0_validate_partition_info(struct amdgpu_device *adev) 1770 { 1771 enum amdgpu_memory_partition mode; 1772 u32 supp_modes; 1773 bool valid; 1774 1775 mode = gmc_v9_0_get_memory_partition(adev, &supp_modes); 1776 1777 /* Mode detected by hardware not present in supported modes */ 1778 if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) && 1779 !(BIT(mode - 1) & supp_modes)) 1780 return false; 1781 1782 switch (mode) { 1783 case UNKNOWN_MEMORY_PARTITION_MODE: 1784 case AMDGPU_NPS1_PARTITION_MODE: 1785 valid = (adev->gmc.num_mem_partitions == 1); 1786 break; 1787 case AMDGPU_NPS2_PARTITION_MODE: 1788 valid = (adev->gmc.num_mem_partitions == 2); 1789 break; 1790 case AMDGPU_NPS4_PARTITION_MODE: 1791 valid = (adev->gmc.num_mem_partitions == 3 || 1792 adev->gmc.num_mem_partitions == 4); 1793 break; 1794 default: 1795 valid = false; 1796 } 1797 1798 return valid; 1799 } 1800 1801 static bool gmc_v9_0_is_node_present(int *node_ids, int num_ids, int nid) 1802 { 1803 int i; 1804 1805 /* Check if node with id 'nid' is present in 'node_ids' array */ 1806 for (i = 0; i < num_ids; ++i) 1807 if (node_ids[i] == nid) 1808 return true; 1809 1810 return false; 1811 } 1812 1813 static void 1814 gmc_v9_0_init_acpi_mem_ranges(struct amdgpu_device *adev, 1815 struct amdgpu_mem_partition_info *mem_ranges) 1816 { 1817 struct amdgpu_numa_info numa_info; 1818 int node_ids[MAX_MEM_RANGES]; 1819 int num_ranges = 0, ret; 1820 int num_xcc, xcc_id; 1821 uint32_t xcc_mask; 1822 1823 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1824 xcc_mask = (1U << num_xcc) - 1; 1825 1826 for_each_inst(xcc_id, xcc_mask) { 1827 ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 1828 if (ret) 1829 continue; 1830 1831 if (numa_info.nid == NUMA_NO_NODE) { 1832 mem_ranges[0].size = numa_info.size; 1833 mem_ranges[0].numa.node = numa_info.nid; 1834 num_ranges = 1; 1835 break; 1836 } 1837 1838 if (gmc_v9_0_is_node_present(node_ids, num_ranges, 1839 numa_info.nid)) 1840 continue; 1841 1842 node_ids[num_ranges] = numa_info.nid; 1843 mem_ranges[num_ranges].numa.node = numa_info.nid; 1844 mem_ranges[num_ranges].size = numa_info.size; 1845 ++num_ranges; 1846 } 1847 1848 adev->gmc.num_mem_partitions = num_ranges; 1849 } 1850 1851 static void 1852 gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device *adev, 1853 struct amdgpu_mem_partition_info *mem_ranges) 1854 { 1855 enum amdgpu_memory_partition mode; 1856 u32 start_addr = 0, size; 1857 int i; 1858 1859 mode = gmc_v9_0_query_memory_partition(adev); 1860 1861 switch (mode) { 1862 case UNKNOWN_MEMORY_PARTITION_MODE: 1863 case AMDGPU_NPS1_PARTITION_MODE: 1864 adev->gmc.num_mem_partitions = 1; 1865 break; 1866 case AMDGPU_NPS2_PARTITION_MODE: 1867 adev->gmc.num_mem_partitions = 2; 1868 break; 1869 case AMDGPU_NPS4_PARTITION_MODE: 1870 if (adev->flags & AMD_IS_APU) 1871 adev->gmc.num_mem_partitions = 3; 1872 else 1873 adev->gmc.num_mem_partitions = 4; 1874 break; 1875 default: 1876 adev->gmc.num_mem_partitions = 1; 1877 break; 1878 } 1879 1880 size = adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT; 1881 size /= adev->gmc.num_mem_partitions; 1882 1883 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 1884 mem_ranges[i].range.fpfn = start_addr; 1885 mem_ranges[i].size = ((u64)size << AMDGPU_GPU_PAGE_SHIFT); 1886 mem_ranges[i].range.lpfn = start_addr + size - 1; 1887 start_addr += size; 1888 } 1889 1890 /* Adjust the last one */ 1891 mem_ranges[adev->gmc.num_mem_partitions - 1].range.lpfn = 1892 (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT) - 1; 1893 mem_ranges[adev->gmc.num_mem_partitions - 1].size = 1894 adev->gmc.real_vram_size - 1895 ((u64)mem_ranges[adev->gmc.num_mem_partitions - 1].range.fpfn 1896 << AMDGPU_GPU_PAGE_SHIFT); 1897 } 1898 1899 static int gmc_v9_0_init_mem_ranges(struct amdgpu_device *adev) 1900 { 1901 bool valid; 1902 1903 adev->gmc.mem_partitions = kcalloc(MAX_MEM_RANGES, 1904 sizeof(struct amdgpu_mem_partition_info), 1905 GFP_KERNEL); 1906 if (!adev->gmc.mem_partitions) 1907 return -ENOMEM; 1908 1909 /* TODO : Get the range from PSP/Discovery for dGPU */ 1910 if (adev->gmc.is_app_apu) 1911 gmc_v9_0_init_acpi_mem_ranges(adev, adev->gmc.mem_partitions); 1912 else 1913 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); 1914 1915 if (amdgpu_sriov_vf(adev)) 1916 valid = true; 1917 else 1918 valid = gmc_v9_0_validate_partition_info(adev); 1919 if (!valid) { 1920 /* TODO: handle invalid case */ 1921 dev_WARN(adev->dev, 1922 "Mem ranges not matching with hardware config"); 1923 } 1924 1925 return 0; 1926 } 1927 1928 static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) 1929 { 1930 static const u32 regBIF_BIOS_SCRATCH_4 = 0x50; 1931 u32 vram_info; 1932 1933 if (!amdgpu_sriov_vf(adev)) { 1934 vram_info = RREG32(regBIF_BIOS_SCRATCH_4); 1935 adev->gmc.vram_vendor = vram_info & 0xF; 1936 } 1937 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 1938 adev->gmc.vram_width = 128 * 64; 1939 } 1940 1941 static int gmc_v9_0_sw_init(void *handle) 1942 { 1943 int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits; 1944 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1945 unsigned long inst_mask = adev->aid_mask; 1946 1947 adev->gfxhub.funcs->init(adev); 1948 1949 adev->mmhub.funcs->init(adev); 1950 1951 spin_lock_init(&adev->gmc.invalidate_lock); 1952 1953 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { 1954 gmc_v9_4_3_init_vram_info(adev); 1955 } else if (!adev->bios) { 1956 if (adev->flags & AMD_IS_APU) { 1957 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 1958 adev->gmc.vram_width = 64 * 64; 1959 } else { 1960 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 1961 adev->gmc.vram_width = 128 * 64; 1962 } 1963 } else { 1964 r = amdgpu_atomfirmware_get_vram_info(adev, 1965 &vram_width, &vram_type, &vram_vendor); 1966 if (amdgpu_sriov_vf(adev)) 1967 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 1968 * and DF related registers is not readable, seems hardcord is the 1969 * only way to set the correct vram_width 1970 */ 1971 adev->gmc.vram_width = 2048; 1972 else if (amdgpu_emu_mode != 1) 1973 adev->gmc.vram_width = vram_width; 1974 1975 if (!adev->gmc.vram_width) { 1976 int chansize, numchan; 1977 1978 /* hbm memory channel size */ 1979 if (adev->flags & AMD_IS_APU) 1980 chansize = 64; 1981 else 1982 chansize = 128; 1983 if (adev->df.funcs && 1984 adev->df.funcs->get_hbm_channel_number) { 1985 numchan = adev->df.funcs->get_hbm_channel_number(adev); 1986 adev->gmc.vram_width = numchan * chansize; 1987 } 1988 } 1989 1990 adev->gmc.vram_type = vram_type; 1991 adev->gmc.vram_vendor = vram_vendor; 1992 } 1993 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1994 case IP_VERSION(9, 1, 0): 1995 case IP_VERSION(9, 2, 2): 1996 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 1997 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 1998 1999 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 2000 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2001 } else { 2002 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 2003 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 2004 adev->gmc.translate_further = 2005 adev->vm_manager.num_level > 1; 2006 } 2007 break; 2008 case IP_VERSION(9, 0, 1): 2009 case IP_VERSION(9, 2, 1): 2010 case IP_VERSION(9, 4, 0): 2011 case IP_VERSION(9, 3, 0): 2012 case IP_VERSION(9, 4, 2): 2013 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2014 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2015 2016 /* 2017 * To fulfill 4-level page support, 2018 * vm size is 256TB (48bit), maximum size of Vega10, 2019 * block size 512 (9bit) 2020 */ 2021 2022 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2023 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 2024 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2025 break; 2026 case IP_VERSION(9, 4, 1): 2027 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2028 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2029 set_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask); 2030 2031 /* Keep the vm size same with Vega20 */ 2032 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2033 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2034 break; 2035 case IP_VERSION(9, 4, 3): 2036 bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0), 2037 NUM_XCC(adev->gfx.xcc_mask)); 2038 2039 inst_mask <<= AMDGPU_MMHUB0(0); 2040 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32); 2041 2042 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2043 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2044 break; 2045 default: 2046 break; 2047 } 2048 2049 /* This interrupt is VMC page fault.*/ 2050 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 2051 &adev->gmc.vm_fault); 2052 if (r) 2053 return r; 2054 2055 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1)) { 2056 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 2057 &adev->gmc.vm_fault); 2058 if (r) 2059 return r; 2060 } 2061 2062 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 2063 &adev->gmc.vm_fault); 2064 2065 if (r) 2066 return r; 2067 2068 if (!amdgpu_sriov_vf(adev) && 2069 !adev->gmc.xgmi.connected_to_cpu && 2070 !adev->gmc.is_app_apu) { 2071 /* interrupt sent to DF. */ 2072 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 2073 &adev->gmc.ecc_irq); 2074 if (r) 2075 return r; 2076 } 2077 2078 /* Set the internal MC address mask 2079 * This is the max address of the GPU's 2080 * internal address space. 2081 */ 2082 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 2083 2084 dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >= 2085 IP_VERSION(9, 4, 2) ? 2086 48 : 2087 44; 2088 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits)); 2089 if (r) { 2090 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 2091 return r; 2092 } 2093 adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits); 2094 2095 r = gmc_v9_0_mc_init(adev); 2096 if (r) 2097 return r; 2098 2099 amdgpu_gmc_get_vbios_allocations(adev); 2100 2101 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { 2102 r = gmc_v9_0_init_mem_ranges(adev); 2103 if (r) 2104 return r; 2105 } 2106 2107 /* Memory manager */ 2108 r = amdgpu_bo_init(adev); 2109 if (r) 2110 return r; 2111 2112 r = gmc_v9_0_gart_init(adev); 2113 if (r) 2114 return r; 2115 2116 /* 2117 * number of VMs 2118 * VMID 0 is reserved for System 2119 * amdgpu graphics/compute will use VMIDs 1..n-1 2120 * amdkfd will use VMIDs n..15 2121 * 2122 * The first KFD VMID is 8 for GPUs with graphics, 3 for 2123 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs 2124 * for video processing. 2125 */ 2126 adev->vm_manager.first_kfd_vmid = 2127 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 2128 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 2129 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) ? 2130 3 : 2131 8; 2132 2133 amdgpu_vm_manager_init(adev); 2134 2135 gmc_v9_0_save_registers(adev); 2136 2137 r = amdgpu_gmc_ras_sw_init(adev); 2138 if (r) 2139 return r; 2140 2141 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 2142 amdgpu_gmc_sysfs_init(adev); 2143 2144 return 0; 2145 } 2146 2147 static int gmc_v9_0_sw_fini(void *handle) 2148 { 2149 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2150 2151 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 2152 amdgpu_gmc_sysfs_fini(adev); 2153 adev->gmc.num_mem_partitions = 0; 2154 kfree(adev->gmc.mem_partitions); 2155 2156 amdgpu_gmc_ras_fini(adev); 2157 amdgpu_gem_force_release(adev); 2158 amdgpu_vm_manager_fini(adev); 2159 if (!adev->gmc.real_vram_size) { 2160 dev_info(adev->dev, "Put GART in system memory for APU free\n"); 2161 amdgpu_gart_table_ram_free(adev); 2162 } else { 2163 amdgpu_gart_table_vram_free(adev); 2164 } 2165 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0); 2166 amdgpu_bo_fini(adev); 2167 2168 return 0; 2169 } 2170 2171 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 2172 { 2173 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 2174 case IP_VERSION(9, 0, 0): 2175 if (amdgpu_sriov_vf(adev)) 2176 break; 2177 fallthrough; 2178 case IP_VERSION(9, 4, 0): 2179 soc15_program_register_sequence(adev, 2180 golden_settings_mmhub_1_0_0, 2181 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 2182 soc15_program_register_sequence(adev, 2183 golden_settings_athub_1_0_0, 2184 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2185 break; 2186 case IP_VERSION(9, 1, 0): 2187 case IP_VERSION(9, 2, 0): 2188 /* TODO for renoir */ 2189 soc15_program_register_sequence(adev, 2190 golden_settings_athub_1_0_0, 2191 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2192 break; 2193 default: 2194 break; 2195 } 2196 } 2197 2198 /** 2199 * gmc_v9_0_restore_registers - restores regs 2200 * 2201 * @adev: amdgpu_device pointer 2202 * 2203 * This restores register values, saved at suspend. 2204 */ 2205 void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 2206 { 2207 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 2208 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) { 2209 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 2210 WARN_ON(adev->gmc.sdpif_register != 2211 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)); 2212 } 2213 } 2214 2215 /** 2216 * gmc_v9_0_gart_enable - gart enable 2217 * 2218 * @adev: amdgpu_device pointer 2219 */ 2220 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 2221 { 2222 int r; 2223 2224 if (adev->gmc.xgmi.connected_to_cpu) 2225 amdgpu_gmc_init_pdb0(adev); 2226 2227 if (adev->gart.bo == NULL) { 2228 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 2229 return -EINVAL; 2230 } 2231 2232 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 2233 2234 if (!adev->in_s0ix) { 2235 r = adev->gfxhub.funcs->gart_enable(adev); 2236 if (r) 2237 return r; 2238 } 2239 2240 r = adev->mmhub.funcs->gart_enable(adev); 2241 if (r) 2242 return r; 2243 2244 DRM_INFO("PCIE GART of %uM enabled.\n", 2245 (unsigned int)(adev->gmc.gart_size >> 20)); 2246 if (adev->gmc.pdb0_bo) 2247 DRM_INFO("PDB0 located at 0x%016llX\n", 2248 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); 2249 DRM_INFO("PTB located at 0x%016llX\n", 2250 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 2251 2252 return 0; 2253 } 2254 2255 static int gmc_v9_0_hw_init(void *handle) 2256 { 2257 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2258 bool value; 2259 int i, r; 2260 2261 adev->gmc.flush_pasid_uses_kiq = true; 2262 2263 /* Vega20+XGMI caches PTEs in TC and TLB. Add a heavy-weight TLB flush 2264 * (type 2), which flushes both. Due to a race condition with 2265 * concurrent memory accesses using the same TLB cache line, we still 2266 * need a second TLB flush after this. 2267 */ 2268 adev->gmc.flush_tlb_needs_extra_type_2 = 2269 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) && 2270 adev->gmc.xgmi.num_physical_nodes; 2271 /* 2272 * TODO: This workaround is badly documented and had a buggy 2273 * implementation. We should probably verify what we do here. 2274 */ 2275 adev->gmc.flush_tlb_needs_extra_type_0 = 2276 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && 2277 adev->rev_id == 0; 2278 2279 /* The sequence of these two function calls matters.*/ 2280 gmc_v9_0_init_golden_registers(adev); 2281 2282 if (adev->mode_info.num_crtc) { 2283 /* Lockout access through VGA aperture*/ 2284 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 2285 /* disable VGA render */ 2286 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 2287 } 2288 2289 if (adev->mmhub.funcs->update_power_gating) 2290 adev->mmhub.funcs->update_power_gating(adev, true); 2291 2292 adev->hdp.funcs->init_registers(adev); 2293 2294 /* After HDP is initialized, flush HDP.*/ 2295 adev->hdp.funcs->flush_hdp(adev, NULL); 2296 2297 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 2298 value = false; 2299 else 2300 value = true; 2301 2302 if (!amdgpu_sriov_vf(adev)) { 2303 if (!adev->in_s0ix) 2304 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 2305 adev->mmhub.funcs->set_fault_enable_default(adev, value); 2306 } 2307 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 2308 if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0))) 2309 continue; 2310 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 2311 } 2312 2313 if (adev->umc.funcs && adev->umc.funcs->init_registers) 2314 adev->umc.funcs->init_registers(adev); 2315 2316 r = gmc_v9_0_gart_enable(adev); 2317 if (r) 2318 return r; 2319 2320 if (amdgpu_emu_mode == 1) 2321 return amdgpu_gmc_vram_checking(adev); 2322 else 2323 return r; 2324 } 2325 2326 /** 2327 * gmc_v9_0_gart_disable - gart disable 2328 * 2329 * @adev: amdgpu_device pointer 2330 * 2331 * This disables all VM page table. 2332 */ 2333 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 2334 { 2335 if (!adev->in_s0ix) 2336 adev->gfxhub.funcs->gart_disable(adev); 2337 adev->mmhub.funcs->gart_disable(adev); 2338 } 2339 2340 static int gmc_v9_0_hw_fini(void *handle) 2341 { 2342 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2343 2344 gmc_v9_0_gart_disable(adev); 2345 2346 if (amdgpu_sriov_vf(adev)) { 2347 /* full access mode, so don't touch any GMC register */ 2348 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 2349 return 0; 2350 } 2351 2352 /* 2353 * Pair the operations did in gmc_v9_0_hw_init and thus maintain 2354 * a correct cached state for GMC. Otherwise, the "gate" again 2355 * operation on S3 resuming will fail due to wrong cached state. 2356 */ 2357 if (adev->mmhub.funcs->update_power_gating) 2358 adev->mmhub.funcs->update_power_gating(adev, false); 2359 2360 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 2361 2362 return 0; 2363 } 2364 2365 static int gmc_v9_0_suspend(void *handle) 2366 { 2367 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2368 2369 return gmc_v9_0_hw_fini(adev); 2370 } 2371 2372 static int gmc_v9_0_resume(void *handle) 2373 { 2374 int r; 2375 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2376 2377 r = gmc_v9_0_hw_init(adev); 2378 if (r) 2379 return r; 2380 2381 amdgpu_vmid_reset_all(adev); 2382 2383 return 0; 2384 } 2385 2386 static bool gmc_v9_0_is_idle(void *handle) 2387 { 2388 /* MC is always ready in GMC v9.*/ 2389 return true; 2390 } 2391 2392 static int gmc_v9_0_wait_for_idle(void *handle) 2393 { 2394 /* There is no need to wait for MC idle in GMC v9.*/ 2395 return 0; 2396 } 2397 2398 static int gmc_v9_0_soft_reset(void *handle) 2399 { 2400 /* XXX for emulation.*/ 2401 return 0; 2402 } 2403 2404 static int gmc_v9_0_set_clockgating_state(void *handle, 2405 enum amd_clockgating_state state) 2406 { 2407 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2408 2409 adev->mmhub.funcs->set_clockgating(adev, state); 2410 2411 athub_v1_0_set_clockgating(adev, state); 2412 2413 return 0; 2414 } 2415 2416 static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags) 2417 { 2418 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2419 2420 adev->mmhub.funcs->get_clockgating(adev, flags); 2421 2422 athub_v1_0_get_clockgating(adev, flags); 2423 } 2424 2425 static int gmc_v9_0_set_powergating_state(void *handle, 2426 enum amd_powergating_state state) 2427 { 2428 return 0; 2429 } 2430 2431 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 2432 .name = "gmc_v9_0", 2433 .early_init = gmc_v9_0_early_init, 2434 .late_init = gmc_v9_0_late_init, 2435 .sw_init = gmc_v9_0_sw_init, 2436 .sw_fini = gmc_v9_0_sw_fini, 2437 .hw_init = gmc_v9_0_hw_init, 2438 .hw_fini = gmc_v9_0_hw_fini, 2439 .suspend = gmc_v9_0_suspend, 2440 .resume = gmc_v9_0_resume, 2441 .is_idle = gmc_v9_0_is_idle, 2442 .wait_for_idle = gmc_v9_0_wait_for_idle, 2443 .soft_reset = gmc_v9_0_soft_reset, 2444 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 2445 .set_powergating_state = gmc_v9_0_set_powergating_state, 2446 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 2447 }; 2448 2449 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = { 2450 .type = AMD_IP_BLOCK_TYPE_GMC, 2451 .major = 9, 2452 .minor = 0, 2453 .rev = 0, 2454 .funcs = &gmc_v9_0_ip_funcs, 2455 }; 2456