1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 26 #include <drm/drm_cache.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atomfirmware.h" 30 #include "gmc_v11_0.h" 31 #include "umc_v8_10.h" 32 #include "athub/athub_3_0_0_sh_mask.h" 33 #include "athub/athub_3_0_0_offset.h" 34 #include "dcn/dcn_3_2_0_offset.h" 35 #include "dcn/dcn_3_2_0_sh_mask.h" 36 #include "oss/osssys_6_0_0_offset.h" 37 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 38 #include "navi10_enum.h" 39 #include "soc15.h" 40 #include "soc15d.h" 41 #include "soc15_common.h" 42 #include "nbio_v4_3.h" 43 #include "gfxhub_v3_0.h" 44 #include "gfxhub_v3_0_3.h" 45 #include "gfxhub_v11_5_0.h" 46 #include "mmhub_v3_0.h" 47 #include "mmhub_v3_0_1.h" 48 #include "mmhub_v3_0_2.h" 49 #include "mmhub_v3_3.h" 50 #include "athub_v3_0.h" 51 52 53 static int gmc_v11_0_ecc_interrupt_state(struct amdgpu_device *adev, 54 struct amdgpu_irq_src *src, 55 unsigned int type, 56 enum amdgpu_interrupt_state state) 57 { 58 return 0; 59 } 60 61 static int 62 gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 63 struct amdgpu_irq_src *src, unsigned int type, 64 enum amdgpu_interrupt_state state) 65 { 66 switch (state) { 67 case AMDGPU_IRQ_STATE_DISABLE: 68 /* MM HUB */ 69 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false); 70 /* GFX HUB */ 71 /* This works because this interrupt is only 72 * enabled at init/resume and disabled in 73 * fini/suspend, so the overall state doesn't 74 * change over the course of suspend/resume. 75 */ 76 if (!adev->in_s0ix) 77 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false); 78 break; 79 case AMDGPU_IRQ_STATE_ENABLE: 80 /* MM HUB */ 81 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true); 82 /* GFX HUB */ 83 /* This works because this interrupt is only 84 * enabled at init/resume and disabled in 85 * fini/suspend, so the overall state doesn't 86 * change over the course of suspend/resume. 87 */ 88 if (!adev->in_s0ix) 89 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true); 90 break; 91 default: 92 break; 93 } 94 95 return 0; 96 } 97 98 static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev, 99 struct amdgpu_irq_src *source, 100 struct amdgpu_iv_entry *entry) 101 { 102 uint32_t vmhub_index = entry->client_id == SOC21_IH_CLIENTID_VMC ? 103 AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0); 104 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub_index]; 105 uint32_t status = 0; 106 u64 addr; 107 108 addr = (u64)entry->src_data[0] << 12; 109 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 110 111 if (!amdgpu_sriov_vf(adev)) { 112 /* 113 * Issue a dummy read to wait for the status register to 114 * be updated to avoid reading an incorrect value due to 115 * the new fast GRBM interface. 116 */ 117 if (entry->vmid_src == AMDGPU_GFXHUB(0)) 118 RREG32(hub->vm_l2_pro_fault_status); 119 120 status = RREG32(hub->vm_l2_pro_fault_status); 121 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 122 123 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, 124 entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); 125 } 126 127 if (printk_ratelimit()) { 128 struct amdgpu_task_info task_info; 129 130 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 131 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 132 133 dev_err(adev->dev, 134 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d)\n", 135 entry->vmid_src ? "mmhub" : "gfxhub", 136 entry->src_id, entry->ring_id, entry->vmid, 137 entry->pasid, task_info.process_name, task_info.tgid, 138 task_info.task_name, task_info.pid); 139 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 140 addr, entry->client_id); 141 if (!amdgpu_sriov_vf(adev)) 142 hub->vmhub_funcs->print_l2_protection_fault_status(adev, status); 143 } 144 145 return 0; 146 } 147 148 static const struct amdgpu_irq_src_funcs gmc_v11_0_irq_funcs = { 149 .set = gmc_v11_0_vm_fault_interrupt_state, 150 .process = gmc_v11_0_process_interrupt, 151 }; 152 153 static const struct amdgpu_irq_src_funcs gmc_v11_0_ecc_funcs = { 154 .set = gmc_v11_0_ecc_interrupt_state, 155 .process = amdgpu_umc_process_ecc_irq, 156 }; 157 158 static void gmc_v11_0_set_irq_funcs(struct amdgpu_device *adev) 159 { 160 adev->gmc.vm_fault.num_types = 1; 161 adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs; 162 163 if (!amdgpu_sriov_vf(adev)) { 164 adev->gmc.ecc_irq.num_types = 1; 165 adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs; 166 } 167 } 168 169 /** 170 * gmc_v11_0_use_invalidate_semaphore - judge whether to use semaphore 171 * 172 * @adev: amdgpu_device pointer 173 * @vmhub: vmhub type 174 * 175 */ 176 static bool gmc_v11_0_use_invalidate_semaphore(struct amdgpu_device *adev, 177 uint32_t vmhub) 178 { 179 return ((vmhub == AMDGPU_MMHUB0(0)) && 180 (!amdgpu_sriov_vf(adev))); 181 } 182 183 static bool gmc_v11_0_get_vmid_pasid_mapping_info( 184 struct amdgpu_device *adev, 185 uint8_t vmid, uint16_t *p_pasid) 186 { 187 *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff; 188 189 return !!(*p_pasid); 190 } 191 192 /** 193 * gmc_v11_0_flush_gpu_tlb - gart tlb flush callback 194 * 195 * @adev: amdgpu_device pointer 196 * @vmid: vm instance to flush 197 * @vmhub: which hub to flush 198 * @flush_type: the flush type 199 * 200 * Flush the TLB for the requested page table. 201 */ 202 static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 203 uint32_t vmhub, uint32_t flush_type) 204 { 205 bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(adev, vmhub); 206 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 207 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 208 /* Use register 17 for GART */ 209 const unsigned int eng = 17; 210 unsigned char hub_ip; 211 u32 sem, req, ack; 212 unsigned int i; 213 u32 tmp; 214 215 if ((vmhub == AMDGPU_GFXHUB(0)) && !adev->gfx.is_poweron) 216 return; 217 218 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; 219 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 220 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 221 222 /* flush hdp cache */ 223 adev->hdp.funcs->flush_hdp(adev, NULL); 224 225 /* For SRIOV run time, driver shouldn't access the register through MMIO 226 * Directly use kiq to do the vm invalidation instead 227 */ 228 if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring.sched.ready) && 229 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 230 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 231 1 << vmid); 232 return; 233 } 234 235 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP; 236 237 spin_lock(&adev->gmc.invalidate_lock); 238 /* 239 * It may lose gpuvm invalidate acknowldege state across power-gating 240 * off cycle, add semaphore acquire before invalidation and semaphore 241 * release after invalidation to avoid entering power gated state 242 * to WA the Issue 243 */ 244 245 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 246 if (use_semaphore) { 247 for (i = 0; i < adev->usec_timeout; i++) { 248 /* a read return value of 1 means semaphore acuqire */ 249 tmp = RREG32_RLC_NO_KIQ(sem, hub_ip); 250 if (tmp & 0x1) 251 break; 252 udelay(1); 253 } 254 255 if (i >= adev->usec_timeout) 256 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 257 } 258 259 WREG32_RLC_NO_KIQ(req, inv_req, hub_ip); 260 261 /* Wait for ACK with a delay.*/ 262 for (i = 0; i < adev->usec_timeout; i++) { 263 tmp = RREG32_RLC_NO_KIQ(ack, hub_ip); 264 tmp &= 1 << vmid; 265 if (tmp) 266 break; 267 268 udelay(1); 269 } 270 271 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 272 if (use_semaphore) 273 WREG32_RLC_NO_KIQ(sem, 0, hub_ip); 274 275 /* Issue additional private vm invalidation to MMHUB */ 276 if ((vmhub != AMDGPU_GFXHUB(0)) && 277 (hub->vm_l2_bank_select_reserved_cid2) && 278 !amdgpu_sriov_vf(adev)) { 279 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 280 /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ 281 inv_req |= (1 << 25); 282 /* Issue private invalidation */ 283 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); 284 /* Read back to ensure invalidation is done*/ 285 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 286 } 287 288 spin_unlock(&adev->gmc.invalidate_lock); 289 290 if (i >= adev->usec_timeout) 291 dev_err(adev->dev, "Timeout waiting for VM flush ACK!\n"); 292 } 293 294 /** 295 * gmc_v11_0_flush_gpu_tlb_pasid - tlb flush via pasid 296 * 297 * @adev: amdgpu_device pointer 298 * @pasid: pasid to be flush 299 * @flush_type: the flush type 300 * @all_hub: flush all hubs 301 * @inst: is used to select which instance of KIQ to use for the invalidation 302 * 303 * Flush the TLB for the requested pasid. 304 */ 305 static void gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 306 uint16_t pasid, uint32_t flush_type, 307 bool all_hub, uint32_t inst) 308 { 309 uint16_t queried; 310 int vmid, i; 311 312 for (vmid = 1; vmid < 16; vmid++) { 313 bool valid; 314 315 valid = gmc_v11_0_get_vmid_pasid_mapping_info(adev, vmid, 316 &queried); 317 if (!valid || queried != pasid) 318 continue; 319 320 if (all_hub) { 321 for_each_set_bit(i, adev->vmhubs_mask, 322 AMDGPU_MAX_VMHUBS) 323 gmc_v11_0_flush_gpu_tlb(adev, vmid, i, 324 flush_type); 325 } else { 326 gmc_v11_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 327 flush_type); 328 } 329 } 330 } 331 332 static uint64_t gmc_v11_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 333 unsigned int vmid, uint64_t pd_addr) 334 { 335 bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 336 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 337 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 338 unsigned int eng = ring->vm_inv_eng; 339 340 /* 341 * It may lose gpuvm invalidate acknowldege state across power-gating 342 * off cycle, add semaphore acquire before invalidation and semaphore 343 * release after invalidation to avoid entering power gated state 344 * to WA the Issue 345 */ 346 347 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 348 if (use_semaphore) 349 /* a read return value of 1 means semaphore acuqire */ 350 amdgpu_ring_emit_reg_wait(ring, 351 hub->vm_inv_eng0_sem + 352 hub->eng_distance * eng, 0x1, 0x1); 353 354 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 355 (hub->ctx_addr_distance * vmid), 356 lower_32_bits(pd_addr)); 357 358 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 359 (hub->ctx_addr_distance * vmid), 360 upper_32_bits(pd_addr)); 361 362 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 363 hub->eng_distance * eng, 364 hub->vm_inv_eng0_ack + 365 hub->eng_distance * eng, 366 req, 1 << vmid); 367 368 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 369 if (use_semaphore) 370 /* 371 * add semaphore release after invalidation, 372 * write with 0 means semaphore release 373 */ 374 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 375 hub->eng_distance * eng, 0); 376 377 return pd_addr; 378 } 379 380 static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 381 unsigned int pasid) 382 { 383 struct amdgpu_device *adev = ring->adev; 384 uint32_t reg; 385 386 /* MES fw manages IH_VMID_x_LUT updating */ 387 if (ring->is_mes_queue) 388 return; 389 390 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 391 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid; 392 else 393 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid; 394 395 amdgpu_ring_emit_wreg(ring, reg, pasid); 396 } 397 398 /* 399 * PTE format: 400 * 63:59 reserved 401 * 58:57 reserved 402 * 56 F 403 * 55 L 404 * 54 reserved 405 * 53:52 SW 406 * 51 T 407 * 50:48 mtype 408 * 47:12 4k physical page base address 409 * 11:7 fragment 410 * 6 write 411 * 5 read 412 * 4 exe 413 * 3 Z 414 * 2 snooped 415 * 1 system 416 * 0 valid 417 * 418 * PDE format: 419 * 63:59 block fragment size 420 * 58:55 reserved 421 * 54 P 422 * 53:48 reserved 423 * 47:6 physical base address of PD or PTE 424 * 5:3 reserved 425 * 2 C 426 * 1 system 427 * 0 valid 428 */ 429 430 static uint64_t gmc_v11_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 431 { 432 switch (flags) { 433 case AMDGPU_VM_MTYPE_DEFAULT: 434 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 435 case AMDGPU_VM_MTYPE_NC: 436 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 437 case AMDGPU_VM_MTYPE_WC: 438 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 439 case AMDGPU_VM_MTYPE_CC: 440 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 441 case AMDGPU_VM_MTYPE_UC: 442 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 443 default: 444 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 445 } 446 } 447 448 static void gmc_v11_0_get_vm_pde(struct amdgpu_device *adev, int level, 449 uint64_t *addr, uint64_t *flags) 450 { 451 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 452 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 453 BUG_ON(*addr & 0xFFFF00000000003FULL); 454 455 if (!adev->gmc.translate_further) 456 return; 457 458 if (level == AMDGPU_VM_PDB1) { 459 /* Set the block fragment size */ 460 if (!(*flags & AMDGPU_PDE_PTE)) 461 *flags |= AMDGPU_PDE_BFS(0x9); 462 463 } else if (level == AMDGPU_VM_PDB0) { 464 if (*flags & AMDGPU_PDE_PTE) 465 *flags &= ~AMDGPU_PDE_PTE; 466 else 467 *flags |= AMDGPU_PTE_TF; 468 } 469 } 470 471 static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev, 472 struct amdgpu_bo_va_mapping *mapping, 473 uint64_t *flags) 474 { 475 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 476 477 *flags &= ~AMDGPU_PTE_EXECUTABLE; 478 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 479 480 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 481 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 482 483 *flags &= ~AMDGPU_PTE_NOALLOC; 484 *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC); 485 486 if (mapping->flags & AMDGPU_PTE_PRT) { 487 *flags |= AMDGPU_PTE_PRT; 488 *flags |= AMDGPU_PTE_SNOOPED; 489 *flags |= AMDGPU_PTE_LOG; 490 *flags |= AMDGPU_PTE_SYSTEM; 491 *flags &= ~AMDGPU_PTE_VALID; 492 } 493 494 if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 495 AMDGPU_GEM_CREATE_EXT_COHERENT | 496 AMDGPU_GEM_CREATE_UNCACHED)) 497 *flags = (*flags & ~AMDGPU_PTE_MTYPE_NV10_MASK) | 498 AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 499 } 500 501 static unsigned int gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev) 502 { 503 u32 d1vga_control = RREG32_SOC15(DCE, 0, regD1VGA_CONTROL); 504 unsigned int size; 505 506 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 507 size = AMDGPU_VBIOS_VGA_ALLOCATION; 508 } else { 509 u32 viewport; 510 u32 pitch; 511 512 viewport = RREG32_SOC15(DCE, 0, regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 513 pitch = RREG32_SOC15(DCE, 0, regHUBPREQ0_DCSURF_SURFACE_PITCH); 514 size = (REG_GET_FIELD(viewport, 515 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 516 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 517 4); 518 } 519 520 return size; 521 } 522 523 static const struct amdgpu_gmc_funcs gmc_v11_0_gmc_funcs = { 524 .flush_gpu_tlb = gmc_v11_0_flush_gpu_tlb, 525 .flush_gpu_tlb_pasid = gmc_v11_0_flush_gpu_tlb_pasid, 526 .emit_flush_gpu_tlb = gmc_v11_0_emit_flush_gpu_tlb, 527 .emit_pasid_mapping = gmc_v11_0_emit_pasid_mapping, 528 .map_mtype = gmc_v11_0_map_mtype, 529 .get_vm_pde = gmc_v11_0_get_vm_pde, 530 .get_vm_pte = gmc_v11_0_get_vm_pte, 531 .get_vbios_fb_size = gmc_v11_0_get_vbios_fb_size, 532 }; 533 534 static void gmc_v11_0_set_gmc_funcs(struct amdgpu_device *adev) 535 { 536 adev->gmc.gmc_funcs = &gmc_v11_0_gmc_funcs; 537 } 538 539 static void gmc_v11_0_set_umc_funcs(struct amdgpu_device *adev) 540 { 541 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 542 case IP_VERSION(8, 10, 0): 543 adev->umc.channel_inst_num = UMC_V8_10_CHANNEL_INSTANCE_NUM; 544 adev->umc.umc_inst_num = UMC_V8_10_UMC_INSTANCE_NUM; 545 adev->umc.max_ras_err_cnt_per_query = UMC_V8_10_TOTAL_CHANNEL_NUM(adev); 546 adev->umc.channel_offs = UMC_V8_10_PER_CHANNEL_OFFSET; 547 adev->umc.retire_unit = UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM; 548 if (adev->umc.node_inst_num == 4) 549 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl_ext0[0][0][0]; 550 else 551 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl[0][0][0]; 552 adev->umc.ras = &umc_v8_10_ras; 553 break; 554 case IP_VERSION(8, 11, 0): 555 break; 556 default: 557 break; 558 } 559 } 560 561 562 static void gmc_v11_0_set_mmhub_funcs(struct amdgpu_device *adev) 563 { 564 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 565 case IP_VERSION(3, 0, 1): 566 adev->mmhub.funcs = &mmhub_v3_0_1_funcs; 567 break; 568 case IP_VERSION(3, 0, 2): 569 adev->mmhub.funcs = &mmhub_v3_0_2_funcs; 570 break; 571 case IP_VERSION(3, 3, 0): 572 adev->mmhub.funcs = &mmhub_v3_3_funcs; 573 break; 574 default: 575 adev->mmhub.funcs = &mmhub_v3_0_funcs; 576 break; 577 } 578 } 579 580 static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev) 581 { 582 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 583 case IP_VERSION(11, 0, 3): 584 adev->gfxhub.funcs = &gfxhub_v3_0_3_funcs; 585 break; 586 case IP_VERSION(11, 5, 0): 587 adev->gfxhub.funcs = &gfxhub_v11_5_0_funcs; 588 break; 589 default: 590 adev->gfxhub.funcs = &gfxhub_v3_0_funcs; 591 break; 592 } 593 } 594 595 static int gmc_v11_0_early_init(void *handle) 596 { 597 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 598 599 gmc_v11_0_set_gfxhub_funcs(adev); 600 gmc_v11_0_set_mmhub_funcs(adev); 601 gmc_v11_0_set_gmc_funcs(adev); 602 gmc_v11_0_set_irq_funcs(adev); 603 gmc_v11_0_set_umc_funcs(adev); 604 605 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 606 adev->gmc.shared_aperture_end = 607 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 608 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 609 adev->gmc.private_aperture_end = 610 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 611 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 612 613 return 0; 614 } 615 616 static int gmc_v11_0_late_init(void *handle) 617 { 618 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 619 int r; 620 621 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 622 if (r) 623 return r; 624 625 r = amdgpu_gmc_ras_late_init(adev); 626 if (r) 627 return r; 628 629 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 630 } 631 632 static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev, 633 struct amdgpu_gmc *mc) 634 { 635 u64 base = 0; 636 637 base = adev->mmhub.funcs->get_fb_location(adev); 638 639 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 640 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_HIGH); 641 if (!amdgpu_sriov_vf(adev) || 642 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(11, 5, 0))) 643 amdgpu_gmc_agp_location(adev, mc); 644 645 /* base offset of vram pages */ 646 if (amdgpu_sriov_vf(adev)) 647 adev->vm_manager.vram_base_offset = 0; 648 else 649 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); 650 } 651 652 /** 653 * gmc_v11_0_mc_init - initialize the memory controller driver params 654 * 655 * @adev: amdgpu_device pointer 656 * 657 * Look up the amount of vram, vram width, and decide how to place 658 * vram and gart within the GPU's physical address space. 659 * Returns 0 for success. 660 */ 661 static int gmc_v11_0_mc_init(struct amdgpu_device *adev) 662 { 663 int r; 664 665 /* size in MB on si */ 666 adev->gmc.mc_vram_size = 667 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 668 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 669 670 if (!(adev->flags & AMD_IS_APU)) { 671 r = amdgpu_device_resize_fb_bar(adev); 672 if (r) 673 return r; 674 } 675 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 676 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 677 678 #ifdef CONFIG_X86_64 679 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 680 adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev); 681 adev->gmc.aper_size = adev->gmc.real_vram_size; 682 } 683 #endif 684 /* In case the PCI BAR is larger than the actual amount of vram */ 685 adev->gmc.visible_vram_size = adev->gmc.aper_size; 686 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 687 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 688 689 /* set the gart size */ 690 if (amdgpu_gart_size == -1) 691 adev->gmc.gart_size = 512ULL << 20; 692 else 693 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 694 695 gmc_v11_0_vram_gtt_location(adev, &adev->gmc); 696 697 return 0; 698 } 699 700 static int gmc_v11_0_gart_init(struct amdgpu_device *adev) 701 { 702 int r; 703 704 if (adev->gart.bo) { 705 WARN(1, "PCIE GART already initialized\n"); 706 return 0; 707 } 708 709 /* Initialize common gart structure */ 710 r = amdgpu_gart_init(adev); 711 if (r) 712 return r; 713 714 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 715 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 716 AMDGPU_PTE_EXECUTABLE; 717 718 return amdgpu_gart_table_vram_alloc(adev); 719 } 720 721 static int gmc_v11_0_sw_init(void *handle) 722 { 723 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 724 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 725 726 adev->mmhub.funcs->init(adev); 727 728 adev->gfxhub.funcs->init(adev); 729 730 spin_lock_init(&adev->gmc.invalidate_lock); 731 732 r = amdgpu_atomfirmware_get_vram_info(adev, 733 &vram_width, &vram_type, &vram_vendor); 734 adev->gmc.vram_width = vram_width; 735 736 adev->gmc.vram_type = vram_type; 737 adev->gmc.vram_vendor = vram_vendor; 738 739 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 740 case IP_VERSION(11, 0, 0): 741 case IP_VERSION(11, 0, 1): 742 case IP_VERSION(11, 0, 2): 743 case IP_VERSION(11, 0, 3): 744 case IP_VERSION(11, 0, 4): 745 case IP_VERSION(11, 5, 0): 746 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 747 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 748 /* 749 * To fulfill 4-level page support, 750 * vm size is 256TB (48bit), maximum size, 751 * block size 512 (9bit) 752 */ 753 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 754 break; 755 default: 756 break; 757 } 758 759 /* This interrupt is VMC page fault.*/ 760 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC, 761 VMC_1_0__SRCID__VM_FAULT, 762 &adev->gmc.vm_fault); 763 764 if (r) 765 return r; 766 767 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 768 UTCL2_1_0__SRCID__FAULT, 769 &adev->gmc.vm_fault); 770 if (r) 771 return r; 772 773 if (!amdgpu_sriov_vf(adev)) { 774 /* interrupt sent to DF. */ 775 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0, 776 &adev->gmc.ecc_irq); 777 if (r) 778 return r; 779 } 780 781 /* 782 * Set the internal MC address mask This is the max address of the GPU's 783 * internal address space. 784 */ 785 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 786 787 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 788 if (r) { 789 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 790 return r; 791 } 792 793 adev->need_swiotlb = drm_need_swiotlb(44); 794 795 r = gmc_v11_0_mc_init(adev); 796 if (r) 797 return r; 798 799 amdgpu_gmc_get_vbios_allocations(adev); 800 801 /* Memory manager */ 802 r = amdgpu_bo_init(adev); 803 if (r) 804 return r; 805 806 r = gmc_v11_0_gart_init(adev); 807 if (r) 808 return r; 809 810 /* 811 * number of VMs 812 * VMID 0 is reserved for System 813 * amdgpu graphics/compute will use VMIDs 1-7 814 * amdkfd will use VMIDs 8-15 815 */ 816 adev->vm_manager.first_kfd_vmid = 8; 817 818 amdgpu_vm_manager_init(adev); 819 820 r = amdgpu_gmc_ras_sw_init(adev); 821 if (r) 822 return r; 823 824 return 0; 825 } 826 827 /** 828 * gmc_v11_0_gart_fini - vm fini callback 829 * 830 * @adev: amdgpu_device pointer 831 * 832 * Tears down the driver GART/VM setup (CIK). 833 */ 834 static void gmc_v11_0_gart_fini(struct amdgpu_device *adev) 835 { 836 amdgpu_gart_table_vram_free(adev); 837 } 838 839 static int gmc_v11_0_sw_fini(void *handle) 840 { 841 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 842 843 amdgpu_vm_manager_fini(adev); 844 gmc_v11_0_gart_fini(adev); 845 amdgpu_gem_force_release(adev); 846 amdgpu_bo_fini(adev); 847 848 return 0; 849 } 850 851 static void gmc_v11_0_init_golden_registers(struct amdgpu_device *adev) 852 { 853 if (amdgpu_sriov_vf(adev)) { 854 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 855 856 WREG32(hub->vm_contexts_disable, 0); 857 return; 858 } 859 } 860 861 /** 862 * gmc_v11_0_gart_enable - gart enable 863 * 864 * @adev: amdgpu_device pointer 865 */ 866 static int gmc_v11_0_gart_enable(struct amdgpu_device *adev) 867 { 868 int r; 869 bool value; 870 871 if (adev->gart.bo == NULL) { 872 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 873 return -EINVAL; 874 } 875 876 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 877 878 r = adev->mmhub.funcs->gart_enable(adev); 879 if (r) 880 return r; 881 882 /* Flush HDP after it is initialized */ 883 adev->hdp.funcs->flush_hdp(adev, NULL); 884 885 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 886 false : true; 887 888 adev->mmhub.funcs->set_fault_enable_default(adev, value); 889 gmc_v11_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); 890 891 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 892 (unsigned int)(adev->gmc.gart_size >> 20), 893 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 894 895 return 0; 896 } 897 898 static int gmc_v11_0_hw_init(void *handle) 899 { 900 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 901 int r; 902 903 adev->gmc.flush_pasid_uses_kiq = !amdgpu_emu_mode; 904 905 /* The sequence of these two function calls matters.*/ 906 gmc_v11_0_init_golden_registers(adev); 907 908 r = gmc_v11_0_gart_enable(adev); 909 if (r) 910 return r; 911 912 if (adev->umc.funcs && adev->umc.funcs->init_registers) 913 adev->umc.funcs->init_registers(adev); 914 915 return 0; 916 } 917 918 /** 919 * gmc_v11_0_gart_disable - gart disable 920 * 921 * @adev: amdgpu_device pointer 922 * 923 * This disables all VM page table. 924 */ 925 static void gmc_v11_0_gart_disable(struct amdgpu_device *adev) 926 { 927 adev->mmhub.funcs->gart_disable(adev); 928 } 929 930 static int gmc_v11_0_hw_fini(void *handle) 931 { 932 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 933 934 if (amdgpu_sriov_vf(adev)) { 935 /* full access mode, so don't touch any GMC register */ 936 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 937 return 0; 938 } 939 940 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 941 gmc_v11_0_gart_disable(adev); 942 943 return 0; 944 } 945 946 static int gmc_v11_0_suspend(void *handle) 947 { 948 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 949 950 gmc_v11_0_hw_fini(adev); 951 952 return 0; 953 } 954 955 static int gmc_v11_0_resume(void *handle) 956 { 957 int r; 958 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 959 960 r = gmc_v11_0_hw_init(adev); 961 if (r) 962 return r; 963 964 amdgpu_vmid_reset_all(adev); 965 966 return 0; 967 } 968 969 static bool gmc_v11_0_is_idle(void *handle) 970 { 971 /* MC is always ready in GMC v11.*/ 972 return true; 973 } 974 975 static int gmc_v11_0_wait_for_idle(void *handle) 976 { 977 /* There is no need to wait for MC idle in GMC v11.*/ 978 return 0; 979 } 980 981 static int gmc_v11_0_soft_reset(void *handle) 982 { 983 return 0; 984 } 985 986 static int gmc_v11_0_set_clockgating_state(void *handle, 987 enum amd_clockgating_state state) 988 { 989 int r; 990 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 991 992 r = adev->mmhub.funcs->set_clockgating(adev, state); 993 if (r) 994 return r; 995 996 return athub_v3_0_set_clockgating(adev, state); 997 } 998 999 static void gmc_v11_0_get_clockgating_state(void *handle, u64 *flags) 1000 { 1001 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1002 1003 adev->mmhub.funcs->get_clockgating(adev, flags); 1004 1005 athub_v3_0_get_clockgating(adev, flags); 1006 } 1007 1008 static int gmc_v11_0_set_powergating_state(void *handle, 1009 enum amd_powergating_state state) 1010 { 1011 return 0; 1012 } 1013 1014 const struct amd_ip_funcs gmc_v11_0_ip_funcs = { 1015 .name = "gmc_v11_0", 1016 .early_init = gmc_v11_0_early_init, 1017 .sw_init = gmc_v11_0_sw_init, 1018 .hw_init = gmc_v11_0_hw_init, 1019 .late_init = gmc_v11_0_late_init, 1020 .sw_fini = gmc_v11_0_sw_fini, 1021 .hw_fini = gmc_v11_0_hw_fini, 1022 .suspend = gmc_v11_0_suspend, 1023 .resume = gmc_v11_0_resume, 1024 .is_idle = gmc_v11_0_is_idle, 1025 .wait_for_idle = gmc_v11_0_wait_for_idle, 1026 .soft_reset = gmc_v11_0_soft_reset, 1027 .set_clockgating_state = gmc_v11_0_set_clockgating_state, 1028 .set_powergating_state = gmc_v11_0_set_powergating_state, 1029 .get_clockgating_state = gmc_v11_0_get_clockgating_state, 1030 }; 1031 1032 const struct amdgpu_ip_block_version gmc_v11_0_ip_block = { 1033 .type = AMD_IP_BLOCK_TYPE_GMC, 1034 .major = 11, 1035 .minor = 0, 1036 .rev = 0, 1037 .funcs = &gmc_v11_0_ip_funcs, 1038 }; 1039