1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "gfx_v9_4_3_cleaner_shader.h" 41 #include "amdgpu_xcp.h" 42 #include "amdgpu_aca.h" 43 44 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_9_4_4_mec.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_9_5_0_mec.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_9_4_4_rlc.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_9_5_0_rlc.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_9_4_3_sjt_mec.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_9_4_4_sjt_mec.bin"); 52 53 #define GFX9_MEC_HPD_SIZE 4096 54 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 55 56 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 57 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301 58 59 #define XCC_REG_RANGE_0_LOW 0x2000 /* XCC gfxdec0 lower Bound */ 60 #define XCC_REG_RANGE_0_HIGH 0x3400 /* XCC gfxdec0 upper Bound */ 61 #define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */ 62 #define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */ 63 64 #define NORMALIZE_XCC_REG_OFFSET(offset) \ 65 (offset & 0xFFFF) 66 67 static const struct amdgpu_hwip_reg_entry gc_reg_list_9_4_3[] = { 68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 69 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 71 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 72 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 73 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 74 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 75 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 76 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 77 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 78 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 79 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 80 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 81 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 82 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT), 83 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT), 84 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS), 85 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 86 SOC15_REG_ENTRY_STR(GC, 0, regSQC_DCACHE_UTCL1_STATUS), 87 SOC15_REG_ENTRY_STR(GC, 0, regSQC_ICACHE_UTCL1_STATUS), 88 SOC15_REG_ENTRY_STR(GC, 0, regSQ_UTCL1_STATUS), 89 SOC15_REG_ENTRY_STR(GC, 0, regTCP_UTCL1_STATUS), 90 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 91 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_CNTL), 92 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_STATUS), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC2_INSTR_PNTR), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 98 SOC15_REG_ENTRY_STR(GC, 0, regRLC_STAT), 99 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_COMMAND), 100 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_MESSAGE), 101 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_1), 102 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_2), 103 SOC15_REG_ENTRY_STR(GC, 0, regSMU_RLC_RESPONSE), 104 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SAFE_MODE), 105 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_SAFE_MODE), 106 SOC15_REG_ENTRY_STR(GC, 0, regRLC_INT_STAT), 107 SOC15_REG_ENTRY_STR(GC, 0, regRLC_GPM_GENERAL_6), 108 /* cp header registers */ 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME2_HEADER_DUMP), 111 /* SE status registers */ 112 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 113 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 114 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 115 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 116 }; 117 118 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9_4_3[] = { 119 /* compute queue registers */ 120 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 121 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ACTIVE), 122 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 123 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 124 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 125 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 126 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 127 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GFX_STATUS), 157 }; 158 159 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 160 161 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 162 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 163 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 164 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 165 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 166 struct amdgpu_cu_info *cu_info); 167 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 168 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 169 170 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 171 uint64_t queue_mask) 172 { 173 struct amdgpu_device *adev = kiq_ring->adev; 174 u64 shader_mc_addr; 175 176 /* Cleaner shader MC address */ 177 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 178 179 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 180 amdgpu_ring_write(kiq_ring, 181 PACKET3_SET_RESOURCES_VMID_MASK(0) | 182 /* vmid_mask:0* queue_type:0 (KIQ) */ 183 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 184 amdgpu_ring_write(kiq_ring, 185 lower_32_bits(queue_mask)); /* queue mask lo */ 186 amdgpu_ring_write(kiq_ring, 187 upper_32_bits(queue_mask)); /* queue mask hi */ 188 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 189 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 190 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 191 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 192 } 193 194 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 195 struct amdgpu_ring *ring) 196 { 197 struct amdgpu_device *adev = kiq_ring->adev; 198 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 199 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 200 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 201 202 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 203 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 204 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 205 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 206 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 207 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 208 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 209 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 210 /*queue_type: normal compute queue */ 211 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 212 /* alloc format: all_on_one_pipe */ 213 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 214 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 215 /* num_queues: must be 1 */ 216 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 217 amdgpu_ring_write(kiq_ring, 218 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 219 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 220 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 221 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 222 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 223 } 224 225 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 226 struct amdgpu_ring *ring, 227 enum amdgpu_unmap_queues_action action, 228 u64 gpu_addr, u64 seq) 229 { 230 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 231 232 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 233 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 234 PACKET3_UNMAP_QUEUES_ACTION(action) | 235 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 236 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 237 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 238 amdgpu_ring_write(kiq_ring, 239 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 240 241 if (action == PREEMPT_QUEUES_NO_UNMAP) { 242 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 243 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 244 amdgpu_ring_write(kiq_ring, seq); 245 } else { 246 amdgpu_ring_write(kiq_ring, 0); 247 amdgpu_ring_write(kiq_ring, 0); 248 amdgpu_ring_write(kiq_ring, 0); 249 } 250 } 251 252 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 253 struct amdgpu_ring *ring, 254 u64 addr, 255 u64 seq) 256 { 257 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 258 259 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 260 amdgpu_ring_write(kiq_ring, 261 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 262 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 263 PACKET3_QUERY_STATUS_COMMAND(2)); 264 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 265 amdgpu_ring_write(kiq_ring, 266 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 267 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 268 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 269 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 270 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 271 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 272 } 273 274 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 275 uint16_t pasid, uint32_t flush_type, 276 bool all_hub) 277 { 278 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 279 amdgpu_ring_write(kiq_ring, 280 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 281 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 282 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 283 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 284 } 285 286 static void gfx_v9_4_3_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type, 287 uint32_t me_id, uint32_t pipe_id, uint32_t queue_id, 288 uint32_t xcc_id, uint32_t vmid) 289 { 290 struct amdgpu_device *adev = kiq_ring->adev; 291 unsigned i; 292 293 /* enter save mode */ 294 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 295 mutex_lock(&adev->srbm_mutex); 296 soc15_grbm_select(adev, me_id, pipe_id, queue_id, 0, xcc_id); 297 298 if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 299 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 0x2); 300 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_COMPUTE_QUEUE_RESET, 0x1); 301 /* wait till dequeue take effects */ 302 for (i = 0; i < adev->usec_timeout; i++) { 303 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 304 break; 305 udelay(1); 306 } 307 if (i >= adev->usec_timeout) 308 dev_err(adev->dev, "fail to wait on hqd deactive\n"); 309 } else { 310 dev_err(adev->dev, "reset queue_type(%d) not supported\n\n", queue_type); 311 } 312 313 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 314 mutex_unlock(&adev->srbm_mutex); 315 /* exit safe mode */ 316 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 317 } 318 319 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 320 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 321 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 322 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 323 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 324 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 325 .kiq_reset_hw_queue = gfx_v9_4_3_kiq_reset_hw_queue, 326 .set_resources_size = 8, 327 .map_queues_size = 7, 328 .unmap_queues_size = 6, 329 .query_status_size = 7, 330 .invalidate_tlbs_size = 2, 331 }; 332 333 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 334 { 335 int i, num_xcc; 336 337 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 338 for (i = 0; i < num_xcc; i++) 339 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 340 } 341 342 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 343 { 344 int i, num_xcc, dev_inst; 345 346 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 347 for (i = 0; i < num_xcc; i++) { 348 dev_inst = GET_INST(GC, i); 349 350 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 351 GOLDEN_GB_ADDR_CONFIG); 352 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) { 353 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, SPARE, 0x1); 354 } else { 355 /* Golden settings applied by driver for ASIC with rev_id 0 */ 356 if (adev->rev_id == 0) { 357 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1, 358 REDUCE_FIFO_DEPTH_BY_2, 2); 359 } else { 360 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, 361 SPARE, 0x1); 362 } 363 } 364 } 365 } 366 367 static uint32_t gfx_v9_4_3_normalize_xcc_reg_offset(uint32_t reg) 368 { 369 uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg); 370 371 /* If it is an XCC reg, normalize the reg to keep 372 lower 16 bits in local xcc */ 373 374 if (((normalized_reg >= XCC_REG_RANGE_0_LOW) && (normalized_reg < XCC_REG_RANGE_0_HIGH)) || 375 ((normalized_reg >= XCC_REG_RANGE_1_LOW) && (normalized_reg < XCC_REG_RANGE_1_HIGH))) 376 return normalized_reg; 377 else 378 return reg; 379 } 380 381 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 382 bool wc, uint32_t reg, uint32_t val) 383 { 384 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 385 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 386 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 387 WRITE_DATA_DST_SEL(0) | 388 (wc ? WR_CONFIRM : 0)); 389 amdgpu_ring_write(ring, reg); 390 amdgpu_ring_write(ring, 0); 391 amdgpu_ring_write(ring, val); 392 } 393 394 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 395 int mem_space, int opt, uint32_t addr0, 396 uint32_t addr1, uint32_t ref, uint32_t mask, 397 uint32_t inv) 398 { 399 /* Only do the normalization on regspace */ 400 if (mem_space == 0) { 401 addr0 = gfx_v9_4_3_normalize_xcc_reg_offset(addr0); 402 addr1 = gfx_v9_4_3_normalize_xcc_reg_offset(addr1); 403 } 404 405 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 406 amdgpu_ring_write(ring, 407 /* memory (1) or register (0) */ 408 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 409 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 410 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 411 WAIT_REG_MEM_ENGINE(eng_sel))); 412 413 if (mem_space) 414 BUG_ON(addr0 & 0x3); /* Dword align */ 415 amdgpu_ring_write(ring, addr0); 416 amdgpu_ring_write(ring, addr1); 417 amdgpu_ring_write(ring, ref); 418 amdgpu_ring_write(ring, mask); 419 amdgpu_ring_write(ring, inv); /* poll interval */ 420 } 421 422 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 423 { 424 uint32_t scratch_reg0_offset, xcc_offset; 425 struct amdgpu_device *adev = ring->adev; 426 uint32_t tmp = 0; 427 unsigned i; 428 int r; 429 430 /* Use register offset which is local to XCC in the packet */ 431 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 432 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 433 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 434 tmp = RREG32(scratch_reg0_offset); 435 436 r = amdgpu_ring_alloc(ring, 3); 437 if (r) 438 return r; 439 440 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 441 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 442 amdgpu_ring_write(ring, 0xDEADBEEF); 443 amdgpu_ring_commit(ring); 444 445 for (i = 0; i < adev->usec_timeout; i++) { 446 tmp = RREG32(scratch_reg0_offset); 447 if (tmp == 0xDEADBEEF) 448 break; 449 udelay(1); 450 } 451 452 if (i >= adev->usec_timeout) 453 r = -ETIMEDOUT; 454 return r; 455 } 456 457 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 458 { 459 struct amdgpu_device *adev = ring->adev; 460 struct amdgpu_ib ib; 461 struct dma_fence *f = NULL; 462 463 unsigned index; 464 uint64_t gpu_addr; 465 uint32_t tmp; 466 long r; 467 468 r = amdgpu_device_wb_get(adev, &index); 469 if (r) 470 return r; 471 472 gpu_addr = adev->wb.gpu_addr + (index * 4); 473 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 474 memset(&ib, 0, sizeof(ib)); 475 476 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 477 if (r) 478 goto err1; 479 480 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 481 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 482 ib.ptr[2] = lower_32_bits(gpu_addr); 483 ib.ptr[3] = upper_32_bits(gpu_addr); 484 ib.ptr[4] = 0xDEADBEEF; 485 ib.length_dw = 5; 486 487 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 488 if (r) 489 goto err2; 490 491 r = dma_fence_wait_timeout(f, false, timeout); 492 if (r == 0) { 493 r = -ETIMEDOUT; 494 goto err2; 495 } else if (r < 0) { 496 goto err2; 497 } 498 499 tmp = adev->wb.wb[index]; 500 if (tmp == 0xDEADBEEF) 501 r = 0; 502 else 503 r = -EINVAL; 504 505 err2: 506 amdgpu_ib_free(&ib, NULL); 507 dma_fence_put(f); 508 err1: 509 amdgpu_device_wb_free(adev, index); 510 return r; 511 } 512 513 514 /* This value might differs per partition */ 515 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 516 { 517 uint64_t clock; 518 519 mutex_lock(&adev->gfx.gpu_clock_mutex); 520 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 521 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 522 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 523 mutex_unlock(&adev->gfx.gpu_clock_mutex); 524 525 return clock; 526 } 527 528 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 529 { 530 amdgpu_ucode_release(&adev->gfx.pfp_fw); 531 amdgpu_ucode_release(&adev->gfx.me_fw); 532 amdgpu_ucode_release(&adev->gfx.ce_fw); 533 amdgpu_ucode_release(&adev->gfx.rlc_fw); 534 amdgpu_ucode_release(&adev->gfx.mec_fw); 535 amdgpu_ucode_release(&adev->gfx.mec2_fw); 536 537 kfree(adev->gfx.rlc.register_list_format); 538 } 539 540 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 541 const char *chip_name) 542 { 543 int err; 544 const struct rlc_firmware_header_v2_0 *rlc_hdr; 545 uint16_t version_major; 546 uint16_t version_minor; 547 548 549 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 550 AMDGPU_UCODE_REQUIRED, 551 "amdgpu/%s_rlc.bin", chip_name); 552 if (err) 553 goto out; 554 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 555 556 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 557 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 558 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 559 out: 560 if (err) 561 amdgpu_ucode_release(&adev->gfx.rlc_fw); 562 563 return err; 564 } 565 566 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 567 const char *chip_name) 568 { 569 int err; 570 571 if (amdgpu_sriov_vf(adev)) { 572 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 573 AMDGPU_UCODE_REQUIRED, 574 "amdgpu/%s_sjt_mec.bin", chip_name); 575 576 if (err) 577 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 578 AMDGPU_UCODE_REQUIRED, 579 "amdgpu/%s_mec.bin", chip_name); 580 } else 581 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 582 AMDGPU_UCODE_REQUIRED, 583 "amdgpu/%s_mec.bin", chip_name); 584 if (err) 585 goto out; 586 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 587 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 588 589 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 590 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 591 592 out: 593 if (err) 594 amdgpu_ucode_release(&adev->gfx.mec_fw); 595 return err; 596 } 597 598 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 599 { 600 char ucode_prefix[15]; 601 int r; 602 603 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 604 605 r = gfx_v9_4_3_init_rlc_microcode(adev, ucode_prefix); 606 if (r) 607 return r; 608 609 r = gfx_v9_4_3_init_cp_compute_microcode(adev, ucode_prefix); 610 if (r) 611 return r; 612 613 return r; 614 } 615 616 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 617 { 618 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 619 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 620 } 621 622 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 623 { 624 int r, i, num_xcc; 625 u32 *hpd; 626 const __le32 *fw_data; 627 unsigned fw_size; 628 u32 *fw; 629 size_t mec_hpd_size; 630 631 const struct gfx_firmware_header_v1_0 *mec_hdr; 632 633 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 634 for (i = 0; i < num_xcc; i++) 635 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 636 AMDGPU_MAX_COMPUTE_QUEUES); 637 638 /* take ownership of the relevant compute queues */ 639 amdgpu_gfx_compute_queue_acquire(adev); 640 mec_hpd_size = 641 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 642 if (mec_hpd_size) { 643 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 644 AMDGPU_GEM_DOMAIN_VRAM | 645 AMDGPU_GEM_DOMAIN_GTT, 646 &adev->gfx.mec.hpd_eop_obj, 647 &adev->gfx.mec.hpd_eop_gpu_addr, 648 (void **)&hpd); 649 if (r) { 650 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 651 gfx_v9_4_3_mec_fini(adev); 652 return r; 653 } 654 655 if (amdgpu_emu_mode == 1) { 656 for (i = 0; i < mec_hpd_size / 4; i++) { 657 memset((void *)(hpd + i), 0, 4); 658 if (i % 50 == 0) 659 msleep(1); 660 } 661 } else { 662 memset(hpd, 0, mec_hpd_size); 663 } 664 665 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 666 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 667 } 668 669 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 670 671 fw_data = (const __le32 *) 672 (adev->gfx.mec_fw->data + 673 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 674 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 675 676 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 677 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 678 &adev->gfx.mec.mec_fw_obj, 679 &adev->gfx.mec.mec_fw_gpu_addr, 680 (void **)&fw); 681 if (r) { 682 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 683 gfx_v9_4_3_mec_fini(adev); 684 return r; 685 } 686 687 memcpy(fw, fw_data, fw_size); 688 689 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 690 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 691 692 return 0; 693 } 694 695 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 696 u32 sh_num, u32 instance, int xcc_id) 697 { 698 u32 data; 699 700 if (instance == 0xffffffff) 701 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 702 INSTANCE_BROADCAST_WRITES, 1); 703 else 704 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 705 INSTANCE_INDEX, instance); 706 707 if (se_num == 0xffffffff) 708 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 709 SE_BROADCAST_WRITES, 1); 710 else 711 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 712 713 if (sh_num == 0xffffffff) 714 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 715 SH_BROADCAST_WRITES, 1); 716 else 717 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 718 719 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 720 } 721 722 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 723 { 724 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 725 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 726 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 727 (address << SQ_IND_INDEX__INDEX__SHIFT) | 728 (SQ_IND_INDEX__FORCE_READ_MASK)); 729 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 730 } 731 732 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 733 uint32_t wave, uint32_t thread, 734 uint32_t regno, uint32_t num, uint32_t *out) 735 { 736 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 737 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 738 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 739 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 740 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 741 (SQ_IND_INDEX__FORCE_READ_MASK) | 742 (SQ_IND_INDEX__AUTO_INCR_MASK)); 743 while (num--) 744 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 745 } 746 747 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 748 uint32_t xcc_id, uint32_t simd, uint32_t wave, 749 uint32_t *dst, int *no_fields) 750 { 751 /* type 1 wave data */ 752 dst[(*no_fields)++] = 1; 753 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 754 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 755 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 756 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 757 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 758 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 759 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 760 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 761 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 762 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 763 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 764 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 765 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 766 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 767 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 768 } 769 770 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 771 uint32_t wave, uint32_t start, 772 uint32_t size, uint32_t *dst) 773 { 774 wave_read_regs(adev, xcc_id, simd, wave, 0, 775 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 776 } 777 778 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 779 uint32_t wave, uint32_t thread, 780 uint32_t start, uint32_t size, 781 uint32_t *dst) 782 { 783 wave_read_regs(adev, xcc_id, simd, wave, thread, 784 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 785 } 786 787 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 788 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 789 { 790 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 791 } 792 793 static int gfx_v9_4_3_get_xccs_per_xcp(struct amdgpu_device *adev) 794 { 795 u32 xcp_ctl; 796 797 /* Value is expected to be the same on all, fetch from first instance */ 798 xcp_ctl = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HYP_XCP_CTL); 799 800 return REG_GET_FIELD(xcp_ctl, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP); 801 } 802 803 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 804 int num_xccs_per_xcp) 805 { 806 int ret, i, num_xcc; 807 u32 tmp = 0; 808 809 if (adev->psp.funcs) { 810 ret = psp_spatial_partition(&adev->psp, 811 NUM_XCC(adev->gfx.xcc_mask) / 812 num_xccs_per_xcp); 813 if (ret) 814 return ret; 815 } else { 816 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 817 818 for (i = 0; i < num_xcc; i++) { 819 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 820 num_xccs_per_xcp); 821 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 822 i % num_xccs_per_xcp); 823 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 824 tmp); 825 } 826 ret = 0; 827 } 828 829 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 830 831 return ret; 832 } 833 834 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 835 { 836 int xcc; 837 838 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 839 if (!xcc) { 840 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 841 return -EINVAL; 842 } 843 844 return xcc - 1; 845 } 846 847 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 848 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 849 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 850 .read_wave_data = &gfx_v9_4_3_read_wave_data, 851 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 852 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 853 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 854 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 855 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 856 .get_xccs_per_xcp = &gfx_v9_4_3_get_xccs_per_xcp, 857 }; 858 859 static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle, 860 struct aca_bank *bank, enum aca_smu_type type, 861 void *data) 862 { 863 struct aca_bank_info info; 864 u64 misc0; 865 u32 instlo; 866 int ret; 867 868 ret = aca_bank_info_decode(bank, &info); 869 if (ret) 870 return ret; 871 872 /* NOTE: overwrite info.die_id with xcd id for gfx */ 873 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 874 instlo &= GENMASK(31, 1); 875 info.die_id = instlo == mmSMNAID_XCD0_MCA_SMU ? 0 : 1; 876 877 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 878 879 switch (type) { 880 case ACA_SMU_TYPE_UE: 881 bank->aca_err_type = ACA_ERROR_TYPE_UE; 882 ret = aca_error_cache_log_bank_error(handle, &info, 883 ACA_ERROR_TYPE_UE, 1ULL); 884 break; 885 case ACA_SMU_TYPE_CE: 886 bank->aca_err_type = ACA_ERROR_TYPE_CE; 887 ret = aca_error_cache_log_bank_error(handle, &info, 888 ACA_ERROR_TYPE_CE, ACA_REG__MISC0__ERRCNT(misc0)); 889 break; 890 default: 891 return -EINVAL; 892 } 893 894 return ret; 895 } 896 897 static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 898 enum aca_smu_type type, void *data) 899 { 900 u32 instlo; 901 902 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 903 instlo &= GENMASK(31, 1); 904 switch (instlo) { 905 case mmSMNAID_XCD0_MCA_SMU: 906 case mmSMNAID_XCD1_MCA_SMU: 907 case mmSMNXCD_XCD0_MCA_SMU: 908 return true; 909 default: 910 break; 911 } 912 913 return false; 914 } 915 916 static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = { 917 .aca_bank_parser = gfx_v9_4_3_aca_bank_parser, 918 .aca_bank_is_valid = gfx_v9_4_3_aca_bank_is_valid, 919 }; 920 921 static const struct aca_info gfx_v9_4_3_aca_info = { 922 .hwip = ACA_HWIP_TYPE_SMU, 923 .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK, 924 .bank_ops = &gfx_v9_4_3_aca_bank_ops, 925 }; 926 927 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 928 { 929 u32 gb_addr_config; 930 931 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 932 adev->gfx.ras = &gfx_v9_4_3_ras; 933 934 adev->gfx.config.max_hw_contexts = 8; 935 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 936 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 937 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 938 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 939 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG); 940 941 adev->gfx.config.gb_addr_config = gb_addr_config; 942 943 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 944 REG_GET_FIELD( 945 adev->gfx.config.gb_addr_config, 946 GB_ADDR_CONFIG, 947 NUM_PIPES); 948 949 adev->gfx.config.max_tile_pipes = 950 adev->gfx.config.gb_addr_config_fields.num_pipes; 951 952 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 953 REG_GET_FIELD( 954 adev->gfx.config.gb_addr_config, 955 GB_ADDR_CONFIG, 956 NUM_BANKS); 957 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 958 REG_GET_FIELD( 959 adev->gfx.config.gb_addr_config, 960 GB_ADDR_CONFIG, 961 MAX_COMPRESSED_FRAGS); 962 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 963 REG_GET_FIELD( 964 adev->gfx.config.gb_addr_config, 965 GB_ADDR_CONFIG, 966 NUM_RB_PER_SE); 967 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 968 REG_GET_FIELD( 969 adev->gfx.config.gb_addr_config, 970 GB_ADDR_CONFIG, 971 NUM_SHADER_ENGINES); 972 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 973 REG_GET_FIELD( 974 adev->gfx.config.gb_addr_config, 975 GB_ADDR_CONFIG, 976 PIPE_INTERLEAVE_SIZE)); 977 978 return 0; 979 } 980 981 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 982 int xcc_id, int mec, int pipe, int queue) 983 { 984 unsigned irq_type; 985 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 986 unsigned int hw_prio; 987 uint32_t xcc_doorbell_start; 988 989 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 990 ring_id]; 991 992 /* mec0 is me1 */ 993 ring->xcc_id = xcc_id; 994 ring->me = mec + 1; 995 ring->pipe = pipe; 996 ring->queue = queue; 997 998 ring->ring_obj = NULL; 999 ring->use_doorbell = true; 1000 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 1001 xcc_id * adev->doorbell_index.xcc_doorbell_range; 1002 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 1003 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 1004 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 1005 GFX9_MEC_HPD_SIZE; 1006 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 1007 sprintf(ring->name, "comp_%d.%d.%d.%d", 1008 ring->xcc_id, ring->me, ring->pipe, ring->queue); 1009 1010 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1011 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1012 + ring->pipe; 1013 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1014 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1015 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1016 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1017 hw_prio, NULL); 1018 } 1019 1020 static void gfx_v9_4_3_alloc_ip_dump(struct amdgpu_device *adev) 1021 { 1022 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 1023 uint32_t *ptr, num_xcc, inst; 1024 1025 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1026 1027 ptr = kcalloc(reg_count * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1028 if (!ptr) { 1029 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1030 adev->gfx.ip_dump_core = NULL; 1031 } else { 1032 adev->gfx.ip_dump_core = ptr; 1033 } 1034 1035 /* Allocate memory for compute queue registers for all the instances */ 1036 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 1037 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1038 adev->gfx.mec.num_queue_per_pipe; 1039 1040 ptr = kcalloc(reg_count * inst * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1041 if (!ptr) { 1042 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1043 adev->gfx.ip_dump_compute_queues = NULL; 1044 } else { 1045 adev->gfx.ip_dump_compute_queues = ptr; 1046 } 1047 } 1048 1049 static int gfx_v9_4_3_sw_init(struct amdgpu_ip_block *ip_block) 1050 { 1051 int i, j, k, r, ring_id, xcc_id, num_xcc; 1052 struct amdgpu_device *adev = ip_block->adev; 1053 1054 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1055 case IP_VERSION(9, 4, 3): 1056 case IP_VERSION(9, 4, 4): 1057 adev->gfx.cleaner_shader_ptr = gfx_9_4_3_cleaner_shader_hex; 1058 adev->gfx.cleaner_shader_size = sizeof(gfx_9_4_3_cleaner_shader_hex); 1059 if (adev->gfx.mec_fw_version >= 153) { 1060 adev->gfx.enable_cleaner_shader = true; 1061 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1062 if (r) { 1063 adev->gfx.enable_cleaner_shader = false; 1064 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1065 } 1066 } 1067 break; 1068 default: 1069 adev->gfx.enable_cleaner_shader = false; 1070 break; 1071 } 1072 1073 adev->gfx.mec.num_mec = 2; 1074 adev->gfx.mec.num_pipe_per_mec = 4; 1075 adev->gfx.mec.num_queue_per_pipe = 8; 1076 1077 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1078 1079 /* EOP Event */ 1080 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 1081 if (r) 1082 return r; 1083 1084 /* Bad opcode Event */ 1085 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1086 GFX_9_0__SRCID__CP_BAD_OPCODE_ERROR, 1087 &adev->gfx.bad_op_irq); 1088 if (r) 1089 return r; 1090 1091 /* Privileged reg */ 1092 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 1093 &adev->gfx.priv_reg_irq); 1094 if (r) 1095 return r; 1096 1097 /* Privileged inst */ 1098 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 1099 &adev->gfx.priv_inst_irq); 1100 if (r) 1101 return r; 1102 1103 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1104 1105 r = adev->gfx.rlc.funcs->init(adev); 1106 if (r) { 1107 DRM_ERROR("Failed to init rlc BOs!\n"); 1108 return r; 1109 } 1110 1111 r = gfx_v9_4_3_mec_init(adev); 1112 if (r) { 1113 DRM_ERROR("Failed to init MEC BOs!\n"); 1114 return r; 1115 } 1116 1117 /* set up the compute queues - allocate horizontally across pipes */ 1118 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1119 ring_id = 0; 1120 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1121 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1122 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 1123 k++) { 1124 if (!amdgpu_gfx_is_mec_queue_enabled( 1125 adev, xcc_id, i, k, j)) 1126 continue; 1127 1128 r = gfx_v9_4_3_compute_ring_init(adev, 1129 ring_id, 1130 xcc_id, 1131 i, k, j); 1132 if (r) 1133 return r; 1134 1135 ring_id++; 1136 } 1137 } 1138 } 1139 1140 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 1141 if (r) { 1142 DRM_ERROR("Failed to init KIQ BOs!\n"); 1143 return r; 1144 } 1145 1146 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1147 if (r) 1148 return r; 1149 1150 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 1151 r = amdgpu_gfx_mqd_sw_init(adev, 1152 sizeof(struct v9_mqd_allocation), xcc_id); 1153 if (r) 1154 return r; 1155 } 1156 1157 adev->gfx.compute_supported_reset = 1158 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1159 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1160 case IP_VERSION(9, 4, 3): 1161 case IP_VERSION(9, 4, 4): 1162 if (adev->gfx.mec_fw_version >= 155) { 1163 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1164 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; 1165 } 1166 break; 1167 default: 1168 break; 1169 } 1170 r = gfx_v9_4_3_gpu_early_init(adev); 1171 if (r) 1172 return r; 1173 1174 r = amdgpu_gfx_ras_sw_init(adev); 1175 if (r) 1176 return r; 1177 1178 r = amdgpu_gfx_sysfs_init(adev); 1179 if (r) 1180 return r; 1181 1182 gfx_v9_4_3_alloc_ip_dump(adev); 1183 1184 return 0; 1185 } 1186 1187 static int gfx_v9_4_3_sw_fini(struct amdgpu_ip_block *ip_block) 1188 { 1189 int i, num_xcc; 1190 struct amdgpu_device *adev = ip_block->adev; 1191 1192 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1193 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 1194 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1195 1196 for (i = 0; i < num_xcc; i++) { 1197 amdgpu_gfx_mqd_sw_fini(adev, i); 1198 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 1199 amdgpu_gfx_kiq_fini(adev, i); 1200 } 1201 1202 amdgpu_gfx_cleaner_shader_sw_fini(adev); 1203 1204 gfx_v9_4_3_mec_fini(adev); 1205 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 1206 gfx_v9_4_3_free_microcode(adev); 1207 amdgpu_gfx_sysfs_fini(adev); 1208 1209 kfree(adev->gfx.ip_dump_core); 1210 kfree(adev->gfx.ip_dump_compute_queues); 1211 1212 return 0; 1213 } 1214 1215 #define DEFAULT_SH_MEM_BASES (0x6000) 1216 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 1217 int xcc_id) 1218 { 1219 int i; 1220 uint32_t sh_mem_config; 1221 uint32_t sh_mem_bases; 1222 uint32_t data; 1223 1224 /* 1225 * Configure apertures: 1226 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1227 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1228 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1229 */ 1230 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1231 1232 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 1233 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1234 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1235 1236 mutex_lock(&adev->srbm_mutex); 1237 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1238 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1239 /* CP and shaders */ 1240 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 1241 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 1242 1243 /* Enable trap for each kfd vmid. */ 1244 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 1245 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1246 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 1247 } 1248 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1249 mutex_unlock(&adev->srbm_mutex); 1250 1251 /* 1252 * Initialize all compute VMIDs to have no GDS, GWS, or OA 1253 * access. These should be enabled by FW for target VMIDs. 1254 */ 1255 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1256 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 1257 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 1258 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 1259 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 1260 } 1261 } 1262 1263 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 1264 { 1265 int vmid; 1266 1267 /* 1268 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1269 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1270 * the driver can enable them for graphics. VMID0 should maintain 1271 * access so that HWS firmware can save/restore entries. 1272 */ 1273 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 1274 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 1275 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 1276 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 1277 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 1278 } 1279 } 1280 1281 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 1282 int xcc_id) 1283 { 1284 u32 tmp; 1285 int i; 1286 1287 /* XXX SH_MEM regs */ 1288 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1289 mutex_lock(&adev->srbm_mutex); 1290 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1291 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1292 /* CP and shaders */ 1293 if (i == 0) { 1294 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1295 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1296 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1297 !!adev->gmc.noretry); 1298 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1299 regSH_MEM_CONFIG, tmp); 1300 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1301 regSH_MEM_BASES, 0); 1302 } else { 1303 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1304 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1305 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1306 !!adev->gmc.noretry); 1307 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1308 regSH_MEM_CONFIG, tmp); 1309 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1310 (adev->gmc.private_aperture_start >> 1311 48)); 1312 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1313 (adev->gmc.shared_aperture_start >> 1314 48)); 1315 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1316 regSH_MEM_BASES, tmp); 1317 } 1318 } 1319 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 1320 1321 mutex_unlock(&adev->srbm_mutex); 1322 1323 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 1324 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 1325 } 1326 1327 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 1328 { 1329 int i, num_xcc; 1330 1331 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1332 1333 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1334 adev->gfx.config.db_debug2 = 1335 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1336 1337 for (i = 0; i < num_xcc; i++) 1338 gfx_v9_4_3_xcc_constants_init(adev, i); 1339 } 1340 1341 static void 1342 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1343 int xcc_id) 1344 { 1345 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1346 } 1347 1348 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1349 { 1350 /* 1351 * Rlc save restore list is workable since v2_1. 1352 */ 1353 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1354 } 1355 1356 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1357 { 1358 uint32_t data; 1359 1360 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1361 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1362 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1363 } 1364 1365 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1366 { 1367 uint32_t rlc_setting; 1368 1369 /* if RLC is not enabled, do nothing */ 1370 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1371 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1372 return false; 1373 1374 return true; 1375 } 1376 1377 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1378 { 1379 uint32_t data; 1380 unsigned i; 1381 1382 data = RLC_SAFE_MODE__CMD_MASK; 1383 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1384 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1385 1386 /* wait for RLC_SAFE_MODE */ 1387 for (i = 0; i < adev->usec_timeout; i++) { 1388 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1389 break; 1390 udelay(1); 1391 } 1392 } 1393 1394 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1395 int xcc_id) 1396 { 1397 uint32_t data; 1398 1399 data = RLC_SAFE_MODE__CMD_MASK; 1400 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1401 } 1402 1403 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1404 { 1405 int xcc_id, num_xcc; 1406 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1407 1408 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1409 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1410 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 1411 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); 1412 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); 1413 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); 1414 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); 1415 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 1416 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1417 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1418 } 1419 adev->gfx.rlc.rlcg_reg_access_supported = true; 1420 } 1421 1422 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1423 { 1424 /* init spm vmid with 0xf */ 1425 if (adev->gfx.rlc.funcs->update_spm_vmid) 1426 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 1427 1428 return 0; 1429 } 1430 1431 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1432 int xcc_id) 1433 { 1434 u32 i, j, k; 1435 u32 mask; 1436 1437 mutex_lock(&adev->grbm_idx_mutex); 1438 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1439 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1440 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1441 xcc_id); 1442 for (k = 0; k < adev->usec_timeout; k++) { 1443 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1444 break; 1445 udelay(1); 1446 } 1447 if (k == adev->usec_timeout) { 1448 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1449 0xffffffff, 1450 0xffffffff, xcc_id); 1451 mutex_unlock(&adev->grbm_idx_mutex); 1452 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1453 i, j); 1454 return; 1455 } 1456 } 1457 } 1458 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1459 xcc_id); 1460 mutex_unlock(&adev->grbm_idx_mutex); 1461 1462 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1463 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1464 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1465 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1466 for (k = 0; k < adev->usec_timeout; k++) { 1467 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1468 break; 1469 udelay(1); 1470 } 1471 } 1472 1473 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1474 bool enable, int xcc_id) 1475 { 1476 u32 tmp; 1477 1478 /* These interrupts should be enabled to drive DS clock */ 1479 1480 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1481 1482 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1483 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1484 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1485 1486 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1487 } 1488 1489 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1490 { 1491 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1492 RLC_ENABLE_F32, 0); 1493 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1494 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1495 } 1496 1497 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1498 { 1499 int i, num_xcc; 1500 1501 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1502 for (i = 0; i < num_xcc; i++) 1503 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1504 } 1505 1506 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1507 { 1508 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1509 SOFT_RESET_RLC, 1); 1510 udelay(50); 1511 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1512 SOFT_RESET_RLC, 0); 1513 udelay(50); 1514 } 1515 1516 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1517 { 1518 int i, num_xcc; 1519 1520 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1521 for (i = 0; i < num_xcc; i++) 1522 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1523 } 1524 1525 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1526 { 1527 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1528 RLC_ENABLE_F32, 1); 1529 udelay(50); 1530 1531 /* carrizo do enable cp interrupt after cp inited */ 1532 if (!(adev->flags & AMD_IS_APU)) { 1533 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1534 udelay(50); 1535 } 1536 } 1537 1538 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1539 { 1540 #ifdef AMDGPU_RLC_DEBUG_RETRY 1541 u32 rlc_ucode_ver; 1542 #endif 1543 int i, num_xcc; 1544 1545 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1546 for (i = 0; i < num_xcc; i++) { 1547 gfx_v9_4_3_xcc_rlc_start(adev, i); 1548 #ifdef AMDGPU_RLC_DEBUG_RETRY 1549 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1550 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1551 if (rlc_ucode_ver == 0x108) { 1552 dev_info(adev->dev, 1553 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1554 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1555 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1556 * default is 0x9C4 to create a 100us interval */ 1557 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1558 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1559 * to disable the page fault retry interrupts, default is 1560 * 0x100 (256) */ 1561 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1562 } 1563 #endif 1564 } 1565 } 1566 1567 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1568 int xcc_id) 1569 { 1570 const struct rlc_firmware_header_v2_0 *hdr; 1571 const __le32 *fw_data; 1572 unsigned i, fw_size; 1573 1574 if (!adev->gfx.rlc_fw) 1575 return -EINVAL; 1576 1577 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1578 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1579 1580 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1581 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1582 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1583 1584 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1585 RLCG_UCODE_LOADING_START_ADDRESS); 1586 for (i = 0; i < fw_size; i++) { 1587 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1588 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1589 msleep(1); 1590 } 1591 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1592 } 1593 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1594 1595 return 0; 1596 } 1597 1598 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1599 { 1600 int r; 1601 1602 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1603 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1604 /* legacy rlc firmware loading */ 1605 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1606 if (r) 1607 return r; 1608 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1609 } 1610 1611 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1612 /* disable CG */ 1613 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1614 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1615 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1616 1617 return 0; 1618 } 1619 1620 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1621 { 1622 int r, i, num_xcc; 1623 1624 if (amdgpu_sriov_vf(adev)) 1625 return 0; 1626 1627 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1628 for (i = 0; i < num_xcc; i++) { 1629 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1630 if (r) 1631 return r; 1632 } 1633 1634 return 0; 1635 } 1636 1637 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1638 unsigned vmid) 1639 { 1640 u32 reg, pre_data, data; 1641 1642 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); 1643 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 1644 pre_data = RREG32_NO_KIQ(reg); 1645 else 1646 pre_data = RREG32(reg); 1647 1648 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 1649 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1650 1651 if (pre_data != data) { 1652 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 1653 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1654 } else 1655 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1656 } 1657 } 1658 1659 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1660 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1661 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1662 }; 1663 1664 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1665 uint32_t offset, 1666 struct soc15_reg_rlcg *entries, int arr_size) 1667 { 1668 int i, inst; 1669 uint32_t reg; 1670 1671 if (!entries) 1672 return false; 1673 1674 for (i = 0; i < arr_size; i++) { 1675 const struct soc15_reg_rlcg *entry; 1676 1677 entry = &entries[i]; 1678 inst = adev->ip_map.logical_to_dev_inst ? 1679 adev->ip_map.logical_to_dev_inst( 1680 adev, entry->hwip, entry->instance) : 1681 entry->instance; 1682 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1683 entry->reg; 1684 if (offset == reg) 1685 return true; 1686 } 1687 1688 return false; 1689 } 1690 1691 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1692 { 1693 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1694 (void *)rlcg_access_gc_9_4_3, 1695 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1696 } 1697 1698 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1699 bool enable, int xcc_id) 1700 { 1701 if (enable) { 1702 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1703 } else { 1704 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1705 (CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK | 1706 CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK | 1707 CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK | 1708 CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK | 1709 CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK | 1710 CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK | 1711 CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK | 1712 CP_MEC_CNTL__MEC_ME1_HALT_MASK | 1713 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1714 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1715 } 1716 udelay(50); 1717 } 1718 1719 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1720 int xcc_id) 1721 { 1722 const struct gfx_firmware_header_v1_0 *mec_hdr; 1723 const __le32 *fw_data; 1724 unsigned i; 1725 u32 tmp; 1726 u32 mec_ucode_addr_offset; 1727 u32 mec_ucode_data_offset; 1728 1729 if (!adev->gfx.mec_fw) 1730 return -EINVAL; 1731 1732 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1733 1734 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1735 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1736 1737 fw_data = (const __le32 *) 1738 (adev->gfx.mec_fw->data + 1739 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1740 tmp = 0; 1741 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1742 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1743 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1744 1745 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1746 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1747 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1748 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1749 1750 mec_ucode_addr_offset = 1751 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1752 mec_ucode_data_offset = 1753 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1754 1755 /* MEC1 */ 1756 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1757 for (i = 0; i < mec_hdr->jt_size; i++) 1758 WREG32(mec_ucode_data_offset, 1759 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1760 1761 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1762 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1763 1764 return 0; 1765 } 1766 1767 /* KIQ functions */ 1768 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1769 { 1770 uint32_t tmp; 1771 struct amdgpu_device *adev = ring->adev; 1772 1773 /* tell RLC which is KIQ queue */ 1774 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1775 tmp &= 0xffffff00; 1776 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1777 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp | 0x80); 1778 } 1779 1780 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1781 { 1782 struct amdgpu_device *adev = ring->adev; 1783 1784 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1785 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1786 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1787 mqd->cp_hqd_queue_priority = 1788 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1789 } 1790 } 1791 } 1792 1793 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1794 { 1795 struct amdgpu_device *adev = ring->adev; 1796 struct v9_mqd *mqd = ring->mqd_ptr; 1797 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1798 uint32_t tmp; 1799 1800 mqd->header = 0xC0310800; 1801 mqd->compute_pipelinestat_enable = 0x00000001; 1802 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1803 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1804 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1805 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1806 mqd->compute_misc_reserved = 0x00000003; 1807 1808 mqd->dynamic_cu_mask_addr_lo = 1809 lower_32_bits(ring->mqd_gpu_addr 1810 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1811 mqd->dynamic_cu_mask_addr_hi = 1812 upper_32_bits(ring->mqd_gpu_addr 1813 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1814 1815 eop_base_addr = ring->eop_gpu_addr >> 8; 1816 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1817 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1818 1819 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1820 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1821 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1822 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1823 1824 mqd->cp_hqd_eop_control = tmp; 1825 1826 /* enable doorbell? */ 1827 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1828 1829 if (ring->use_doorbell) { 1830 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1831 DOORBELL_OFFSET, ring->doorbell_index); 1832 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1833 DOORBELL_EN, 1); 1834 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1835 DOORBELL_SOURCE, 0); 1836 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1837 DOORBELL_HIT, 0); 1838 if (amdgpu_sriov_vf(adev)) 1839 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1840 DOORBELL_MODE, 1); 1841 } else { 1842 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1843 DOORBELL_EN, 0); 1844 } 1845 1846 mqd->cp_hqd_pq_doorbell_control = tmp; 1847 1848 /* disable the queue if it's active */ 1849 ring->wptr = 0; 1850 mqd->cp_hqd_dequeue_request = 0; 1851 mqd->cp_hqd_pq_rptr = 0; 1852 mqd->cp_hqd_pq_wptr_lo = 0; 1853 mqd->cp_hqd_pq_wptr_hi = 0; 1854 1855 /* set the pointer to the MQD */ 1856 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1857 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1858 1859 /* set MQD vmid to 0 */ 1860 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1861 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1862 mqd->cp_mqd_control = tmp; 1863 1864 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1865 hqd_gpu_addr = ring->gpu_addr >> 8; 1866 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1867 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1868 1869 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1870 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1871 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1872 (order_base_2(ring->ring_size / 4) - 1)); 1873 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1874 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1875 #ifdef __BIG_ENDIAN 1876 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1877 #endif 1878 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1879 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1880 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1881 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1882 mqd->cp_hqd_pq_control = tmp; 1883 1884 /* set the wb address whether it's enabled or not */ 1885 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1886 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1887 mqd->cp_hqd_pq_rptr_report_addr_hi = 1888 upper_32_bits(wb_gpu_addr) & 0xffff; 1889 1890 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1891 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1892 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1893 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1894 1895 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1896 ring->wptr = 0; 1897 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1898 1899 /* set the vmid for the queue */ 1900 mqd->cp_hqd_vmid = 0; 1901 1902 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1903 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1904 mqd->cp_hqd_persistent_state = tmp; 1905 1906 /* set MIN_IB_AVAIL_SIZE */ 1907 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1908 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1909 mqd->cp_hqd_ib_control = tmp; 1910 1911 /* set static priority for a queue/ring */ 1912 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1913 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1914 1915 /* map_queues packet doesn't need activate the queue, 1916 * so only kiq need set this field. 1917 */ 1918 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1919 mqd->cp_hqd_active = 1; 1920 1921 return 0; 1922 } 1923 1924 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1925 int xcc_id) 1926 { 1927 struct amdgpu_device *adev = ring->adev; 1928 struct v9_mqd *mqd = ring->mqd_ptr; 1929 int j; 1930 1931 /* disable wptr polling */ 1932 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1933 1934 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1935 mqd->cp_hqd_eop_base_addr_lo); 1936 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1937 mqd->cp_hqd_eop_base_addr_hi); 1938 1939 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1940 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1941 mqd->cp_hqd_eop_control); 1942 1943 /* enable doorbell? */ 1944 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1945 mqd->cp_hqd_pq_doorbell_control); 1946 1947 /* disable the queue if it's active */ 1948 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1949 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1950 for (j = 0; j < adev->usec_timeout; j++) { 1951 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1952 break; 1953 udelay(1); 1954 } 1955 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1956 mqd->cp_hqd_dequeue_request); 1957 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1958 mqd->cp_hqd_pq_rptr); 1959 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1960 mqd->cp_hqd_pq_wptr_lo); 1961 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1962 mqd->cp_hqd_pq_wptr_hi); 1963 } 1964 1965 /* set the pointer to the MQD */ 1966 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 1967 mqd->cp_mqd_base_addr_lo); 1968 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 1969 mqd->cp_mqd_base_addr_hi); 1970 1971 /* set MQD vmid to 0 */ 1972 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 1973 mqd->cp_mqd_control); 1974 1975 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1976 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 1977 mqd->cp_hqd_pq_base_lo); 1978 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 1979 mqd->cp_hqd_pq_base_hi); 1980 1981 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1982 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 1983 mqd->cp_hqd_pq_control); 1984 1985 /* set the wb address whether it's enabled or not */ 1986 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 1987 mqd->cp_hqd_pq_rptr_report_addr_lo); 1988 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1989 mqd->cp_hqd_pq_rptr_report_addr_hi); 1990 1991 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1992 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 1993 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1994 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1995 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1996 1997 /* enable the doorbell if requested */ 1998 if (ring->use_doorbell) { 1999 WREG32_SOC15( 2000 GC, GET_INST(GC, xcc_id), 2001 regCP_MEC_DOORBELL_RANGE_LOWER, 2002 ((adev->doorbell_index.kiq + 2003 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2004 2) << 2); 2005 WREG32_SOC15( 2006 GC, GET_INST(GC, xcc_id), 2007 regCP_MEC_DOORBELL_RANGE_UPPER, 2008 ((adev->doorbell_index.userqueue_end + 2009 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2010 2) << 2); 2011 } 2012 2013 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 2014 mqd->cp_hqd_pq_doorbell_control); 2015 2016 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2017 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 2018 mqd->cp_hqd_pq_wptr_lo); 2019 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 2020 mqd->cp_hqd_pq_wptr_hi); 2021 2022 /* set the vmid for the queue */ 2023 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 2024 2025 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 2026 mqd->cp_hqd_persistent_state); 2027 2028 /* activate the queue */ 2029 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 2030 mqd->cp_hqd_active); 2031 2032 if (ring->use_doorbell) 2033 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 2034 2035 return 0; 2036 } 2037 2038 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 2039 int xcc_id) 2040 { 2041 struct amdgpu_device *adev = ring->adev; 2042 int j; 2043 2044 /* disable the queue if it's active */ 2045 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 2046 2047 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 2048 2049 for (j = 0; j < adev->usec_timeout; j++) { 2050 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 2051 break; 2052 udelay(1); 2053 } 2054 2055 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 2056 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 2057 2058 /* Manual disable if dequeue request times out */ 2059 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 2060 } 2061 2062 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 2063 0); 2064 } 2065 2066 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 2067 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 2068 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT); 2069 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 2070 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 2071 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 2072 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 2073 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 2074 2075 return 0; 2076 } 2077 2078 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 2079 { 2080 struct amdgpu_device *adev = ring->adev; 2081 struct v9_mqd *mqd = ring->mqd_ptr; 2082 struct v9_mqd *tmp_mqd; 2083 2084 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 2085 2086 /* GPU could be in bad state during probe, driver trigger the reset 2087 * after load the SMU, in this case , the mqd is not be initialized. 2088 * driver need to re-init the mqd. 2089 * check mqd->cp_hqd_pq_control since this value should not be 0 2090 */ 2091 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 2092 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 2093 /* for GPU_RESET case , reset MQD to a clean status */ 2094 if (adev->gfx.kiq[xcc_id].mqd_backup) 2095 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 2096 2097 /* reset ring buffer */ 2098 ring->wptr = 0; 2099 amdgpu_ring_clear_ring(ring); 2100 mutex_lock(&adev->srbm_mutex); 2101 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2102 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2103 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2104 mutex_unlock(&adev->srbm_mutex); 2105 } else { 2106 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2107 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2108 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2109 mutex_lock(&adev->srbm_mutex); 2110 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 2111 amdgpu_ring_clear_ring(ring); 2112 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2113 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2114 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2115 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2116 mutex_unlock(&adev->srbm_mutex); 2117 2118 if (adev->gfx.kiq[xcc_id].mqd_backup) 2119 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 2120 } 2121 2122 return 0; 2123 } 2124 2125 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id, bool restore) 2126 { 2127 struct amdgpu_device *adev = ring->adev; 2128 struct v9_mqd *mqd = ring->mqd_ptr; 2129 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 2130 struct v9_mqd *tmp_mqd; 2131 2132 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 2133 * is not be initialized before 2134 */ 2135 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 2136 2137 if (!restore && (!tmp_mqd->cp_hqd_pq_control || 2138 (!amdgpu_in_reset(adev) && !adev->in_suspend))) { 2139 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2140 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2141 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2142 mutex_lock(&adev->srbm_mutex); 2143 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2144 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2145 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2146 mutex_unlock(&adev->srbm_mutex); 2147 2148 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2149 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 2150 } else { 2151 /* restore MQD to a clean status */ 2152 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2153 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 2154 /* reset ring buffer */ 2155 ring->wptr = 0; 2156 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 2157 amdgpu_ring_clear_ring(ring); 2158 } 2159 2160 return 0; 2161 } 2162 2163 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 2164 { 2165 struct amdgpu_ring *ring; 2166 int j; 2167 2168 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2169 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 2170 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2171 mutex_lock(&adev->srbm_mutex); 2172 soc15_grbm_select(adev, ring->me, 2173 ring->pipe, 2174 ring->queue, 0, GET_INST(GC, xcc_id)); 2175 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 2176 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2177 mutex_unlock(&adev->srbm_mutex); 2178 } 2179 } 2180 2181 return 0; 2182 } 2183 2184 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 2185 { 2186 struct amdgpu_ring *ring; 2187 int r; 2188 2189 ring = &adev->gfx.kiq[xcc_id].ring; 2190 2191 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2192 if (unlikely(r != 0)) 2193 return r; 2194 2195 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2196 if (unlikely(r != 0)) { 2197 amdgpu_bo_unreserve(ring->mqd_obj); 2198 return r; 2199 } 2200 2201 gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id); 2202 amdgpu_bo_kunmap(ring->mqd_obj); 2203 ring->mqd_ptr = NULL; 2204 amdgpu_bo_unreserve(ring->mqd_obj); 2205 return 0; 2206 } 2207 2208 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 2209 { 2210 struct amdgpu_ring *ring = NULL; 2211 int r = 0, i; 2212 2213 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 2214 2215 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2216 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 2217 2218 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2219 if (unlikely(r != 0)) 2220 goto done; 2221 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2222 if (!r) { 2223 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id, false); 2224 amdgpu_bo_kunmap(ring->mqd_obj); 2225 ring->mqd_ptr = NULL; 2226 } 2227 amdgpu_bo_unreserve(ring->mqd_obj); 2228 if (r) 2229 goto done; 2230 } 2231 2232 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 2233 done: 2234 return r; 2235 } 2236 2237 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 2238 { 2239 struct amdgpu_ring *ring; 2240 int r, j; 2241 2242 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 2243 2244 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2245 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 2246 2247 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 2248 if (r) 2249 return r; 2250 } else { 2251 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2252 } 2253 2254 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 2255 if (r) 2256 return r; 2257 2258 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 2259 if (r) 2260 return r; 2261 2262 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2263 ring = &adev->gfx.compute_ring 2264 [j + xcc_id * adev->gfx.num_compute_rings]; 2265 r = amdgpu_ring_test_helper(ring); 2266 if (r) 2267 return r; 2268 } 2269 2270 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 2271 2272 return 0; 2273 } 2274 2275 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 2276 { 2277 int r = 0, i, num_xcc, num_xcp, num_xcc_per_xcp; 2278 2279 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2280 if (amdgpu_sriov_vf(adev)) { 2281 enum amdgpu_gfx_partition mode; 2282 2283 mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2284 AMDGPU_XCP_FL_NONE); 2285 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2286 return -EINVAL; 2287 num_xcc_per_xcp = gfx_v9_4_3_get_xccs_per_xcp(adev); 2288 adev->gfx.num_xcc_per_xcp = num_xcc_per_xcp; 2289 num_xcp = num_xcc / num_xcc_per_xcp; 2290 r = amdgpu_xcp_init(adev->xcp_mgr, num_xcp, mode); 2291 2292 } else { 2293 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2294 AMDGPU_XCP_FL_NONE) == 2295 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2296 r = amdgpu_xcp_switch_partition_mode( 2297 adev->xcp_mgr, amdgpu_user_partt_mode); 2298 } 2299 if (r) 2300 return r; 2301 2302 for (i = 0; i < num_xcc; i++) { 2303 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 2304 if (r) 2305 return r; 2306 } 2307 2308 return 0; 2309 } 2310 2311 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 2312 { 2313 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 2314 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 2315 2316 if (amdgpu_sriov_vf(adev)) { 2317 /* must disable polling for SRIOV when hw finished, otherwise 2318 * CPC engine may still keep fetching WB address which is already 2319 * invalid after sw finished and trigger DMAR reading error in 2320 * hypervisor side. 2321 */ 2322 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 2323 return; 2324 } 2325 2326 /* Use deinitialize sequence from CAIL when unbinding device 2327 * from driver, otherwise KIQ is hanging when binding back 2328 */ 2329 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2330 mutex_lock(&adev->srbm_mutex); 2331 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 2332 adev->gfx.kiq[xcc_id].ring.pipe, 2333 adev->gfx.kiq[xcc_id].ring.queue, 0, 2334 GET_INST(GC, xcc_id)); 2335 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 2336 xcc_id); 2337 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2338 mutex_unlock(&adev->srbm_mutex); 2339 } 2340 2341 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 2342 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2343 } 2344 2345 static int gfx_v9_4_3_hw_init(struct amdgpu_ip_block *ip_block) 2346 { 2347 int r; 2348 struct amdgpu_device *adev = ip_block->adev; 2349 2350 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 2351 adev->gfx.cleaner_shader_ptr); 2352 2353 if (!amdgpu_sriov_vf(adev)) 2354 gfx_v9_4_3_init_golden_registers(adev); 2355 2356 gfx_v9_4_3_constants_init(adev); 2357 2358 r = adev->gfx.rlc.funcs->resume(adev); 2359 if (r) 2360 return r; 2361 2362 r = gfx_v9_4_3_cp_resume(adev); 2363 if (r) 2364 return r; 2365 2366 return r; 2367 } 2368 2369 static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) 2370 { 2371 struct amdgpu_device *adev = ip_block->adev; 2372 int i, num_xcc; 2373 2374 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2375 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2376 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 2377 2378 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2379 for (i = 0; i < num_xcc; i++) { 2380 gfx_v9_4_3_xcc_fini(adev, i); 2381 } 2382 2383 return 0; 2384 } 2385 2386 static int gfx_v9_4_3_suspend(struct amdgpu_ip_block *ip_block) 2387 { 2388 return gfx_v9_4_3_hw_fini(ip_block); 2389 } 2390 2391 static int gfx_v9_4_3_resume(struct amdgpu_ip_block *ip_block) 2392 { 2393 return gfx_v9_4_3_hw_init(ip_block); 2394 } 2395 2396 static bool gfx_v9_4_3_is_idle(struct amdgpu_ip_block *ip_block) 2397 { 2398 struct amdgpu_device *adev = ip_block->adev; 2399 int i, num_xcc; 2400 2401 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2402 for (i = 0; i < num_xcc; i++) { 2403 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2404 GRBM_STATUS, GUI_ACTIVE)) 2405 return false; 2406 } 2407 return true; 2408 } 2409 2410 static int gfx_v9_4_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 2411 { 2412 unsigned i; 2413 struct amdgpu_device *adev = ip_block->adev; 2414 2415 for (i = 0; i < adev->usec_timeout; i++) { 2416 if (gfx_v9_4_3_is_idle(ip_block)) 2417 return 0; 2418 udelay(1); 2419 } 2420 return -ETIMEDOUT; 2421 } 2422 2423 static int gfx_v9_4_3_soft_reset(struct amdgpu_ip_block *ip_block) 2424 { 2425 u32 grbm_soft_reset = 0; 2426 u32 tmp; 2427 struct amdgpu_device *adev = ip_block->adev; 2428 2429 /* GRBM_STATUS */ 2430 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2431 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2432 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2433 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2434 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2435 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2436 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2437 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2438 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2439 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2440 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2441 } 2442 2443 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2444 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2445 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2446 } 2447 2448 /* GRBM_STATUS2 */ 2449 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2450 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2451 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2452 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2453 2454 2455 if (grbm_soft_reset) { 2456 /* stop the rlc */ 2457 adev->gfx.rlc.funcs->stop(adev); 2458 2459 /* Disable MEC parsing/prefetching */ 2460 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2461 2462 if (grbm_soft_reset) { 2463 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2464 tmp |= grbm_soft_reset; 2465 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2466 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2467 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2468 2469 udelay(50); 2470 2471 tmp &= ~grbm_soft_reset; 2472 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2473 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2474 } 2475 2476 /* Wait a little for things to settle down */ 2477 udelay(50); 2478 } 2479 return 0; 2480 } 2481 2482 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2483 uint32_t vmid, 2484 uint32_t gds_base, uint32_t gds_size, 2485 uint32_t gws_base, uint32_t gws_size, 2486 uint32_t oa_base, uint32_t oa_size) 2487 { 2488 struct amdgpu_device *adev = ring->adev; 2489 2490 /* GDS Base */ 2491 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2492 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2493 gds_base); 2494 2495 /* GDS Size */ 2496 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2497 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2498 gds_size); 2499 2500 /* GWS */ 2501 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2502 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2503 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2504 2505 /* OA */ 2506 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2507 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2508 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2509 } 2510 2511 static int gfx_v9_4_3_early_init(struct amdgpu_ip_block *ip_block) 2512 { 2513 struct amdgpu_device *adev = ip_block->adev; 2514 2515 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2516 AMDGPU_MAX_COMPUTE_RINGS); 2517 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2518 gfx_v9_4_3_set_ring_funcs(adev); 2519 gfx_v9_4_3_set_irq_funcs(adev); 2520 gfx_v9_4_3_set_gds_init(adev); 2521 gfx_v9_4_3_set_rlc_funcs(adev); 2522 2523 /* init rlcg reg access ctrl */ 2524 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev); 2525 2526 return gfx_v9_4_3_init_microcode(adev); 2527 } 2528 2529 static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) 2530 { 2531 struct amdgpu_device *adev = ip_block->adev; 2532 int r; 2533 2534 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2535 if (r) 2536 return r; 2537 2538 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2539 if (r) 2540 return r; 2541 2542 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 2543 if (r) 2544 return r; 2545 2546 if (adev->gfx.ras && 2547 adev->gfx.ras->enable_watchdog_timer) 2548 adev->gfx.ras->enable_watchdog_timer(adev); 2549 2550 return 0; 2551 } 2552 2553 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2554 bool enable, int xcc_id) 2555 { 2556 uint32_t def, data; 2557 2558 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2559 return; 2560 2561 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2562 regRLC_CGTT_MGCG_OVERRIDE); 2563 2564 if (enable) 2565 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2566 else 2567 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2568 2569 if (def != data) 2570 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2571 regRLC_CGTT_MGCG_OVERRIDE, data); 2572 2573 } 2574 2575 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2576 bool enable, int xcc_id) 2577 { 2578 uint32_t def, data; 2579 2580 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2581 return; 2582 2583 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2584 regRLC_CGTT_MGCG_OVERRIDE); 2585 2586 if (enable) 2587 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2588 else 2589 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2590 2591 if (def != data) 2592 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2593 regRLC_CGTT_MGCG_OVERRIDE, data); 2594 } 2595 2596 static void 2597 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2598 bool enable, int xcc_id) 2599 { 2600 uint32_t data, def; 2601 2602 /* It is disabled by HW by default */ 2603 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2604 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2605 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2606 2607 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2608 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2609 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2610 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2611 2612 if (def != data) 2613 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2614 2615 /* MGLS is a global flag to control all MGLS in GFX */ 2616 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2617 /* 2 - RLC memory Light sleep */ 2618 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2619 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2620 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2621 if (def != data) 2622 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2623 } 2624 /* 3 - CP memory Light sleep */ 2625 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2626 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2627 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2628 if (def != data) 2629 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2630 } 2631 } 2632 } else { 2633 /* 1 - MGCG_OVERRIDE */ 2634 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2635 2636 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2637 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2638 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2639 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2640 2641 if (def != data) 2642 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2643 2644 /* 2 - disable MGLS in RLC */ 2645 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2646 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2647 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2648 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2649 } 2650 2651 /* 3 - disable MGLS in CP */ 2652 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2653 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2654 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2655 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2656 } 2657 } 2658 2659 } 2660 2661 static void 2662 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2663 bool enable, int xcc_id) 2664 { 2665 uint32_t def, data; 2666 2667 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2668 2669 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2670 /* unset CGCG override */ 2671 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2672 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2673 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2674 else 2675 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2676 /* update CGCG and CGLS override bits */ 2677 if (def != data) 2678 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2679 2680 /* CGCG Hysteresis: 400us */ 2681 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2682 2683 data = (0x2710 2684 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2685 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2686 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2687 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2688 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2689 if (def != data) 2690 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2691 2692 /* set IDLE_POLL_COUNT(0x33450100)*/ 2693 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2694 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2695 (0x3345 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2696 if (def != data) 2697 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2698 } else { 2699 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2700 /* reset CGCG/CGLS bits */ 2701 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2702 /* disable cgcg and cgls in FSM */ 2703 if (def != data) 2704 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2705 } 2706 2707 } 2708 2709 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2710 bool enable, int xcc_id) 2711 { 2712 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2713 2714 if (enable) { 2715 /* FGCG */ 2716 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2717 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2718 2719 /* CGCG/CGLS should be enabled after MGCG/MGLS 2720 * === MGCG + MGLS === 2721 */ 2722 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2723 xcc_id); 2724 /* === CGCG + CGLS === */ 2725 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2726 xcc_id); 2727 } else { 2728 /* CGCG/CGLS should be disabled before MGCG/MGLS 2729 * === CGCG + CGLS === 2730 */ 2731 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2732 xcc_id); 2733 /* === MGCG + MGLS === */ 2734 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2735 xcc_id); 2736 2737 /* FGCG */ 2738 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2739 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2740 } 2741 2742 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2743 2744 return 0; 2745 } 2746 2747 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2748 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2749 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2750 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2751 .init = gfx_v9_4_3_rlc_init, 2752 .resume = gfx_v9_4_3_rlc_resume, 2753 .stop = gfx_v9_4_3_rlc_stop, 2754 .reset = gfx_v9_4_3_rlc_reset, 2755 .start = gfx_v9_4_3_rlc_start, 2756 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2757 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2758 }; 2759 2760 static int gfx_v9_4_3_set_powergating_state(struct amdgpu_ip_block *ip_block, 2761 enum amd_powergating_state state) 2762 { 2763 return 0; 2764 } 2765 2766 static int gfx_v9_4_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2767 enum amd_clockgating_state state) 2768 { 2769 struct amdgpu_device *adev = ip_block->adev; 2770 int i, num_xcc; 2771 2772 if (amdgpu_sriov_vf(adev)) 2773 return 0; 2774 2775 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2776 for (i = 0; i < num_xcc; i++) 2777 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2778 adev, state == AMD_CG_STATE_GATE, i); 2779 2780 return 0; 2781 } 2782 2783 static void gfx_v9_4_3_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 2784 { 2785 struct amdgpu_device *adev = ip_block->adev; 2786 int data; 2787 2788 if (amdgpu_sriov_vf(adev)) 2789 *flags = 0; 2790 2791 /* AMD_CG_SUPPORT_GFX_MGCG */ 2792 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2793 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2794 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2795 2796 /* AMD_CG_SUPPORT_GFX_CGCG */ 2797 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2798 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2799 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2800 2801 /* AMD_CG_SUPPORT_GFX_CGLS */ 2802 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2803 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2804 2805 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2806 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2807 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2808 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2809 2810 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2811 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2812 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2813 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2814 } 2815 2816 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2817 { 2818 struct amdgpu_device *adev = ring->adev; 2819 u32 ref_and_mask, reg_mem_engine; 2820 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 2821 2822 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2823 switch (ring->me) { 2824 case 1: 2825 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 2826 break; 2827 case 2: 2828 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 2829 break; 2830 default: 2831 return; 2832 } 2833 reg_mem_engine = 0; 2834 } else { 2835 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 2836 reg_mem_engine = 1; /* pfp */ 2837 } 2838 2839 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2840 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2841 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2842 ref_and_mask, ref_and_mask, 0x20); 2843 } 2844 2845 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2846 struct amdgpu_job *job, 2847 struct amdgpu_ib *ib, 2848 uint32_t flags) 2849 { 2850 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2851 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2852 2853 /* Currently, there is a high possibility to get wave ID mismatch 2854 * between ME and GDS, leading to a hw deadlock, because ME generates 2855 * different wave IDs than the GDS expects. This situation happens 2856 * randomly when at least 5 compute pipes use GDS ordered append. 2857 * The wave IDs generated by ME are also wrong after suspend/resume. 2858 * Those are probably bugs somewhere else in the kernel driver. 2859 * 2860 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2861 * GDS to 0 for this ring (me/pipe). 2862 */ 2863 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2864 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2865 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2866 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2867 } 2868 2869 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2870 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2871 amdgpu_ring_write(ring, 2872 #ifdef __BIG_ENDIAN 2873 (2 << 0) | 2874 #endif 2875 lower_32_bits(ib->gpu_addr)); 2876 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2877 amdgpu_ring_write(ring, control); 2878 } 2879 2880 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2881 u64 seq, unsigned flags) 2882 { 2883 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2884 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2885 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2886 2887 /* RELEASE_MEM - flush caches, send int */ 2888 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2889 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2890 EOP_TC_NC_ACTION_EN) : 2891 (EOP_TCL1_ACTION_EN | 2892 EOP_TC_ACTION_EN | 2893 EOP_TC_WB_ACTION_EN | 2894 EOP_TC_MD_ACTION_EN)) | 2895 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2896 EVENT_INDEX(5))); 2897 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2898 2899 /* 2900 * the address should be Qword aligned if 64bit write, Dword 2901 * aligned if only send 32bit data low (discard data high) 2902 */ 2903 if (write64bit) 2904 BUG_ON(addr & 0x7); 2905 else 2906 BUG_ON(addr & 0x3); 2907 amdgpu_ring_write(ring, lower_32_bits(addr)); 2908 amdgpu_ring_write(ring, upper_32_bits(addr)); 2909 amdgpu_ring_write(ring, lower_32_bits(seq)); 2910 amdgpu_ring_write(ring, upper_32_bits(seq)); 2911 amdgpu_ring_write(ring, 0); 2912 } 2913 2914 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2915 { 2916 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2917 uint32_t seq = ring->fence_drv.sync_seq; 2918 uint64_t addr = ring->fence_drv.gpu_addr; 2919 2920 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2921 lower_32_bits(addr), upper_32_bits(addr), 2922 seq, 0xffffffff, 4); 2923 } 2924 2925 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2926 unsigned vmid, uint64_t pd_addr) 2927 { 2928 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2929 } 2930 2931 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2932 { 2933 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2934 } 2935 2936 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2937 { 2938 u64 wptr; 2939 2940 /* XXX check if swapping is necessary on BE */ 2941 if (ring->use_doorbell) 2942 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2943 else 2944 BUG(); 2945 return wptr; 2946 } 2947 2948 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2949 { 2950 struct amdgpu_device *adev = ring->adev; 2951 2952 /* XXX check if swapping is necessary on BE */ 2953 if (ring->use_doorbell) { 2954 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2955 WDOORBELL64(ring->doorbell_index, ring->wptr); 2956 } else { 2957 BUG(); /* only DOORBELL method supported on gfx9 now */ 2958 } 2959 } 2960 2961 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2962 u64 seq, unsigned int flags) 2963 { 2964 struct amdgpu_device *adev = ring->adev; 2965 2966 /* we only allocate 32bit for each seq wb address */ 2967 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2968 2969 /* write fence seq to the "addr" */ 2970 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2971 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2972 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2973 amdgpu_ring_write(ring, lower_32_bits(addr)); 2974 amdgpu_ring_write(ring, upper_32_bits(addr)); 2975 amdgpu_ring_write(ring, lower_32_bits(seq)); 2976 2977 if (flags & AMDGPU_FENCE_FLAG_INT) { 2978 /* set register to trigger INT */ 2979 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2980 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2981 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 2982 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 2983 amdgpu_ring_write(ring, 0); 2984 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 2985 } 2986 } 2987 2988 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 2989 uint32_t reg_val_offs) 2990 { 2991 struct amdgpu_device *adev = ring->adev; 2992 2993 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 2994 2995 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 2996 amdgpu_ring_write(ring, 0 | /* src: register*/ 2997 (5 << 8) | /* dst: memory */ 2998 (1 << 20)); /* write confirm */ 2999 amdgpu_ring_write(ring, reg); 3000 amdgpu_ring_write(ring, 0); 3001 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 3002 reg_val_offs * 4)); 3003 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 3004 reg_val_offs * 4)); 3005 } 3006 3007 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 3008 uint32_t val) 3009 { 3010 uint32_t cmd = 0; 3011 3012 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 3013 3014 switch (ring->funcs->type) { 3015 case AMDGPU_RING_TYPE_GFX: 3016 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 3017 break; 3018 case AMDGPU_RING_TYPE_KIQ: 3019 cmd = (1 << 16); /* no inc addr */ 3020 break; 3021 default: 3022 cmd = WR_CONFIRM; 3023 break; 3024 } 3025 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3026 amdgpu_ring_write(ring, cmd); 3027 amdgpu_ring_write(ring, reg); 3028 amdgpu_ring_write(ring, 0); 3029 amdgpu_ring_write(ring, val); 3030 } 3031 3032 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 3033 uint32_t val, uint32_t mask) 3034 { 3035 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 3036 } 3037 3038 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 3039 uint32_t reg0, uint32_t reg1, 3040 uint32_t ref, uint32_t mask) 3041 { 3042 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 3043 ref, mask); 3044 } 3045 3046 static void gfx_v9_4_3_ring_soft_recovery(struct amdgpu_ring *ring, 3047 unsigned vmid) 3048 { 3049 struct amdgpu_device *adev = ring->adev; 3050 uint32_t value = 0; 3051 3052 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 3053 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 3054 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 3055 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 3056 amdgpu_gfx_rlc_enter_safe_mode(adev, ring->xcc_id); 3057 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regSQ_CMD, value); 3058 amdgpu_gfx_rlc_exit_safe_mode(adev, ring->xcc_id); 3059 } 3060 3061 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3062 struct amdgpu_device *adev, int me, int pipe, 3063 enum amdgpu_interrupt_state state, int xcc_id) 3064 { 3065 u32 mec_int_cntl, mec_int_cntl_reg; 3066 3067 /* 3068 * amdgpu controls only the first MEC. That's why this function only 3069 * handles the setting of interrupts for this specific MEC. All other 3070 * pipes' interrupts are set by amdkfd. 3071 */ 3072 3073 if (me == 1) { 3074 switch (pipe) { 3075 case 0: 3076 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3077 break; 3078 case 1: 3079 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3080 break; 3081 case 2: 3082 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3083 break; 3084 case 3: 3085 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3086 break; 3087 default: 3088 DRM_DEBUG("invalid pipe %d\n", pipe); 3089 return; 3090 } 3091 } else { 3092 DRM_DEBUG("invalid me %d\n", me); 3093 return; 3094 } 3095 3096 switch (state) { 3097 case AMDGPU_IRQ_STATE_DISABLE: 3098 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3099 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3100 TIME_STAMP_INT_ENABLE, 0); 3101 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3102 break; 3103 case AMDGPU_IRQ_STATE_ENABLE: 3104 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3105 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3106 TIME_STAMP_INT_ENABLE, 1); 3107 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3108 break; 3109 default: 3110 break; 3111 } 3112 } 3113 3114 static u32 gfx_v9_4_3_get_cpc_int_cntl(struct amdgpu_device *adev, 3115 int xcc_id, int me, int pipe) 3116 { 3117 /* 3118 * amdgpu controls only the first MEC. That's why this function only 3119 * handles the setting of interrupts for this specific MEC. All other 3120 * pipes' interrupts are set by amdkfd. 3121 */ 3122 if (me != 1) 3123 return 0; 3124 3125 switch (pipe) { 3126 case 0: 3127 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3128 case 1: 3129 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3130 case 2: 3131 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3132 case 3: 3133 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3134 default: 3135 return 0; 3136 } 3137 } 3138 3139 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 3140 struct amdgpu_irq_src *source, 3141 unsigned type, 3142 enum amdgpu_interrupt_state state) 3143 { 3144 u32 mec_int_cntl_reg, mec_int_cntl; 3145 int i, j, k, num_xcc; 3146 3147 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3148 switch (state) { 3149 case AMDGPU_IRQ_STATE_DISABLE: 3150 case AMDGPU_IRQ_STATE_ENABLE: 3151 for (i = 0; i < num_xcc; i++) { 3152 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3153 PRIV_REG_INT_ENABLE, 3154 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3155 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3156 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3157 /* MECs start at 1 */ 3158 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3159 3160 if (mec_int_cntl_reg) { 3161 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3162 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3163 PRIV_REG_INT_ENABLE, 3164 state == AMDGPU_IRQ_STATE_ENABLE ? 3165 1 : 0); 3166 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3167 } 3168 } 3169 } 3170 } 3171 break; 3172 default: 3173 break; 3174 } 3175 3176 return 0; 3177 } 3178 3179 static int gfx_v9_4_3_set_bad_op_fault_state(struct amdgpu_device *adev, 3180 struct amdgpu_irq_src *source, 3181 unsigned type, 3182 enum amdgpu_interrupt_state state) 3183 { 3184 u32 mec_int_cntl_reg, mec_int_cntl; 3185 int i, j, k, num_xcc; 3186 3187 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3188 switch (state) { 3189 case AMDGPU_IRQ_STATE_DISABLE: 3190 case AMDGPU_IRQ_STATE_ENABLE: 3191 for (i = 0; i < num_xcc; i++) { 3192 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3193 OPCODE_ERROR_INT_ENABLE, 3194 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3195 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3196 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3197 /* MECs start at 1 */ 3198 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3199 3200 if (mec_int_cntl_reg) { 3201 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3202 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3203 OPCODE_ERROR_INT_ENABLE, 3204 state == AMDGPU_IRQ_STATE_ENABLE ? 3205 1 : 0); 3206 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3207 } 3208 } 3209 } 3210 } 3211 break; 3212 default: 3213 break; 3214 } 3215 3216 return 0; 3217 } 3218 3219 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 3220 struct amdgpu_irq_src *source, 3221 unsigned type, 3222 enum amdgpu_interrupt_state state) 3223 { 3224 int i, num_xcc; 3225 3226 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3227 switch (state) { 3228 case AMDGPU_IRQ_STATE_DISABLE: 3229 case AMDGPU_IRQ_STATE_ENABLE: 3230 for (i = 0; i < num_xcc; i++) 3231 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3232 PRIV_INSTR_INT_ENABLE, 3233 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3234 break; 3235 default: 3236 break; 3237 } 3238 3239 return 0; 3240 } 3241 3242 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 3243 struct amdgpu_irq_src *src, 3244 unsigned type, 3245 enum amdgpu_interrupt_state state) 3246 { 3247 int i, num_xcc; 3248 3249 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3250 for (i = 0; i < num_xcc; i++) { 3251 switch (type) { 3252 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3253 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3254 adev, 1, 0, state, i); 3255 break; 3256 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3257 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3258 adev, 1, 1, state, i); 3259 break; 3260 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 3261 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3262 adev, 1, 2, state, i); 3263 break; 3264 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 3265 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3266 adev, 1, 3, state, i); 3267 break; 3268 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 3269 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3270 adev, 2, 0, state, i); 3271 break; 3272 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 3273 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3274 adev, 2, 1, state, i); 3275 break; 3276 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 3277 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3278 adev, 2, 2, state, i); 3279 break; 3280 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 3281 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3282 adev, 2, 3, state, i); 3283 break; 3284 default: 3285 break; 3286 } 3287 } 3288 3289 return 0; 3290 } 3291 3292 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 3293 struct amdgpu_irq_src *source, 3294 struct amdgpu_iv_entry *entry) 3295 { 3296 int i, xcc_id; 3297 u8 me_id, pipe_id, queue_id; 3298 struct amdgpu_ring *ring; 3299 3300 DRM_DEBUG("IH: CP EOP\n"); 3301 me_id = (entry->ring_id & 0x0c) >> 2; 3302 pipe_id = (entry->ring_id & 0x03) >> 0; 3303 queue_id = (entry->ring_id & 0x70) >> 4; 3304 3305 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3306 3307 if (xcc_id == -EINVAL) 3308 return -EINVAL; 3309 3310 switch (me_id) { 3311 case 0: 3312 case 1: 3313 case 2: 3314 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3315 ring = &adev->gfx.compute_ring 3316 [i + 3317 xcc_id * adev->gfx.num_compute_rings]; 3318 /* Per-queue interrupt is supported for MEC starting from VI. 3319 * The interrupt can only be enabled/disabled per pipe instead of per queue. 3320 */ 3321 3322 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 3323 amdgpu_fence_process(ring); 3324 } 3325 break; 3326 } 3327 return 0; 3328 } 3329 3330 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 3331 struct amdgpu_iv_entry *entry) 3332 { 3333 u8 me_id, pipe_id, queue_id; 3334 struct amdgpu_ring *ring; 3335 int i, xcc_id; 3336 3337 me_id = (entry->ring_id & 0x0c) >> 2; 3338 pipe_id = (entry->ring_id & 0x03) >> 0; 3339 queue_id = (entry->ring_id & 0x70) >> 4; 3340 3341 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3342 3343 if (xcc_id == -EINVAL) 3344 return; 3345 3346 switch (me_id) { 3347 case 0: 3348 case 1: 3349 case 2: 3350 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3351 ring = &adev->gfx.compute_ring 3352 [i + 3353 xcc_id * adev->gfx.num_compute_rings]; 3354 if (ring->me == me_id && ring->pipe == pipe_id && 3355 ring->queue == queue_id) 3356 drm_sched_fault(&ring->sched); 3357 } 3358 break; 3359 } 3360 } 3361 3362 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 3363 struct amdgpu_irq_src *source, 3364 struct amdgpu_iv_entry *entry) 3365 { 3366 DRM_ERROR("Illegal register access in command stream\n"); 3367 gfx_v9_4_3_fault(adev, entry); 3368 return 0; 3369 } 3370 3371 static int gfx_v9_4_3_bad_op_irq(struct amdgpu_device *adev, 3372 struct amdgpu_irq_src *source, 3373 struct amdgpu_iv_entry *entry) 3374 { 3375 DRM_ERROR("Illegal opcode in command stream\n"); 3376 gfx_v9_4_3_fault(adev, entry); 3377 return 0; 3378 } 3379 3380 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 3381 struct amdgpu_irq_src *source, 3382 struct amdgpu_iv_entry *entry) 3383 { 3384 DRM_ERROR("Illegal instruction in command stream\n"); 3385 gfx_v9_4_3_fault(adev, entry); 3386 return 0; 3387 } 3388 3389 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 3390 { 3391 const unsigned int cp_coher_cntl = 3392 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 3393 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 3394 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 3395 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 3396 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 3397 3398 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 3399 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 3400 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 3401 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3402 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 3403 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3404 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 3405 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 3406 } 3407 3408 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 3409 uint32_t pipe, bool enable) 3410 { 3411 struct amdgpu_device *adev = ring->adev; 3412 uint32_t val; 3413 uint32_t wcl_cs_reg; 3414 3415 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 3416 val = enable ? 0x1 : 0x7f; 3417 3418 switch (pipe) { 3419 case 0: 3420 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 3421 break; 3422 case 1: 3423 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 3424 break; 3425 case 2: 3426 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 3427 break; 3428 case 3: 3429 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 3430 break; 3431 default: 3432 DRM_DEBUG("invalid pipe %d\n", pipe); 3433 return; 3434 } 3435 3436 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 3437 3438 } 3439 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 3440 { 3441 struct amdgpu_device *adev = ring->adev; 3442 uint32_t val; 3443 int i; 3444 3445 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 3446 * number of gfx waves. Setting 5 bit will make sure gfx only gets 3447 * around 25% of gpu resources. 3448 */ 3449 val = enable ? 0x1f : 0x07ffffff; 3450 amdgpu_ring_emit_wreg(ring, 3451 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 3452 val); 3453 3454 /* Restrict waves for normal/low priority compute queues as well 3455 * to get best QoS for high priority compute jobs. 3456 * 3457 * amdgpu controls only 1st ME(0-3 CS pipes). 3458 */ 3459 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3460 if (i != ring->pipe) 3461 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3462 3463 } 3464 } 3465 3466 static int gfx_v9_4_3_unmap_done(struct amdgpu_device *adev, uint32_t me, 3467 uint32_t pipe, uint32_t queue, 3468 uint32_t xcc_id) 3469 { 3470 int i, r; 3471 /* make sure dequeue is complete*/ 3472 gfx_v9_4_3_xcc_set_safe_mode(adev, xcc_id); 3473 mutex_lock(&adev->srbm_mutex); 3474 soc15_grbm_select(adev, me, pipe, queue, 0, GET_INST(GC, xcc_id)); 3475 for (i = 0; i < adev->usec_timeout; i++) { 3476 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 3477 break; 3478 udelay(1); 3479 } 3480 if (i >= adev->usec_timeout) 3481 r = -ETIMEDOUT; 3482 else 3483 r = 0; 3484 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 3485 mutex_unlock(&adev->srbm_mutex); 3486 gfx_v9_4_3_xcc_unset_safe_mode(adev, xcc_id); 3487 3488 return r; 3489 3490 } 3491 3492 static bool gfx_v9_4_3_pipe_reset_support(struct amdgpu_device *adev) 3493 { 3494 /*TODO: Need check gfx9.4.4 mec fw whether supports pipe reset as well.*/ 3495 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && 3496 adev->gfx.mec_fw_version >= 0x0000009b) 3497 return true; 3498 else 3499 dev_warn_once(adev->dev, "Please use the latest MEC version to see whether support pipe reset\n"); 3500 3501 return false; 3502 } 3503 3504 static int gfx_v9_4_3_reset_hw_pipe(struct amdgpu_ring *ring) 3505 { 3506 struct amdgpu_device *adev = ring->adev; 3507 uint32_t reset_pipe, clean_pipe; 3508 int r; 3509 3510 if (!gfx_v9_4_3_pipe_reset_support(adev)) 3511 return -EINVAL; 3512 3513 gfx_v9_4_3_xcc_set_safe_mode(adev, ring->xcc_id); 3514 mutex_lock(&adev->srbm_mutex); 3515 3516 reset_pipe = RREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL); 3517 clean_pipe = reset_pipe; 3518 3519 if (ring->me == 1) { 3520 switch (ring->pipe) { 3521 case 0: 3522 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3523 MEC_ME1_PIPE0_RESET, 1); 3524 break; 3525 case 1: 3526 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3527 MEC_ME1_PIPE1_RESET, 1); 3528 break; 3529 case 2: 3530 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3531 MEC_ME1_PIPE2_RESET, 1); 3532 break; 3533 case 3: 3534 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3535 MEC_ME1_PIPE3_RESET, 1); 3536 break; 3537 default: 3538 break; 3539 } 3540 } else { 3541 if (ring->pipe) 3542 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3543 MEC_ME2_PIPE1_RESET, 1); 3544 else 3545 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3546 MEC_ME2_PIPE0_RESET, 1); 3547 } 3548 3549 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, reset_pipe); 3550 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, clean_pipe); 3551 mutex_unlock(&adev->srbm_mutex); 3552 gfx_v9_4_3_xcc_unset_safe_mode(adev, ring->xcc_id); 3553 3554 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3555 return r; 3556 } 3557 3558 static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, 3559 unsigned int vmid) 3560 { 3561 struct amdgpu_device *adev = ring->adev; 3562 struct amdgpu_kiq *kiq = &adev->gfx.kiq[ring->xcc_id]; 3563 struct amdgpu_ring *kiq_ring = &kiq->ring; 3564 unsigned long flags; 3565 int r; 3566 3567 if (amdgpu_sriov_vf(adev)) 3568 return -EINVAL; 3569 3570 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 3571 return -EINVAL; 3572 3573 spin_lock_irqsave(&kiq->ring_lock, flags); 3574 3575 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 3576 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3577 return -ENOMEM; 3578 } 3579 3580 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 3581 0, 0); 3582 amdgpu_ring_commit(kiq_ring); 3583 3584 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3585 3586 r = amdgpu_ring_test_ring(kiq_ring); 3587 if (r) { 3588 dev_err(adev->dev, "kiq ring test failed after ring: %s queue reset\n", 3589 ring->name); 3590 goto pipe_reset; 3591 } 3592 3593 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3594 if (r) 3595 dev_err(adev->dev, "fail to wait on hqd deactive and will try pipe reset\n"); 3596 3597 pipe_reset: 3598 if(r) { 3599 r = gfx_v9_4_3_reset_hw_pipe(ring); 3600 dev_info(adev->dev, "ring: %s pipe reset :%s\n", ring->name, 3601 r ? "failed" : "successfully"); 3602 if (r) 3603 return r; 3604 } 3605 3606 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3607 if (unlikely(r != 0)){ 3608 dev_err(adev->dev, "fail to resv mqd_obj\n"); 3609 return r; 3610 } 3611 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3612 if (!r) { 3613 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, ring->xcc_id, true); 3614 amdgpu_bo_kunmap(ring->mqd_obj); 3615 ring->mqd_ptr = NULL; 3616 } 3617 amdgpu_bo_unreserve(ring->mqd_obj); 3618 if (r) { 3619 dev_err(adev->dev, "fail to unresv mqd_obj\n"); 3620 return r; 3621 } 3622 spin_lock_irqsave(&kiq->ring_lock, flags); 3623 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 3624 if (r) { 3625 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3626 return -ENOMEM; 3627 } 3628 kiq->pmf->kiq_map_queues(kiq_ring, ring); 3629 amdgpu_ring_commit(kiq_ring); 3630 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3631 3632 r = amdgpu_ring_test_ring(kiq_ring); 3633 if (r) { 3634 dev_err(adev->dev, "fail to remap queue\n"); 3635 return r; 3636 } 3637 return amdgpu_ring_test_ring(ring); 3638 } 3639 3640 enum amdgpu_gfx_cp_ras_mem_id { 3641 AMDGPU_GFX_CP_MEM1 = 1, 3642 AMDGPU_GFX_CP_MEM2, 3643 AMDGPU_GFX_CP_MEM3, 3644 AMDGPU_GFX_CP_MEM4, 3645 AMDGPU_GFX_CP_MEM5, 3646 }; 3647 3648 enum amdgpu_gfx_gcea_ras_mem_id { 3649 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3650 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3651 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3652 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3653 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3654 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3655 AMDGPU_GFX_GCEA_MAM_DMEM0, 3656 AMDGPU_GFX_GCEA_MAM_DMEM1, 3657 AMDGPU_GFX_GCEA_MAM_DMEM2, 3658 AMDGPU_GFX_GCEA_MAM_DMEM3, 3659 AMDGPU_GFX_GCEA_MAM_AMEM0, 3660 AMDGPU_GFX_GCEA_MAM_AMEM1, 3661 AMDGPU_GFX_GCEA_MAM_AMEM2, 3662 AMDGPU_GFX_GCEA_MAM_AMEM3, 3663 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3664 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3665 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3666 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3667 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3668 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3669 }; 3670 3671 enum amdgpu_gfx_gc_cane_ras_mem_id { 3672 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3673 }; 3674 3675 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3676 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3677 }; 3678 3679 enum amdgpu_gfx_gds_ras_mem_id { 3680 AMDGPU_GFX_GDS_MEM0 = 0, 3681 }; 3682 3683 enum amdgpu_gfx_lds_ras_mem_id { 3684 AMDGPU_GFX_LDS_BANK0 = 0, 3685 AMDGPU_GFX_LDS_BANK1, 3686 AMDGPU_GFX_LDS_BANK2, 3687 AMDGPU_GFX_LDS_BANK3, 3688 AMDGPU_GFX_LDS_BANK4, 3689 AMDGPU_GFX_LDS_BANK5, 3690 AMDGPU_GFX_LDS_BANK6, 3691 AMDGPU_GFX_LDS_BANK7, 3692 AMDGPU_GFX_LDS_BANK8, 3693 AMDGPU_GFX_LDS_BANK9, 3694 AMDGPU_GFX_LDS_BANK10, 3695 AMDGPU_GFX_LDS_BANK11, 3696 AMDGPU_GFX_LDS_BANK12, 3697 AMDGPU_GFX_LDS_BANK13, 3698 AMDGPU_GFX_LDS_BANK14, 3699 AMDGPU_GFX_LDS_BANK15, 3700 AMDGPU_GFX_LDS_BANK16, 3701 AMDGPU_GFX_LDS_BANK17, 3702 AMDGPU_GFX_LDS_BANK18, 3703 AMDGPU_GFX_LDS_BANK19, 3704 AMDGPU_GFX_LDS_BANK20, 3705 AMDGPU_GFX_LDS_BANK21, 3706 AMDGPU_GFX_LDS_BANK22, 3707 AMDGPU_GFX_LDS_BANK23, 3708 AMDGPU_GFX_LDS_BANK24, 3709 AMDGPU_GFX_LDS_BANK25, 3710 AMDGPU_GFX_LDS_BANK26, 3711 AMDGPU_GFX_LDS_BANK27, 3712 AMDGPU_GFX_LDS_BANK28, 3713 AMDGPU_GFX_LDS_BANK29, 3714 AMDGPU_GFX_LDS_BANK30, 3715 AMDGPU_GFX_LDS_BANK31, 3716 AMDGPU_GFX_LDS_SP_BUFFER_A, 3717 AMDGPU_GFX_LDS_SP_BUFFER_B, 3718 }; 3719 3720 enum amdgpu_gfx_rlc_ras_mem_id { 3721 AMDGPU_GFX_RLC_GPMF32 = 1, 3722 AMDGPU_GFX_RLC_RLCVF32, 3723 AMDGPU_GFX_RLC_SCRATCH, 3724 AMDGPU_GFX_RLC_SRM_ARAM, 3725 AMDGPU_GFX_RLC_SRM_DRAM, 3726 AMDGPU_GFX_RLC_TCTAG, 3727 AMDGPU_GFX_RLC_SPM_SE, 3728 AMDGPU_GFX_RLC_SPM_GRBMT, 3729 }; 3730 3731 enum amdgpu_gfx_sp_ras_mem_id { 3732 AMDGPU_GFX_SP_SIMDID0 = 0, 3733 }; 3734 3735 enum amdgpu_gfx_spi_ras_mem_id { 3736 AMDGPU_GFX_SPI_MEM0 = 0, 3737 AMDGPU_GFX_SPI_MEM1, 3738 AMDGPU_GFX_SPI_MEM2, 3739 AMDGPU_GFX_SPI_MEM3, 3740 }; 3741 3742 enum amdgpu_gfx_sqc_ras_mem_id { 3743 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3744 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3745 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3746 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3747 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3748 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3749 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3750 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3751 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3752 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3753 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3754 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3755 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3756 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3757 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3758 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3759 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3760 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3761 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3762 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3763 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3764 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3765 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3766 }; 3767 3768 enum amdgpu_gfx_sq_ras_mem_id { 3769 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3770 AMDGPU_GFX_SQ_SGPR_MEM1, 3771 AMDGPU_GFX_SQ_SGPR_MEM2, 3772 AMDGPU_GFX_SQ_SGPR_MEM3, 3773 }; 3774 3775 enum amdgpu_gfx_ta_ras_mem_id { 3776 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3777 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3778 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3779 AMDGPU_GFX_TA_FSX_LFIFO, 3780 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3781 }; 3782 3783 enum amdgpu_gfx_tcc_ras_mem_id { 3784 AMDGPU_GFX_TCC_MEM1 = 1, 3785 }; 3786 3787 enum amdgpu_gfx_tca_ras_mem_id { 3788 AMDGPU_GFX_TCA_MEM1 = 1, 3789 }; 3790 3791 enum amdgpu_gfx_tci_ras_mem_id { 3792 AMDGPU_GFX_TCIW_MEM = 1, 3793 }; 3794 3795 enum amdgpu_gfx_tcp_ras_mem_id { 3796 AMDGPU_GFX_TCP_LFIFO0 = 1, 3797 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3798 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3799 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3800 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3801 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3802 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3803 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3804 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3805 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3806 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3807 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3808 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3809 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3810 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3811 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3812 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3813 AMDGPU_GFX_TCP_VM_FIFO, 3814 AMDGPU_GFX_TCP_DB_TAGRAM0, 3815 AMDGPU_GFX_TCP_DB_TAGRAM1, 3816 AMDGPU_GFX_TCP_DB_TAGRAM2, 3817 AMDGPU_GFX_TCP_DB_TAGRAM3, 3818 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3819 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3820 AMDGPU_GFX_TCP_CMD_FIFO, 3821 }; 3822 3823 enum amdgpu_gfx_td_ras_mem_id { 3824 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3825 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3826 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3827 }; 3828 3829 enum amdgpu_gfx_tcx_ras_mem_id { 3830 AMDGPU_GFX_TCX_FIFOD0 = 0, 3831 AMDGPU_GFX_TCX_FIFOD1, 3832 AMDGPU_GFX_TCX_FIFOD2, 3833 AMDGPU_GFX_TCX_FIFOD3, 3834 AMDGPU_GFX_TCX_FIFOD4, 3835 AMDGPU_GFX_TCX_FIFOD5, 3836 AMDGPU_GFX_TCX_FIFOD6, 3837 AMDGPU_GFX_TCX_FIFOD7, 3838 AMDGPU_GFX_TCX_FIFOB0, 3839 AMDGPU_GFX_TCX_FIFOB1, 3840 AMDGPU_GFX_TCX_FIFOB2, 3841 AMDGPU_GFX_TCX_FIFOB3, 3842 AMDGPU_GFX_TCX_FIFOB4, 3843 AMDGPU_GFX_TCX_FIFOB5, 3844 AMDGPU_GFX_TCX_FIFOB6, 3845 AMDGPU_GFX_TCX_FIFOB7, 3846 AMDGPU_GFX_TCX_FIFOA0, 3847 AMDGPU_GFX_TCX_FIFOA1, 3848 AMDGPU_GFX_TCX_FIFOA2, 3849 AMDGPU_GFX_TCX_FIFOA3, 3850 AMDGPU_GFX_TCX_FIFOA4, 3851 AMDGPU_GFX_TCX_FIFOA5, 3852 AMDGPU_GFX_TCX_FIFOA6, 3853 AMDGPU_GFX_TCX_FIFOA7, 3854 AMDGPU_GFX_TCX_CFIFO0, 3855 AMDGPU_GFX_TCX_CFIFO1, 3856 AMDGPU_GFX_TCX_CFIFO2, 3857 AMDGPU_GFX_TCX_CFIFO3, 3858 AMDGPU_GFX_TCX_CFIFO4, 3859 AMDGPU_GFX_TCX_CFIFO5, 3860 AMDGPU_GFX_TCX_CFIFO6, 3861 AMDGPU_GFX_TCX_CFIFO7, 3862 AMDGPU_GFX_TCX_FIFO_ACKB0, 3863 AMDGPU_GFX_TCX_FIFO_ACKB1, 3864 AMDGPU_GFX_TCX_FIFO_ACKB2, 3865 AMDGPU_GFX_TCX_FIFO_ACKB3, 3866 AMDGPU_GFX_TCX_FIFO_ACKB4, 3867 AMDGPU_GFX_TCX_FIFO_ACKB5, 3868 AMDGPU_GFX_TCX_FIFO_ACKB6, 3869 AMDGPU_GFX_TCX_FIFO_ACKB7, 3870 AMDGPU_GFX_TCX_FIFO_ACKD0, 3871 AMDGPU_GFX_TCX_FIFO_ACKD1, 3872 AMDGPU_GFX_TCX_FIFO_ACKD2, 3873 AMDGPU_GFX_TCX_FIFO_ACKD3, 3874 AMDGPU_GFX_TCX_FIFO_ACKD4, 3875 AMDGPU_GFX_TCX_FIFO_ACKD5, 3876 AMDGPU_GFX_TCX_FIFO_ACKD6, 3877 AMDGPU_GFX_TCX_FIFO_ACKD7, 3878 AMDGPU_GFX_TCX_DST_FIFOA0, 3879 AMDGPU_GFX_TCX_DST_FIFOA1, 3880 AMDGPU_GFX_TCX_DST_FIFOA2, 3881 AMDGPU_GFX_TCX_DST_FIFOA3, 3882 AMDGPU_GFX_TCX_DST_FIFOA4, 3883 AMDGPU_GFX_TCX_DST_FIFOA5, 3884 AMDGPU_GFX_TCX_DST_FIFOA6, 3885 AMDGPU_GFX_TCX_DST_FIFOA7, 3886 AMDGPU_GFX_TCX_DST_FIFOB0, 3887 AMDGPU_GFX_TCX_DST_FIFOB1, 3888 AMDGPU_GFX_TCX_DST_FIFOB2, 3889 AMDGPU_GFX_TCX_DST_FIFOB3, 3890 AMDGPU_GFX_TCX_DST_FIFOB4, 3891 AMDGPU_GFX_TCX_DST_FIFOB5, 3892 AMDGPU_GFX_TCX_DST_FIFOB6, 3893 AMDGPU_GFX_TCX_DST_FIFOB7, 3894 AMDGPU_GFX_TCX_DST_FIFOD0, 3895 AMDGPU_GFX_TCX_DST_FIFOD1, 3896 AMDGPU_GFX_TCX_DST_FIFOD2, 3897 AMDGPU_GFX_TCX_DST_FIFOD3, 3898 AMDGPU_GFX_TCX_DST_FIFOD4, 3899 AMDGPU_GFX_TCX_DST_FIFOD5, 3900 AMDGPU_GFX_TCX_DST_FIFOD6, 3901 AMDGPU_GFX_TCX_DST_FIFOD7, 3902 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 3903 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 3904 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 3905 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 3906 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 3907 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 3908 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 3909 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 3910 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 3911 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 3912 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 3913 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 3914 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 3915 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 3916 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 3917 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 3918 }; 3919 3920 enum amdgpu_gfx_atc_l2_ras_mem_id { 3921 AMDGPU_GFX_ATC_L2_MEM0 = 0, 3922 }; 3923 3924 enum amdgpu_gfx_utcl2_ras_mem_id { 3925 AMDGPU_GFX_UTCL2_MEM0 = 0, 3926 }; 3927 3928 enum amdgpu_gfx_vml2_ras_mem_id { 3929 AMDGPU_GFX_VML2_MEM0 = 0, 3930 }; 3931 3932 enum amdgpu_gfx_vml2_walker_ras_mem_id { 3933 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 3934 }; 3935 3936 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 3937 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 3938 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 3939 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 3940 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 3941 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 3942 }; 3943 3944 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 3945 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 3946 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 3947 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 3948 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 3949 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 3950 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 3951 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 3952 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 3953 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 3954 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 3955 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 3956 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 3957 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 3958 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 3959 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 3960 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 3961 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 3962 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 3963 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 3964 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 3965 }; 3966 3967 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 3968 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 3969 }; 3970 3971 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 3972 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 3973 }; 3974 3975 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 3976 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 3977 }; 3978 3979 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 3980 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 3981 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 3982 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 3983 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 3984 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 3985 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 3986 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 3987 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 3988 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 3989 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 3990 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 3991 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 3992 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 3993 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 3994 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 3995 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 3996 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 3997 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 3998 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 3999 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 4000 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 4001 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 4002 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 4003 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 4004 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 4005 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 4006 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 4007 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 4008 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 4009 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 4010 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 4011 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 4012 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 4013 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 4014 }; 4015 4016 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 4017 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 4018 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 4019 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 4020 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 4021 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 4022 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 4023 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 4024 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 4025 }; 4026 4027 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 4028 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 4029 }; 4030 4031 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 4032 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 4033 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 4034 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 4035 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 4036 }; 4037 4038 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 4039 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 4040 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 4041 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 4042 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 4043 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 4044 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 4045 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 4046 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 4047 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 4048 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 4049 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 4050 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 4051 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 4052 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 4053 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 4054 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 4055 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 4056 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 4057 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 4058 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 4059 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 4060 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 4061 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 4062 }; 4063 4064 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 4065 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 4066 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 4067 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 4068 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 4069 }; 4070 4071 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 4072 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 4073 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 4074 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 4075 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 4076 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 4077 }; 4078 4079 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 4080 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 4081 }; 4082 4083 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 4084 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 4085 }; 4086 4087 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 4088 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 4089 }; 4090 4091 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 4092 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 4093 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 4094 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 4095 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 4096 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 4097 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 4098 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 4099 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 4100 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 4101 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 4102 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 4103 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 4104 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 4105 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 4106 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 4107 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 4108 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 4109 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 4110 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 4111 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 4112 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 4113 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 4114 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 4115 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 4116 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 4117 }; 4118 4119 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 4120 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 4121 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 4122 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 4123 }; 4124 4125 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 4126 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 4127 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 4128 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 4129 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 4130 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 4131 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 4132 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 4133 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 4134 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 4135 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 4136 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 4137 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 4138 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 4139 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 4140 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 4141 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 4142 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 4143 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 4144 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 4145 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 4146 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 4147 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 4148 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 4149 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 4150 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 4151 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 4152 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 4153 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 4154 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 4155 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 4156 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 4157 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 4158 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 4159 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 4160 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 4161 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 4162 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 4163 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 4164 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 4165 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 4166 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 4167 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 4168 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 4169 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 4170 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 4171 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 4172 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 4173 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 4174 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 4175 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 4176 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 4177 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 4178 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 4179 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 4180 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 4181 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 4182 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 4183 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 4184 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 4185 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 4186 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 4187 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 4188 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 4189 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 4190 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 4191 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 4192 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 4193 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 4194 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 4195 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 4196 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 4197 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 4198 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 4199 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 4200 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 4201 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 4202 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 4203 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 4204 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 4205 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 4206 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 4207 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 4208 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 4209 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 4210 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 4211 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 4212 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 4213 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 4214 }; 4215 4216 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 4217 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 4218 }; 4219 4220 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 4221 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 4222 }; 4223 4224 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 4225 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 4226 }; 4227 4228 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 4229 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 4230 }; 4231 4232 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 4233 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 4234 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 4235 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 4236 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 4237 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 4238 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 4239 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 4240 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 4241 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 4242 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 4243 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 4244 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 4245 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 4246 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 4247 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 4248 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 4249 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 4250 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 4251 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 4252 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 4253 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 4254 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 4255 }; 4256 4257 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 4258 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 4259 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4260 AMDGPU_GFX_RLC_MEM, 1}, 4261 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 4262 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4263 AMDGPU_GFX_CP_MEM, 1}, 4264 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 4265 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4266 AMDGPU_GFX_CP_MEM, 1}, 4267 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 4268 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4269 AMDGPU_GFX_CP_MEM, 1}, 4270 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 4271 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4272 AMDGPU_GFX_GDS_MEM, 1}, 4273 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 4274 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4275 AMDGPU_GFX_GC_CANE_MEM, 1}, 4276 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 4277 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4278 AMDGPU_GFX_SPI_MEM, 1}, 4279 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 4280 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4281 AMDGPU_GFX_SP_MEM, 4}, 4282 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 4283 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4284 AMDGPU_GFX_SP_MEM, 4}, 4285 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 4286 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4287 AMDGPU_GFX_SQ_MEM, 4}, 4288 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 4289 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4290 AMDGPU_GFX_SQC_MEM, 4}, 4291 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 4292 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4293 AMDGPU_GFX_TCX_MEM, 1}, 4294 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 4295 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4296 AMDGPU_GFX_TCC_MEM, 1}, 4297 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 4298 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4299 AMDGPU_GFX_TA_MEM, 4}, 4300 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 4301 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4302 AMDGPU_GFX_TCI_MEM, 1}, 4303 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 4304 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4305 AMDGPU_GFX_TCP_MEM, 4}, 4306 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 4307 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4308 AMDGPU_GFX_TD_MEM, 4}, 4309 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 4310 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4311 AMDGPU_GFX_GCEA_MEM, 1}, 4312 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 4313 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4314 AMDGPU_GFX_LDS_MEM, 4}, 4315 }; 4316 4317 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 4318 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 4319 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4320 AMDGPU_GFX_RLC_MEM, 1}, 4321 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 4322 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4323 AMDGPU_GFX_CP_MEM, 1}, 4324 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 4325 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4326 AMDGPU_GFX_CP_MEM, 1}, 4327 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 4328 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4329 AMDGPU_GFX_CP_MEM, 1}, 4330 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 4331 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4332 AMDGPU_GFX_GDS_MEM, 1}, 4333 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 4334 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4335 AMDGPU_GFX_GC_CANE_MEM, 1}, 4336 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 4337 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4338 AMDGPU_GFX_SPI_MEM, 1}, 4339 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 4340 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4341 AMDGPU_GFX_SP_MEM, 4}, 4342 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 4343 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4344 AMDGPU_GFX_SP_MEM, 4}, 4345 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 4346 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4347 AMDGPU_GFX_SQ_MEM, 4}, 4348 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 4349 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4350 AMDGPU_GFX_SQC_MEM, 4}, 4351 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 4352 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4353 AMDGPU_GFX_TCX_MEM, 1}, 4354 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 4355 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4356 AMDGPU_GFX_TCC_MEM, 1}, 4357 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 4358 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4359 AMDGPU_GFX_TA_MEM, 4}, 4360 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 4361 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4362 AMDGPU_GFX_TCI_MEM, 1}, 4363 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 4364 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4365 AMDGPU_GFX_TCP_MEM, 4}, 4366 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 4367 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4368 AMDGPU_GFX_TD_MEM, 4}, 4369 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 4370 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 4371 AMDGPU_GFX_TCA_MEM, 1}, 4372 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 4373 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4374 AMDGPU_GFX_GCEA_MEM, 1}, 4375 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 4376 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4377 AMDGPU_GFX_LDS_MEM, 4}, 4378 }; 4379 4380 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 4381 void *ras_error_status, int xcc_id) 4382 { 4383 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 4384 unsigned long ce_count = 0, ue_count = 0; 4385 uint32_t i, j, k; 4386 4387 /* NOTE: convert xcc_id to physical XCD ID (XCD0 or XCD1) */ 4388 struct amdgpu_smuio_mcm_config_info mcm_info = { 4389 .socket_id = adev->smuio.funcs->get_socket_id(adev), 4390 .die_id = xcc_id & 0x01 ? 1 : 0, 4391 }; 4392 4393 mutex_lock(&adev->grbm_idx_mutex); 4394 4395 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4396 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4397 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4398 /* no need to select if instance number is 1 */ 4399 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4400 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4401 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4402 4403 amdgpu_ras_inst_query_ras_error_count(adev, 4404 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4405 1, 4406 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 4407 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 4408 GET_INST(GC, xcc_id), 4409 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 4410 &ce_count); 4411 4412 amdgpu_ras_inst_query_ras_error_count(adev, 4413 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4414 1, 4415 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4416 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4417 GET_INST(GC, xcc_id), 4418 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4419 &ue_count); 4420 } 4421 } 4422 } 4423 4424 /* handle extra register entries of UE */ 4425 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4426 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4427 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4428 /* no need to select if instance number is 1 */ 4429 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4430 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4431 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4432 4433 amdgpu_ras_inst_query_ras_error_count(adev, 4434 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4435 1, 4436 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4437 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4438 GET_INST(GC, xcc_id), 4439 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4440 &ue_count); 4441 } 4442 } 4443 } 4444 4445 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4446 xcc_id); 4447 mutex_unlock(&adev->grbm_idx_mutex); 4448 4449 /* the caller should make sure initialize value of 4450 * err_data->ue_count and err_data->ce_count 4451 */ 4452 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 4453 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, ce_count); 4454 } 4455 4456 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 4457 void *ras_error_status, int xcc_id) 4458 { 4459 uint32_t i, j, k; 4460 4461 mutex_lock(&adev->grbm_idx_mutex); 4462 4463 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4464 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4465 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4466 /* no need to select if instance number is 1 */ 4467 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4468 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4469 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4470 4471 amdgpu_ras_inst_reset_ras_error_count(adev, 4472 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4473 1, 4474 GET_INST(GC, xcc_id)); 4475 4476 amdgpu_ras_inst_reset_ras_error_count(adev, 4477 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4478 1, 4479 GET_INST(GC, xcc_id)); 4480 } 4481 } 4482 } 4483 4484 /* handle extra register entries of UE */ 4485 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4486 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4487 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4488 /* no need to select if instance number is 1 */ 4489 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4490 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4491 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4492 4493 amdgpu_ras_inst_reset_ras_error_count(adev, 4494 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4495 1, 4496 GET_INST(GC, xcc_id)); 4497 } 4498 } 4499 } 4500 4501 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4502 xcc_id); 4503 mutex_unlock(&adev->grbm_idx_mutex); 4504 } 4505 4506 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 4507 void *ras_error_status, int xcc_id) 4508 { 4509 uint32_t i; 4510 uint32_t data; 4511 4512 if (amdgpu_sriov_vf(adev)) 4513 return; 4514 4515 data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG); 4516 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 4517 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 4518 4519 if (amdgpu_watchdog_timer.timeout_fatal_disable && 4520 (amdgpu_watchdog_timer.period < 1 || 4521 amdgpu_watchdog_timer.period > 0x23)) { 4522 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 4523 amdgpu_watchdog_timer.period = 0x23; 4524 } 4525 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 4526 amdgpu_watchdog_timer.period); 4527 4528 mutex_lock(&adev->grbm_idx_mutex); 4529 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4530 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 4531 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 4532 } 4533 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4534 xcc_id); 4535 mutex_unlock(&adev->grbm_idx_mutex); 4536 } 4537 4538 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 4539 void *ras_error_status) 4540 { 4541 amdgpu_gfx_ras_error_func(adev, ras_error_status, 4542 gfx_v9_4_3_inst_query_ras_err_count); 4543 } 4544 4545 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 4546 { 4547 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 4548 } 4549 4550 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 4551 { 4552 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 4553 } 4554 4555 static void gfx_v9_4_3_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 4556 { 4557 /* Header itself is a NOP packet */ 4558 if (num_nop == 1) { 4559 amdgpu_ring_write(ring, ring->funcs->nop); 4560 return; 4561 } 4562 4563 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 4564 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 4565 4566 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 4567 amdgpu_ring_insert_nop(ring, num_nop - 1); 4568 } 4569 4570 static void gfx_v9_4_3_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 4571 { 4572 struct amdgpu_device *adev = ip_block->adev; 4573 uint32_t i, j, k; 4574 uint32_t xcc_id, xcc_offset, inst_offset; 4575 uint32_t num_xcc, reg, num_inst; 4576 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4577 4578 if (!adev->gfx.ip_dump_core) 4579 return; 4580 4581 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4582 drm_printf(p, "Number of Instances:%d\n", num_xcc); 4583 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4584 xcc_offset = xcc_id * reg_count; 4585 drm_printf(p, "\nInstance id:%d\n", xcc_id); 4586 for (i = 0; i < reg_count; i++) 4587 drm_printf(p, "%-50s \t 0x%08x\n", 4588 gc_reg_list_9_4_3[i].reg_name, 4589 adev->gfx.ip_dump_core[xcc_offset + i]); 4590 } 4591 4592 /* print compute queue registers for all instances */ 4593 if (!adev->gfx.ip_dump_compute_queues) 4594 return; 4595 4596 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4597 adev->gfx.mec.num_queue_per_pipe; 4598 4599 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4600 drm_printf(p, "\nnum_xcc: %d num_mec: %d num_pipe: %d num_queue: %d\n", 4601 num_xcc, 4602 adev->gfx.mec.num_mec, 4603 adev->gfx.mec.num_pipe_per_mec, 4604 adev->gfx.mec.num_queue_per_pipe); 4605 4606 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4607 xcc_offset = xcc_id * reg_count * num_inst; 4608 inst_offset = 0; 4609 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4610 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4611 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4612 drm_printf(p, 4613 "\nxcc:%d mec:%d, pipe:%d, queue:%d\n", 4614 xcc_id, i, j, k); 4615 for (reg = 0; reg < reg_count; reg++) { 4616 drm_printf(p, 4617 "%-50s \t 0x%08x\n", 4618 gc_cp_reg_list_9_4_3[reg].reg_name, 4619 adev->gfx.ip_dump_compute_queues 4620 [xcc_offset + inst_offset + 4621 reg]); 4622 } 4623 inst_offset += reg_count; 4624 } 4625 } 4626 } 4627 } 4628 } 4629 4630 static void gfx_v9_4_3_ip_dump(struct amdgpu_ip_block *ip_block) 4631 { 4632 struct amdgpu_device *adev = ip_block->adev; 4633 uint32_t i, j, k; 4634 uint32_t num_xcc, reg, num_inst; 4635 uint32_t xcc_id, xcc_offset, inst_offset; 4636 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4637 4638 if (!adev->gfx.ip_dump_core) 4639 return; 4640 4641 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4642 4643 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4644 xcc_offset = xcc_id * reg_count; 4645 for (i = 0; i < reg_count; i++) 4646 adev->gfx.ip_dump_core[xcc_offset + i] = 4647 RREG32(SOC15_REG_ENTRY_OFFSET_INST(gc_reg_list_9_4_3[i], 4648 GET_INST(GC, xcc_id))); 4649 } 4650 4651 /* dump compute queue registers for all instances */ 4652 if (!adev->gfx.ip_dump_compute_queues) 4653 return; 4654 4655 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4656 adev->gfx.mec.num_queue_per_pipe; 4657 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4658 mutex_lock(&adev->srbm_mutex); 4659 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4660 xcc_offset = xcc_id * reg_count * num_inst; 4661 inst_offset = 0; 4662 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4663 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4664 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4665 /* ME0 is for GFX so start from 1 for CP */ 4666 soc15_grbm_select(adev, 1 + i, j, k, 0, 4667 GET_INST(GC, xcc_id)); 4668 4669 for (reg = 0; reg < reg_count; reg++) { 4670 adev->gfx.ip_dump_compute_queues 4671 [xcc_offset + 4672 inst_offset + reg] = 4673 RREG32(SOC15_REG_ENTRY_OFFSET_INST( 4674 gc_cp_reg_list_9_4_3[reg], 4675 GET_INST(GC, xcc_id))); 4676 } 4677 inst_offset += reg_count; 4678 } 4679 } 4680 } 4681 } 4682 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 4683 mutex_unlock(&adev->srbm_mutex); 4684 } 4685 4686 static void gfx_v9_4_3_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 4687 { 4688 /* Emit the cleaner shader */ 4689 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 4690 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 4691 } 4692 4693 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 4694 .name = "gfx_v9_4_3", 4695 .early_init = gfx_v9_4_3_early_init, 4696 .late_init = gfx_v9_4_3_late_init, 4697 .sw_init = gfx_v9_4_3_sw_init, 4698 .sw_fini = gfx_v9_4_3_sw_fini, 4699 .hw_init = gfx_v9_4_3_hw_init, 4700 .hw_fini = gfx_v9_4_3_hw_fini, 4701 .suspend = gfx_v9_4_3_suspend, 4702 .resume = gfx_v9_4_3_resume, 4703 .is_idle = gfx_v9_4_3_is_idle, 4704 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4705 .soft_reset = gfx_v9_4_3_soft_reset, 4706 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4707 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4708 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4709 .dump_ip_state = gfx_v9_4_3_ip_dump, 4710 .print_ip_state = gfx_v9_4_3_ip_print, 4711 }; 4712 4713 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4714 .type = AMDGPU_RING_TYPE_COMPUTE, 4715 .align_mask = 0xff, 4716 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4717 .support_64bit_ptrs = true, 4718 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4719 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4720 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4721 .emit_frame_size = 4722 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4723 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4724 5 + /* hdp invalidate */ 4725 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4726 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4727 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4728 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4729 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4730 7 + /* gfx_v9_4_3_emit_mem_sync */ 4731 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4732 15 + /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4733 2, /* gfx_v9_4_3_ring_emit_cleaner_shader */ 4734 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4735 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4736 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4737 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4738 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4739 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4740 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4741 .test_ring = gfx_v9_4_3_ring_test_ring, 4742 .test_ib = gfx_v9_4_3_ring_test_ib, 4743 .insert_nop = gfx_v9_4_3_ring_insert_nop, 4744 .pad_ib = amdgpu_ring_generic_pad_ib, 4745 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4746 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4747 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4748 .soft_recovery = gfx_v9_4_3_ring_soft_recovery, 4749 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4750 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4751 .reset = gfx_v9_4_3_reset_kcq, 4752 .emit_cleaner_shader = gfx_v9_4_3_ring_emit_cleaner_shader, 4753 .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, 4754 .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, 4755 }; 4756 4757 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4758 .type = AMDGPU_RING_TYPE_KIQ, 4759 .align_mask = 0xff, 4760 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4761 .support_64bit_ptrs = true, 4762 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4763 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4764 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4765 .emit_frame_size = 4766 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4767 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4768 5 + /* hdp invalidate */ 4769 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4770 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4771 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4772 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4773 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4774 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4775 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4776 .test_ring = gfx_v9_4_3_ring_test_ring, 4777 .insert_nop = amdgpu_ring_insert_nop, 4778 .pad_ib = amdgpu_ring_generic_pad_ib, 4779 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4780 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4781 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4782 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4783 }; 4784 4785 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4786 { 4787 int i, j, num_xcc; 4788 4789 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4790 for (i = 0; i < num_xcc; i++) { 4791 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4792 4793 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4794 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4795 = &gfx_v9_4_3_ring_funcs_compute; 4796 } 4797 } 4798 4799 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4800 .set = gfx_v9_4_3_set_eop_interrupt_state, 4801 .process = gfx_v9_4_3_eop_irq, 4802 }; 4803 4804 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4805 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4806 .process = gfx_v9_4_3_priv_reg_irq, 4807 }; 4808 4809 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_bad_op_irq_funcs = { 4810 .set = gfx_v9_4_3_set_bad_op_fault_state, 4811 .process = gfx_v9_4_3_bad_op_irq, 4812 }; 4813 4814 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4815 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4816 .process = gfx_v9_4_3_priv_inst_irq, 4817 }; 4818 4819 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4820 { 4821 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4822 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4823 4824 adev->gfx.priv_reg_irq.num_types = 1; 4825 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4826 4827 adev->gfx.bad_op_irq.num_types = 1; 4828 adev->gfx.bad_op_irq.funcs = &gfx_v9_4_3_bad_op_irq_funcs; 4829 4830 adev->gfx.priv_inst_irq.num_types = 1; 4831 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4832 } 4833 4834 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4835 { 4836 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4837 } 4838 4839 4840 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4841 { 4842 /* 9.4.3 variants removed all the GDS internal memory, 4843 * only support GWS opcode in kernel, like barrier 4844 * semaphore.etc */ 4845 4846 /* init asic gds info */ 4847 adev->gds.gds_size = 0; 4848 adev->gds.gds_compute_max_wave_id = 0; 4849 adev->gds.gws_size = 64; 4850 adev->gds.oa_size = 16; 4851 } 4852 4853 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4854 u32 bitmap, int xcc_id) 4855 { 4856 u32 data; 4857 4858 if (!bitmap) 4859 return; 4860 4861 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4862 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4863 4864 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); 4865 } 4866 4867 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id) 4868 { 4869 u32 data, mask; 4870 4871 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); 4872 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); 4873 4874 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4875 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4876 4877 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4878 4879 return (~data) & mask; 4880 } 4881 4882 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4883 struct amdgpu_cu_info *cu_info) 4884 { 4885 int i, j, k, prev_counter, counter, xcc_id, active_cu_number = 0; 4886 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp; 4887 unsigned disable_masks[4 * 4]; 4888 bool is_symmetric_cus; 4889 4890 if (!adev || !cu_info) 4891 return -EINVAL; 4892 4893 /* 4894 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4895 */ 4896 if (adev->gfx.config.max_shader_engines * 4897 adev->gfx.config.max_sh_per_se > 16) 4898 return -EINVAL; 4899 4900 amdgpu_gfx_parse_disable_cu(disable_masks, 4901 adev->gfx.config.max_shader_engines, 4902 adev->gfx.config.max_sh_per_se); 4903 4904 mutex_lock(&adev->grbm_idx_mutex); 4905 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 4906 is_symmetric_cus = true; 4907 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4908 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4909 mask = 1; 4910 ao_bitmap = 0; 4911 counter = 0; 4912 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 4913 gfx_v9_4_3_set_user_cu_inactive_bitmap( 4914 adev, 4915 disable_masks[i * adev->gfx.config.max_sh_per_se + j], 4916 xcc_id); 4917 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id); 4918 4919 cu_info->bitmap[xcc_id][i][j] = bitmap; 4920 4921 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4922 if (bitmap & mask) { 4923 if (counter < adev->gfx.config.max_cu_per_sh) 4924 ao_bitmap |= mask; 4925 counter++; 4926 } 4927 mask <<= 1; 4928 } 4929 active_cu_number += counter; 4930 if (i < 2 && j < 2) 4931 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4932 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 4933 } 4934 if (i && is_symmetric_cus && prev_counter != counter) 4935 is_symmetric_cus = false; 4936 prev_counter = counter; 4937 } 4938 if (is_symmetric_cus) { 4939 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG); 4940 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1); 4941 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1); 4942 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp); 4943 } 4944 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4945 xcc_id); 4946 } 4947 mutex_unlock(&adev->grbm_idx_mutex); 4948 4949 cu_info->number = active_cu_number; 4950 cu_info->ao_cu_mask = ao_cu_mask; 4951 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4952 4953 return 0; 4954 } 4955 4956 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 4957 .type = AMD_IP_BLOCK_TYPE_GFX, 4958 .major = 9, 4959 .minor = 4, 4960 .rev = 3, 4961 .funcs = &gfx_v9_4_3_ip_funcs, 4962 }; 4963 4964 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 4965 { 4966 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4967 uint32_t tmp_mask; 4968 int i, r; 4969 4970 /* TODO : Initialize golden regs */ 4971 /* gfx_v9_4_3_init_golden_registers(adev); */ 4972 4973 tmp_mask = inst_mask; 4974 for_each_inst(i, tmp_mask) 4975 gfx_v9_4_3_xcc_constants_init(adev, i); 4976 4977 if (!amdgpu_sriov_vf(adev)) { 4978 tmp_mask = inst_mask; 4979 for_each_inst(i, tmp_mask) { 4980 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 4981 if (r) 4982 return r; 4983 } 4984 } 4985 4986 tmp_mask = inst_mask; 4987 for_each_inst(i, tmp_mask) { 4988 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 4989 if (r) 4990 return r; 4991 } 4992 4993 return 0; 4994 } 4995 4996 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 4997 { 4998 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4999 int i; 5000 5001 for_each_inst(i, inst_mask) 5002 gfx_v9_4_3_xcc_fini(adev, i); 5003 5004 return 0; 5005 } 5006 5007 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 5008 .suspend = &gfx_v9_4_3_xcp_suspend, 5009 .resume = &gfx_v9_4_3_xcp_resume 5010 }; 5011 5012 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 5013 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 5014 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 5015 }; 5016 5017 static int gfx_v9_4_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 5018 { 5019 int r; 5020 5021 r = amdgpu_ras_block_late_init(adev, ras_block); 5022 if (r) 5023 return r; 5024 5025 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__GFX, 5026 &gfx_v9_4_3_aca_info, 5027 NULL); 5028 if (r) 5029 goto late_fini; 5030 5031 return 0; 5032 5033 late_fini: 5034 amdgpu_ras_block_late_fini(adev, ras_block); 5035 5036 return r; 5037 } 5038 5039 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 5040 .ras_block = { 5041 .hw_ops = &gfx_v9_4_3_ras_ops, 5042 .ras_late_init = &gfx_v9_4_3_ras_late_init, 5043 }, 5044 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 5045 }; 5046