1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "amdgpu_xcp.h" 41 42 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 44 45 #define GFX9_MEC_HPD_SIZE 4096 46 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 47 48 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 49 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301 50 51 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 52 53 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 54 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 55 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 56 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 57 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 58 struct amdgpu_cu_info *cu_info); 59 60 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 61 uint64_t queue_mask) 62 { 63 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 64 amdgpu_ring_write(kiq_ring, 65 PACKET3_SET_RESOURCES_VMID_MASK(0) | 66 /* vmid_mask:0* queue_type:0 (KIQ) */ 67 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 68 amdgpu_ring_write(kiq_ring, 69 lower_32_bits(queue_mask)); /* queue mask lo */ 70 amdgpu_ring_write(kiq_ring, 71 upper_32_bits(queue_mask)); /* queue mask hi */ 72 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 73 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 74 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 75 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 76 } 77 78 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 79 struct amdgpu_ring *ring) 80 { 81 struct amdgpu_device *adev = kiq_ring->adev; 82 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 83 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 84 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 85 86 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 87 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 88 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 89 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 90 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 91 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 92 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 93 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 94 /*queue_type: normal compute queue */ 95 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 96 /* alloc format: all_on_one_pipe */ 97 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 98 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 99 /* num_queues: must be 1 */ 100 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 101 amdgpu_ring_write(kiq_ring, 102 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 103 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 104 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 105 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 106 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 107 } 108 109 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 110 struct amdgpu_ring *ring, 111 enum amdgpu_unmap_queues_action action, 112 u64 gpu_addr, u64 seq) 113 { 114 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 115 116 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 117 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 118 PACKET3_UNMAP_QUEUES_ACTION(action) | 119 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 120 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 121 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 122 amdgpu_ring_write(kiq_ring, 123 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 124 125 if (action == PREEMPT_QUEUES_NO_UNMAP) { 126 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 127 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 128 amdgpu_ring_write(kiq_ring, seq); 129 } else { 130 amdgpu_ring_write(kiq_ring, 0); 131 amdgpu_ring_write(kiq_ring, 0); 132 amdgpu_ring_write(kiq_ring, 0); 133 } 134 } 135 136 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 137 struct amdgpu_ring *ring, 138 u64 addr, 139 u64 seq) 140 { 141 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 142 143 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 144 amdgpu_ring_write(kiq_ring, 145 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 146 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 147 PACKET3_QUERY_STATUS_COMMAND(2)); 148 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 149 amdgpu_ring_write(kiq_ring, 150 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 151 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 152 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 153 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 154 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 155 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 156 } 157 158 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 159 uint16_t pasid, uint32_t flush_type, 160 bool all_hub) 161 { 162 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 163 amdgpu_ring_write(kiq_ring, 164 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 165 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 166 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 167 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 168 } 169 170 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 171 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 172 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 173 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 174 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 175 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 176 .set_resources_size = 8, 177 .map_queues_size = 7, 178 .unmap_queues_size = 6, 179 .query_status_size = 7, 180 .invalidate_tlbs_size = 2, 181 }; 182 183 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 184 { 185 int i, num_xcc; 186 187 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 188 for (i = 0; i < num_xcc; i++) 189 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 190 } 191 192 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 193 { 194 int i, num_xcc, dev_inst; 195 196 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 197 for (i = 0; i < num_xcc; i++) { 198 dev_inst = GET_INST(GC, i); 199 200 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 201 GOLDEN_GB_ADDR_CONFIG); 202 /* Golden settings applied by driver for ASIC with rev_id 0 */ 203 if (adev->rev_id == 0) { 204 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1, 205 REDUCE_FIFO_DEPTH_BY_2, 2); 206 } else { 207 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, 208 SPARE, 0x1); 209 } 210 } 211 } 212 213 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 214 bool wc, uint32_t reg, uint32_t val) 215 { 216 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 217 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 218 WRITE_DATA_DST_SEL(0) | 219 (wc ? WR_CONFIRM : 0)); 220 amdgpu_ring_write(ring, reg); 221 amdgpu_ring_write(ring, 0); 222 amdgpu_ring_write(ring, val); 223 } 224 225 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 226 int mem_space, int opt, uint32_t addr0, 227 uint32_t addr1, uint32_t ref, uint32_t mask, 228 uint32_t inv) 229 { 230 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 231 amdgpu_ring_write(ring, 232 /* memory (1) or register (0) */ 233 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 234 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 235 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 236 WAIT_REG_MEM_ENGINE(eng_sel))); 237 238 if (mem_space) 239 BUG_ON(addr0 & 0x3); /* Dword align */ 240 amdgpu_ring_write(ring, addr0); 241 amdgpu_ring_write(ring, addr1); 242 amdgpu_ring_write(ring, ref); 243 amdgpu_ring_write(ring, mask); 244 amdgpu_ring_write(ring, inv); /* poll interval */ 245 } 246 247 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 248 { 249 uint32_t scratch_reg0_offset, xcc_offset; 250 struct amdgpu_device *adev = ring->adev; 251 uint32_t tmp = 0; 252 unsigned i; 253 int r; 254 255 /* Use register offset which is local to XCC in the packet */ 256 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 257 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 258 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 259 260 r = amdgpu_ring_alloc(ring, 3); 261 if (r) 262 return r; 263 264 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 265 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 266 amdgpu_ring_write(ring, 0xDEADBEEF); 267 amdgpu_ring_commit(ring); 268 269 for (i = 0; i < adev->usec_timeout; i++) { 270 tmp = RREG32(scratch_reg0_offset); 271 if (tmp == 0xDEADBEEF) 272 break; 273 udelay(1); 274 } 275 276 if (i >= adev->usec_timeout) 277 r = -ETIMEDOUT; 278 return r; 279 } 280 281 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 282 { 283 struct amdgpu_device *adev = ring->adev; 284 struct amdgpu_ib ib; 285 struct dma_fence *f = NULL; 286 287 unsigned index; 288 uint64_t gpu_addr; 289 uint32_t tmp; 290 long r; 291 292 r = amdgpu_device_wb_get(adev, &index); 293 if (r) 294 return r; 295 296 gpu_addr = adev->wb.gpu_addr + (index * 4); 297 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 298 memset(&ib, 0, sizeof(ib)); 299 r = amdgpu_ib_get(adev, NULL, 16, 300 AMDGPU_IB_POOL_DIRECT, &ib); 301 if (r) 302 goto err1; 303 304 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 305 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 306 ib.ptr[2] = lower_32_bits(gpu_addr); 307 ib.ptr[3] = upper_32_bits(gpu_addr); 308 ib.ptr[4] = 0xDEADBEEF; 309 ib.length_dw = 5; 310 311 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 312 if (r) 313 goto err2; 314 315 r = dma_fence_wait_timeout(f, false, timeout); 316 if (r == 0) { 317 r = -ETIMEDOUT; 318 goto err2; 319 } else if (r < 0) { 320 goto err2; 321 } 322 323 tmp = adev->wb.wb[index]; 324 if (tmp == 0xDEADBEEF) 325 r = 0; 326 else 327 r = -EINVAL; 328 329 err2: 330 amdgpu_ib_free(adev, &ib, NULL); 331 dma_fence_put(f); 332 err1: 333 amdgpu_device_wb_free(adev, index); 334 return r; 335 } 336 337 338 /* This value might differs per partition */ 339 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 340 { 341 uint64_t clock; 342 343 mutex_lock(&adev->gfx.gpu_clock_mutex); 344 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 345 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 346 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 347 mutex_unlock(&adev->gfx.gpu_clock_mutex); 348 349 return clock; 350 } 351 352 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 353 { 354 amdgpu_ucode_release(&adev->gfx.pfp_fw); 355 amdgpu_ucode_release(&adev->gfx.me_fw); 356 amdgpu_ucode_release(&adev->gfx.ce_fw); 357 amdgpu_ucode_release(&adev->gfx.rlc_fw); 358 amdgpu_ucode_release(&adev->gfx.mec_fw); 359 amdgpu_ucode_release(&adev->gfx.mec2_fw); 360 361 kfree(adev->gfx.rlc.register_list_format); 362 } 363 364 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 365 const char *chip_name) 366 { 367 char fw_name[30]; 368 int err; 369 const struct rlc_firmware_header_v2_0 *rlc_hdr; 370 uint16_t version_major; 371 uint16_t version_minor; 372 373 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 374 375 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 376 if (err) 377 goto out; 378 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 379 380 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 381 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 382 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 383 out: 384 if (err) 385 amdgpu_ucode_release(&adev->gfx.rlc_fw); 386 387 return err; 388 } 389 390 static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev) 391 { 392 return true; 393 } 394 395 static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev) 396 { 397 if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev)) 398 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 399 } 400 401 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 402 const char *chip_name) 403 { 404 char fw_name[30]; 405 int err; 406 407 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 408 409 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 410 if (err) 411 goto out; 412 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 413 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 414 415 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 416 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 417 418 gfx_v9_4_3_check_if_need_gfxoff(adev); 419 420 out: 421 if (err) 422 amdgpu_ucode_release(&adev->gfx.mec_fw); 423 return err; 424 } 425 426 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 427 { 428 const char *chip_name; 429 int r; 430 431 chip_name = "gc_9_4_3"; 432 433 r = gfx_v9_4_3_init_rlc_microcode(adev, chip_name); 434 if (r) 435 return r; 436 437 r = gfx_v9_4_3_init_cp_compute_microcode(adev, chip_name); 438 if (r) 439 return r; 440 441 return r; 442 } 443 444 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 445 { 446 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 447 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 448 } 449 450 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 451 { 452 int r, i, num_xcc; 453 u32 *hpd; 454 const __le32 *fw_data; 455 unsigned fw_size; 456 u32 *fw; 457 size_t mec_hpd_size; 458 459 const struct gfx_firmware_header_v1_0 *mec_hdr; 460 461 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 462 for (i = 0; i < num_xcc; i++) 463 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 464 AMDGPU_MAX_COMPUTE_QUEUES); 465 466 /* take ownership of the relevant compute queues */ 467 amdgpu_gfx_compute_queue_acquire(adev); 468 mec_hpd_size = 469 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 470 if (mec_hpd_size) { 471 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 472 AMDGPU_GEM_DOMAIN_VRAM | 473 AMDGPU_GEM_DOMAIN_GTT, 474 &adev->gfx.mec.hpd_eop_obj, 475 &adev->gfx.mec.hpd_eop_gpu_addr, 476 (void **)&hpd); 477 if (r) { 478 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 479 gfx_v9_4_3_mec_fini(adev); 480 return r; 481 } 482 483 if (amdgpu_emu_mode == 1) { 484 for (i = 0; i < mec_hpd_size / 4; i++) { 485 memset((void *)(hpd + i), 0, 4); 486 if (i % 50 == 0) 487 msleep(1); 488 } 489 } else { 490 memset(hpd, 0, mec_hpd_size); 491 } 492 493 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 494 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 495 } 496 497 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 498 499 fw_data = (const __le32 *) 500 (adev->gfx.mec_fw->data + 501 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 502 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 503 504 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 505 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 506 &adev->gfx.mec.mec_fw_obj, 507 &adev->gfx.mec.mec_fw_gpu_addr, 508 (void **)&fw); 509 if (r) { 510 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 511 gfx_v9_4_3_mec_fini(adev); 512 return r; 513 } 514 515 memcpy(fw, fw_data, fw_size); 516 517 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 518 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 519 520 return 0; 521 } 522 523 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 524 u32 sh_num, u32 instance, int xcc_id) 525 { 526 u32 data; 527 528 if (instance == 0xffffffff) 529 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 530 INSTANCE_BROADCAST_WRITES, 1); 531 else 532 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 533 INSTANCE_INDEX, instance); 534 535 if (se_num == 0xffffffff) 536 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 537 SE_BROADCAST_WRITES, 1); 538 else 539 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 540 541 if (sh_num == 0xffffffff) 542 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 543 SH_BROADCAST_WRITES, 1); 544 else 545 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 546 547 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 548 } 549 550 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 551 { 552 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 553 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 554 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 555 (address << SQ_IND_INDEX__INDEX__SHIFT) | 556 (SQ_IND_INDEX__FORCE_READ_MASK)); 557 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 558 } 559 560 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 561 uint32_t wave, uint32_t thread, 562 uint32_t regno, uint32_t num, uint32_t *out) 563 { 564 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 565 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 566 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 567 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 568 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 569 (SQ_IND_INDEX__FORCE_READ_MASK) | 570 (SQ_IND_INDEX__AUTO_INCR_MASK)); 571 while (num--) 572 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 573 } 574 575 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 576 uint32_t xcc_id, uint32_t simd, uint32_t wave, 577 uint32_t *dst, int *no_fields) 578 { 579 /* type 1 wave data */ 580 dst[(*no_fields)++] = 1; 581 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 582 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 583 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 584 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 585 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 586 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 587 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 588 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 589 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 590 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 591 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 592 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 593 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 594 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 595 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 596 } 597 598 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 599 uint32_t wave, uint32_t start, 600 uint32_t size, uint32_t *dst) 601 { 602 wave_read_regs(adev, xcc_id, simd, wave, 0, 603 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 604 } 605 606 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 607 uint32_t wave, uint32_t thread, 608 uint32_t start, uint32_t size, 609 uint32_t *dst) 610 { 611 wave_read_regs(adev, xcc_id, simd, wave, thread, 612 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 613 } 614 615 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 616 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 617 { 618 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 619 } 620 621 622 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 623 int num_xccs_per_xcp) 624 { 625 int ret, i, num_xcc; 626 u32 tmp = 0; 627 628 if (adev->psp.funcs) { 629 ret = psp_spatial_partition(&adev->psp, 630 NUM_XCC(adev->gfx.xcc_mask) / 631 num_xccs_per_xcp); 632 if (ret) 633 return ret; 634 } else { 635 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 636 637 for (i = 0; i < num_xcc; i++) { 638 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 639 num_xccs_per_xcp); 640 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 641 i % num_xccs_per_xcp); 642 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 643 tmp); 644 } 645 ret = 0; 646 } 647 648 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 649 650 return ret; 651 } 652 653 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 654 { 655 int xcc; 656 657 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 658 if (!xcc) { 659 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 660 return -EINVAL; 661 } 662 663 return xcc - 1; 664 } 665 666 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 667 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 668 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 669 .read_wave_data = &gfx_v9_4_3_read_wave_data, 670 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 671 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 672 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 673 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 674 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 675 }; 676 677 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 678 { 679 u32 gb_addr_config; 680 681 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 682 adev->gfx.ras = &gfx_v9_4_3_ras; 683 684 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 685 case IP_VERSION(9, 4, 3): 686 adev->gfx.config.max_hw_contexts = 8; 687 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 688 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 689 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 690 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 691 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG); 692 break; 693 default: 694 BUG(); 695 break; 696 } 697 698 adev->gfx.config.gb_addr_config = gb_addr_config; 699 700 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 701 REG_GET_FIELD( 702 adev->gfx.config.gb_addr_config, 703 GB_ADDR_CONFIG, 704 NUM_PIPES); 705 706 adev->gfx.config.max_tile_pipes = 707 adev->gfx.config.gb_addr_config_fields.num_pipes; 708 709 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 710 REG_GET_FIELD( 711 adev->gfx.config.gb_addr_config, 712 GB_ADDR_CONFIG, 713 NUM_BANKS); 714 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 715 REG_GET_FIELD( 716 adev->gfx.config.gb_addr_config, 717 GB_ADDR_CONFIG, 718 MAX_COMPRESSED_FRAGS); 719 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 720 REG_GET_FIELD( 721 adev->gfx.config.gb_addr_config, 722 GB_ADDR_CONFIG, 723 NUM_RB_PER_SE); 724 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 725 REG_GET_FIELD( 726 adev->gfx.config.gb_addr_config, 727 GB_ADDR_CONFIG, 728 NUM_SHADER_ENGINES); 729 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 730 REG_GET_FIELD( 731 adev->gfx.config.gb_addr_config, 732 GB_ADDR_CONFIG, 733 PIPE_INTERLEAVE_SIZE)); 734 735 return 0; 736 } 737 738 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 739 int xcc_id, int mec, int pipe, int queue) 740 { 741 unsigned irq_type; 742 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 743 unsigned int hw_prio; 744 uint32_t xcc_doorbell_start; 745 746 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 747 ring_id]; 748 749 /* mec0 is me1 */ 750 ring->xcc_id = xcc_id; 751 ring->me = mec + 1; 752 ring->pipe = pipe; 753 ring->queue = queue; 754 755 ring->ring_obj = NULL; 756 ring->use_doorbell = true; 757 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 758 xcc_id * adev->doorbell_index.xcc_doorbell_range; 759 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 760 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 761 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 762 GFX9_MEC_HPD_SIZE; 763 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 764 sprintf(ring->name, "comp_%d.%d.%d.%d", 765 ring->xcc_id, ring->me, ring->pipe, ring->queue); 766 767 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 768 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 769 + ring->pipe; 770 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 771 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 772 /* type-2 packets are deprecated on MEC, use type-3 instead */ 773 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 774 hw_prio, NULL); 775 } 776 777 static int gfx_v9_4_3_sw_init(void *handle) 778 { 779 int i, j, k, r, ring_id, xcc_id, num_xcc; 780 struct amdgpu_kiq *kiq; 781 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 782 783 adev->gfx.mec.num_mec = 2; 784 adev->gfx.mec.num_pipe_per_mec = 4; 785 adev->gfx.mec.num_queue_per_pipe = 8; 786 787 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 788 789 /* EOP Event */ 790 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 791 if (r) 792 return r; 793 794 /* Privileged reg */ 795 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 796 &adev->gfx.priv_reg_irq); 797 if (r) 798 return r; 799 800 /* Privileged inst */ 801 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 802 &adev->gfx.priv_inst_irq); 803 if (r) 804 return r; 805 806 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 807 808 r = adev->gfx.rlc.funcs->init(adev); 809 if (r) { 810 DRM_ERROR("Failed to init rlc BOs!\n"); 811 return r; 812 } 813 814 r = gfx_v9_4_3_mec_init(adev); 815 if (r) { 816 DRM_ERROR("Failed to init MEC BOs!\n"); 817 return r; 818 } 819 820 /* set up the compute queues - allocate horizontally across pipes */ 821 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 822 ring_id = 0; 823 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 824 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 825 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 826 k++) { 827 if (!amdgpu_gfx_is_mec_queue_enabled( 828 adev, xcc_id, i, k, j)) 829 continue; 830 831 r = gfx_v9_4_3_compute_ring_init(adev, 832 ring_id, 833 xcc_id, 834 i, k, j); 835 if (r) 836 return r; 837 838 ring_id++; 839 } 840 } 841 } 842 843 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 844 if (r) { 845 DRM_ERROR("Failed to init KIQ BOs!\n"); 846 return r; 847 } 848 849 kiq = &adev->gfx.kiq[xcc_id]; 850 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, xcc_id); 851 if (r) 852 return r; 853 854 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 855 r = amdgpu_gfx_mqd_sw_init(adev, 856 sizeof(struct v9_mqd_allocation), xcc_id); 857 if (r) 858 return r; 859 } 860 861 r = gfx_v9_4_3_gpu_early_init(adev); 862 if (r) 863 return r; 864 865 r = amdgpu_gfx_ras_sw_init(adev); 866 if (r) 867 return r; 868 869 870 if (!amdgpu_sriov_vf(adev)) 871 r = amdgpu_gfx_sysfs_init(adev); 872 873 return r; 874 } 875 876 static int gfx_v9_4_3_sw_fini(void *handle) 877 { 878 int i, num_xcc; 879 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 880 881 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 882 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 883 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 884 885 for (i = 0; i < num_xcc; i++) { 886 amdgpu_gfx_mqd_sw_fini(adev, i); 887 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 888 amdgpu_gfx_kiq_fini(adev, i); 889 } 890 891 gfx_v9_4_3_mec_fini(adev); 892 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 893 gfx_v9_4_3_free_microcode(adev); 894 if (!amdgpu_sriov_vf(adev)) 895 amdgpu_gfx_sysfs_fini(adev); 896 897 return 0; 898 } 899 900 #define DEFAULT_SH_MEM_BASES (0x6000) 901 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 902 int xcc_id) 903 { 904 int i; 905 uint32_t sh_mem_config; 906 uint32_t sh_mem_bases; 907 uint32_t data; 908 909 /* 910 * Configure apertures: 911 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 912 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 913 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 914 */ 915 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 916 917 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 918 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 919 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 920 921 mutex_lock(&adev->srbm_mutex); 922 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 923 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 924 /* CP and shaders */ 925 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 926 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 927 928 /* Enable trap for each kfd vmid. */ 929 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 930 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 931 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 932 } 933 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 934 mutex_unlock(&adev->srbm_mutex); 935 936 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 937 acccess. These should be enabled by FW for target VMIDs. */ 938 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 939 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 940 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 941 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 942 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 943 } 944 } 945 946 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 947 { 948 int vmid; 949 950 /* 951 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 952 * access. Compute VMIDs should be enabled by FW for target VMIDs, 953 * the driver can enable them for graphics. VMID0 should maintain 954 * access so that HWS firmware can save/restore entries. 955 */ 956 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 957 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 958 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 959 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 960 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 961 } 962 } 963 964 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 965 int xcc_id) 966 { 967 u32 tmp; 968 int i; 969 970 /* XXX SH_MEM regs */ 971 /* where to put LDS, scratch, GPUVM in FSA64 space */ 972 mutex_lock(&adev->srbm_mutex); 973 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 974 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 975 /* CP and shaders */ 976 if (i == 0) { 977 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 978 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 979 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 980 !!adev->gmc.noretry); 981 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 982 regSH_MEM_CONFIG, tmp); 983 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 984 regSH_MEM_BASES, 0); 985 } else { 986 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 987 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 988 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 989 !!adev->gmc.noretry); 990 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 991 regSH_MEM_CONFIG, tmp); 992 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 993 (adev->gmc.private_aperture_start >> 994 48)); 995 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 996 (adev->gmc.shared_aperture_start >> 997 48)); 998 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 999 regSH_MEM_BASES, tmp); 1000 } 1001 } 1002 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 1003 1004 mutex_unlock(&adev->srbm_mutex); 1005 1006 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 1007 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 1008 } 1009 1010 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 1011 { 1012 int i, num_xcc; 1013 1014 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1015 1016 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1017 adev->gfx.config.db_debug2 = 1018 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1019 1020 for (i = 0; i < num_xcc; i++) 1021 gfx_v9_4_3_xcc_constants_init(adev, i); 1022 } 1023 1024 static void 1025 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1026 int xcc_id) 1027 { 1028 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1029 } 1030 1031 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1032 { 1033 /* 1034 * Rlc save restore list is workable since v2_1. 1035 * And it's needed by gfxoff feature. 1036 */ 1037 if (adev->gfx.rlc.is_rlc_v2_1) 1038 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1039 } 1040 1041 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1042 { 1043 uint32_t data; 1044 1045 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1046 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1047 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1048 } 1049 1050 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1051 { 1052 uint32_t rlc_setting; 1053 1054 /* if RLC is not enabled, do nothing */ 1055 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1056 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1057 return false; 1058 1059 return true; 1060 } 1061 1062 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1063 { 1064 uint32_t data; 1065 unsigned i; 1066 1067 data = RLC_SAFE_MODE__CMD_MASK; 1068 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1069 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1070 1071 /* wait for RLC_SAFE_MODE */ 1072 for (i = 0; i < adev->usec_timeout; i++) { 1073 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1074 break; 1075 udelay(1); 1076 } 1077 } 1078 1079 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1080 int xcc_id) 1081 { 1082 uint32_t data; 1083 1084 data = RLC_SAFE_MODE__CMD_MASK; 1085 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1086 } 1087 1088 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1089 { 1090 int xcc_id, num_xcc; 1091 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1092 1093 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1094 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1095 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 1096 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); 1097 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); 1098 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); 1099 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); 1100 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 1101 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1102 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1103 } 1104 } 1105 1106 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1107 { 1108 /* init spm vmid with 0xf */ 1109 if (adev->gfx.rlc.funcs->update_spm_vmid) 1110 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 1111 1112 return 0; 1113 } 1114 1115 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1116 int xcc_id) 1117 { 1118 u32 i, j, k; 1119 u32 mask; 1120 1121 mutex_lock(&adev->grbm_idx_mutex); 1122 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1123 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1124 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1125 xcc_id); 1126 for (k = 0; k < adev->usec_timeout; k++) { 1127 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1128 break; 1129 udelay(1); 1130 } 1131 if (k == adev->usec_timeout) { 1132 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1133 0xffffffff, 1134 0xffffffff, xcc_id); 1135 mutex_unlock(&adev->grbm_idx_mutex); 1136 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1137 i, j); 1138 return; 1139 } 1140 } 1141 } 1142 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1143 xcc_id); 1144 mutex_unlock(&adev->grbm_idx_mutex); 1145 1146 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1147 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1148 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1149 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1150 for (k = 0; k < adev->usec_timeout; k++) { 1151 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1152 break; 1153 udelay(1); 1154 } 1155 } 1156 1157 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1158 bool enable, int xcc_id) 1159 { 1160 u32 tmp; 1161 1162 /* These interrupts should be enabled to drive DS clock */ 1163 1164 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1165 1166 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1167 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1168 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1169 1170 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1171 } 1172 1173 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1174 { 1175 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1176 RLC_ENABLE_F32, 0); 1177 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1178 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1179 } 1180 1181 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1182 { 1183 int i, num_xcc; 1184 1185 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1186 for (i = 0; i < num_xcc; i++) 1187 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1188 } 1189 1190 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1191 { 1192 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1193 SOFT_RESET_RLC, 1); 1194 udelay(50); 1195 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1196 SOFT_RESET_RLC, 0); 1197 udelay(50); 1198 } 1199 1200 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1201 { 1202 int i, num_xcc; 1203 1204 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1205 for (i = 0; i < num_xcc; i++) 1206 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1207 } 1208 1209 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1210 { 1211 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1212 RLC_ENABLE_F32, 1); 1213 udelay(50); 1214 1215 /* carrizo do enable cp interrupt after cp inited */ 1216 if (!(adev->flags & AMD_IS_APU)) { 1217 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1218 udelay(50); 1219 } 1220 } 1221 1222 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1223 { 1224 #ifdef AMDGPU_RLC_DEBUG_RETRY 1225 u32 rlc_ucode_ver; 1226 #endif 1227 int i, num_xcc; 1228 1229 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1230 for (i = 0; i < num_xcc; i++) { 1231 gfx_v9_4_3_xcc_rlc_start(adev, i); 1232 #ifdef AMDGPU_RLC_DEBUG_RETRY 1233 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1234 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1235 if (rlc_ucode_ver == 0x108) { 1236 dev_info(adev->dev, 1237 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1238 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1239 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1240 * default is 0x9C4 to create a 100us interval */ 1241 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1242 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1243 * to disable the page fault retry interrupts, default is 1244 * 0x100 (256) */ 1245 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1246 } 1247 #endif 1248 } 1249 } 1250 1251 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1252 int xcc_id) 1253 { 1254 const struct rlc_firmware_header_v2_0 *hdr; 1255 const __le32 *fw_data; 1256 unsigned i, fw_size; 1257 1258 if (!adev->gfx.rlc_fw) 1259 return -EINVAL; 1260 1261 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1262 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1263 1264 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1265 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1266 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1267 1268 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1269 RLCG_UCODE_LOADING_START_ADDRESS); 1270 for (i = 0; i < fw_size; i++) { 1271 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1272 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1273 msleep(1); 1274 } 1275 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1276 } 1277 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1278 1279 return 0; 1280 } 1281 1282 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1283 { 1284 int r; 1285 1286 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1287 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1288 /* legacy rlc firmware loading */ 1289 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1290 if (r) 1291 return r; 1292 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1293 } 1294 1295 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1296 /* disable CG */ 1297 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1298 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1299 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1300 1301 return 0; 1302 } 1303 1304 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1305 { 1306 int r, i, num_xcc; 1307 1308 if (amdgpu_sriov_vf(adev)) 1309 return 0; 1310 1311 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1312 for (i = 0; i < num_xcc; i++) { 1313 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1314 if (r) 1315 return r; 1316 } 1317 1318 return 0; 1319 } 1320 1321 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, 1322 unsigned vmid) 1323 { 1324 u32 reg, data; 1325 1326 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); 1327 if (amdgpu_sriov_is_pp_one_vf(adev)) 1328 data = RREG32_NO_KIQ(reg); 1329 else 1330 data = RREG32(reg); 1331 1332 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 1333 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1334 1335 if (amdgpu_sriov_is_pp_one_vf(adev)) 1336 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1337 else 1338 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1339 } 1340 1341 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1342 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1343 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1344 }; 1345 1346 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1347 uint32_t offset, 1348 struct soc15_reg_rlcg *entries, int arr_size) 1349 { 1350 int i, inst; 1351 uint32_t reg; 1352 1353 if (!entries) 1354 return false; 1355 1356 for (i = 0; i < arr_size; i++) { 1357 const struct soc15_reg_rlcg *entry; 1358 1359 entry = &entries[i]; 1360 inst = adev->ip_map.logical_to_dev_inst ? 1361 adev->ip_map.logical_to_dev_inst( 1362 adev, entry->hwip, entry->instance) : 1363 entry->instance; 1364 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1365 entry->reg; 1366 if (offset == reg) 1367 return true; 1368 } 1369 1370 return false; 1371 } 1372 1373 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1374 { 1375 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1376 (void *)rlcg_access_gc_9_4_3, 1377 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1378 } 1379 1380 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1381 bool enable, int xcc_id) 1382 { 1383 if (enable) { 1384 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1385 } else { 1386 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1387 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1388 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1389 } 1390 udelay(50); 1391 } 1392 1393 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1394 int xcc_id) 1395 { 1396 const struct gfx_firmware_header_v1_0 *mec_hdr; 1397 const __le32 *fw_data; 1398 unsigned i; 1399 u32 tmp; 1400 u32 mec_ucode_addr_offset; 1401 u32 mec_ucode_data_offset; 1402 1403 if (!adev->gfx.mec_fw) 1404 return -EINVAL; 1405 1406 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1407 1408 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1409 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1410 1411 fw_data = (const __le32 *) 1412 (adev->gfx.mec_fw->data + 1413 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1414 tmp = 0; 1415 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1416 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1417 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1418 1419 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1420 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1421 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1422 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1423 1424 mec_ucode_addr_offset = 1425 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1426 mec_ucode_data_offset = 1427 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1428 1429 /* MEC1 */ 1430 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1431 for (i = 0; i < mec_hdr->jt_size; i++) 1432 WREG32(mec_ucode_data_offset, 1433 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1434 1435 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1436 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1437 1438 return 0; 1439 } 1440 1441 /* KIQ functions */ 1442 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1443 { 1444 uint32_t tmp; 1445 struct amdgpu_device *adev = ring->adev; 1446 1447 /* tell RLC which is KIQ queue */ 1448 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1449 tmp &= 0xffffff00; 1450 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1451 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1452 tmp |= 0x80; 1453 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1454 } 1455 1456 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1457 { 1458 struct amdgpu_device *adev = ring->adev; 1459 1460 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1461 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1462 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1463 mqd->cp_hqd_queue_priority = 1464 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1465 } 1466 } 1467 } 1468 1469 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1470 { 1471 struct amdgpu_device *adev = ring->adev; 1472 struct v9_mqd *mqd = ring->mqd_ptr; 1473 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1474 uint32_t tmp; 1475 1476 mqd->header = 0xC0310800; 1477 mqd->compute_pipelinestat_enable = 0x00000001; 1478 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1479 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1480 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1481 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1482 mqd->compute_misc_reserved = 0x00000003; 1483 1484 mqd->dynamic_cu_mask_addr_lo = 1485 lower_32_bits(ring->mqd_gpu_addr 1486 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1487 mqd->dynamic_cu_mask_addr_hi = 1488 upper_32_bits(ring->mqd_gpu_addr 1489 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1490 1491 eop_base_addr = ring->eop_gpu_addr >> 8; 1492 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1493 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1494 1495 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1496 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1497 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1498 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1499 1500 mqd->cp_hqd_eop_control = tmp; 1501 1502 /* enable doorbell? */ 1503 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1504 1505 if (ring->use_doorbell) { 1506 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1507 DOORBELL_OFFSET, ring->doorbell_index); 1508 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1509 DOORBELL_EN, 1); 1510 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1511 DOORBELL_SOURCE, 0); 1512 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1513 DOORBELL_HIT, 0); 1514 } else { 1515 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1516 DOORBELL_EN, 0); 1517 } 1518 1519 mqd->cp_hqd_pq_doorbell_control = tmp; 1520 1521 /* disable the queue if it's active */ 1522 ring->wptr = 0; 1523 mqd->cp_hqd_dequeue_request = 0; 1524 mqd->cp_hqd_pq_rptr = 0; 1525 mqd->cp_hqd_pq_wptr_lo = 0; 1526 mqd->cp_hqd_pq_wptr_hi = 0; 1527 1528 /* set the pointer to the MQD */ 1529 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1530 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1531 1532 /* set MQD vmid to 0 */ 1533 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1534 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1535 mqd->cp_mqd_control = tmp; 1536 1537 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1538 hqd_gpu_addr = ring->gpu_addr >> 8; 1539 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1540 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1541 1542 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1543 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1544 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1545 (order_base_2(ring->ring_size / 4) - 1)); 1546 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1547 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1548 #ifdef __BIG_ENDIAN 1549 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1550 #endif 1551 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1552 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1553 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1554 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1555 mqd->cp_hqd_pq_control = tmp; 1556 1557 /* set the wb address whether it's enabled or not */ 1558 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1559 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1560 mqd->cp_hqd_pq_rptr_report_addr_hi = 1561 upper_32_bits(wb_gpu_addr) & 0xffff; 1562 1563 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1564 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1565 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1566 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1567 1568 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1569 ring->wptr = 0; 1570 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1571 1572 /* set the vmid for the queue */ 1573 mqd->cp_hqd_vmid = 0; 1574 1575 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1576 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1577 mqd->cp_hqd_persistent_state = tmp; 1578 1579 /* set MIN_IB_AVAIL_SIZE */ 1580 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1581 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1582 mqd->cp_hqd_ib_control = tmp; 1583 1584 /* set static priority for a queue/ring */ 1585 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1586 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1587 1588 /* map_queues packet doesn't need activate the queue, 1589 * so only kiq need set this field. 1590 */ 1591 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1592 mqd->cp_hqd_active = 1; 1593 1594 return 0; 1595 } 1596 1597 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1598 int xcc_id) 1599 { 1600 struct amdgpu_device *adev = ring->adev; 1601 struct v9_mqd *mqd = ring->mqd_ptr; 1602 int j; 1603 1604 /* disable wptr polling */ 1605 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1606 1607 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1608 mqd->cp_hqd_eop_base_addr_lo); 1609 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1610 mqd->cp_hqd_eop_base_addr_hi); 1611 1612 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1613 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1614 mqd->cp_hqd_eop_control); 1615 1616 /* enable doorbell? */ 1617 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1618 mqd->cp_hqd_pq_doorbell_control); 1619 1620 /* disable the queue if it's active */ 1621 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1622 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1623 for (j = 0; j < adev->usec_timeout; j++) { 1624 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1625 break; 1626 udelay(1); 1627 } 1628 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1629 mqd->cp_hqd_dequeue_request); 1630 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1631 mqd->cp_hqd_pq_rptr); 1632 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1633 mqd->cp_hqd_pq_wptr_lo); 1634 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1635 mqd->cp_hqd_pq_wptr_hi); 1636 } 1637 1638 /* set the pointer to the MQD */ 1639 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 1640 mqd->cp_mqd_base_addr_lo); 1641 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 1642 mqd->cp_mqd_base_addr_hi); 1643 1644 /* set MQD vmid to 0 */ 1645 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 1646 mqd->cp_mqd_control); 1647 1648 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1649 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 1650 mqd->cp_hqd_pq_base_lo); 1651 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 1652 mqd->cp_hqd_pq_base_hi); 1653 1654 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1655 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 1656 mqd->cp_hqd_pq_control); 1657 1658 /* set the wb address whether it's enabled or not */ 1659 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 1660 mqd->cp_hqd_pq_rptr_report_addr_lo); 1661 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1662 mqd->cp_hqd_pq_rptr_report_addr_hi); 1663 1664 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1665 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 1666 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1667 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1668 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1669 1670 /* enable the doorbell if requested */ 1671 if (ring->use_doorbell) { 1672 WREG32_SOC15( 1673 GC, GET_INST(GC, xcc_id), 1674 regCP_MEC_DOORBELL_RANGE_LOWER, 1675 ((adev->doorbell_index.kiq + 1676 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1677 2) << 2); 1678 WREG32_SOC15( 1679 GC, GET_INST(GC, xcc_id), 1680 regCP_MEC_DOORBELL_RANGE_UPPER, 1681 ((adev->doorbell_index.userqueue_end + 1682 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1683 2) << 2); 1684 } 1685 1686 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1687 mqd->cp_hqd_pq_doorbell_control); 1688 1689 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1690 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1691 mqd->cp_hqd_pq_wptr_lo); 1692 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1693 mqd->cp_hqd_pq_wptr_hi); 1694 1695 /* set the vmid for the queue */ 1696 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 1697 1698 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 1699 mqd->cp_hqd_persistent_state); 1700 1701 /* activate the queue */ 1702 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 1703 mqd->cp_hqd_active); 1704 1705 if (ring->use_doorbell) 1706 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 1707 1708 return 0; 1709 } 1710 1711 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 1712 int xcc_id) 1713 { 1714 struct amdgpu_device *adev = ring->adev; 1715 int j; 1716 1717 /* disable the queue if it's active */ 1718 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1719 1720 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1721 1722 for (j = 0; j < adev->usec_timeout; j++) { 1723 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1724 break; 1725 udelay(1); 1726 } 1727 1728 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 1729 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 1730 1731 /* Manual disable if dequeue request times out */ 1732 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 1733 } 1734 1735 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1736 0); 1737 } 1738 1739 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 1740 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 1741 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT); 1742 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 1743 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1744 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 1745 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 1746 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 1747 1748 return 0; 1749 } 1750 1751 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1752 { 1753 struct amdgpu_device *adev = ring->adev; 1754 struct v9_mqd *mqd = ring->mqd_ptr; 1755 struct v9_mqd *tmp_mqd; 1756 1757 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 1758 1759 /* GPU could be in bad state during probe, driver trigger the reset 1760 * after load the SMU, in this case , the mqd is not be initialized. 1761 * driver need to re-init the mqd. 1762 * check mqd->cp_hqd_pq_control since this value should not be 0 1763 */ 1764 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 1765 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 1766 /* for GPU_RESET case , reset MQD to a clean status */ 1767 if (adev->gfx.kiq[xcc_id].mqd_backup) 1768 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 1769 1770 /* reset ring buffer */ 1771 ring->wptr = 0; 1772 amdgpu_ring_clear_ring(ring); 1773 mutex_lock(&adev->srbm_mutex); 1774 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1775 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1776 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1777 mutex_unlock(&adev->srbm_mutex); 1778 } else { 1779 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1780 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1781 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1782 mutex_lock(&adev->srbm_mutex); 1783 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 1784 amdgpu_ring_clear_ring(ring); 1785 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1786 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1787 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1788 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1789 mutex_unlock(&adev->srbm_mutex); 1790 1791 if (adev->gfx.kiq[xcc_id].mqd_backup) 1792 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 1793 } 1794 1795 return 0; 1796 } 1797 1798 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1799 { 1800 struct amdgpu_device *adev = ring->adev; 1801 struct v9_mqd *mqd = ring->mqd_ptr; 1802 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 1803 struct v9_mqd *tmp_mqd; 1804 1805 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 1806 * is not be initialized before 1807 */ 1808 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 1809 1810 if (!tmp_mqd->cp_hqd_pq_control || 1811 (!amdgpu_in_reset(adev) && !adev->in_suspend)) { 1812 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1813 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1814 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1815 mutex_lock(&adev->srbm_mutex); 1816 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1817 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1818 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1819 mutex_unlock(&adev->srbm_mutex); 1820 1821 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1822 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 1823 } else { 1824 /* restore MQD to a clean status */ 1825 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1826 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 1827 /* reset ring buffer */ 1828 ring->wptr = 0; 1829 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 1830 amdgpu_ring_clear_ring(ring); 1831 } 1832 1833 return 0; 1834 } 1835 1836 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 1837 { 1838 struct amdgpu_ring *ring; 1839 int j; 1840 1841 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 1842 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 1843 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 1844 mutex_lock(&adev->srbm_mutex); 1845 soc15_grbm_select(adev, ring->me, 1846 ring->pipe, 1847 ring->queue, 0, GET_INST(GC, xcc_id)); 1848 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 1849 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1850 mutex_unlock(&adev->srbm_mutex); 1851 } 1852 } 1853 1854 return 0; 1855 } 1856 1857 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 1858 { 1859 struct amdgpu_ring *ring; 1860 int r; 1861 1862 ring = &adev->gfx.kiq[xcc_id].ring; 1863 1864 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1865 if (unlikely(r != 0)) 1866 return r; 1867 1868 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1869 if (unlikely(r != 0)) { 1870 amdgpu_bo_unreserve(ring->mqd_obj); 1871 return r; 1872 } 1873 1874 gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id); 1875 amdgpu_bo_kunmap(ring->mqd_obj); 1876 ring->mqd_ptr = NULL; 1877 amdgpu_bo_unreserve(ring->mqd_obj); 1878 return 0; 1879 } 1880 1881 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 1882 { 1883 struct amdgpu_ring *ring = NULL; 1884 int r = 0, i; 1885 1886 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 1887 1888 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 1889 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 1890 1891 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1892 if (unlikely(r != 0)) 1893 goto done; 1894 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1895 if (!r) { 1896 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id); 1897 amdgpu_bo_kunmap(ring->mqd_obj); 1898 ring->mqd_ptr = NULL; 1899 } 1900 amdgpu_bo_unreserve(ring->mqd_obj); 1901 if (r) 1902 goto done; 1903 } 1904 1905 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 1906 done: 1907 return r; 1908 } 1909 1910 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 1911 { 1912 struct amdgpu_ring *ring; 1913 int r, j; 1914 1915 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1916 1917 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1918 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 1919 1920 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 1921 if (r) 1922 return r; 1923 } 1924 1925 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 1926 if (r) 1927 return r; 1928 1929 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 1930 if (r) 1931 return r; 1932 1933 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 1934 ring = &adev->gfx.compute_ring 1935 [j + xcc_id * adev->gfx.num_compute_rings]; 1936 r = amdgpu_ring_test_helper(ring); 1937 if (r) 1938 return r; 1939 } 1940 1941 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1942 1943 return 0; 1944 } 1945 1946 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 1947 { 1948 int r = 0, i, num_xcc; 1949 1950 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 1951 AMDGPU_XCP_FL_NONE) == 1952 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 1953 r = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr, 1954 amdgpu_user_partt_mode); 1955 1956 if (r) 1957 return r; 1958 1959 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1960 for (i = 0; i < num_xcc; i++) { 1961 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 1962 if (r) 1963 return r; 1964 } 1965 1966 return 0; 1967 } 1968 1969 static void gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device *adev, bool enable, 1970 int xcc_id) 1971 { 1972 gfx_v9_4_3_xcc_cp_compute_enable(adev, enable, xcc_id); 1973 } 1974 1975 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 1976 { 1977 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 1978 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 1979 1980 if (amdgpu_sriov_vf(adev)) { 1981 /* must disable polling for SRIOV when hw finished, otherwise 1982 * CPC engine may still keep fetching WB address which is already 1983 * invalid after sw finished and trigger DMAR reading error in 1984 * hypervisor side. 1985 */ 1986 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1987 return; 1988 } 1989 1990 /* Use deinitialize sequence from CAIL when unbinding device 1991 * from driver, otherwise KIQ is hanging when binding back 1992 */ 1993 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 1994 mutex_lock(&adev->srbm_mutex); 1995 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 1996 adev->gfx.kiq[xcc_id].ring.pipe, 1997 adev->gfx.kiq[xcc_id].ring.queue, 0, 1998 GET_INST(GC, xcc_id)); 1999 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 2000 xcc_id); 2001 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2002 mutex_unlock(&adev->srbm_mutex); 2003 } 2004 2005 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 2006 gfx_v9_4_3_xcc_cp_enable(adev, false, xcc_id); 2007 } 2008 2009 static int gfx_v9_4_3_hw_init(void *handle) 2010 { 2011 int r; 2012 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2013 2014 if (!amdgpu_sriov_vf(adev)) 2015 gfx_v9_4_3_init_golden_registers(adev); 2016 2017 gfx_v9_4_3_constants_init(adev); 2018 2019 r = adev->gfx.rlc.funcs->resume(adev); 2020 if (r) 2021 return r; 2022 2023 r = gfx_v9_4_3_cp_resume(adev); 2024 if (r) 2025 return r; 2026 2027 return r; 2028 } 2029 2030 static int gfx_v9_4_3_hw_fini(void *handle) 2031 { 2032 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2033 int i, num_xcc; 2034 2035 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2036 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2037 2038 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2039 for (i = 0; i < num_xcc; i++) { 2040 gfx_v9_4_3_xcc_fini(adev, i); 2041 } 2042 2043 return 0; 2044 } 2045 2046 static int gfx_v9_4_3_suspend(void *handle) 2047 { 2048 return gfx_v9_4_3_hw_fini(handle); 2049 } 2050 2051 static int gfx_v9_4_3_resume(void *handle) 2052 { 2053 return gfx_v9_4_3_hw_init(handle); 2054 } 2055 2056 static bool gfx_v9_4_3_is_idle(void *handle) 2057 { 2058 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2059 int i, num_xcc; 2060 2061 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2062 for (i = 0; i < num_xcc; i++) { 2063 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2064 GRBM_STATUS, GUI_ACTIVE)) 2065 return false; 2066 } 2067 return true; 2068 } 2069 2070 static int gfx_v9_4_3_wait_for_idle(void *handle) 2071 { 2072 unsigned i; 2073 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2074 2075 for (i = 0; i < adev->usec_timeout; i++) { 2076 if (gfx_v9_4_3_is_idle(handle)) 2077 return 0; 2078 udelay(1); 2079 } 2080 return -ETIMEDOUT; 2081 } 2082 2083 static int gfx_v9_4_3_soft_reset(void *handle) 2084 { 2085 u32 grbm_soft_reset = 0; 2086 u32 tmp; 2087 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2088 2089 /* GRBM_STATUS */ 2090 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2091 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2092 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2093 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2094 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2095 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2096 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2097 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2098 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2099 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2100 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2101 } 2102 2103 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2104 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2105 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2106 } 2107 2108 /* GRBM_STATUS2 */ 2109 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2110 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2111 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2112 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2113 2114 2115 if (grbm_soft_reset) { 2116 /* stop the rlc */ 2117 adev->gfx.rlc.funcs->stop(adev); 2118 2119 /* Disable MEC parsing/prefetching */ 2120 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2121 2122 if (grbm_soft_reset) { 2123 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2124 tmp |= grbm_soft_reset; 2125 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2126 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2127 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2128 2129 udelay(50); 2130 2131 tmp &= ~grbm_soft_reset; 2132 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2133 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2134 } 2135 2136 /* Wait a little for things to settle down */ 2137 udelay(50); 2138 } 2139 return 0; 2140 } 2141 2142 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2143 uint32_t vmid, 2144 uint32_t gds_base, uint32_t gds_size, 2145 uint32_t gws_base, uint32_t gws_size, 2146 uint32_t oa_base, uint32_t oa_size) 2147 { 2148 struct amdgpu_device *adev = ring->adev; 2149 2150 /* GDS Base */ 2151 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2152 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2153 gds_base); 2154 2155 /* GDS Size */ 2156 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2157 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2158 gds_size); 2159 2160 /* GWS */ 2161 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2162 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2163 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2164 2165 /* OA */ 2166 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2167 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2168 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2169 } 2170 2171 static int gfx_v9_4_3_early_init(void *handle) 2172 { 2173 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2174 2175 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2176 AMDGPU_MAX_COMPUTE_RINGS); 2177 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2178 gfx_v9_4_3_set_ring_funcs(adev); 2179 gfx_v9_4_3_set_irq_funcs(adev); 2180 gfx_v9_4_3_set_gds_init(adev); 2181 gfx_v9_4_3_set_rlc_funcs(adev); 2182 2183 /* init rlcg reg access ctrl */ 2184 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev); 2185 2186 return gfx_v9_4_3_init_microcode(adev); 2187 } 2188 2189 static int gfx_v9_4_3_late_init(void *handle) 2190 { 2191 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2192 int r; 2193 2194 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2195 if (r) 2196 return r; 2197 2198 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2199 if (r) 2200 return r; 2201 2202 if (adev->gfx.ras && 2203 adev->gfx.ras->enable_watchdog_timer) 2204 adev->gfx.ras->enable_watchdog_timer(adev); 2205 2206 return 0; 2207 } 2208 2209 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2210 bool enable, int xcc_id) 2211 { 2212 uint32_t def, data; 2213 2214 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2215 return; 2216 2217 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2218 regRLC_CGTT_MGCG_OVERRIDE); 2219 2220 if (enable) 2221 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2222 else 2223 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2224 2225 if (def != data) 2226 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2227 regRLC_CGTT_MGCG_OVERRIDE, data); 2228 2229 } 2230 2231 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2232 bool enable, int xcc_id) 2233 { 2234 uint32_t def, data; 2235 2236 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2237 return; 2238 2239 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2240 regRLC_CGTT_MGCG_OVERRIDE); 2241 2242 if (enable) 2243 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2244 else 2245 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2246 2247 if (def != data) 2248 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2249 regRLC_CGTT_MGCG_OVERRIDE, data); 2250 } 2251 2252 static void 2253 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2254 bool enable, int xcc_id) 2255 { 2256 uint32_t data, def; 2257 2258 /* It is disabled by HW by default */ 2259 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2260 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2261 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2262 2263 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2264 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2265 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2266 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2267 2268 if (def != data) 2269 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2270 2271 /* MGLS is a global flag to control all MGLS in GFX */ 2272 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2273 /* 2 - RLC memory Light sleep */ 2274 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2275 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2276 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2277 if (def != data) 2278 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2279 } 2280 /* 3 - CP memory Light sleep */ 2281 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2282 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2283 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2284 if (def != data) 2285 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2286 } 2287 } 2288 } else { 2289 /* 1 - MGCG_OVERRIDE */ 2290 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2291 2292 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2293 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2294 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2295 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2296 2297 if (def != data) 2298 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2299 2300 /* 2 - disable MGLS in RLC */ 2301 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2302 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2303 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2304 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2305 } 2306 2307 /* 3 - disable MGLS in CP */ 2308 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2309 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2310 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2311 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2312 } 2313 } 2314 2315 } 2316 2317 static void 2318 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2319 bool enable, int xcc_id) 2320 { 2321 uint32_t def, data; 2322 2323 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2324 2325 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2326 /* unset CGCG override */ 2327 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2328 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2329 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2330 else 2331 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2332 /* update CGCG and CGLS override bits */ 2333 if (def != data) 2334 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2335 2336 /* enable cgcg FSM(0x0000363F) */ 2337 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2338 2339 data = (0x36 2340 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2341 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2342 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2343 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2344 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2345 if (def != data) 2346 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2347 2348 /* set IDLE_POLL_COUNT(0x00900100) */ 2349 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2350 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2351 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2352 if (def != data) 2353 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2354 } else { 2355 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2356 /* reset CGCG/CGLS bits */ 2357 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2358 /* disable cgcg and cgls in FSM */ 2359 if (def != data) 2360 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2361 } 2362 2363 } 2364 2365 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2366 bool enable, int xcc_id) 2367 { 2368 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2369 2370 if (enable) { 2371 /* FGCG */ 2372 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2373 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2374 2375 /* CGCG/CGLS should be enabled after MGCG/MGLS 2376 * === MGCG + MGLS === 2377 */ 2378 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2379 xcc_id); 2380 /* === CGCG + CGLS === */ 2381 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2382 xcc_id); 2383 } else { 2384 /* CGCG/CGLS should be disabled before MGCG/MGLS 2385 * === CGCG + CGLS === 2386 */ 2387 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2388 xcc_id); 2389 /* === MGCG + MGLS === */ 2390 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2391 xcc_id); 2392 2393 /* FGCG */ 2394 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2395 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2396 } 2397 2398 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2399 2400 return 0; 2401 } 2402 2403 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2404 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2405 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2406 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2407 .init = gfx_v9_4_3_rlc_init, 2408 .resume = gfx_v9_4_3_rlc_resume, 2409 .stop = gfx_v9_4_3_rlc_stop, 2410 .reset = gfx_v9_4_3_rlc_reset, 2411 .start = gfx_v9_4_3_rlc_start, 2412 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2413 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2414 }; 2415 2416 static int gfx_v9_4_3_set_powergating_state(void *handle, 2417 enum amd_powergating_state state) 2418 { 2419 return 0; 2420 } 2421 2422 static int gfx_v9_4_3_set_clockgating_state(void *handle, 2423 enum amd_clockgating_state state) 2424 { 2425 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2426 int i, num_xcc; 2427 2428 if (amdgpu_sriov_vf(adev)) 2429 return 0; 2430 2431 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2432 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2433 case IP_VERSION(9, 4, 3): 2434 for (i = 0; i < num_xcc; i++) 2435 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2436 adev, state == AMD_CG_STATE_GATE, i); 2437 break; 2438 default: 2439 break; 2440 } 2441 return 0; 2442 } 2443 2444 static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags) 2445 { 2446 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2447 int data; 2448 2449 if (amdgpu_sriov_vf(adev)) 2450 *flags = 0; 2451 2452 /* AMD_CG_SUPPORT_GFX_MGCG */ 2453 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2454 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2455 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2456 2457 /* AMD_CG_SUPPORT_GFX_CGCG */ 2458 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2459 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2460 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2461 2462 /* AMD_CG_SUPPORT_GFX_CGLS */ 2463 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2464 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2465 2466 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2467 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2468 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2469 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2470 2471 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2472 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2473 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2474 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2475 } 2476 2477 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2478 { 2479 struct amdgpu_device *adev = ring->adev; 2480 u32 ref_and_mask, reg_mem_engine; 2481 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 2482 2483 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2484 switch (ring->me) { 2485 case 1: 2486 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 2487 break; 2488 case 2: 2489 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 2490 break; 2491 default: 2492 return; 2493 } 2494 reg_mem_engine = 0; 2495 } else { 2496 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 2497 reg_mem_engine = 1; /* pfp */ 2498 } 2499 2500 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2501 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2502 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2503 ref_and_mask, ref_and_mask, 0x20); 2504 } 2505 2506 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2507 struct amdgpu_job *job, 2508 struct amdgpu_ib *ib, 2509 uint32_t flags) 2510 { 2511 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2512 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2513 2514 /* Currently, there is a high possibility to get wave ID mismatch 2515 * between ME and GDS, leading to a hw deadlock, because ME generates 2516 * different wave IDs than the GDS expects. This situation happens 2517 * randomly when at least 5 compute pipes use GDS ordered append. 2518 * The wave IDs generated by ME are also wrong after suspend/resume. 2519 * Those are probably bugs somewhere else in the kernel driver. 2520 * 2521 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2522 * GDS to 0 for this ring (me/pipe). 2523 */ 2524 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2525 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2526 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2527 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2528 } 2529 2530 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2531 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2532 amdgpu_ring_write(ring, 2533 #ifdef __BIG_ENDIAN 2534 (2 << 0) | 2535 #endif 2536 lower_32_bits(ib->gpu_addr)); 2537 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2538 amdgpu_ring_write(ring, control); 2539 } 2540 2541 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2542 u64 seq, unsigned flags) 2543 { 2544 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2545 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2546 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2547 2548 /* RELEASE_MEM - flush caches, send int */ 2549 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2550 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2551 EOP_TC_NC_ACTION_EN) : 2552 (EOP_TCL1_ACTION_EN | 2553 EOP_TC_ACTION_EN | 2554 EOP_TC_WB_ACTION_EN | 2555 EOP_TC_MD_ACTION_EN)) | 2556 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2557 EVENT_INDEX(5))); 2558 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2559 2560 /* 2561 * the address should be Qword aligned if 64bit write, Dword 2562 * aligned if only send 32bit data low (discard data high) 2563 */ 2564 if (write64bit) 2565 BUG_ON(addr & 0x7); 2566 else 2567 BUG_ON(addr & 0x3); 2568 amdgpu_ring_write(ring, lower_32_bits(addr)); 2569 amdgpu_ring_write(ring, upper_32_bits(addr)); 2570 amdgpu_ring_write(ring, lower_32_bits(seq)); 2571 amdgpu_ring_write(ring, upper_32_bits(seq)); 2572 amdgpu_ring_write(ring, 0); 2573 } 2574 2575 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2576 { 2577 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2578 uint32_t seq = ring->fence_drv.sync_seq; 2579 uint64_t addr = ring->fence_drv.gpu_addr; 2580 2581 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2582 lower_32_bits(addr), upper_32_bits(addr), 2583 seq, 0xffffffff, 4); 2584 } 2585 2586 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2587 unsigned vmid, uint64_t pd_addr) 2588 { 2589 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2590 } 2591 2592 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2593 { 2594 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2595 } 2596 2597 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2598 { 2599 u64 wptr; 2600 2601 /* XXX check if swapping is necessary on BE */ 2602 if (ring->use_doorbell) 2603 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2604 else 2605 BUG(); 2606 return wptr; 2607 } 2608 2609 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2610 { 2611 struct amdgpu_device *adev = ring->adev; 2612 2613 /* XXX check if swapping is necessary on BE */ 2614 if (ring->use_doorbell) { 2615 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2616 WDOORBELL64(ring->doorbell_index, ring->wptr); 2617 } else { 2618 BUG(); /* only DOORBELL method supported on gfx9 now */ 2619 } 2620 } 2621 2622 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2623 u64 seq, unsigned int flags) 2624 { 2625 struct amdgpu_device *adev = ring->adev; 2626 2627 /* we only allocate 32bit for each seq wb address */ 2628 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2629 2630 /* write fence seq to the "addr" */ 2631 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2632 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2633 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2634 amdgpu_ring_write(ring, lower_32_bits(addr)); 2635 amdgpu_ring_write(ring, upper_32_bits(addr)); 2636 amdgpu_ring_write(ring, lower_32_bits(seq)); 2637 2638 if (flags & AMDGPU_FENCE_FLAG_INT) { 2639 /* set register to trigger INT */ 2640 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2641 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2642 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 2643 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 2644 amdgpu_ring_write(ring, 0); 2645 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 2646 } 2647 } 2648 2649 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 2650 uint32_t reg_val_offs) 2651 { 2652 struct amdgpu_device *adev = ring->adev; 2653 2654 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 2655 amdgpu_ring_write(ring, 0 | /* src: register*/ 2656 (5 << 8) | /* dst: memory */ 2657 (1 << 20)); /* write confirm */ 2658 amdgpu_ring_write(ring, reg); 2659 amdgpu_ring_write(ring, 0); 2660 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 2661 reg_val_offs * 4)); 2662 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 2663 reg_val_offs * 4)); 2664 } 2665 2666 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 2667 uint32_t val) 2668 { 2669 uint32_t cmd = 0; 2670 2671 switch (ring->funcs->type) { 2672 case AMDGPU_RING_TYPE_GFX: 2673 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 2674 break; 2675 case AMDGPU_RING_TYPE_KIQ: 2676 cmd = (1 << 16); /* no inc addr */ 2677 break; 2678 default: 2679 cmd = WR_CONFIRM; 2680 break; 2681 } 2682 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2683 amdgpu_ring_write(ring, cmd); 2684 amdgpu_ring_write(ring, reg); 2685 amdgpu_ring_write(ring, 0); 2686 amdgpu_ring_write(ring, val); 2687 } 2688 2689 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 2690 uint32_t val, uint32_t mask) 2691 { 2692 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 2693 } 2694 2695 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 2696 uint32_t reg0, uint32_t reg1, 2697 uint32_t ref, uint32_t mask) 2698 { 2699 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 2700 ref, mask); 2701 } 2702 2703 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2704 struct amdgpu_device *adev, int me, int pipe, 2705 enum amdgpu_interrupt_state state, int xcc_id) 2706 { 2707 u32 mec_int_cntl, mec_int_cntl_reg; 2708 2709 /* 2710 * amdgpu controls only the first MEC. That's why this function only 2711 * handles the setting of interrupts for this specific MEC. All other 2712 * pipes' interrupts are set by amdkfd. 2713 */ 2714 2715 if (me == 1) { 2716 switch (pipe) { 2717 case 0: 2718 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 2719 break; 2720 case 1: 2721 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 2722 break; 2723 case 2: 2724 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 2725 break; 2726 case 3: 2727 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 2728 break; 2729 default: 2730 DRM_DEBUG("invalid pipe %d\n", pipe); 2731 return; 2732 } 2733 } else { 2734 DRM_DEBUG("invalid me %d\n", me); 2735 return; 2736 } 2737 2738 switch (state) { 2739 case AMDGPU_IRQ_STATE_DISABLE: 2740 mec_int_cntl = RREG32(mec_int_cntl_reg); 2741 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2742 TIME_STAMP_INT_ENABLE, 0); 2743 WREG32(mec_int_cntl_reg, mec_int_cntl); 2744 break; 2745 case AMDGPU_IRQ_STATE_ENABLE: 2746 mec_int_cntl = RREG32(mec_int_cntl_reg); 2747 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2748 TIME_STAMP_INT_ENABLE, 1); 2749 WREG32(mec_int_cntl_reg, mec_int_cntl); 2750 break; 2751 default: 2752 break; 2753 } 2754 } 2755 2756 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 2757 struct amdgpu_irq_src *source, 2758 unsigned type, 2759 enum amdgpu_interrupt_state state) 2760 { 2761 int i, num_xcc; 2762 2763 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2764 switch (state) { 2765 case AMDGPU_IRQ_STATE_DISABLE: 2766 case AMDGPU_IRQ_STATE_ENABLE: 2767 for (i = 0; i < num_xcc; i++) 2768 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2769 PRIV_REG_INT_ENABLE, 2770 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2771 break; 2772 default: 2773 break; 2774 } 2775 2776 return 0; 2777 } 2778 2779 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 2780 struct amdgpu_irq_src *source, 2781 unsigned type, 2782 enum amdgpu_interrupt_state state) 2783 { 2784 int i, num_xcc; 2785 2786 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2787 switch (state) { 2788 case AMDGPU_IRQ_STATE_DISABLE: 2789 case AMDGPU_IRQ_STATE_ENABLE: 2790 for (i = 0; i < num_xcc; i++) 2791 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2792 PRIV_INSTR_INT_ENABLE, 2793 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2794 break; 2795 default: 2796 break; 2797 } 2798 2799 return 0; 2800 } 2801 2802 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 2803 struct amdgpu_irq_src *src, 2804 unsigned type, 2805 enum amdgpu_interrupt_state state) 2806 { 2807 int i, num_xcc; 2808 2809 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2810 for (i = 0; i < num_xcc; i++) { 2811 switch (type) { 2812 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 2813 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2814 adev, 1, 0, state, i); 2815 break; 2816 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 2817 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2818 adev, 1, 1, state, i); 2819 break; 2820 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 2821 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2822 adev, 1, 2, state, i); 2823 break; 2824 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 2825 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2826 adev, 1, 3, state, i); 2827 break; 2828 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 2829 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2830 adev, 2, 0, state, i); 2831 break; 2832 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 2833 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2834 adev, 2, 1, state, i); 2835 break; 2836 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 2837 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2838 adev, 2, 2, state, i); 2839 break; 2840 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 2841 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2842 adev, 2, 3, state, i); 2843 break; 2844 default: 2845 break; 2846 } 2847 } 2848 2849 return 0; 2850 } 2851 2852 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 2853 struct amdgpu_irq_src *source, 2854 struct amdgpu_iv_entry *entry) 2855 { 2856 int i, xcc_id; 2857 u8 me_id, pipe_id, queue_id; 2858 struct amdgpu_ring *ring; 2859 2860 DRM_DEBUG("IH: CP EOP\n"); 2861 me_id = (entry->ring_id & 0x0c) >> 2; 2862 pipe_id = (entry->ring_id & 0x03) >> 0; 2863 queue_id = (entry->ring_id & 0x70) >> 4; 2864 2865 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 2866 2867 if (xcc_id == -EINVAL) 2868 return -EINVAL; 2869 2870 switch (me_id) { 2871 case 0: 2872 case 1: 2873 case 2: 2874 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2875 ring = &adev->gfx.compute_ring 2876 [i + 2877 xcc_id * adev->gfx.num_compute_rings]; 2878 /* Per-queue interrupt is supported for MEC starting from VI. 2879 * The interrupt can only be enabled/disabled per pipe instead of per queue. 2880 */ 2881 2882 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 2883 amdgpu_fence_process(ring); 2884 } 2885 break; 2886 } 2887 return 0; 2888 } 2889 2890 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 2891 struct amdgpu_iv_entry *entry) 2892 { 2893 u8 me_id, pipe_id, queue_id; 2894 struct amdgpu_ring *ring; 2895 int i, xcc_id; 2896 2897 me_id = (entry->ring_id & 0x0c) >> 2; 2898 pipe_id = (entry->ring_id & 0x03) >> 0; 2899 queue_id = (entry->ring_id & 0x70) >> 4; 2900 2901 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 2902 2903 if (xcc_id == -EINVAL) 2904 return; 2905 2906 switch (me_id) { 2907 case 0: 2908 case 1: 2909 case 2: 2910 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2911 ring = &adev->gfx.compute_ring 2912 [i + 2913 xcc_id * adev->gfx.num_compute_rings]; 2914 if (ring->me == me_id && ring->pipe == pipe_id && 2915 ring->queue == queue_id) 2916 drm_sched_fault(&ring->sched); 2917 } 2918 break; 2919 } 2920 } 2921 2922 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 2923 struct amdgpu_irq_src *source, 2924 struct amdgpu_iv_entry *entry) 2925 { 2926 DRM_ERROR("Illegal register access in command stream\n"); 2927 gfx_v9_4_3_fault(adev, entry); 2928 return 0; 2929 } 2930 2931 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 2932 struct amdgpu_irq_src *source, 2933 struct amdgpu_iv_entry *entry) 2934 { 2935 DRM_ERROR("Illegal instruction in command stream\n"); 2936 gfx_v9_4_3_fault(adev, entry); 2937 return 0; 2938 } 2939 2940 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 2941 { 2942 const unsigned int cp_coher_cntl = 2943 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 2944 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 2945 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 2946 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 2947 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 2948 2949 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 2950 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 2951 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 2952 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 2953 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 2954 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 2955 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 2956 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 2957 } 2958 2959 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 2960 uint32_t pipe, bool enable) 2961 { 2962 struct amdgpu_device *adev = ring->adev; 2963 uint32_t val; 2964 uint32_t wcl_cs_reg; 2965 2966 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 2967 val = enable ? 0x1 : 0x7f; 2968 2969 switch (pipe) { 2970 case 0: 2971 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 2972 break; 2973 case 1: 2974 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 2975 break; 2976 case 2: 2977 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 2978 break; 2979 case 3: 2980 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 2981 break; 2982 default: 2983 DRM_DEBUG("invalid pipe %d\n", pipe); 2984 return; 2985 } 2986 2987 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 2988 2989 } 2990 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 2991 { 2992 struct amdgpu_device *adev = ring->adev; 2993 uint32_t val; 2994 int i; 2995 2996 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 2997 * number of gfx waves. Setting 5 bit will make sure gfx only gets 2998 * around 25% of gpu resources. 2999 */ 3000 val = enable ? 0x1f : 0x07ffffff; 3001 amdgpu_ring_emit_wreg(ring, 3002 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 3003 val); 3004 3005 /* Restrict waves for normal/low priority compute queues as well 3006 * to get best QoS for high priority compute jobs. 3007 * 3008 * amdgpu controls only 1st ME(0-3 CS pipes). 3009 */ 3010 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3011 if (i != ring->pipe) 3012 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3013 3014 } 3015 } 3016 3017 enum amdgpu_gfx_cp_ras_mem_id { 3018 AMDGPU_GFX_CP_MEM1 = 1, 3019 AMDGPU_GFX_CP_MEM2, 3020 AMDGPU_GFX_CP_MEM3, 3021 AMDGPU_GFX_CP_MEM4, 3022 AMDGPU_GFX_CP_MEM5, 3023 }; 3024 3025 enum amdgpu_gfx_gcea_ras_mem_id { 3026 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3027 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3028 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3029 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3030 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3031 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3032 AMDGPU_GFX_GCEA_MAM_DMEM0, 3033 AMDGPU_GFX_GCEA_MAM_DMEM1, 3034 AMDGPU_GFX_GCEA_MAM_DMEM2, 3035 AMDGPU_GFX_GCEA_MAM_DMEM3, 3036 AMDGPU_GFX_GCEA_MAM_AMEM0, 3037 AMDGPU_GFX_GCEA_MAM_AMEM1, 3038 AMDGPU_GFX_GCEA_MAM_AMEM2, 3039 AMDGPU_GFX_GCEA_MAM_AMEM3, 3040 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3041 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3042 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3043 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3044 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3045 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3046 }; 3047 3048 enum amdgpu_gfx_gc_cane_ras_mem_id { 3049 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3050 }; 3051 3052 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3053 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3054 }; 3055 3056 enum amdgpu_gfx_gds_ras_mem_id { 3057 AMDGPU_GFX_GDS_MEM0 = 0, 3058 }; 3059 3060 enum amdgpu_gfx_lds_ras_mem_id { 3061 AMDGPU_GFX_LDS_BANK0 = 0, 3062 AMDGPU_GFX_LDS_BANK1, 3063 AMDGPU_GFX_LDS_BANK2, 3064 AMDGPU_GFX_LDS_BANK3, 3065 AMDGPU_GFX_LDS_BANK4, 3066 AMDGPU_GFX_LDS_BANK5, 3067 AMDGPU_GFX_LDS_BANK6, 3068 AMDGPU_GFX_LDS_BANK7, 3069 AMDGPU_GFX_LDS_BANK8, 3070 AMDGPU_GFX_LDS_BANK9, 3071 AMDGPU_GFX_LDS_BANK10, 3072 AMDGPU_GFX_LDS_BANK11, 3073 AMDGPU_GFX_LDS_BANK12, 3074 AMDGPU_GFX_LDS_BANK13, 3075 AMDGPU_GFX_LDS_BANK14, 3076 AMDGPU_GFX_LDS_BANK15, 3077 AMDGPU_GFX_LDS_BANK16, 3078 AMDGPU_GFX_LDS_BANK17, 3079 AMDGPU_GFX_LDS_BANK18, 3080 AMDGPU_GFX_LDS_BANK19, 3081 AMDGPU_GFX_LDS_BANK20, 3082 AMDGPU_GFX_LDS_BANK21, 3083 AMDGPU_GFX_LDS_BANK22, 3084 AMDGPU_GFX_LDS_BANK23, 3085 AMDGPU_GFX_LDS_BANK24, 3086 AMDGPU_GFX_LDS_BANK25, 3087 AMDGPU_GFX_LDS_BANK26, 3088 AMDGPU_GFX_LDS_BANK27, 3089 AMDGPU_GFX_LDS_BANK28, 3090 AMDGPU_GFX_LDS_BANK29, 3091 AMDGPU_GFX_LDS_BANK30, 3092 AMDGPU_GFX_LDS_BANK31, 3093 AMDGPU_GFX_LDS_SP_BUFFER_A, 3094 AMDGPU_GFX_LDS_SP_BUFFER_B, 3095 }; 3096 3097 enum amdgpu_gfx_rlc_ras_mem_id { 3098 AMDGPU_GFX_RLC_GPMF32 = 1, 3099 AMDGPU_GFX_RLC_RLCVF32, 3100 AMDGPU_GFX_RLC_SCRATCH, 3101 AMDGPU_GFX_RLC_SRM_ARAM, 3102 AMDGPU_GFX_RLC_SRM_DRAM, 3103 AMDGPU_GFX_RLC_TCTAG, 3104 AMDGPU_GFX_RLC_SPM_SE, 3105 AMDGPU_GFX_RLC_SPM_GRBMT, 3106 }; 3107 3108 enum amdgpu_gfx_sp_ras_mem_id { 3109 AMDGPU_GFX_SP_SIMDID0 = 0, 3110 }; 3111 3112 enum amdgpu_gfx_spi_ras_mem_id { 3113 AMDGPU_GFX_SPI_MEM0 = 0, 3114 AMDGPU_GFX_SPI_MEM1, 3115 AMDGPU_GFX_SPI_MEM2, 3116 AMDGPU_GFX_SPI_MEM3, 3117 }; 3118 3119 enum amdgpu_gfx_sqc_ras_mem_id { 3120 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3121 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3122 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3123 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3124 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3125 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3126 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3127 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3128 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3129 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3130 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3131 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3132 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3133 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3134 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3135 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3136 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3137 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3138 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3139 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3140 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3141 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3142 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3143 }; 3144 3145 enum amdgpu_gfx_sq_ras_mem_id { 3146 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3147 AMDGPU_GFX_SQ_SGPR_MEM1, 3148 AMDGPU_GFX_SQ_SGPR_MEM2, 3149 AMDGPU_GFX_SQ_SGPR_MEM3, 3150 }; 3151 3152 enum amdgpu_gfx_ta_ras_mem_id { 3153 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3154 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3155 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3156 AMDGPU_GFX_TA_FSX_LFIFO, 3157 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3158 }; 3159 3160 enum amdgpu_gfx_tcc_ras_mem_id { 3161 AMDGPU_GFX_TCC_MEM1 = 1, 3162 }; 3163 3164 enum amdgpu_gfx_tca_ras_mem_id { 3165 AMDGPU_GFX_TCA_MEM1 = 1, 3166 }; 3167 3168 enum amdgpu_gfx_tci_ras_mem_id { 3169 AMDGPU_GFX_TCIW_MEM = 1, 3170 }; 3171 3172 enum amdgpu_gfx_tcp_ras_mem_id { 3173 AMDGPU_GFX_TCP_LFIFO0 = 1, 3174 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3175 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3176 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3177 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3178 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3179 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3180 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3181 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3182 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3183 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3184 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3185 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3186 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3187 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3188 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3189 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3190 AMDGPU_GFX_TCP_VM_FIFO, 3191 AMDGPU_GFX_TCP_DB_TAGRAM0, 3192 AMDGPU_GFX_TCP_DB_TAGRAM1, 3193 AMDGPU_GFX_TCP_DB_TAGRAM2, 3194 AMDGPU_GFX_TCP_DB_TAGRAM3, 3195 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3196 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3197 AMDGPU_GFX_TCP_CMD_FIFO, 3198 }; 3199 3200 enum amdgpu_gfx_td_ras_mem_id { 3201 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3202 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3203 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3204 }; 3205 3206 enum amdgpu_gfx_tcx_ras_mem_id { 3207 AMDGPU_GFX_TCX_FIFOD0 = 0, 3208 AMDGPU_GFX_TCX_FIFOD1, 3209 AMDGPU_GFX_TCX_FIFOD2, 3210 AMDGPU_GFX_TCX_FIFOD3, 3211 AMDGPU_GFX_TCX_FIFOD4, 3212 AMDGPU_GFX_TCX_FIFOD5, 3213 AMDGPU_GFX_TCX_FIFOD6, 3214 AMDGPU_GFX_TCX_FIFOD7, 3215 AMDGPU_GFX_TCX_FIFOB0, 3216 AMDGPU_GFX_TCX_FIFOB1, 3217 AMDGPU_GFX_TCX_FIFOB2, 3218 AMDGPU_GFX_TCX_FIFOB3, 3219 AMDGPU_GFX_TCX_FIFOB4, 3220 AMDGPU_GFX_TCX_FIFOB5, 3221 AMDGPU_GFX_TCX_FIFOB6, 3222 AMDGPU_GFX_TCX_FIFOB7, 3223 AMDGPU_GFX_TCX_FIFOA0, 3224 AMDGPU_GFX_TCX_FIFOA1, 3225 AMDGPU_GFX_TCX_FIFOA2, 3226 AMDGPU_GFX_TCX_FIFOA3, 3227 AMDGPU_GFX_TCX_FIFOA4, 3228 AMDGPU_GFX_TCX_FIFOA5, 3229 AMDGPU_GFX_TCX_FIFOA6, 3230 AMDGPU_GFX_TCX_FIFOA7, 3231 AMDGPU_GFX_TCX_CFIFO0, 3232 AMDGPU_GFX_TCX_CFIFO1, 3233 AMDGPU_GFX_TCX_CFIFO2, 3234 AMDGPU_GFX_TCX_CFIFO3, 3235 AMDGPU_GFX_TCX_CFIFO4, 3236 AMDGPU_GFX_TCX_CFIFO5, 3237 AMDGPU_GFX_TCX_CFIFO6, 3238 AMDGPU_GFX_TCX_CFIFO7, 3239 AMDGPU_GFX_TCX_FIFO_ACKB0, 3240 AMDGPU_GFX_TCX_FIFO_ACKB1, 3241 AMDGPU_GFX_TCX_FIFO_ACKB2, 3242 AMDGPU_GFX_TCX_FIFO_ACKB3, 3243 AMDGPU_GFX_TCX_FIFO_ACKB4, 3244 AMDGPU_GFX_TCX_FIFO_ACKB5, 3245 AMDGPU_GFX_TCX_FIFO_ACKB6, 3246 AMDGPU_GFX_TCX_FIFO_ACKB7, 3247 AMDGPU_GFX_TCX_FIFO_ACKD0, 3248 AMDGPU_GFX_TCX_FIFO_ACKD1, 3249 AMDGPU_GFX_TCX_FIFO_ACKD2, 3250 AMDGPU_GFX_TCX_FIFO_ACKD3, 3251 AMDGPU_GFX_TCX_FIFO_ACKD4, 3252 AMDGPU_GFX_TCX_FIFO_ACKD5, 3253 AMDGPU_GFX_TCX_FIFO_ACKD6, 3254 AMDGPU_GFX_TCX_FIFO_ACKD7, 3255 AMDGPU_GFX_TCX_DST_FIFOA0, 3256 AMDGPU_GFX_TCX_DST_FIFOA1, 3257 AMDGPU_GFX_TCX_DST_FIFOA2, 3258 AMDGPU_GFX_TCX_DST_FIFOA3, 3259 AMDGPU_GFX_TCX_DST_FIFOA4, 3260 AMDGPU_GFX_TCX_DST_FIFOA5, 3261 AMDGPU_GFX_TCX_DST_FIFOA6, 3262 AMDGPU_GFX_TCX_DST_FIFOA7, 3263 AMDGPU_GFX_TCX_DST_FIFOB0, 3264 AMDGPU_GFX_TCX_DST_FIFOB1, 3265 AMDGPU_GFX_TCX_DST_FIFOB2, 3266 AMDGPU_GFX_TCX_DST_FIFOB3, 3267 AMDGPU_GFX_TCX_DST_FIFOB4, 3268 AMDGPU_GFX_TCX_DST_FIFOB5, 3269 AMDGPU_GFX_TCX_DST_FIFOB6, 3270 AMDGPU_GFX_TCX_DST_FIFOB7, 3271 AMDGPU_GFX_TCX_DST_FIFOD0, 3272 AMDGPU_GFX_TCX_DST_FIFOD1, 3273 AMDGPU_GFX_TCX_DST_FIFOD2, 3274 AMDGPU_GFX_TCX_DST_FIFOD3, 3275 AMDGPU_GFX_TCX_DST_FIFOD4, 3276 AMDGPU_GFX_TCX_DST_FIFOD5, 3277 AMDGPU_GFX_TCX_DST_FIFOD6, 3278 AMDGPU_GFX_TCX_DST_FIFOD7, 3279 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 3280 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 3281 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 3282 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 3283 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 3284 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 3285 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 3286 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 3287 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 3288 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 3289 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 3290 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 3291 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 3292 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 3293 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 3294 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 3295 }; 3296 3297 enum amdgpu_gfx_atc_l2_ras_mem_id { 3298 AMDGPU_GFX_ATC_L2_MEM0 = 0, 3299 }; 3300 3301 enum amdgpu_gfx_utcl2_ras_mem_id { 3302 AMDGPU_GFX_UTCL2_MEM0 = 0, 3303 }; 3304 3305 enum amdgpu_gfx_vml2_ras_mem_id { 3306 AMDGPU_GFX_VML2_MEM0 = 0, 3307 }; 3308 3309 enum amdgpu_gfx_vml2_walker_ras_mem_id { 3310 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 3311 }; 3312 3313 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 3314 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 3315 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 3316 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 3317 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 3318 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 3319 }; 3320 3321 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 3322 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 3323 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 3324 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 3325 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 3326 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 3327 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 3328 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 3329 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 3330 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 3331 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 3332 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 3333 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 3334 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 3335 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 3336 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 3337 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 3338 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 3339 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 3340 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 3341 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 3342 }; 3343 3344 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 3345 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 3346 }; 3347 3348 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 3349 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 3350 }; 3351 3352 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 3353 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 3354 }; 3355 3356 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 3357 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 3358 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 3359 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 3360 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 3361 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 3362 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 3363 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 3364 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 3365 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 3366 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 3367 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 3368 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 3369 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 3370 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 3371 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 3372 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 3373 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 3374 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 3375 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 3376 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 3377 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 3378 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 3379 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 3380 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 3381 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 3382 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 3383 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 3384 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 3385 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 3386 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 3387 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 3388 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 3389 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 3390 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 3391 }; 3392 3393 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 3394 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 3395 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 3396 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 3397 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 3398 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 3399 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 3400 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 3401 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 3402 }; 3403 3404 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 3405 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 3406 }; 3407 3408 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 3409 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 3410 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 3411 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 3412 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 3413 }; 3414 3415 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 3416 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 3417 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 3418 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 3419 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 3420 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 3421 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 3422 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 3423 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 3424 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 3425 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 3426 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 3427 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 3428 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 3429 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 3430 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 3431 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 3432 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 3433 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 3434 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 3435 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 3436 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 3437 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 3438 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 3439 }; 3440 3441 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 3442 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 3443 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 3444 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 3445 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 3446 }; 3447 3448 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 3449 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 3450 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 3451 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 3452 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 3453 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 3454 }; 3455 3456 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 3457 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 3458 }; 3459 3460 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 3461 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 3462 }; 3463 3464 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 3465 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 3466 }; 3467 3468 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 3469 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 3470 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 3471 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 3472 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 3473 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 3474 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 3475 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 3476 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 3477 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 3478 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 3479 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 3480 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 3481 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 3482 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 3483 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 3484 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 3485 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 3486 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 3487 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 3488 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 3489 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 3490 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 3491 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 3492 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 3493 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 3494 }; 3495 3496 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 3497 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 3498 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 3499 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 3500 }; 3501 3502 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 3503 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 3504 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 3505 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 3506 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 3507 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 3508 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 3509 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 3510 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 3511 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 3512 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 3513 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 3514 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 3515 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 3516 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 3517 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 3518 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 3519 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 3520 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 3521 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 3522 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 3523 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 3524 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 3525 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 3526 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 3527 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 3528 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 3529 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 3530 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 3531 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 3532 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 3533 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 3534 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 3535 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 3536 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 3537 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 3538 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 3539 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 3540 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 3541 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 3542 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 3543 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 3544 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 3545 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 3546 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 3547 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 3548 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 3549 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 3550 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 3551 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 3552 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 3553 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 3554 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 3555 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 3556 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 3557 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 3558 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 3559 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 3560 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 3561 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 3562 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 3563 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 3564 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 3565 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 3566 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 3567 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 3568 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 3569 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 3570 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 3571 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 3572 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 3573 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 3574 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 3575 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 3576 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 3577 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 3578 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 3579 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 3580 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 3581 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 3582 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 3583 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 3584 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 3585 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 3586 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 3587 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 3588 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 3589 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 3590 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 3591 }; 3592 3593 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 3594 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 3595 }; 3596 3597 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 3598 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 3599 }; 3600 3601 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 3602 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 3603 }; 3604 3605 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 3606 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 3607 }; 3608 3609 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 3610 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 3611 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 3612 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 3613 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 3614 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 3615 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 3616 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 3617 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 3618 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 3619 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 3620 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 3621 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 3622 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 3623 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 3624 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 3625 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 3626 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 3627 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 3628 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 3629 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 3630 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 3631 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 3632 }; 3633 3634 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 3635 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 3636 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 3637 AMDGPU_GFX_RLC_MEM, 1}, 3638 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 3639 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 3640 AMDGPU_GFX_CP_MEM, 1}, 3641 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 3642 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 3643 AMDGPU_GFX_CP_MEM, 1}, 3644 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 3645 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 3646 AMDGPU_GFX_CP_MEM, 1}, 3647 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 3648 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 3649 AMDGPU_GFX_GDS_MEM, 1}, 3650 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 3651 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 3652 AMDGPU_GFX_GC_CANE_MEM, 1}, 3653 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 3654 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 3655 AMDGPU_GFX_SPI_MEM, 1}, 3656 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 3657 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 3658 AMDGPU_GFX_SP_MEM, 4}, 3659 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 3660 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 3661 AMDGPU_GFX_SP_MEM, 4}, 3662 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 3663 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 3664 AMDGPU_GFX_SQ_MEM, 4}, 3665 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 3666 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 3667 AMDGPU_GFX_SQC_MEM, 4}, 3668 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 3669 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 3670 AMDGPU_GFX_TCX_MEM, 1}, 3671 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 3672 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 3673 AMDGPU_GFX_TCC_MEM, 1}, 3674 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 3675 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 3676 AMDGPU_GFX_TA_MEM, 4}, 3677 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 3678 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 3679 AMDGPU_GFX_TCI_MEM, 1}, 3680 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 3681 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 3682 AMDGPU_GFX_TCP_MEM, 4}, 3683 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 3684 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 3685 AMDGPU_GFX_TD_MEM, 4}, 3686 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 3687 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 3688 AMDGPU_GFX_GCEA_MEM, 1}, 3689 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 3690 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 3691 AMDGPU_GFX_LDS_MEM, 4}, 3692 }; 3693 3694 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 3695 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 3696 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 3697 AMDGPU_GFX_RLC_MEM, 1}, 3698 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 3699 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 3700 AMDGPU_GFX_CP_MEM, 1}, 3701 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 3702 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 3703 AMDGPU_GFX_CP_MEM, 1}, 3704 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 3705 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 3706 AMDGPU_GFX_CP_MEM, 1}, 3707 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 3708 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 3709 AMDGPU_GFX_GDS_MEM, 1}, 3710 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 3711 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 3712 AMDGPU_GFX_GC_CANE_MEM, 1}, 3713 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 3714 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 3715 AMDGPU_GFX_SPI_MEM, 1}, 3716 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 3717 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 3718 AMDGPU_GFX_SP_MEM, 4}, 3719 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 3720 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 3721 AMDGPU_GFX_SP_MEM, 4}, 3722 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 3723 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 3724 AMDGPU_GFX_SQ_MEM, 4}, 3725 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 3726 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 3727 AMDGPU_GFX_SQC_MEM, 4}, 3728 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 3729 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 3730 AMDGPU_GFX_TCX_MEM, 1}, 3731 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 3732 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 3733 AMDGPU_GFX_TCC_MEM, 1}, 3734 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 3735 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 3736 AMDGPU_GFX_TA_MEM, 4}, 3737 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 3738 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 3739 AMDGPU_GFX_TCI_MEM, 1}, 3740 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 3741 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 3742 AMDGPU_GFX_TCP_MEM, 4}, 3743 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 3744 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 3745 AMDGPU_GFX_TD_MEM, 4}, 3746 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 3747 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 3748 AMDGPU_GFX_TCA_MEM, 1}, 3749 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 3750 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 3751 AMDGPU_GFX_GCEA_MEM, 1}, 3752 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 3753 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 3754 AMDGPU_GFX_LDS_MEM, 4}, 3755 }; 3756 3757 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 3758 void *ras_error_status, int xcc_id) 3759 { 3760 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 3761 unsigned long ce_count = 0, ue_count = 0; 3762 uint32_t i, j, k; 3763 3764 /* NOTE: convert xcc_id to physical XCD ID (XCD0 or XCD1) */ 3765 struct amdgpu_smuio_mcm_config_info mcm_info = { 3766 .socket_id = adev->smuio.funcs->get_socket_id(adev), 3767 .die_id = xcc_id & 0x01 ? 1 : 0, 3768 }; 3769 3770 mutex_lock(&adev->grbm_idx_mutex); 3771 3772 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 3773 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 3774 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 3775 /* no need to select if instance number is 1 */ 3776 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 3777 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 3778 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3779 3780 amdgpu_ras_inst_query_ras_error_count(adev, 3781 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 3782 1, 3783 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 3784 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 3785 GET_INST(GC, xcc_id), 3786 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 3787 &ce_count); 3788 3789 amdgpu_ras_inst_query_ras_error_count(adev, 3790 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3791 1, 3792 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 3793 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 3794 GET_INST(GC, xcc_id), 3795 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 3796 &ue_count); 3797 } 3798 } 3799 } 3800 3801 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3802 xcc_id); 3803 mutex_unlock(&adev->grbm_idx_mutex); 3804 3805 /* the caller should make sure initialize value of 3806 * err_data->ue_count and err_data->ce_count 3807 */ 3808 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 3809 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, ce_count); 3810 } 3811 3812 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 3813 void *ras_error_status, int xcc_id) 3814 { 3815 uint32_t i, j, k; 3816 3817 mutex_lock(&adev->grbm_idx_mutex); 3818 3819 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 3820 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 3821 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 3822 /* no need to select if instance number is 1 */ 3823 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 3824 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 3825 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3826 3827 amdgpu_ras_inst_reset_ras_error_count(adev, 3828 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 3829 1, 3830 GET_INST(GC, xcc_id)); 3831 3832 amdgpu_ras_inst_reset_ras_error_count(adev, 3833 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3834 1, 3835 GET_INST(GC, xcc_id)); 3836 } 3837 } 3838 } 3839 3840 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3841 xcc_id); 3842 mutex_unlock(&adev->grbm_idx_mutex); 3843 } 3844 3845 static void gfx_v9_4_3_inst_query_utc_err_status(struct amdgpu_device *adev, 3846 int xcc_id) 3847 { 3848 uint32_t data; 3849 3850 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS); 3851 if (data) { 3852 dev_warn(adev->dev, "GFX UTCL2 Mem Ecc Status: 0x%x!\n", data); 3853 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS, 0x3); 3854 } 3855 3856 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS); 3857 if (data) { 3858 dev_warn(adev->dev, "GFX VML2 Mem Ecc Status: 0x%x!\n", data); 3859 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS, 0x3); 3860 } 3861 3862 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3863 regVML2_WALKER_MEM_ECC_STATUS); 3864 if (data) { 3865 dev_warn(adev->dev, "GFX VML2 Walker Mem Ecc Status: 0x%x!\n", data); 3866 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS, 3867 0x3); 3868 } 3869 } 3870 3871 static void gfx_v9_4_3_log_cu_timeout_status(struct amdgpu_device *adev, 3872 uint32_t status, int xcc_id) 3873 { 3874 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 3875 uint32_t i, simd, wave; 3876 uint32_t wave_status; 3877 uint32_t wave_pc_lo, wave_pc_hi; 3878 uint32_t wave_exec_lo, wave_exec_hi; 3879 uint32_t wave_inst_dw0, wave_inst_dw1; 3880 uint32_t wave_ib_sts; 3881 3882 for (i = 0; i < 32; i++) { 3883 if (!((i << 1) & status)) 3884 continue; 3885 3886 simd = i / cu_info->max_waves_per_simd; 3887 wave = i % cu_info->max_waves_per_simd; 3888 3889 wave_status = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 3890 wave_pc_lo = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 3891 wave_pc_hi = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 3892 wave_exec_lo = 3893 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 3894 wave_exec_hi = 3895 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 3896 wave_inst_dw0 = 3897 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 3898 wave_inst_dw1 = 3899 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 3900 wave_ib_sts = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 3901 3902 dev_info( 3903 adev->dev, 3904 "\t SIMD %d, Wave %d: status 0x%x, pc 0x%llx, exec 0x%llx, inst 0x%llx, ib_sts 0x%x\n", 3905 simd, wave, wave_status, 3906 ((uint64_t)wave_pc_hi << 32 | wave_pc_lo), 3907 ((uint64_t)wave_exec_hi << 32 | wave_exec_lo), 3908 ((uint64_t)wave_inst_dw1 << 32 | wave_inst_dw0), 3909 wave_ib_sts); 3910 } 3911 } 3912 3913 static void gfx_v9_4_3_inst_query_sq_timeout_status(struct amdgpu_device *adev, 3914 int xcc_id) 3915 { 3916 uint32_t se_idx, sh_idx, cu_idx; 3917 uint32_t status; 3918 3919 mutex_lock(&adev->grbm_idx_mutex); 3920 for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; se_idx++) { 3921 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) { 3922 for (cu_idx = 0; cu_idx < adev->gfx.config.max_cu_per_sh; cu_idx++) { 3923 gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx, 3924 cu_idx, xcc_id); 3925 status = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3926 regSQ_TIMEOUT_STATUS); 3927 if (status != 0) { 3928 dev_info( 3929 adev->dev, 3930 "GFX Watchdog Timeout: SE %d, SH %d, CU %d\n", 3931 se_idx, sh_idx, cu_idx); 3932 gfx_v9_4_3_log_cu_timeout_status( 3933 adev, status, xcc_id); 3934 } 3935 /* clear old status */ 3936 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 3937 regSQ_TIMEOUT_STATUS, 0); 3938 } 3939 } 3940 } 3941 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3942 xcc_id); 3943 mutex_unlock(&adev->grbm_idx_mutex); 3944 } 3945 3946 static void gfx_v9_4_3_inst_query_ras_err_status(struct amdgpu_device *adev, 3947 void *ras_error_status, int xcc_id) 3948 { 3949 gfx_v9_4_3_inst_query_utc_err_status(adev, xcc_id); 3950 gfx_v9_4_3_inst_query_sq_timeout_status(adev, xcc_id); 3951 } 3952 3953 static void gfx_v9_4_3_inst_reset_utc_err_status(struct amdgpu_device *adev, 3954 int xcc_id) 3955 { 3956 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS, 0x3); 3957 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS, 0x3); 3958 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS, 0x3); 3959 } 3960 3961 static void gfx_v9_4_3_inst_reset_sq_timeout_status(struct amdgpu_device *adev, 3962 int xcc_id) 3963 { 3964 uint32_t se_idx, sh_idx, cu_idx; 3965 3966 mutex_lock(&adev->grbm_idx_mutex); 3967 for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; se_idx++) { 3968 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) { 3969 for (cu_idx = 0; cu_idx < adev->gfx.config.max_cu_per_sh; cu_idx++) { 3970 gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx, 3971 cu_idx, xcc_id); 3972 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 3973 regSQ_TIMEOUT_STATUS, 0); 3974 } 3975 } 3976 } 3977 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3978 xcc_id); 3979 mutex_unlock(&adev->grbm_idx_mutex); 3980 } 3981 3982 static void gfx_v9_4_3_inst_reset_ras_err_status(struct amdgpu_device *adev, 3983 void *ras_error_status, int xcc_id) 3984 { 3985 gfx_v9_4_3_inst_reset_utc_err_status(adev, xcc_id); 3986 gfx_v9_4_3_inst_reset_sq_timeout_status(adev, xcc_id); 3987 } 3988 3989 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 3990 void *ras_error_status, int xcc_id) 3991 { 3992 uint32_t i; 3993 uint32_t data; 3994 3995 data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG); 3996 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 3997 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 3998 3999 if (amdgpu_watchdog_timer.timeout_fatal_disable && 4000 (amdgpu_watchdog_timer.period < 1 || 4001 amdgpu_watchdog_timer.period > 0x23)) { 4002 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 4003 amdgpu_watchdog_timer.period = 0x23; 4004 } 4005 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 4006 amdgpu_watchdog_timer.period); 4007 4008 mutex_lock(&adev->grbm_idx_mutex); 4009 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4010 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 4011 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 4012 } 4013 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4014 xcc_id); 4015 mutex_unlock(&adev->grbm_idx_mutex); 4016 } 4017 4018 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 4019 void *ras_error_status) 4020 { 4021 amdgpu_gfx_ras_error_func(adev, ras_error_status, 4022 gfx_v9_4_3_inst_query_ras_err_count); 4023 } 4024 4025 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 4026 { 4027 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 4028 } 4029 4030 static void gfx_v9_4_3_query_ras_error_status(struct amdgpu_device *adev) 4031 { 4032 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_query_ras_err_status); 4033 } 4034 4035 static void gfx_v9_4_3_reset_ras_error_status(struct amdgpu_device *adev) 4036 { 4037 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_status); 4038 } 4039 4040 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 4041 { 4042 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 4043 } 4044 4045 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 4046 .name = "gfx_v9_4_3", 4047 .early_init = gfx_v9_4_3_early_init, 4048 .late_init = gfx_v9_4_3_late_init, 4049 .sw_init = gfx_v9_4_3_sw_init, 4050 .sw_fini = gfx_v9_4_3_sw_fini, 4051 .hw_init = gfx_v9_4_3_hw_init, 4052 .hw_fini = gfx_v9_4_3_hw_fini, 4053 .suspend = gfx_v9_4_3_suspend, 4054 .resume = gfx_v9_4_3_resume, 4055 .is_idle = gfx_v9_4_3_is_idle, 4056 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4057 .soft_reset = gfx_v9_4_3_soft_reset, 4058 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4059 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4060 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4061 }; 4062 4063 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4064 .type = AMDGPU_RING_TYPE_COMPUTE, 4065 .align_mask = 0xff, 4066 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4067 .support_64bit_ptrs = true, 4068 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4069 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4070 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4071 .emit_frame_size = 4072 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4073 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4074 5 + /* hdp invalidate */ 4075 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4076 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4077 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4078 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4079 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4080 7 + /* gfx_v9_4_3_emit_mem_sync */ 4081 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4082 15, /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4083 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4084 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4085 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4086 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4087 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4088 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4089 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4090 .test_ring = gfx_v9_4_3_ring_test_ring, 4091 .test_ib = gfx_v9_4_3_ring_test_ib, 4092 .insert_nop = amdgpu_ring_insert_nop, 4093 .pad_ib = amdgpu_ring_generic_pad_ib, 4094 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4095 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4096 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4097 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4098 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4099 }; 4100 4101 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4102 .type = AMDGPU_RING_TYPE_KIQ, 4103 .align_mask = 0xff, 4104 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4105 .support_64bit_ptrs = true, 4106 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4107 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4108 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4109 .emit_frame_size = 4110 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4111 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4112 5 + /* hdp invalidate */ 4113 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4114 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4115 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4116 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4117 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4118 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4119 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4120 .test_ring = gfx_v9_4_3_ring_test_ring, 4121 .insert_nop = amdgpu_ring_insert_nop, 4122 .pad_ib = amdgpu_ring_generic_pad_ib, 4123 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4124 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4125 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4126 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4127 }; 4128 4129 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4130 { 4131 int i, j, num_xcc; 4132 4133 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4134 for (i = 0; i < num_xcc; i++) { 4135 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4136 4137 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4138 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4139 = &gfx_v9_4_3_ring_funcs_compute; 4140 } 4141 } 4142 4143 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4144 .set = gfx_v9_4_3_set_eop_interrupt_state, 4145 .process = gfx_v9_4_3_eop_irq, 4146 }; 4147 4148 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4149 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4150 .process = gfx_v9_4_3_priv_reg_irq, 4151 }; 4152 4153 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4154 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4155 .process = gfx_v9_4_3_priv_inst_irq, 4156 }; 4157 4158 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4159 { 4160 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4161 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4162 4163 adev->gfx.priv_reg_irq.num_types = 1; 4164 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4165 4166 adev->gfx.priv_inst_irq.num_types = 1; 4167 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4168 } 4169 4170 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4171 { 4172 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4173 } 4174 4175 4176 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4177 { 4178 /* init asci gds info */ 4179 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4180 case IP_VERSION(9, 4, 3): 4181 /* 9.4.3 removed all the GDS internal memory, 4182 * only support GWS opcode in kernel, like barrier 4183 * semaphore.etc */ 4184 adev->gds.gds_size = 0; 4185 break; 4186 default: 4187 adev->gds.gds_size = 0x10000; 4188 break; 4189 } 4190 4191 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4192 case IP_VERSION(9, 4, 3): 4193 /* deprecated for 9.4.3, no usage at all */ 4194 adev->gds.gds_compute_max_wave_id = 0; 4195 break; 4196 default: 4197 /* this really depends on the chip */ 4198 adev->gds.gds_compute_max_wave_id = 0x7ff; 4199 break; 4200 } 4201 4202 adev->gds.gws_size = 64; 4203 adev->gds.oa_size = 16; 4204 } 4205 4206 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4207 u32 bitmap, int xcc_id) 4208 { 4209 u32 data; 4210 4211 if (!bitmap) 4212 return; 4213 4214 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4215 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4216 4217 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); 4218 } 4219 4220 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id) 4221 { 4222 u32 data, mask; 4223 4224 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); 4225 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); 4226 4227 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4228 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4229 4230 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4231 4232 return (~data) & mask; 4233 } 4234 4235 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4236 struct amdgpu_cu_info *cu_info) 4237 { 4238 int i, j, k, counter, xcc_id, active_cu_number = 0; 4239 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 4240 unsigned disable_masks[4 * 4]; 4241 4242 if (!adev || !cu_info) 4243 return -EINVAL; 4244 4245 /* 4246 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4247 */ 4248 if (adev->gfx.config.max_shader_engines * 4249 adev->gfx.config.max_sh_per_se > 16) 4250 return -EINVAL; 4251 4252 amdgpu_gfx_parse_disable_cu(disable_masks, 4253 adev->gfx.config.max_shader_engines, 4254 adev->gfx.config.max_sh_per_se); 4255 4256 mutex_lock(&adev->grbm_idx_mutex); 4257 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 4258 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4259 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4260 mask = 1; 4261 ao_bitmap = 0; 4262 counter = 0; 4263 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 4264 gfx_v9_4_3_set_user_cu_inactive_bitmap( 4265 adev, 4266 disable_masks[i * adev->gfx.config.max_sh_per_se + j], 4267 xcc_id); 4268 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id); 4269 4270 cu_info->bitmap[xcc_id][i][j] = bitmap; 4271 4272 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4273 if (bitmap & mask) { 4274 if (counter < adev->gfx.config.max_cu_per_sh) 4275 ao_bitmap |= mask; 4276 counter++; 4277 } 4278 mask <<= 1; 4279 } 4280 active_cu_number += counter; 4281 if (i < 2 && j < 2) 4282 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4283 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 4284 } 4285 } 4286 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4287 xcc_id); 4288 } 4289 mutex_unlock(&adev->grbm_idx_mutex); 4290 4291 cu_info->number = active_cu_number; 4292 cu_info->ao_cu_mask = ao_cu_mask; 4293 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4294 4295 return 0; 4296 } 4297 4298 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 4299 .type = AMD_IP_BLOCK_TYPE_GFX, 4300 .major = 9, 4301 .minor = 4, 4302 .rev = 0, 4303 .funcs = &gfx_v9_4_3_ip_funcs, 4304 }; 4305 4306 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 4307 { 4308 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4309 uint32_t tmp_mask; 4310 int i, r; 4311 4312 /* TODO : Initialize golden regs */ 4313 /* gfx_v9_4_3_init_golden_registers(adev); */ 4314 4315 tmp_mask = inst_mask; 4316 for_each_inst(i, tmp_mask) 4317 gfx_v9_4_3_xcc_constants_init(adev, i); 4318 4319 if (!amdgpu_sriov_vf(adev)) { 4320 tmp_mask = inst_mask; 4321 for_each_inst(i, tmp_mask) { 4322 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 4323 if (r) 4324 return r; 4325 } 4326 } 4327 4328 tmp_mask = inst_mask; 4329 for_each_inst(i, tmp_mask) { 4330 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 4331 if (r) 4332 return r; 4333 } 4334 4335 return 0; 4336 } 4337 4338 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 4339 { 4340 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4341 int i; 4342 4343 for_each_inst(i, inst_mask) 4344 gfx_v9_4_3_xcc_fini(adev, i); 4345 4346 return 0; 4347 } 4348 4349 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 4350 .suspend = &gfx_v9_4_3_xcp_suspend, 4351 .resume = &gfx_v9_4_3_xcp_resume 4352 }; 4353 4354 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 4355 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 4356 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 4357 .query_ras_error_status = &gfx_v9_4_3_query_ras_error_status, 4358 .reset_ras_error_status = &gfx_v9_4_3_reset_ras_error_status, 4359 }; 4360 4361 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 4362 .ras_block = { 4363 .hw_ops = &gfx_v9_4_3_ras_ops, 4364 }, 4365 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 4366 }; 4367