1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "nv.h" 33 #include "nvd.h" 34 35 #include "gc/gc_10_1_0_offset.h" 36 #include "gc/gc_10_1_0_sh_mask.h" 37 #include "smuio/smuio_11_0_0_offset.h" 38 #include "smuio/smuio_11_0_0_sh_mask.h" 39 #include "navi10_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15d.h" 44 #include "soc15_common.h" 45 #include "clearstate_gfx10.h" 46 #include "v10_structs.h" 47 #include "gfx_v10_0.h" 48 #include "gfx_v10_0_cleaner_shader.h" 49 #include "nbio_v2_3.h" 50 51 /* 52 * Navi10 has two graphic rings to share each graphic pipe. 53 * 1. Primary ring 54 * 2. Async ring 55 */ 56 #define GFX10_NUM_GFX_RINGS_NV1X 1 57 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2 58 #define GFX10_MEC_HPD_SIZE 2048 59 60 #define F32_CE_PROGRAM_RAM_SIZE 65536 61 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 62 63 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 64 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 65 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 66 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 67 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 68 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 69 70 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 71 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 72 73 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006 74 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1 75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007 76 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1 77 78 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 79 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 80 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 81 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 83 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 85 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 87 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 89 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 91 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 93 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 95 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 97 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 99 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 101 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 102 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 104 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 105 106 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish 0x0105 107 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX 1 108 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish 0x0106 109 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX 1 110 111 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 112 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 113 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 114 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1 115 116 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d 117 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1 118 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e 119 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1 120 121 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 122 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 123 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 124 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 125 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 126 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 127 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 128 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 129 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 130 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 131 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 132 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 133 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 134 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 135 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 136 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 137 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580 138 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0 139 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL 140 141 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 142 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 143 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 144 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 145 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 146 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 147 #define mmCP_HYP_CE_UCODE_DATA 0x5819 148 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 149 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 150 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 151 #define mmCP_HYP_ME_UCODE_DATA 0x5817 152 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 153 154 #define mmCPG_PSP_DEBUG 0x5c10 155 #define mmCPG_PSP_DEBUG_BASE_IDX 1 156 #define mmCPC_PSP_DEBUG 0x5c11 157 #define mmCPC_PSP_DEBUG_BASE_IDX 1 158 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 159 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 160 161 //CC_GC_SA_UNIT_DISABLE 162 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 163 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 164 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 165 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 166 //GC_USER_SA_UNIT_DISABLE 167 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 168 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 169 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 170 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 171 //PA_SC_ENHANCE_3 172 #define mmPA_SC_ENHANCE_3 0x1085 173 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 174 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 175 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 176 177 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 178 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 179 180 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 181 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 182 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 183 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 184 185 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 186 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 187 188 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5 189 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1 190 191 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 192 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 193 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 194 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 195 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 196 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 197 198 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 199 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 200 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 201 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 202 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 203 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 204 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 205 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 206 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 207 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 208 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 209 210 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 211 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 212 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 213 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 214 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 215 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 216 217 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 218 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 219 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 220 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 221 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 222 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 223 224 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 225 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 226 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 227 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 228 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 229 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 230 231 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 232 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 233 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 234 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 235 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 236 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 237 238 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 239 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 240 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 241 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 242 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 243 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 244 245 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin"); 246 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin"); 247 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin"); 248 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin"); 249 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin"); 250 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin"); 251 252 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin"); 253 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin"); 254 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin"); 255 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin"); 256 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin"); 257 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin"); 258 259 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin"); 260 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin"); 261 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin"); 262 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin"); 263 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin"); 264 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin"); 265 266 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin"); 267 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin"); 268 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin"); 269 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin"); 270 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin"); 271 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin"); 272 273 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin"); 274 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin"); 275 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin"); 276 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin"); 277 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin"); 278 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin"); 279 280 static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = { 281 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS), 282 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2), 283 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3), 284 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1), 285 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2), 286 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1), 287 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1), 288 SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT), 289 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT), 290 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT), 291 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2), 292 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2), 293 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS), 294 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR), 295 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0), 296 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE), 297 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR), 298 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR), 299 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE), 300 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR), 301 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR), 302 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE), 303 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR), 304 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR), 305 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE), 306 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR), 307 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR), 308 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ), 309 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ), 310 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ), 311 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ), 312 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO), 313 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI), 314 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ), 315 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO), 316 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI), 317 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ), 318 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO), 319 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI), 320 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ), 321 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO), 322 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI), 323 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ), 324 SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS), 325 SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS), 326 SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS), 327 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT), 328 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT), 329 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS), 330 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2), 331 SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS), 332 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS), 333 SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS), 334 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS), 335 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS), 336 SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS), 337 SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS), 338 SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS), 339 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL), 340 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS), 341 SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG), 342 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL), 343 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL), 344 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR), 345 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR), 346 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR), 347 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR), 348 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR), 349 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR), 350 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR), 351 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS), 352 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT), 353 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND), 354 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE), 355 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1), 356 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2), 357 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3), 358 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4), 359 SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE), 360 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE), 361 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE), 362 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2), 363 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS), 364 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS), 365 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT), 366 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6), 367 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A), 368 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B), 369 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR), 370 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST), 371 /* cp header registers */ 372 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 373 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 374 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP), 375 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 376 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 377 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP), 378 /* SE status registers */ 379 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0), 380 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1), 381 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2), 382 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3) 383 }; 384 385 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_10[] = { 386 /* compute registers */ 387 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID), 388 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE), 389 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY), 390 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY), 391 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM), 392 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE), 393 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI), 394 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR), 395 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), 396 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), 397 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), 398 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL), 399 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR), 400 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI), 401 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR), 402 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL), 403 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), 404 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR), 405 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI), 406 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL), 407 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR), 408 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR), 409 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS), 410 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO), 411 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI), 412 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL), 413 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET), 414 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE), 415 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET), 416 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE), 417 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE), 418 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR), 419 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM), 420 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO), 421 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI), 422 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 423 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 424 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET), 425 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS) 426 }; 427 428 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = { 429 /* gfx queue registers */ 430 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_ACTIVE), 431 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY), 432 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE), 433 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE_HI), 434 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_OFFSET), 435 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CSMD_RPTR), 436 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR), 437 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR_HI), 438 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_DEQUEUE_REQUEST), 439 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_MAPPED), 440 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUE_MGR_CONTROL), 441 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0), 442 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_STATUS0), 443 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO), 444 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI), 445 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_OFFSET), 446 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_CSMD_RPTR), 447 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR), 448 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_HI), 449 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR), 450 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI), 451 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO), 452 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI) 453 }; 454 455 static const struct soc15_reg_golden golden_settings_gc_10_1[] = { 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 496 }; 497 498 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = { 499 /* Pending on emulation bring up */ 500 }; 501 502 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = { 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1555 }; 1556 1557 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = { 1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1596 }; 1597 1598 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = { 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000) 1641 }; 1642 1643 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = { 1644 /* Pending on emulation bring up */ 1645 }; 1646 1647 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = { 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2268 }; 2269 2270 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = { 2271 /* Pending on emulation bring up */ 2272 }; 2273 2274 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = { 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3327 }; 3328 3329 static const struct soc15_reg_golden golden_settings_gc_10_3[] = { 3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3373 }; 3374 3375 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = { 3376 /* Pending on emulation bring up */ 3377 }; 3378 3379 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = { 3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3421 3422 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3424 }; 3425 3426 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = { 3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3451 3452 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3454 }; 3455 3456 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = { 3457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), 3463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3477 }; 3478 3479 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = { 3480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500), 3487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3516 }; 3517 3518 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = { 3519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100), 3521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100), 3522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3551 }; 3552 3553 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = { 3554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000), 3555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e), 3556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 3557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100), 3558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000), 3559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014), 3560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8), 3562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003), 3563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 3564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 3565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 3567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210), 3568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 3569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500), 3570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff), 3571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8), 3573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130), 3574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130), 3575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 3578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f), 3579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188), 3580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009), 3581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02), 3582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000), 3583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101), 3584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 3585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 3586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000), 3587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) 3588 }; 3589 3590 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = { 3591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044), 3593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042), 3597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044), 3599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3613 }; 3614 3615 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = { 3616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041), 3622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007), 3632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3638 }; 3639 3640 #define DEFAULT_SH_MEM_CONFIG \ 3641 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3642 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3643 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3644 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3645 3646 /* TODO: pending on golden setting value of gb address config */ 3647 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044 3648 3649 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3650 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3651 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3652 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3653 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev); 3654 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3655 struct amdgpu_cu_info *cu_info); 3656 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3657 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3658 u32 sh_num, u32 instance, int xcc_id); 3659 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3660 3661 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3662 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3663 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3664 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3665 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3666 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3667 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3668 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3669 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3670 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev); 3671 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 3672 uint16_t pasid, uint32_t flush_type, 3673 bool all_hub, uint8_t dst_sel); 3674 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 3675 unsigned int vmid); 3676 3677 static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 3678 enum amd_powergating_state state); 3679 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3680 { 3681 struct amdgpu_device *adev = kiq_ring->adev; 3682 u64 shader_mc_addr; 3683 3684 /* Cleaner shader MC address */ 3685 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 3686 3687 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3688 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3689 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3690 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3691 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3692 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 3693 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 3694 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3695 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3696 } 3697 3698 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3699 struct amdgpu_ring *ring) 3700 { 3701 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3702 uint64_t wptr_addr = ring->wptr_gpu_addr; 3703 uint32_t eng_sel = 0; 3704 3705 switch (ring->funcs->type) { 3706 case AMDGPU_RING_TYPE_COMPUTE: 3707 eng_sel = 0; 3708 break; 3709 case AMDGPU_RING_TYPE_GFX: 3710 eng_sel = 4; 3711 break; 3712 case AMDGPU_RING_TYPE_MES: 3713 eng_sel = 5; 3714 break; 3715 default: 3716 WARN_ON(1); 3717 } 3718 3719 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3720 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3721 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3722 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3723 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3724 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3725 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3726 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3727 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3728 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3729 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3730 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3731 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3732 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3733 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3734 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3735 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3736 } 3737 3738 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3739 struct amdgpu_ring *ring, 3740 enum amdgpu_unmap_queues_action action, 3741 u64 gpu_addr, u64 seq) 3742 { 3743 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3744 3745 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3746 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3747 PACKET3_UNMAP_QUEUES_ACTION(action) | 3748 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3749 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3750 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3751 amdgpu_ring_write(kiq_ring, 3752 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3753 3754 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3755 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3756 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3757 amdgpu_ring_write(kiq_ring, seq); 3758 } else { 3759 amdgpu_ring_write(kiq_ring, 0); 3760 amdgpu_ring_write(kiq_ring, 0); 3761 amdgpu_ring_write(kiq_ring, 0); 3762 } 3763 } 3764 3765 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3766 struct amdgpu_ring *ring, 3767 u64 addr, 3768 u64 seq) 3769 { 3770 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3771 3772 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3773 amdgpu_ring_write(kiq_ring, 3774 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3775 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3776 PACKET3_QUERY_STATUS_COMMAND(2)); 3777 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3778 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3779 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3780 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3781 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3782 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3783 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3784 } 3785 3786 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3787 uint16_t pasid, uint32_t flush_type, 3788 bool all_hub) 3789 { 3790 gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 3791 } 3792 3793 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3794 .kiq_set_resources = gfx10_kiq_set_resources, 3795 .kiq_map_queues = gfx10_kiq_map_queues, 3796 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3797 .kiq_query_status = gfx10_kiq_query_status, 3798 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3799 .set_resources_size = 8, 3800 .map_queues_size = 7, 3801 .unmap_queues_size = 6, 3802 .query_status_size = 7, 3803 .invalidate_tlbs_size = 2, 3804 }; 3805 3806 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3807 { 3808 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs; 3809 } 3810 3811 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3812 { 3813 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3814 case IP_VERSION(10, 1, 10): 3815 soc15_program_register_sequence(adev, 3816 golden_settings_gc_rlc_spm_10_0_nv10, 3817 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3818 break; 3819 case IP_VERSION(10, 1, 1): 3820 soc15_program_register_sequence(adev, 3821 golden_settings_gc_rlc_spm_10_1_nv14, 3822 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3823 break; 3824 case IP_VERSION(10, 1, 2): 3825 soc15_program_register_sequence(adev, 3826 golden_settings_gc_rlc_spm_10_1_2_nv12, 3827 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3828 break; 3829 default: 3830 break; 3831 } 3832 } 3833 3834 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3835 { 3836 if (amdgpu_sriov_vf(adev)) 3837 return; 3838 3839 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3840 case IP_VERSION(10, 1, 10): 3841 soc15_program_register_sequence(adev, 3842 golden_settings_gc_10_1, 3843 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3844 soc15_program_register_sequence(adev, 3845 golden_settings_gc_10_0_nv10, 3846 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3847 break; 3848 case IP_VERSION(10, 1, 1): 3849 soc15_program_register_sequence(adev, 3850 golden_settings_gc_10_1_1, 3851 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3852 soc15_program_register_sequence(adev, 3853 golden_settings_gc_10_1_nv14, 3854 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3855 break; 3856 case IP_VERSION(10, 1, 2): 3857 soc15_program_register_sequence(adev, 3858 golden_settings_gc_10_1_2, 3859 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3860 soc15_program_register_sequence(adev, 3861 golden_settings_gc_10_1_2_nv12, 3862 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3863 break; 3864 case IP_VERSION(10, 3, 0): 3865 soc15_program_register_sequence(adev, 3866 golden_settings_gc_10_3, 3867 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3868 soc15_program_register_sequence(adev, 3869 golden_settings_gc_10_3_sienna_cichlid, 3870 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3871 break; 3872 case IP_VERSION(10, 3, 2): 3873 soc15_program_register_sequence(adev, 3874 golden_settings_gc_10_3_2, 3875 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3876 break; 3877 case IP_VERSION(10, 3, 1): 3878 soc15_program_register_sequence(adev, 3879 golden_settings_gc_10_3_vangogh, 3880 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3881 break; 3882 case IP_VERSION(10, 3, 3): 3883 soc15_program_register_sequence(adev, 3884 golden_settings_gc_10_3_3, 3885 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3)); 3886 break; 3887 case IP_VERSION(10, 3, 4): 3888 soc15_program_register_sequence(adev, 3889 golden_settings_gc_10_3_4, 3890 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3891 break; 3892 case IP_VERSION(10, 3, 5): 3893 soc15_program_register_sequence(adev, 3894 golden_settings_gc_10_3_5, 3895 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5)); 3896 break; 3897 case IP_VERSION(10, 1, 3): 3898 case IP_VERSION(10, 1, 4): 3899 soc15_program_register_sequence(adev, 3900 golden_settings_gc_10_0_cyan_skillfish, 3901 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish)); 3902 break; 3903 case IP_VERSION(10, 3, 6): 3904 soc15_program_register_sequence(adev, 3905 golden_settings_gc_10_3_6, 3906 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6)); 3907 break; 3908 case IP_VERSION(10, 3, 7): 3909 soc15_program_register_sequence(adev, 3910 golden_settings_gc_10_3_7, 3911 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7)); 3912 break; 3913 default: 3914 break; 3915 } 3916 gfx_v10_0_init_spm_golden_registers(adev); 3917 } 3918 3919 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3920 bool wc, uint32_t reg, uint32_t val) 3921 { 3922 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3923 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3924 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3925 amdgpu_ring_write(ring, reg); 3926 amdgpu_ring_write(ring, 0); 3927 amdgpu_ring_write(ring, val); 3928 } 3929 3930 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3931 int mem_space, int opt, uint32_t addr0, 3932 uint32_t addr1, uint32_t ref, uint32_t mask, 3933 uint32_t inv) 3934 { 3935 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3936 amdgpu_ring_write(ring, 3937 /* memory (1) or register (0) */ 3938 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3939 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3940 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3941 WAIT_REG_MEM_ENGINE(eng_sel))); 3942 3943 if (mem_space) 3944 BUG_ON(addr0 & 0x3); /* Dword align */ 3945 amdgpu_ring_write(ring, addr0); 3946 amdgpu_ring_write(ring, addr1); 3947 amdgpu_ring_write(ring, ref); 3948 amdgpu_ring_write(ring, mask); 3949 amdgpu_ring_write(ring, inv); /* poll interval */ 3950 } 3951 3952 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3953 { 3954 struct amdgpu_device *adev = ring->adev; 3955 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3956 uint32_t tmp = 0; 3957 unsigned int i; 3958 int r; 3959 3960 WREG32(scratch, 0xCAFEDEAD); 3961 r = amdgpu_ring_alloc(ring, 3); 3962 if (r) { 3963 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3964 ring->idx, r); 3965 return r; 3966 } 3967 3968 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3969 amdgpu_ring_write(ring, scratch - 3970 PACKET3_SET_UCONFIG_REG_START); 3971 amdgpu_ring_write(ring, 0xDEADBEEF); 3972 amdgpu_ring_commit(ring); 3973 3974 for (i = 0; i < adev->usec_timeout; i++) { 3975 tmp = RREG32(scratch); 3976 if (tmp == 0xDEADBEEF) 3977 break; 3978 if (amdgpu_emu_mode == 1) 3979 msleep(1); 3980 else 3981 udelay(1); 3982 } 3983 3984 if (i >= adev->usec_timeout) 3985 r = -ETIMEDOUT; 3986 3987 return r; 3988 } 3989 3990 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3991 { 3992 struct amdgpu_device *adev = ring->adev; 3993 struct amdgpu_ib ib; 3994 struct dma_fence *f = NULL; 3995 unsigned int index; 3996 uint64_t gpu_addr; 3997 volatile uint32_t *cpu_ptr; 3998 long r; 3999 4000 memset(&ib, 0, sizeof(ib)); 4001 4002 r = amdgpu_device_wb_get(adev, &index); 4003 if (r) 4004 return r; 4005 4006 gpu_addr = adev->wb.gpu_addr + (index * 4); 4007 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 4008 cpu_ptr = &adev->wb.wb[index]; 4009 4010 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 4011 if (r) { 4012 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 4013 goto err1; 4014 } 4015 4016 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 4017 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 4018 ib.ptr[2] = lower_32_bits(gpu_addr); 4019 ib.ptr[3] = upper_32_bits(gpu_addr); 4020 ib.ptr[4] = 0xDEADBEEF; 4021 ib.length_dw = 5; 4022 4023 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 4024 if (r) 4025 goto err2; 4026 4027 r = dma_fence_wait_timeout(f, false, timeout); 4028 if (r == 0) { 4029 r = -ETIMEDOUT; 4030 goto err2; 4031 } else if (r < 0) { 4032 goto err2; 4033 } 4034 4035 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 4036 r = 0; 4037 else 4038 r = -EINVAL; 4039 err2: 4040 amdgpu_ib_free(&ib, NULL); 4041 dma_fence_put(f); 4042 err1: 4043 amdgpu_device_wb_free(adev, index); 4044 return r; 4045 } 4046 4047 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 4048 { 4049 amdgpu_ucode_release(&adev->gfx.pfp_fw); 4050 amdgpu_ucode_release(&adev->gfx.me_fw); 4051 amdgpu_ucode_release(&adev->gfx.ce_fw); 4052 amdgpu_ucode_release(&adev->gfx.rlc_fw); 4053 amdgpu_ucode_release(&adev->gfx.mec_fw); 4054 amdgpu_ucode_release(&adev->gfx.mec2_fw); 4055 4056 kfree(adev->gfx.rlc.register_list_format); 4057 } 4058 4059 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 4060 { 4061 adev->gfx.cp_fw_write_wait = false; 4062 4063 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4064 case IP_VERSION(10, 1, 10): 4065 case IP_VERSION(10, 1, 2): 4066 case IP_VERSION(10, 1, 1): 4067 case IP_VERSION(10, 1, 3): 4068 case IP_VERSION(10, 1, 4): 4069 if ((adev->gfx.me_fw_version >= 0x00000046) && 4070 (adev->gfx.me_feature_version >= 27) && 4071 (adev->gfx.pfp_fw_version >= 0x00000068) && 4072 (adev->gfx.pfp_feature_version >= 27) && 4073 (adev->gfx.mec_fw_version >= 0x0000005b) && 4074 (adev->gfx.mec_feature_version >= 27)) 4075 adev->gfx.cp_fw_write_wait = true; 4076 break; 4077 case IP_VERSION(10, 3, 0): 4078 case IP_VERSION(10, 3, 2): 4079 case IP_VERSION(10, 3, 1): 4080 case IP_VERSION(10, 3, 4): 4081 case IP_VERSION(10, 3, 5): 4082 case IP_VERSION(10, 3, 6): 4083 case IP_VERSION(10, 3, 3): 4084 case IP_VERSION(10, 3, 7): 4085 adev->gfx.cp_fw_write_wait = true; 4086 break; 4087 default: 4088 break; 4089 } 4090 4091 if (!adev->gfx.cp_fw_write_wait) 4092 DRM_WARN_ONCE("CP firmware version too old, please update!"); 4093 } 4094 4095 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 4096 { 4097 bool ret = false; 4098 4099 switch (adev->pdev->revision) { 4100 case 0xc2: 4101 case 0xc3: 4102 ret = true; 4103 break; 4104 default: 4105 ret = false; 4106 break; 4107 } 4108 4109 return ret; 4110 } 4111 4112 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 4113 { 4114 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4115 case IP_VERSION(10, 1, 10): 4116 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 4117 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 4118 break; 4119 default: 4120 break; 4121 } 4122 } 4123 4124 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 4125 { 4126 char fw_name[53]; 4127 char ucode_prefix[30]; 4128 const char *wks = ""; 4129 int err; 4130 const struct rlc_firmware_header_v2_0 *rlc_hdr; 4131 uint16_t version_major; 4132 uint16_t version_minor; 4133 4134 DRM_DEBUG("\n"); 4135 4136 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) && 4137 (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00))) 4138 wks = "_wks"; 4139 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 4140 4141 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 4142 AMDGPU_UCODE_REQUIRED, 4143 "amdgpu/%s_pfp%s.bin", ucode_prefix, wks); 4144 if (err) 4145 goto out; 4146 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 4147 4148 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 4149 AMDGPU_UCODE_REQUIRED, 4150 "amdgpu/%s_me%s.bin", ucode_prefix, wks); 4151 if (err) 4152 goto out; 4153 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 4154 4155 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, 4156 AMDGPU_UCODE_REQUIRED, 4157 "amdgpu/%s_ce%s.bin", ucode_prefix, wks); 4158 if (err) 4159 goto out; 4160 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); 4161 4162 if (!amdgpu_sriov_vf(adev)) { 4163 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 4164 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 4165 if (err) 4166 goto out; 4167 4168 /* don't validate this firmware. There are apparently firmwares 4169 * in the wild with incorrect size in the header 4170 */ 4171 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 4172 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 4173 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 4174 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 4175 if (err) 4176 goto out; 4177 } 4178 4179 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 4180 AMDGPU_UCODE_REQUIRED, 4181 "amdgpu/%s_mec%s.bin", ucode_prefix, wks); 4182 if (err) 4183 goto out; 4184 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 4185 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 4186 4187 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, 4188 AMDGPU_UCODE_REQUIRED, 4189 "amdgpu/%s_mec2%s.bin", ucode_prefix, wks); 4190 if (!err) { 4191 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 4192 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 4193 } else { 4194 err = 0; 4195 adev->gfx.mec2_fw = NULL; 4196 } 4197 4198 gfx_v10_0_check_fw_write_wait(adev); 4199 out: 4200 if (err) { 4201 amdgpu_ucode_release(&adev->gfx.pfp_fw); 4202 amdgpu_ucode_release(&adev->gfx.me_fw); 4203 amdgpu_ucode_release(&adev->gfx.ce_fw); 4204 amdgpu_ucode_release(&adev->gfx.rlc_fw); 4205 amdgpu_ucode_release(&adev->gfx.mec_fw); 4206 amdgpu_ucode_release(&adev->gfx.mec2_fw); 4207 } 4208 4209 gfx_v10_0_check_gfxoff_flag(adev); 4210 4211 return err; 4212 } 4213 4214 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4215 { 4216 u32 count = 0; 4217 const struct cs_section_def *sect = NULL; 4218 const struct cs_extent_def *ext = NULL; 4219 4220 /* begin clear state */ 4221 count += 2; 4222 /* context control state */ 4223 count += 3; 4224 4225 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4226 for (ext = sect->section; ext->extent != NULL; ++ext) { 4227 if (sect->id == SECT_CONTEXT) 4228 count += 2 + ext->reg_count; 4229 else 4230 return 0; 4231 } 4232 } 4233 4234 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4235 count += 3; 4236 /* end clear state */ 4237 count += 2; 4238 /* clear state */ 4239 count += 2; 4240 4241 return count; 4242 } 4243 4244 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4245 volatile u32 *buffer) 4246 { 4247 u32 count = 0, i; 4248 const struct cs_section_def *sect = NULL; 4249 const struct cs_extent_def *ext = NULL; 4250 int ctx_reg_offset; 4251 4252 if (adev->gfx.rlc.cs_data == NULL) 4253 return; 4254 if (buffer == NULL) 4255 return; 4256 4257 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4258 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4259 4260 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4261 buffer[count++] = cpu_to_le32(0x80000000); 4262 buffer[count++] = cpu_to_le32(0x80000000); 4263 4264 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4265 for (ext = sect->section; ext->extent != NULL; ++ext) { 4266 if (sect->id == SECT_CONTEXT) { 4267 buffer[count++] = 4268 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4269 buffer[count++] = cpu_to_le32(ext->reg_index - 4270 PACKET3_SET_CONTEXT_REG_START); 4271 for (i = 0; i < ext->reg_count; i++) 4272 buffer[count++] = cpu_to_le32(ext->extent[i]); 4273 } else { 4274 return; 4275 } 4276 } 4277 } 4278 4279 ctx_reg_offset = 4280 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4281 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4282 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4283 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4284 4285 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4286 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4287 4288 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4289 buffer[count++] = cpu_to_le32(0); 4290 } 4291 4292 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4293 { 4294 /* clear state block */ 4295 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4296 &adev->gfx.rlc.clear_state_gpu_addr, 4297 (void **)&adev->gfx.rlc.cs_ptr); 4298 4299 /* jump table block */ 4300 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4301 &adev->gfx.rlc.cp_table_gpu_addr, 4302 (void **)&adev->gfx.rlc.cp_table_ptr); 4303 } 4304 4305 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 4306 { 4307 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 4308 4309 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 4310 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 4311 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); 4312 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); 4313 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); 4314 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); 4315 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); 4316 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4317 case IP_VERSION(10, 3, 0): 4318 reg_access_ctrl->spare_int = 4319 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid); 4320 break; 4321 default: 4322 reg_access_ctrl->spare_int = 4323 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); 4324 break; 4325 } 4326 adev->gfx.rlc.rlcg_reg_access_supported = true; 4327 } 4328 4329 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4330 { 4331 const struct cs_section_def *cs_data; 4332 int r; 4333 4334 adev->gfx.rlc.cs_data = gfx10_cs_data; 4335 4336 cs_data = adev->gfx.rlc.cs_data; 4337 4338 if (cs_data) { 4339 /* init clear state block */ 4340 r = amdgpu_gfx_rlc_init_csb(adev); 4341 if (r) 4342 return r; 4343 } 4344 4345 return 0; 4346 } 4347 4348 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4349 { 4350 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4351 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4352 } 4353 4354 static void gfx_v10_0_me_init(struct amdgpu_device *adev) 4355 { 4356 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4357 4358 amdgpu_gfx_graphics_queue_acquire(adev); 4359 } 4360 4361 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4362 { 4363 int r; 4364 u32 *hpd; 4365 const __le32 *fw_data = NULL; 4366 unsigned int fw_size; 4367 u32 *fw = NULL; 4368 size_t mec_hpd_size; 4369 4370 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4371 4372 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4373 4374 /* take ownership of the relevant compute queues */ 4375 amdgpu_gfx_compute_queue_acquire(adev); 4376 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4377 4378 if (mec_hpd_size) { 4379 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4380 AMDGPU_GEM_DOMAIN_GTT, 4381 &adev->gfx.mec.hpd_eop_obj, 4382 &adev->gfx.mec.hpd_eop_gpu_addr, 4383 (void **)&hpd); 4384 if (r) { 4385 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4386 gfx_v10_0_mec_fini(adev); 4387 return r; 4388 } 4389 4390 memset(hpd, 0, mec_hpd_size); 4391 4392 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4393 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4394 } 4395 4396 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4397 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4398 4399 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4400 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4401 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4402 4403 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4404 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4405 &adev->gfx.mec.mec_fw_obj, 4406 &adev->gfx.mec.mec_fw_gpu_addr, 4407 (void **)&fw); 4408 if (r) { 4409 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4410 gfx_v10_0_mec_fini(adev); 4411 return r; 4412 } 4413 4414 memcpy(fw, fw_data, fw_size); 4415 4416 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4417 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4418 } 4419 4420 return 0; 4421 } 4422 4423 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4424 { 4425 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4426 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4427 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4428 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4429 } 4430 4431 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4432 uint32_t thread, uint32_t regno, 4433 uint32_t num, uint32_t *out) 4434 { 4435 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4436 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4437 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4438 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4439 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4440 while (num--) 4441 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4442 } 4443 4444 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4445 { 4446 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4447 * field when performing a select_se_sh so it should be 4448 * zero here 4449 */ 4450 WARN_ON(simd != 0); 4451 4452 /* type 2 wave data */ 4453 dst[(*no_fields)++] = 2; 4454 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4455 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4456 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4457 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4458 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4459 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4460 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4461 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4462 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4463 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4464 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4465 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4466 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4467 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4468 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4469 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 4470 } 4471 4472 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4473 uint32_t wave, uint32_t start, 4474 uint32_t size, uint32_t *dst) 4475 { 4476 WARN_ON(simd != 0); 4477 4478 wave_read_regs( 4479 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4480 dst); 4481 } 4482 4483 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4484 uint32_t wave, uint32_t thread, 4485 uint32_t start, uint32_t size, 4486 uint32_t *dst) 4487 { 4488 wave_read_regs( 4489 adev, wave, thread, 4490 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4491 } 4492 4493 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4494 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 4495 { 4496 nv_grbm_select(adev, me, pipe, q, vm); 4497 } 4498 4499 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4500 bool enable) 4501 { 4502 uint32_t data, def; 4503 4504 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4505 4506 if (enable) 4507 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4508 else 4509 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4510 4511 if (data != def) 4512 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4513 } 4514 4515 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4516 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4517 .select_se_sh = &gfx_v10_0_select_se_sh, 4518 .read_wave_data = &gfx_v10_0_read_wave_data, 4519 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4520 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4521 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4522 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4523 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4524 }; 4525 4526 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4527 { 4528 u32 gb_addr_config; 4529 4530 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4531 case IP_VERSION(10, 1, 10): 4532 case IP_VERSION(10, 1, 1): 4533 case IP_VERSION(10, 1, 2): 4534 adev->gfx.config.max_hw_contexts = 8; 4535 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4536 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4537 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4538 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4539 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4540 break; 4541 case IP_VERSION(10, 3, 0): 4542 case IP_VERSION(10, 3, 2): 4543 case IP_VERSION(10, 3, 1): 4544 case IP_VERSION(10, 3, 4): 4545 case IP_VERSION(10, 3, 5): 4546 case IP_VERSION(10, 3, 6): 4547 case IP_VERSION(10, 3, 3): 4548 case IP_VERSION(10, 3, 7): 4549 adev->gfx.config.max_hw_contexts = 8; 4550 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4551 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4552 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4553 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4554 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4555 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4556 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4557 break; 4558 case IP_VERSION(10, 1, 3): 4559 case IP_VERSION(10, 1, 4): 4560 adev->gfx.config.max_hw_contexts = 8; 4561 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4562 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4563 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4564 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4565 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN; 4566 break; 4567 default: 4568 BUG(); 4569 break; 4570 } 4571 4572 adev->gfx.config.gb_addr_config = gb_addr_config; 4573 4574 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4575 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4576 GB_ADDR_CONFIG, NUM_PIPES); 4577 4578 adev->gfx.config.max_tile_pipes = 4579 adev->gfx.config.gb_addr_config_fields.num_pipes; 4580 4581 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4582 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4583 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4584 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4585 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4586 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4587 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4588 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4589 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4590 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4591 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4592 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4593 } 4594 4595 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4596 int me, int pipe, int queue) 4597 { 4598 struct amdgpu_ring *ring; 4599 unsigned int irq_type; 4600 unsigned int hw_prio; 4601 4602 ring = &adev->gfx.gfx_ring[ring_id]; 4603 4604 ring->me = me; 4605 ring->pipe = pipe; 4606 ring->queue = queue; 4607 4608 ring->ring_obj = NULL; 4609 ring->use_doorbell = true; 4610 4611 if (!ring_id) 4612 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4613 else 4614 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4615 ring->vm_hub = AMDGPU_GFXHUB(0); 4616 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4617 4618 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4619 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? 4620 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4621 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4622 hw_prio, NULL); 4623 } 4624 4625 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4626 int mec, int pipe, int queue) 4627 { 4628 unsigned int irq_type; 4629 struct amdgpu_ring *ring; 4630 unsigned int hw_prio; 4631 4632 ring = &adev->gfx.compute_ring[ring_id]; 4633 4634 /* mec0 is me1 */ 4635 ring->me = mec + 1; 4636 ring->pipe = pipe; 4637 ring->queue = queue; 4638 4639 ring->ring_obj = NULL; 4640 ring->use_doorbell = true; 4641 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4642 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4643 + (ring_id * GFX10_MEC_HPD_SIZE); 4644 ring->vm_hub = AMDGPU_GFXHUB(0); 4645 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4646 4647 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4648 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4649 + ring->pipe; 4650 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 4651 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; 4652 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4653 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4654 hw_prio, NULL); 4655 } 4656 4657 static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev) 4658 { 4659 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 4660 uint32_t *ptr; 4661 uint32_t inst; 4662 4663 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 4664 if (!ptr) { 4665 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 4666 adev->gfx.ip_dump_core = NULL; 4667 } else { 4668 adev->gfx.ip_dump_core = ptr; 4669 } 4670 4671 /* Allocate memory for compute queue registers for all the instances */ 4672 reg_count = ARRAY_SIZE(gc_cp_reg_list_10); 4673 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4674 adev->gfx.mec.num_queue_per_pipe; 4675 4676 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 4677 if (!ptr) { 4678 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 4679 adev->gfx.ip_dump_compute_queues = NULL; 4680 } else { 4681 adev->gfx.ip_dump_compute_queues = ptr; 4682 } 4683 4684 /* Allocate memory for gfx queue registers for all the instances */ 4685 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10); 4686 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 4687 adev->gfx.me.num_queue_per_pipe; 4688 4689 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 4690 if (!ptr) { 4691 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 4692 adev->gfx.ip_dump_gfx_queues = NULL; 4693 } else { 4694 adev->gfx.ip_dump_gfx_queues = ptr; 4695 } 4696 } 4697 4698 static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block) 4699 { 4700 int i, j, k, r, ring_id = 0; 4701 int xcc_id = 0; 4702 struct amdgpu_device *adev = ip_block->adev; 4703 4704 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4705 case IP_VERSION(10, 1, 10): 4706 case IP_VERSION(10, 1, 1): 4707 case IP_VERSION(10, 1, 2): 4708 case IP_VERSION(10, 1, 3): 4709 case IP_VERSION(10, 1, 4): 4710 adev->gfx.me.num_me = 1; 4711 adev->gfx.me.num_pipe_per_me = 1; 4712 adev->gfx.me.num_queue_per_pipe = 1; 4713 adev->gfx.mec.num_mec = 2; 4714 adev->gfx.mec.num_pipe_per_mec = 4; 4715 adev->gfx.mec.num_queue_per_pipe = 8; 4716 break; 4717 case IP_VERSION(10, 3, 0): 4718 case IP_VERSION(10, 3, 2): 4719 case IP_VERSION(10, 3, 1): 4720 case IP_VERSION(10, 3, 4): 4721 case IP_VERSION(10, 3, 5): 4722 case IP_VERSION(10, 3, 6): 4723 case IP_VERSION(10, 3, 3): 4724 case IP_VERSION(10, 3, 7): 4725 adev->gfx.me.num_me = 1; 4726 adev->gfx.me.num_pipe_per_me = 2; 4727 adev->gfx.me.num_queue_per_pipe = 1; 4728 adev->gfx.mec.num_mec = 2; 4729 adev->gfx.mec.num_pipe_per_mec = 4; 4730 adev->gfx.mec.num_queue_per_pipe = 4; 4731 break; 4732 default: 4733 adev->gfx.me.num_me = 1; 4734 adev->gfx.me.num_pipe_per_me = 1; 4735 adev->gfx.me.num_queue_per_pipe = 1; 4736 adev->gfx.mec.num_mec = 1; 4737 adev->gfx.mec.num_pipe_per_mec = 4; 4738 adev->gfx.mec.num_queue_per_pipe = 8; 4739 break; 4740 } 4741 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4742 case IP_VERSION(10, 3, 0): 4743 adev->gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex; 4744 adev->gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex); 4745 if (adev->gfx.me_fw_version >= 64 && 4746 adev->gfx.pfp_fw_version >= 100 && 4747 adev->gfx.mec_fw_version >= 122) { 4748 adev->gfx.enable_cleaner_shader = true; 4749 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 4750 if (r) { 4751 adev->gfx.enable_cleaner_shader = false; 4752 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 4753 } 4754 } 4755 break; 4756 default: 4757 adev->gfx.enable_cleaner_shader = false; 4758 break; 4759 } 4760 4761 /* KIQ event */ 4762 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4763 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4764 &adev->gfx.kiq[0].irq); 4765 if (r) 4766 return r; 4767 4768 /* EOP Event */ 4769 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4770 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4771 &adev->gfx.eop_irq); 4772 if (r) 4773 return r; 4774 4775 /* Bad opcode Event */ 4776 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4777 GFX_10_1__SRCID__CP_BAD_OPCODE_ERROR, 4778 &adev->gfx.bad_op_irq); 4779 if (r) 4780 return r; 4781 4782 /* Privileged reg */ 4783 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4784 &adev->gfx.priv_reg_irq); 4785 if (r) 4786 return r; 4787 4788 /* Privileged inst */ 4789 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4790 &adev->gfx.priv_inst_irq); 4791 if (r) 4792 return r; 4793 4794 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4795 4796 gfx_v10_0_me_init(adev); 4797 4798 if (adev->gfx.rlc.funcs) { 4799 if (adev->gfx.rlc.funcs->init) { 4800 r = adev->gfx.rlc.funcs->init(adev); 4801 if (r) { 4802 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 4803 return r; 4804 } 4805 } 4806 } 4807 4808 r = gfx_v10_0_mec_init(adev); 4809 if (r) { 4810 DRM_ERROR("Failed to init MEC BOs!\n"); 4811 return r; 4812 } 4813 4814 /* set up the gfx ring */ 4815 for (i = 0; i < adev->gfx.me.num_me; i++) { 4816 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4817 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4818 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4819 continue; 4820 4821 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4822 i, k, j); 4823 if (r) 4824 return r; 4825 ring_id++; 4826 } 4827 } 4828 } 4829 4830 ring_id = 0; 4831 /* set up the compute queues - allocate horizontally across pipes */ 4832 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4833 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4834 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4835 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 4836 k, j)) 4837 continue; 4838 4839 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4840 i, k, j); 4841 if (r) 4842 return r; 4843 4844 ring_id++; 4845 } 4846 } 4847 } 4848 /* TODO: Add queue reset mask when FW fully supports it */ 4849 adev->gfx.gfx_supported_reset = 4850 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 4851 adev->gfx.compute_supported_reset = 4852 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 4853 4854 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0); 4855 if (r) { 4856 DRM_ERROR("Failed to init KIQ BOs!\n"); 4857 return r; 4858 } 4859 4860 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 4861 if (r) 4862 return r; 4863 4864 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0); 4865 if (r) 4866 return r; 4867 4868 /* allocate visible FB for rlc auto-loading fw */ 4869 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4870 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4871 if (r) 4872 return r; 4873 } 4874 4875 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4876 4877 gfx_v10_0_gpu_early_init(adev); 4878 4879 gfx_v10_0_alloc_ip_dump(adev); 4880 4881 r = amdgpu_gfx_sysfs_init(adev); 4882 if (r) 4883 return r; 4884 4885 return 0; 4886 } 4887 4888 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4889 { 4890 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4891 &adev->gfx.pfp.pfp_fw_gpu_addr, 4892 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4893 } 4894 4895 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4896 { 4897 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4898 &adev->gfx.ce.ce_fw_gpu_addr, 4899 (void **)&adev->gfx.ce.ce_fw_ptr); 4900 } 4901 4902 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4903 { 4904 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4905 &adev->gfx.me.me_fw_gpu_addr, 4906 (void **)&adev->gfx.me.me_fw_ptr); 4907 } 4908 4909 static int gfx_v10_0_sw_fini(struct amdgpu_ip_block *ip_block) 4910 { 4911 int i; 4912 struct amdgpu_device *adev = ip_block->adev; 4913 4914 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4915 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4916 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4917 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4918 4919 amdgpu_gfx_mqd_sw_fini(adev, 0); 4920 4921 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 4922 amdgpu_gfx_kiq_fini(adev, 0); 4923 4924 amdgpu_gfx_cleaner_shader_sw_fini(adev); 4925 4926 gfx_v10_0_pfp_fini(adev); 4927 gfx_v10_0_ce_fini(adev); 4928 gfx_v10_0_me_fini(adev); 4929 gfx_v10_0_rlc_fini(adev); 4930 gfx_v10_0_mec_fini(adev); 4931 4932 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 4933 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4934 4935 gfx_v10_0_free_microcode(adev); 4936 amdgpu_gfx_sysfs_fini(adev); 4937 4938 kfree(adev->gfx.ip_dump_core); 4939 kfree(adev->gfx.ip_dump_compute_queues); 4940 kfree(adev->gfx.ip_dump_gfx_queues); 4941 4942 return 0; 4943 } 4944 4945 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4946 u32 sh_num, u32 instance, int xcc_id) 4947 { 4948 u32 data; 4949 4950 if (instance == 0xffffffff) 4951 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 4952 INSTANCE_BROADCAST_WRITES, 1); 4953 else 4954 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 4955 instance); 4956 4957 if (se_num == 0xffffffff) 4958 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 4959 1); 4960 else 4961 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 4962 4963 if (sh_num == 0xffffffff) 4964 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 4965 1); 4966 else 4967 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 4968 4969 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 4970 } 4971 4972 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 4973 { 4974 u32 data, mask; 4975 4976 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 4977 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 4978 4979 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 4980 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 4981 4982 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 4983 adev->gfx.config.max_sh_per_se); 4984 4985 return (~data) & mask; 4986 } 4987 4988 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 4989 { 4990 int i, j; 4991 u32 data; 4992 u32 active_rbs = 0; 4993 u32 bitmap; 4994 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 4995 adev->gfx.config.max_sh_per_se; 4996 4997 mutex_lock(&adev->grbm_idx_mutex); 4998 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4999 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5000 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5001 if (((amdgpu_ip_version(adev, GC_HWIP, 0) == 5002 IP_VERSION(10, 3, 0)) || 5003 (amdgpu_ip_version(adev, GC_HWIP, 0) == 5004 IP_VERSION(10, 3, 3)) || 5005 (amdgpu_ip_version(adev, GC_HWIP, 0) == 5006 IP_VERSION(10, 3, 6))) && 5007 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 5008 continue; 5009 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5010 data = gfx_v10_0_get_rb_active_bitmap(adev); 5011 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 5012 rb_bitmap_width_per_sh); 5013 } 5014 } 5015 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5016 mutex_unlock(&adev->grbm_idx_mutex); 5017 5018 adev->gfx.config.backend_enable_mask = active_rbs; 5019 adev->gfx.config.num_rbs = hweight32(active_rbs); 5020 } 5021 5022 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 5023 { 5024 uint32_t num_sc; 5025 uint32_t enabled_rb_per_sh; 5026 uint32_t active_rb_bitmap; 5027 uint32_t num_rb_per_sc; 5028 uint32_t num_packer_per_sc; 5029 uint32_t pa_sc_tile_steering_override; 5030 5031 /* for ASICs that integrates GFX v10.3 5032 * pa_sc_tile_steering_override should be set to 0 5033 */ 5034 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) 5035 return 0; 5036 5037 /* init num_sc */ 5038 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 5039 adev->gfx.config.num_sc_per_sh; 5040 /* init num_rb_per_sc */ 5041 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 5042 enabled_rb_per_sh = hweight32(active_rb_bitmap); 5043 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 5044 /* init num_packer_per_sc */ 5045 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 5046 5047 pa_sc_tile_steering_override = 0; 5048 pa_sc_tile_steering_override |= 5049 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 5050 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 5051 pa_sc_tile_steering_override |= 5052 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 5053 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 5054 pa_sc_tile_steering_override |= 5055 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 5056 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 5057 5058 return pa_sc_tile_steering_override; 5059 } 5060 5061 #define DEFAULT_SH_MEM_BASES (0x6000) 5062 5063 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev, 5064 uint32_t first_vmid, 5065 uint32_t last_vmid) 5066 { 5067 uint32_t data; 5068 uint32_t trap_config_vmid_mask = 0; 5069 int i; 5070 5071 /* Calculate trap config vmid mask */ 5072 for (i = first_vmid; i < last_vmid; i++) 5073 trap_config_vmid_mask |= (1 << i); 5074 5075 data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG, 5076 VMID_SEL, trap_config_vmid_mask); 5077 data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG, 5078 TRAP_EN, 1); 5079 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data); 5080 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); 5081 5082 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0); 5083 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0); 5084 } 5085 5086 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 5087 { 5088 int i; 5089 uint32_t sh_mem_bases; 5090 5091 /* 5092 * Configure apertures: 5093 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 5094 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 5095 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 5096 */ 5097 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 5098 5099 mutex_lock(&adev->srbm_mutex); 5100 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 5101 nv_grbm_select(adev, 0, 0, 0, i); 5102 /* CP and shaders */ 5103 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5104 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 5105 } 5106 nv_grbm_select(adev, 0, 0, 0, 0); 5107 mutex_unlock(&adev->srbm_mutex); 5108 5109 /* 5110 * Initialize all compute VMIDs to have no GDS, GWS, or OA 5111 * access. These should be enabled by FW for target VMIDs. 5112 */ 5113 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 5114 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 5115 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 5116 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 5117 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 5118 } 5119 5120 gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid, 5121 AMDGPU_NUM_VMID); 5122 } 5123 5124 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 5125 { 5126 int vmid; 5127 5128 /* 5129 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 5130 * access. Compute VMIDs should be enabled by FW for target VMIDs, 5131 * the driver can enable them for graphics. VMID0 should maintain 5132 * access so that HWS firmware can save/restore entries. 5133 */ 5134 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 5135 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 5136 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 5137 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 5138 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 5139 } 5140 } 5141 5142 5143 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 5144 { 5145 int i, j, k; 5146 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 5147 u32 tmp, wgp_active_bitmap = 0; 5148 u32 gcrd_targets_disable_tcp = 0; 5149 u32 utcl_invreq_disable = 0; 5150 /* 5151 * GCRD_TARGETS_DISABLE field contains 5152 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 5153 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 5154 */ 5155 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 5156 2 * max_wgp_per_sh + /* TCP */ 5157 max_wgp_per_sh + /* SQC */ 5158 4); /* GL1C */ 5159 /* 5160 * UTCL1_UTCL0_INVREQ_DISABLE field contains 5161 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 5162 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 5163 */ 5164 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 5165 2 * max_wgp_per_sh + /* TCP */ 5166 2 * max_wgp_per_sh + /* SQC */ 5167 4 + /* RMI */ 5168 1); /* SQG */ 5169 5170 mutex_lock(&adev->grbm_idx_mutex); 5171 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5172 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5173 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5174 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 5175 /* 5176 * Set corresponding TCP bits for the inactive WGPs in 5177 * GCRD_SA_TARGETS_DISABLE 5178 */ 5179 gcrd_targets_disable_tcp = 0; 5180 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 5181 utcl_invreq_disable = 0; 5182 5183 for (k = 0; k < max_wgp_per_sh; k++) { 5184 if (!(wgp_active_bitmap & (1 << k))) { 5185 gcrd_targets_disable_tcp |= 3 << (2 * k); 5186 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2)); 5187 utcl_invreq_disable |= (3 << (2 * k)) | 5188 (3 << (2 * (max_wgp_per_sh + k))); 5189 } 5190 } 5191 5192 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 5193 /* only override TCP & SQC bits */ 5194 tmp &= (0xffffffffU << (4 * max_wgp_per_sh)); 5195 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 5196 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 5197 5198 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 5199 /* only override TCP & SQC bits */ 5200 tmp &= (0xffffffffU << (3 * max_wgp_per_sh)); 5201 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 5202 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 5203 } 5204 } 5205 5206 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5207 mutex_unlock(&adev->grbm_idx_mutex); 5208 } 5209 5210 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 5211 { 5212 /* TCCs are global (not instanced). */ 5213 uint32_t tcc_disable; 5214 5215 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) { 5216 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) | 5217 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3); 5218 } else { 5219 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 5220 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 5221 } 5222 5223 adev->gfx.config.tcc_disabled_mask = 5224 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 5225 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 5226 } 5227 5228 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 5229 { 5230 u32 tmp; 5231 int i; 5232 5233 if (!amdgpu_sriov_vf(adev)) 5234 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 5235 5236 gfx_v10_0_setup_rb(adev); 5237 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 5238 gfx_v10_0_get_tcc_info(adev); 5239 adev->gfx.config.pa_sc_tile_steering_override = 5240 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 5241 5242 /* XXX SH_MEM regs */ 5243 /* where to put LDS, scratch, GPUVM in FSA64 space */ 5244 mutex_lock(&adev->srbm_mutex); 5245 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 5246 nv_grbm_select(adev, 0, 0, 0, i); 5247 /* CP and shaders */ 5248 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5249 if (i != 0) { 5250 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 5251 (adev->gmc.private_aperture_start >> 48)); 5252 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 5253 (adev->gmc.shared_aperture_start >> 48)); 5254 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 5255 } 5256 } 5257 nv_grbm_select(adev, 0, 0, 0, 0); 5258 5259 mutex_unlock(&adev->srbm_mutex); 5260 5261 gfx_v10_0_init_compute_vmid(adev); 5262 gfx_v10_0_init_gds_vmid(adev); 5263 5264 } 5265 5266 static u32 gfx_v10_0_get_cpg_int_cntl(struct amdgpu_device *adev, 5267 int me, int pipe) 5268 { 5269 if (me != 0) 5270 return 0; 5271 5272 switch (pipe) { 5273 case 0: 5274 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 5275 case 1: 5276 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 5277 default: 5278 return 0; 5279 } 5280 } 5281 5282 static u32 gfx_v10_0_get_cpc_int_cntl(struct amdgpu_device *adev, 5283 int me, int pipe) 5284 { 5285 /* 5286 * amdgpu controls only the first MEC. That's why this function only 5287 * handles the setting of interrupts for this specific MEC. All other 5288 * pipes' interrupts are set by amdkfd. 5289 */ 5290 if (me != 1) 5291 return 0; 5292 5293 switch (pipe) { 5294 case 0: 5295 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 5296 case 1: 5297 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 5298 case 2: 5299 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 5300 case 3: 5301 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 5302 default: 5303 return 0; 5304 } 5305 } 5306 5307 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 5308 bool enable) 5309 { 5310 u32 tmp, cp_int_cntl_reg; 5311 int i, j; 5312 5313 if (amdgpu_sriov_vf(adev)) 5314 return; 5315 5316 for (i = 0; i < adev->gfx.me.num_me; i++) { 5317 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5318 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); 5319 5320 if (cp_int_cntl_reg) { 5321 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5322 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 5323 enable ? 1 : 0); 5324 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 5325 enable ? 1 : 0); 5326 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 5327 enable ? 1 : 0); 5328 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 5329 enable ? 1 : 0); 5330 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 5331 } 5332 } 5333 } 5334 } 5335 5336 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5337 { 5338 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5339 5340 /* csib */ 5341 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) { 5342 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5343 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5344 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5345 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5346 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5347 } else { 5348 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5349 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5350 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5351 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5352 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5353 } 5354 return 0; 5355 } 5356 5357 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5358 { 5359 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5360 5361 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5362 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5363 } 5364 5365 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5366 { 5367 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5368 udelay(50); 5369 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5370 udelay(50); 5371 } 5372 5373 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5374 bool enable) 5375 { 5376 uint32_t rlc_pg_cntl; 5377 5378 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5379 5380 if (!enable) { 5381 /* RLC_PG_CNTL[23] = 0 (default) 5382 * RLC will wait for handshake acks with SMU 5383 * GFXOFF will be enabled 5384 * RLC_PG_CNTL[23] = 1 5385 * RLC will not issue any message to SMU 5386 * hence no handshake between SMU & RLC 5387 * GFXOFF will be disabled 5388 */ 5389 rlc_pg_cntl |= 0x800000; 5390 } else 5391 rlc_pg_cntl &= ~0x800000; 5392 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5393 } 5394 5395 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5396 { 5397 /* 5398 * TODO: enable rlc & smu handshake until smu 5399 * and gfxoff feature works as expected 5400 */ 5401 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5402 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5403 5404 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5405 udelay(50); 5406 } 5407 5408 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5409 { 5410 uint32_t tmp; 5411 5412 /* enable Save Restore Machine */ 5413 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL); 5414 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5415 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5416 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp); 5417 } 5418 5419 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5420 { 5421 const struct rlc_firmware_header_v2_0 *hdr; 5422 const __le32 *fw_data; 5423 unsigned int i, fw_size; 5424 5425 if (!adev->gfx.rlc_fw) 5426 return -EINVAL; 5427 5428 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5429 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5430 5431 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5432 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5433 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5434 5435 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5436 RLCG_UCODE_LOADING_START_ADDRESS); 5437 5438 for (i = 0; i < fw_size; i++) 5439 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5440 le32_to_cpup(fw_data++)); 5441 5442 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5443 5444 return 0; 5445 } 5446 5447 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5448 { 5449 int r; 5450 5451 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5452 adev->psp.autoload_supported) { 5453 5454 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5455 if (r) 5456 return r; 5457 5458 gfx_v10_0_init_csb(adev); 5459 5460 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5461 5462 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5463 gfx_v10_0_rlc_enable_srm(adev); 5464 } else { 5465 if (amdgpu_sriov_vf(adev)) { 5466 gfx_v10_0_init_csb(adev); 5467 return 0; 5468 } 5469 5470 adev->gfx.rlc.funcs->stop(adev); 5471 5472 /* disable CG */ 5473 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5474 5475 /* disable PG */ 5476 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5477 5478 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5479 /* legacy rlc firmware loading */ 5480 r = gfx_v10_0_rlc_load_microcode(adev); 5481 if (r) 5482 return r; 5483 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5484 /* rlc backdoor autoload firmware */ 5485 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5486 if (r) 5487 return r; 5488 } 5489 5490 gfx_v10_0_init_csb(adev); 5491 5492 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5493 5494 adev->gfx.rlc.funcs->start(adev); 5495 5496 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5497 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5498 if (r) 5499 return r; 5500 } 5501 } 5502 5503 return 0; 5504 } 5505 5506 static struct { 5507 FIRMWARE_ID id; 5508 unsigned int offset; 5509 unsigned int size; 5510 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5511 5512 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5513 { 5514 int ret; 5515 RLC_TABLE_OF_CONTENT *rlc_toc; 5516 5517 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE, 5518 AMDGPU_GEM_DOMAIN_GTT, 5519 &adev->gfx.rlc.rlc_toc_bo, 5520 &adev->gfx.rlc.rlc_toc_gpu_addr, 5521 (void **)&adev->gfx.rlc.rlc_toc_buf); 5522 if (ret) { 5523 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5524 return ret; 5525 } 5526 5527 /* Copy toc from psp sos fw to rlc toc buffer */ 5528 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes); 5529 5530 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5531 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5532 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5533 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5534 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5535 /* Offset needs 4KB alignment */ 5536 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5537 } 5538 5539 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5540 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5541 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5542 5543 rlc_toc++; 5544 } 5545 5546 return 0; 5547 } 5548 5549 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5550 { 5551 uint32_t total_size = 0; 5552 FIRMWARE_ID id; 5553 int ret; 5554 5555 ret = gfx_v10_0_parse_rlc_toc(adev); 5556 if (ret) { 5557 dev_err(adev->dev, "failed to parse rlc toc\n"); 5558 return 0; 5559 } 5560 5561 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5562 total_size += rlc_autoload_info[id].size; 5563 5564 /* In case the offset in rlc toc ucode is aligned */ 5565 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5566 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5567 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5568 5569 return total_size; 5570 } 5571 5572 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5573 { 5574 int r; 5575 uint32_t total_size; 5576 5577 total_size = gfx_v10_0_calc_toc_total_size(adev); 5578 5579 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5580 AMDGPU_GEM_DOMAIN_GTT, 5581 &adev->gfx.rlc.rlc_autoload_bo, 5582 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5583 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5584 if (r) { 5585 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5586 return r; 5587 } 5588 5589 return 0; 5590 } 5591 5592 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5593 { 5594 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5595 &adev->gfx.rlc.rlc_toc_gpu_addr, 5596 (void **)&adev->gfx.rlc.rlc_toc_buf); 5597 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5598 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5599 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5600 } 5601 5602 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5603 FIRMWARE_ID id, 5604 const void *fw_data, 5605 uint32_t fw_size) 5606 { 5607 uint32_t toc_offset; 5608 uint32_t toc_fw_size; 5609 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5610 5611 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5612 return; 5613 5614 toc_offset = rlc_autoload_info[id].offset; 5615 toc_fw_size = rlc_autoload_info[id].size; 5616 5617 if (fw_size == 0) 5618 fw_size = toc_fw_size; 5619 5620 if (fw_size > toc_fw_size) 5621 fw_size = toc_fw_size; 5622 5623 memcpy(ptr + toc_offset, fw_data, fw_size); 5624 5625 if (fw_size < toc_fw_size) 5626 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5627 } 5628 5629 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5630 { 5631 void *data; 5632 uint32_t size; 5633 5634 data = adev->gfx.rlc.rlc_toc_buf; 5635 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5636 5637 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5638 FIRMWARE_ID_RLC_TOC, 5639 data, size); 5640 } 5641 5642 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5643 { 5644 const __le32 *fw_data; 5645 uint32_t fw_size; 5646 const struct gfx_firmware_header_v1_0 *cp_hdr; 5647 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5648 5649 /* pfp ucode */ 5650 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5651 adev->gfx.pfp_fw->data; 5652 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5653 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5654 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5655 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5656 FIRMWARE_ID_CP_PFP, 5657 fw_data, fw_size); 5658 5659 /* ce ucode */ 5660 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5661 adev->gfx.ce_fw->data; 5662 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5663 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5664 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5665 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5666 FIRMWARE_ID_CP_CE, 5667 fw_data, fw_size); 5668 5669 /* me ucode */ 5670 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5671 adev->gfx.me_fw->data; 5672 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5673 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5674 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5675 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5676 FIRMWARE_ID_CP_ME, 5677 fw_data, fw_size); 5678 5679 /* rlc ucode */ 5680 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5681 adev->gfx.rlc_fw->data; 5682 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5683 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5684 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5685 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5686 FIRMWARE_ID_RLC_G_UCODE, 5687 fw_data, fw_size); 5688 5689 /* mec1 ucode */ 5690 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5691 adev->gfx.mec_fw->data; 5692 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5693 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5694 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5695 cp_hdr->jt_size * 4; 5696 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5697 FIRMWARE_ID_CP_MEC, 5698 fw_data, fw_size); 5699 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5700 } 5701 5702 /* Temporarily put sdma part here */ 5703 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5704 { 5705 const __le32 *fw_data; 5706 uint32_t fw_size; 5707 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5708 int i; 5709 5710 for (i = 0; i < adev->sdma.num_instances; i++) { 5711 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5712 adev->sdma.instance[i].fw->data; 5713 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5714 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5715 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5716 5717 if (i == 0) { 5718 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5719 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5720 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5721 FIRMWARE_ID_SDMA0_JT, 5722 (uint32_t *)fw_data + 5723 sdma_hdr->jt_offset, 5724 sdma_hdr->jt_size * 4); 5725 } else if (i == 1) { 5726 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5727 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5728 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5729 FIRMWARE_ID_SDMA1_JT, 5730 (uint32_t *)fw_data + 5731 sdma_hdr->jt_offset, 5732 sdma_hdr->jt_size * 4); 5733 } 5734 } 5735 } 5736 5737 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5738 { 5739 uint32_t rlc_g_offset, rlc_g_size, tmp; 5740 uint64_t gpu_addr; 5741 5742 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5743 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5744 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5745 5746 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5747 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5748 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5749 5750 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5751 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5752 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5753 5754 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5755 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5756 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5757 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5758 return -EINVAL; 5759 } 5760 5761 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5762 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5763 DRM_ERROR("RLC ROM should halt itself\n"); 5764 return -EINVAL; 5765 } 5766 5767 return 0; 5768 } 5769 5770 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5771 { 5772 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5773 uint32_t tmp; 5774 int i; 5775 uint64_t addr; 5776 5777 /* Trigger an invalidation of the L1 instruction caches */ 5778 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5779 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5780 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5781 5782 /* Wait for invalidation complete */ 5783 for (i = 0; i < usec_timeout; i++) { 5784 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5785 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5786 INVALIDATE_CACHE_COMPLETE)) 5787 break; 5788 udelay(1); 5789 } 5790 5791 if (i >= usec_timeout) { 5792 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5793 return -EINVAL; 5794 } 5795 5796 /* Program me ucode address into intruction cache address register */ 5797 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5798 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5799 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5800 lower_32_bits(addr) & 0xFFFFF000); 5801 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5802 upper_32_bits(addr)); 5803 5804 return 0; 5805 } 5806 5807 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5808 { 5809 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5810 uint32_t tmp; 5811 int i; 5812 uint64_t addr; 5813 5814 /* Trigger an invalidation of the L1 instruction caches */ 5815 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5816 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5817 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5818 5819 /* Wait for invalidation complete */ 5820 for (i = 0; i < usec_timeout; i++) { 5821 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5822 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5823 INVALIDATE_CACHE_COMPLETE)) 5824 break; 5825 udelay(1); 5826 } 5827 5828 if (i >= usec_timeout) { 5829 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5830 return -EINVAL; 5831 } 5832 5833 /* Program ce ucode address into intruction cache address register */ 5834 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5835 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5836 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5837 lower_32_bits(addr) & 0xFFFFF000); 5838 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5839 upper_32_bits(addr)); 5840 5841 return 0; 5842 } 5843 5844 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5845 { 5846 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5847 uint32_t tmp; 5848 int i; 5849 uint64_t addr; 5850 5851 /* Trigger an invalidation of the L1 instruction caches */ 5852 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5853 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5854 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5855 5856 /* Wait for invalidation complete */ 5857 for (i = 0; i < usec_timeout; i++) { 5858 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5859 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5860 INVALIDATE_CACHE_COMPLETE)) 5861 break; 5862 udelay(1); 5863 } 5864 5865 if (i >= usec_timeout) { 5866 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5867 return -EINVAL; 5868 } 5869 5870 /* Program pfp ucode address into intruction cache address register */ 5871 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5872 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5873 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5874 lower_32_bits(addr) & 0xFFFFF000); 5875 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5876 upper_32_bits(addr)); 5877 5878 return 0; 5879 } 5880 5881 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5882 { 5883 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5884 uint32_t tmp; 5885 int i; 5886 uint64_t addr; 5887 5888 /* Trigger an invalidation of the L1 instruction caches */ 5889 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5890 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5891 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5892 5893 /* Wait for invalidation complete */ 5894 for (i = 0; i < usec_timeout; i++) { 5895 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5896 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5897 INVALIDATE_CACHE_COMPLETE)) 5898 break; 5899 udelay(1); 5900 } 5901 5902 if (i >= usec_timeout) { 5903 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5904 return -EINVAL; 5905 } 5906 5907 /* Program mec1 ucode address into intruction cache address register */ 5908 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5909 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5910 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5911 lower_32_bits(addr) & 0xFFFFF000); 5912 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5913 upper_32_bits(addr)); 5914 5915 return 0; 5916 } 5917 5918 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5919 { 5920 uint32_t cp_status; 5921 uint32_t bootload_status; 5922 int i, r; 5923 5924 for (i = 0; i < adev->usec_timeout; i++) { 5925 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5926 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5927 if ((cp_status == 0) && 5928 (REG_GET_FIELD(bootload_status, 5929 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5930 break; 5931 } 5932 udelay(1); 5933 } 5934 5935 if (i >= adev->usec_timeout) { 5936 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5937 return -ETIMEDOUT; 5938 } 5939 5940 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5941 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5942 if (r) 5943 return r; 5944 5945 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5946 if (r) 5947 return r; 5948 5949 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5950 if (r) 5951 return r; 5952 5953 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5954 if (r) 5955 return r; 5956 } 5957 5958 return 0; 5959 } 5960 5961 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5962 { 5963 int i; 5964 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5965 5966 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5967 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5968 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5969 5970 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) 5971 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5972 else 5973 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5974 5975 if (amdgpu_in_reset(adev) && !enable) 5976 return 0; 5977 5978 for (i = 0; i < adev->usec_timeout; i++) { 5979 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5980 break; 5981 udelay(1); 5982 } 5983 5984 if (i >= adev->usec_timeout) 5985 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5986 5987 return 0; 5988 } 5989 5990 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5991 { 5992 int r; 5993 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5994 const __le32 *fw_data; 5995 unsigned int i, fw_size; 5996 uint32_t tmp; 5997 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5998 5999 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 6000 adev->gfx.pfp_fw->data; 6001 6002 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 6003 6004 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 6005 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 6006 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 6007 6008 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 6009 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 6010 &adev->gfx.pfp.pfp_fw_obj, 6011 &adev->gfx.pfp.pfp_fw_gpu_addr, 6012 (void **)&adev->gfx.pfp.pfp_fw_ptr); 6013 if (r) { 6014 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 6015 gfx_v10_0_pfp_fini(adev); 6016 return r; 6017 } 6018 6019 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 6020 6021 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 6022 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 6023 6024 /* Trigger an invalidation of the L1 instruction caches */ 6025 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 6026 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6027 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 6028 6029 /* Wait for invalidation complete */ 6030 for (i = 0; i < usec_timeout; i++) { 6031 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 6032 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 6033 INVALIDATE_CACHE_COMPLETE)) 6034 break; 6035 udelay(1); 6036 } 6037 6038 if (i >= usec_timeout) { 6039 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6040 return -EINVAL; 6041 } 6042 6043 if (amdgpu_emu_mode == 1) 6044 adev->hdp.funcs->flush_hdp(adev, NULL); 6045 6046 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 6047 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 6048 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 6049 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 6050 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6051 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 6052 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 6053 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 6054 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 6055 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 6056 6057 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 6058 6059 for (i = 0; i < pfp_hdr->jt_size; i++) 6060 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 6061 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 6062 6063 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 6064 6065 return 0; 6066 } 6067 6068 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 6069 { 6070 int r; 6071 const struct gfx_firmware_header_v1_0 *ce_hdr; 6072 const __le32 *fw_data; 6073 unsigned int i, fw_size; 6074 uint32_t tmp; 6075 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6076 6077 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 6078 adev->gfx.ce_fw->data; 6079 6080 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 6081 6082 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 6083 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 6084 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 6085 6086 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 6087 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 6088 &adev->gfx.ce.ce_fw_obj, 6089 &adev->gfx.ce.ce_fw_gpu_addr, 6090 (void **)&adev->gfx.ce.ce_fw_ptr); 6091 if (r) { 6092 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 6093 gfx_v10_0_ce_fini(adev); 6094 return r; 6095 } 6096 6097 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 6098 6099 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 6100 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 6101 6102 /* Trigger an invalidation of the L1 instruction caches */ 6103 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 6104 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6105 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 6106 6107 /* Wait for invalidation complete */ 6108 for (i = 0; i < usec_timeout; i++) { 6109 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 6110 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 6111 INVALIDATE_CACHE_COMPLETE)) 6112 break; 6113 udelay(1); 6114 } 6115 6116 if (i >= usec_timeout) { 6117 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6118 return -EINVAL; 6119 } 6120 6121 if (amdgpu_emu_mode == 1) 6122 adev->hdp.funcs->flush_hdp(adev, NULL); 6123 6124 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 6125 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 6126 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 6127 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 6128 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6129 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 6130 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 6131 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 6132 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 6133 6134 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 6135 6136 for (i = 0; i < ce_hdr->jt_size; i++) 6137 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 6138 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 6139 6140 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 6141 6142 return 0; 6143 } 6144 6145 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 6146 { 6147 int r; 6148 const struct gfx_firmware_header_v1_0 *me_hdr; 6149 const __le32 *fw_data; 6150 unsigned int i, fw_size; 6151 uint32_t tmp; 6152 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6153 6154 me_hdr = (const struct gfx_firmware_header_v1_0 *) 6155 adev->gfx.me_fw->data; 6156 6157 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 6158 6159 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 6160 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 6161 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 6162 6163 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 6164 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 6165 &adev->gfx.me.me_fw_obj, 6166 &adev->gfx.me.me_fw_gpu_addr, 6167 (void **)&adev->gfx.me.me_fw_ptr); 6168 if (r) { 6169 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 6170 gfx_v10_0_me_fini(adev); 6171 return r; 6172 } 6173 6174 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 6175 6176 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 6177 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 6178 6179 /* Trigger an invalidation of the L1 instruction caches */ 6180 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 6181 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6182 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 6183 6184 /* Wait for invalidation complete */ 6185 for (i = 0; i < usec_timeout; i++) { 6186 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 6187 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 6188 INVALIDATE_CACHE_COMPLETE)) 6189 break; 6190 udelay(1); 6191 } 6192 6193 if (i >= usec_timeout) { 6194 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6195 return -EINVAL; 6196 } 6197 6198 if (amdgpu_emu_mode == 1) 6199 adev->hdp.funcs->flush_hdp(adev, NULL); 6200 6201 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 6202 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 6203 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 6204 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 6205 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6206 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 6207 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 6208 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 6209 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 6210 6211 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 6212 6213 for (i = 0; i < me_hdr->jt_size; i++) 6214 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 6215 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 6216 6217 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 6218 6219 return 0; 6220 } 6221 6222 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 6223 { 6224 int r; 6225 6226 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 6227 return -EINVAL; 6228 6229 gfx_v10_0_cp_gfx_enable(adev, false); 6230 6231 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 6232 if (r) { 6233 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 6234 return r; 6235 } 6236 6237 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 6238 if (r) { 6239 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 6240 return r; 6241 } 6242 6243 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 6244 if (r) { 6245 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 6246 return r; 6247 } 6248 6249 return 0; 6250 } 6251 6252 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 6253 { 6254 struct amdgpu_ring *ring; 6255 const struct cs_section_def *sect = NULL; 6256 const struct cs_extent_def *ext = NULL; 6257 int r, i; 6258 int ctx_reg_offset; 6259 6260 /* init the CP */ 6261 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 6262 adev->gfx.config.max_hw_contexts - 1); 6263 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 6264 6265 gfx_v10_0_cp_gfx_enable(adev, true); 6266 6267 ring = &adev->gfx.gfx_ring[0]; 6268 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 6269 if (r) { 6270 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6271 return r; 6272 } 6273 6274 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6275 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 6276 6277 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 6278 amdgpu_ring_write(ring, 0x80000000); 6279 amdgpu_ring_write(ring, 0x80000000); 6280 6281 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 6282 for (ext = sect->section; ext->extent != NULL; ++ext) { 6283 if (sect->id == SECT_CONTEXT) { 6284 amdgpu_ring_write(ring, 6285 PACKET3(PACKET3_SET_CONTEXT_REG, 6286 ext->reg_count)); 6287 amdgpu_ring_write(ring, ext->reg_index - 6288 PACKET3_SET_CONTEXT_REG_START); 6289 for (i = 0; i < ext->reg_count; i++) 6290 amdgpu_ring_write(ring, ext->extent[i]); 6291 } 6292 } 6293 } 6294 6295 ctx_reg_offset = 6296 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 6297 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 6298 amdgpu_ring_write(ring, ctx_reg_offset); 6299 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 6300 6301 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6302 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 6303 6304 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6305 amdgpu_ring_write(ring, 0); 6306 6307 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 6308 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 6309 amdgpu_ring_write(ring, 0x8000); 6310 amdgpu_ring_write(ring, 0x8000); 6311 6312 amdgpu_ring_commit(ring); 6313 6314 /* submit cs packet to copy state 0 to next available state */ 6315 if (adev->gfx.num_gfx_rings > 1) { 6316 /* maximum supported gfx ring is 2 */ 6317 ring = &adev->gfx.gfx_ring[1]; 6318 r = amdgpu_ring_alloc(ring, 2); 6319 if (r) { 6320 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6321 return r; 6322 } 6323 6324 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6325 amdgpu_ring_write(ring, 0); 6326 6327 amdgpu_ring_commit(ring); 6328 } 6329 return 0; 6330 } 6331 6332 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 6333 CP_PIPE_ID pipe) 6334 { 6335 u32 tmp; 6336 6337 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 6338 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 6339 6340 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 6341 } 6342 6343 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 6344 struct amdgpu_ring *ring) 6345 { 6346 u32 tmp; 6347 6348 if (!amdgpu_async_gfx_ring) { 6349 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6350 if (ring->use_doorbell) { 6351 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6352 DOORBELL_OFFSET, ring->doorbell_index); 6353 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6354 DOORBELL_EN, 1); 6355 } else { 6356 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6357 DOORBELL_EN, 0); 6358 } 6359 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6360 } 6361 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6362 case IP_VERSION(10, 3, 0): 6363 case IP_VERSION(10, 3, 2): 6364 case IP_VERSION(10, 3, 1): 6365 case IP_VERSION(10, 3, 4): 6366 case IP_VERSION(10, 3, 5): 6367 case IP_VERSION(10, 3, 6): 6368 case IP_VERSION(10, 3, 3): 6369 case IP_VERSION(10, 3, 7): 6370 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6371 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6372 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6373 6374 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6375 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6376 break; 6377 default: 6378 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6379 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6380 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6381 6382 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6383 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6384 break; 6385 } 6386 } 6387 6388 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6389 { 6390 struct amdgpu_ring *ring; 6391 u32 tmp; 6392 u32 rb_bufsz; 6393 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6394 6395 /* Set the write pointer delay */ 6396 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6397 6398 /* set the RB to use vmid 0 */ 6399 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6400 6401 /* Init gfx ring 0 for pipe 0 */ 6402 mutex_lock(&adev->srbm_mutex); 6403 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6404 6405 /* Set ring buffer size */ 6406 ring = &adev->gfx.gfx_ring[0]; 6407 rb_bufsz = order_base_2(ring->ring_size / 8); 6408 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6409 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6410 #ifdef __BIG_ENDIAN 6411 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6412 #endif 6413 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6414 6415 /* Initialize the ring buffer's write pointers */ 6416 ring->wptr = 0; 6417 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6418 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6419 6420 /* set the wb address whether it's enabled or not */ 6421 rptr_addr = ring->rptr_gpu_addr; 6422 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6423 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6424 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6425 6426 wptr_gpu_addr = ring->wptr_gpu_addr; 6427 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6428 lower_32_bits(wptr_gpu_addr)); 6429 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6430 upper_32_bits(wptr_gpu_addr)); 6431 6432 mdelay(1); 6433 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6434 6435 rb_addr = ring->gpu_addr >> 8; 6436 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6437 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6438 6439 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6440 6441 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6442 mutex_unlock(&adev->srbm_mutex); 6443 6444 /* Init gfx ring 1 for pipe 1 */ 6445 if (adev->gfx.num_gfx_rings > 1) { 6446 mutex_lock(&adev->srbm_mutex); 6447 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6448 /* maximum supported gfx ring is 2 */ 6449 ring = &adev->gfx.gfx_ring[1]; 6450 rb_bufsz = order_base_2(ring->ring_size / 8); 6451 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6452 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6453 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6454 /* Initialize the ring buffer's write pointers */ 6455 ring->wptr = 0; 6456 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6457 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6458 /* Set the wb address whether it's enabled or not */ 6459 rptr_addr = ring->rptr_gpu_addr; 6460 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6461 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6462 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6463 wptr_gpu_addr = ring->wptr_gpu_addr; 6464 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6465 lower_32_bits(wptr_gpu_addr)); 6466 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6467 upper_32_bits(wptr_gpu_addr)); 6468 6469 mdelay(1); 6470 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6471 6472 rb_addr = ring->gpu_addr >> 8; 6473 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6474 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6475 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6476 6477 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6478 mutex_unlock(&adev->srbm_mutex); 6479 } 6480 /* Switch to pipe 0 */ 6481 mutex_lock(&adev->srbm_mutex); 6482 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6483 mutex_unlock(&adev->srbm_mutex); 6484 6485 /* start the ring */ 6486 gfx_v10_0_cp_gfx_start(adev); 6487 6488 return 0; 6489 } 6490 6491 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6492 { 6493 if (enable) { 6494 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6495 case IP_VERSION(10, 3, 0): 6496 case IP_VERSION(10, 3, 2): 6497 case IP_VERSION(10, 3, 1): 6498 case IP_VERSION(10, 3, 4): 6499 case IP_VERSION(10, 3, 5): 6500 case IP_VERSION(10, 3, 6): 6501 case IP_VERSION(10, 3, 3): 6502 case IP_VERSION(10, 3, 7): 6503 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6504 break; 6505 default: 6506 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6507 break; 6508 } 6509 } else { 6510 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6511 case IP_VERSION(10, 3, 0): 6512 case IP_VERSION(10, 3, 2): 6513 case IP_VERSION(10, 3, 1): 6514 case IP_VERSION(10, 3, 4): 6515 case IP_VERSION(10, 3, 5): 6516 case IP_VERSION(10, 3, 6): 6517 case IP_VERSION(10, 3, 3): 6518 case IP_VERSION(10, 3, 7): 6519 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6520 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6521 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6522 break; 6523 default: 6524 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6525 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6526 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6527 break; 6528 } 6529 adev->gfx.kiq[0].ring.sched.ready = false; 6530 } 6531 udelay(50); 6532 } 6533 6534 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6535 { 6536 const struct gfx_firmware_header_v1_0 *mec_hdr; 6537 const __le32 *fw_data; 6538 unsigned int i; 6539 u32 tmp; 6540 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6541 6542 if (!adev->gfx.mec_fw) 6543 return -EINVAL; 6544 6545 gfx_v10_0_cp_compute_enable(adev, false); 6546 6547 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6548 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6549 6550 fw_data = (const __le32 *) 6551 (adev->gfx.mec_fw->data + 6552 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6553 6554 /* Trigger an invalidation of the L1 instruction caches */ 6555 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6556 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6557 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6558 6559 /* Wait for invalidation complete */ 6560 for (i = 0; i < usec_timeout; i++) { 6561 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6562 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6563 INVALIDATE_CACHE_COMPLETE)) 6564 break; 6565 udelay(1); 6566 } 6567 6568 if (i >= usec_timeout) { 6569 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6570 return -EINVAL; 6571 } 6572 6573 if (amdgpu_emu_mode == 1) 6574 adev->hdp.funcs->flush_hdp(adev, NULL); 6575 6576 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6577 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6578 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6579 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6580 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6581 6582 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6583 0xFFFFF000); 6584 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6585 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6586 6587 /* MEC1 */ 6588 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6589 6590 for (i = 0; i < mec_hdr->jt_size; i++) 6591 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6592 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6593 6594 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6595 6596 /* 6597 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6598 * different microcode than MEC1. 6599 */ 6600 6601 return 0; 6602 } 6603 6604 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6605 { 6606 uint32_t tmp; 6607 struct amdgpu_device *adev = ring->adev; 6608 6609 /* tell RLC which is KIQ queue */ 6610 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6611 case IP_VERSION(10, 3, 0): 6612 case IP_VERSION(10, 3, 2): 6613 case IP_VERSION(10, 3, 1): 6614 case IP_VERSION(10, 3, 4): 6615 case IP_VERSION(10, 3, 5): 6616 case IP_VERSION(10, 3, 6): 6617 case IP_VERSION(10, 3, 3): 6618 case IP_VERSION(10, 3, 7): 6619 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6620 tmp &= 0xffffff00; 6621 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6622 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp | 0x80); 6623 break; 6624 default: 6625 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6626 tmp &= 0xffffff00; 6627 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6628 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp | 0x80); 6629 break; 6630 } 6631 } 6632 6633 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev, 6634 struct v10_gfx_mqd *mqd, 6635 struct amdgpu_mqd_prop *prop) 6636 { 6637 bool priority = 0; 6638 u32 tmp; 6639 6640 /* set up default queue priority level 6641 * 0x0 = low priority, 0x1 = high priority 6642 */ 6643 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) 6644 priority = 1; 6645 6646 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6647 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 6648 mqd->cp_gfx_hqd_queue_priority = tmp; 6649 } 6650 6651 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 6652 struct amdgpu_mqd_prop *prop) 6653 { 6654 struct v10_gfx_mqd *mqd = m; 6655 uint64_t hqd_gpu_addr, wb_gpu_addr; 6656 uint32_t tmp; 6657 uint32_t rb_bufsz; 6658 6659 /* set up gfx hqd wptr */ 6660 mqd->cp_gfx_hqd_wptr = 0; 6661 mqd->cp_gfx_hqd_wptr_hi = 0; 6662 6663 /* set the pointer to the MQD */ 6664 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 6665 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6666 6667 /* set up mqd control */ 6668 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6669 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6670 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6671 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6672 mqd->cp_gfx_mqd_control = tmp; 6673 6674 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6675 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6676 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6677 mqd->cp_gfx_hqd_vmid = 0; 6678 6679 /* set up gfx queue priority */ 6680 gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop); 6681 6682 /* set up time quantum */ 6683 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6684 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6685 mqd->cp_gfx_hqd_quantum = tmp; 6686 6687 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6688 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6689 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6690 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6691 6692 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6693 wb_gpu_addr = prop->rptr_gpu_addr; 6694 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6695 mqd->cp_gfx_hqd_rptr_addr_hi = 6696 upper_32_bits(wb_gpu_addr) & 0xffff; 6697 6698 /* set up rb_wptr_poll addr */ 6699 wb_gpu_addr = prop->wptr_gpu_addr; 6700 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6701 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6702 6703 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6704 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 6705 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6706 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6707 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6708 #ifdef __BIG_ENDIAN 6709 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6710 #endif 6711 mqd->cp_gfx_hqd_cntl = tmp; 6712 6713 /* set up cp_doorbell_control */ 6714 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6715 if (prop->use_doorbell) { 6716 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6717 DOORBELL_OFFSET, prop->doorbell_index); 6718 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6719 DOORBELL_EN, 1); 6720 } else 6721 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6722 DOORBELL_EN, 0); 6723 mqd->cp_rb_doorbell_control = tmp; 6724 6725 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6726 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6727 6728 /* active the queue */ 6729 mqd->cp_gfx_hqd_active = 1; 6730 6731 return 0; 6732 } 6733 6734 static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 6735 { 6736 struct amdgpu_device *adev = ring->adev; 6737 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6738 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6739 6740 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 6741 memset((void *)mqd, 0, sizeof(*mqd)); 6742 mutex_lock(&adev->srbm_mutex); 6743 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6744 amdgpu_ring_init_mqd(ring); 6745 6746 /* 6747 * if there are 2 gfx rings, set the lower doorbell 6748 * range of the first ring, otherwise the range of 6749 * the second ring will override the first ring 6750 */ 6751 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6752 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6753 6754 nv_grbm_select(adev, 0, 0, 0, 0); 6755 mutex_unlock(&adev->srbm_mutex); 6756 if (adev->gfx.me.mqd_backup[mqd_idx]) 6757 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6758 } else { 6759 mutex_lock(&adev->srbm_mutex); 6760 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6761 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6762 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6763 6764 nv_grbm_select(adev, 0, 0, 0, 0); 6765 mutex_unlock(&adev->srbm_mutex); 6766 /* restore mqd with the backup copy */ 6767 if (adev->gfx.me.mqd_backup[mqd_idx]) 6768 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6769 /* reset the ring */ 6770 ring->wptr = 0; 6771 *ring->wptr_cpu_addr = 0; 6772 amdgpu_ring_clear_ring(ring); 6773 } 6774 6775 return 0; 6776 } 6777 6778 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6779 { 6780 int r, i; 6781 struct amdgpu_ring *ring; 6782 6783 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6784 ring = &adev->gfx.gfx_ring[i]; 6785 6786 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6787 if (unlikely(r != 0)) 6788 return r; 6789 6790 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6791 if (!r) { 6792 r = gfx_v10_0_kgq_init_queue(ring, false); 6793 amdgpu_bo_kunmap(ring->mqd_obj); 6794 ring->mqd_ptr = NULL; 6795 } 6796 amdgpu_bo_unreserve(ring->mqd_obj); 6797 if (r) 6798 return r; 6799 } 6800 6801 r = amdgpu_gfx_enable_kgq(adev, 0); 6802 if (r) 6803 return r; 6804 6805 return gfx_v10_0_cp_gfx_start(adev); 6806 } 6807 6808 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 6809 struct amdgpu_mqd_prop *prop) 6810 { 6811 struct v10_compute_mqd *mqd = m; 6812 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6813 uint32_t tmp; 6814 6815 mqd->header = 0xC0310800; 6816 mqd->compute_pipelinestat_enable = 0x00000001; 6817 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6818 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6819 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6820 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6821 mqd->compute_misc_reserved = 0x00000003; 6822 6823 eop_base_addr = prop->eop_gpu_addr >> 8; 6824 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6825 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6826 6827 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6828 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6829 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6830 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6831 6832 mqd->cp_hqd_eop_control = tmp; 6833 6834 /* enable doorbell? */ 6835 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6836 6837 if (prop->use_doorbell) { 6838 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6839 DOORBELL_OFFSET, prop->doorbell_index); 6840 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6841 DOORBELL_EN, 1); 6842 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6843 DOORBELL_SOURCE, 0); 6844 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6845 DOORBELL_HIT, 0); 6846 } else { 6847 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6848 DOORBELL_EN, 0); 6849 } 6850 6851 mqd->cp_hqd_pq_doorbell_control = tmp; 6852 6853 /* disable the queue if it's active */ 6854 mqd->cp_hqd_dequeue_request = 0; 6855 mqd->cp_hqd_pq_rptr = 0; 6856 mqd->cp_hqd_pq_wptr_lo = 0; 6857 mqd->cp_hqd_pq_wptr_hi = 0; 6858 6859 /* set the pointer to the MQD */ 6860 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 6861 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6862 6863 /* set MQD vmid to 0 */ 6864 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6865 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6866 mqd->cp_mqd_control = tmp; 6867 6868 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6869 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6870 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6871 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6872 6873 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6874 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6875 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6876 (order_base_2(prop->queue_size / 4) - 1)); 6877 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6878 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 6879 #ifdef __BIG_ENDIAN 6880 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6881 #endif 6882 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 6883 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 6884 prop->allow_tunneling); 6885 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6886 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6887 mqd->cp_hqd_pq_control = tmp; 6888 6889 /* set the wb address whether it's enabled or not */ 6890 wb_gpu_addr = prop->rptr_gpu_addr; 6891 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6892 mqd->cp_hqd_pq_rptr_report_addr_hi = 6893 upper_32_bits(wb_gpu_addr) & 0xffff; 6894 6895 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6896 wb_gpu_addr = prop->wptr_gpu_addr; 6897 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6898 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6899 6900 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6901 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6902 6903 /* set the vmid for the queue */ 6904 mqd->cp_hqd_vmid = 0; 6905 6906 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6907 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6908 mqd->cp_hqd_persistent_state = tmp; 6909 6910 /* set MIN_IB_AVAIL_SIZE */ 6911 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6912 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6913 mqd->cp_hqd_ib_control = tmp; 6914 6915 /* set static priority for a compute queue/ring */ 6916 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 6917 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 6918 6919 mqd->cp_hqd_active = prop->hqd_active; 6920 6921 return 0; 6922 } 6923 6924 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 6925 { 6926 struct amdgpu_device *adev = ring->adev; 6927 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6928 int j; 6929 6930 /* inactivate the queue */ 6931 if (amdgpu_sriov_vf(adev)) 6932 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 6933 6934 /* disable wptr polling */ 6935 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6936 6937 /* disable the queue if it's active */ 6938 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 6939 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 6940 for (j = 0; j < adev->usec_timeout; j++) { 6941 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 6942 break; 6943 udelay(1); 6944 } 6945 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 6946 mqd->cp_hqd_dequeue_request); 6947 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 6948 mqd->cp_hqd_pq_rptr); 6949 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6950 mqd->cp_hqd_pq_wptr_lo); 6951 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6952 mqd->cp_hqd_pq_wptr_hi); 6953 } 6954 6955 /* disable doorbells */ 6956 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 6957 6958 /* write the EOP addr */ 6959 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 6960 mqd->cp_hqd_eop_base_addr_lo); 6961 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 6962 mqd->cp_hqd_eop_base_addr_hi); 6963 6964 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6965 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 6966 mqd->cp_hqd_eop_control); 6967 6968 /* set the pointer to the MQD */ 6969 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 6970 mqd->cp_mqd_base_addr_lo); 6971 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 6972 mqd->cp_mqd_base_addr_hi); 6973 6974 /* set MQD vmid to 0 */ 6975 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 6976 mqd->cp_mqd_control); 6977 6978 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6979 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 6980 mqd->cp_hqd_pq_base_lo); 6981 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 6982 mqd->cp_hqd_pq_base_hi); 6983 6984 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6985 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 6986 mqd->cp_hqd_pq_control); 6987 6988 /* set the wb address whether it's enabled or not */ 6989 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 6990 mqd->cp_hqd_pq_rptr_report_addr_lo); 6991 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 6992 mqd->cp_hqd_pq_rptr_report_addr_hi); 6993 6994 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6995 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 6996 mqd->cp_hqd_pq_wptr_poll_addr_lo); 6997 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 6998 mqd->cp_hqd_pq_wptr_poll_addr_hi); 6999 7000 /* enable the doorbell if requested */ 7001 if (ring->use_doorbell) { 7002 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 7003 (adev->doorbell_index.kiq * 2) << 2); 7004 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 7005 (adev->doorbell_index.userqueue_end * 2) << 2); 7006 } 7007 7008 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 7009 mqd->cp_hqd_pq_doorbell_control); 7010 7011 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 7012 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 7013 mqd->cp_hqd_pq_wptr_lo); 7014 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 7015 mqd->cp_hqd_pq_wptr_hi); 7016 7017 /* set the vmid for the queue */ 7018 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 7019 7020 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 7021 mqd->cp_hqd_persistent_state); 7022 7023 /* activate the queue */ 7024 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 7025 mqd->cp_hqd_active); 7026 7027 if (ring->use_doorbell) 7028 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 7029 7030 return 0; 7031 } 7032 7033 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 7034 { 7035 struct amdgpu_device *adev = ring->adev; 7036 struct v10_compute_mqd *mqd = ring->mqd_ptr; 7037 7038 gfx_v10_0_kiq_setting(ring); 7039 7040 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 7041 /* reset MQD to a clean status */ 7042 if (adev->gfx.kiq[0].mqd_backup) 7043 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 7044 7045 /* reset ring buffer */ 7046 ring->wptr = 0; 7047 amdgpu_ring_clear_ring(ring); 7048 7049 mutex_lock(&adev->srbm_mutex); 7050 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7051 gfx_v10_0_kiq_init_register(ring); 7052 nv_grbm_select(adev, 0, 0, 0, 0); 7053 mutex_unlock(&adev->srbm_mutex); 7054 } else { 7055 memset((void *)mqd, 0, sizeof(*mqd)); 7056 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 7057 amdgpu_ring_clear_ring(ring); 7058 mutex_lock(&adev->srbm_mutex); 7059 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7060 amdgpu_ring_init_mqd(ring); 7061 gfx_v10_0_kiq_init_register(ring); 7062 nv_grbm_select(adev, 0, 0, 0, 0); 7063 mutex_unlock(&adev->srbm_mutex); 7064 7065 if (adev->gfx.kiq[0].mqd_backup) 7066 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 7067 } 7068 7069 return 0; 7070 } 7071 7072 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring, bool restore) 7073 { 7074 struct amdgpu_device *adev = ring->adev; 7075 struct v10_compute_mqd *mqd = ring->mqd_ptr; 7076 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 7077 7078 if (!restore && !amdgpu_in_reset(adev) && !adev->in_suspend) { 7079 memset((void *)mqd, 0, sizeof(*mqd)); 7080 mutex_lock(&adev->srbm_mutex); 7081 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7082 amdgpu_ring_init_mqd(ring); 7083 nv_grbm_select(adev, 0, 0, 0, 0); 7084 mutex_unlock(&adev->srbm_mutex); 7085 7086 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7087 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 7088 } else { 7089 /* restore MQD to a clean status */ 7090 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7091 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 7092 /* reset ring buffer */ 7093 ring->wptr = 0; 7094 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 7095 amdgpu_ring_clear_ring(ring); 7096 } 7097 7098 return 0; 7099 } 7100 7101 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 7102 { 7103 struct amdgpu_ring *ring; 7104 int r; 7105 7106 ring = &adev->gfx.kiq[0].ring; 7107 7108 r = amdgpu_bo_reserve(ring->mqd_obj, false); 7109 if (unlikely(r != 0)) 7110 return r; 7111 7112 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 7113 if (unlikely(r != 0)) { 7114 amdgpu_bo_unreserve(ring->mqd_obj); 7115 return r; 7116 } 7117 7118 gfx_v10_0_kiq_init_queue(ring); 7119 amdgpu_bo_kunmap(ring->mqd_obj); 7120 ring->mqd_ptr = NULL; 7121 amdgpu_bo_unreserve(ring->mqd_obj); 7122 return 0; 7123 } 7124 7125 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 7126 { 7127 struct amdgpu_ring *ring = NULL; 7128 int r = 0, i; 7129 7130 gfx_v10_0_cp_compute_enable(adev, true); 7131 7132 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7133 ring = &adev->gfx.compute_ring[i]; 7134 7135 r = amdgpu_bo_reserve(ring->mqd_obj, false); 7136 if (unlikely(r != 0)) 7137 goto done; 7138 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 7139 if (!r) { 7140 r = gfx_v10_0_kcq_init_queue(ring, false); 7141 amdgpu_bo_kunmap(ring->mqd_obj); 7142 ring->mqd_ptr = NULL; 7143 } 7144 amdgpu_bo_unreserve(ring->mqd_obj); 7145 if (r) 7146 goto done; 7147 } 7148 7149 r = amdgpu_gfx_enable_kcq(adev, 0); 7150 done: 7151 return r; 7152 } 7153 7154 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 7155 { 7156 int r, i; 7157 struct amdgpu_ring *ring; 7158 7159 if (!(adev->flags & AMD_IS_APU)) 7160 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7161 7162 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7163 /* legacy firmware loading */ 7164 r = gfx_v10_0_cp_gfx_load_microcode(adev); 7165 if (r) 7166 return r; 7167 7168 r = gfx_v10_0_cp_compute_load_microcode(adev); 7169 if (r) 7170 return r; 7171 } 7172 7173 r = gfx_v10_0_kiq_resume(adev); 7174 if (r) 7175 return r; 7176 7177 r = gfx_v10_0_kcq_resume(adev); 7178 if (r) 7179 return r; 7180 7181 if (!amdgpu_async_gfx_ring) { 7182 r = gfx_v10_0_cp_gfx_resume(adev); 7183 if (r) 7184 return r; 7185 } else { 7186 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 7187 if (r) 7188 return r; 7189 } 7190 7191 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 7192 ring = &adev->gfx.gfx_ring[i]; 7193 r = amdgpu_ring_test_helper(ring); 7194 if (r) 7195 return r; 7196 } 7197 7198 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7199 ring = &adev->gfx.compute_ring[i]; 7200 r = amdgpu_ring_test_helper(ring); 7201 if (r) 7202 return r; 7203 } 7204 7205 return 0; 7206 } 7207 7208 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 7209 { 7210 gfx_v10_0_cp_gfx_enable(adev, enable); 7211 gfx_v10_0_cp_compute_enable(adev, enable); 7212 } 7213 7214 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 7215 { 7216 uint32_t data, pattern = 0xDEADBEEF; 7217 7218 /* 7219 * check if mmVGT_ESGS_RING_SIZE_UMD 7220 * has been remapped to mmVGT_ESGS_RING_SIZE 7221 */ 7222 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7223 case IP_VERSION(10, 3, 0): 7224 case IP_VERSION(10, 3, 2): 7225 case IP_VERSION(10, 3, 4): 7226 case IP_VERSION(10, 3, 5): 7227 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 7228 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 7229 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7230 7231 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 7232 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7233 return true; 7234 } 7235 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 7236 break; 7237 case IP_VERSION(10, 3, 1): 7238 case IP_VERSION(10, 3, 3): 7239 case IP_VERSION(10, 3, 6): 7240 case IP_VERSION(10, 3, 7): 7241 return true; 7242 default: 7243 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 7244 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 7245 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7246 7247 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 7248 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7249 return true; 7250 } 7251 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 7252 break; 7253 } 7254 7255 return false; 7256 } 7257 7258 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 7259 { 7260 uint32_t data; 7261 7262 if (amdgpu_sriov_vf(adev)) 7263 return; 7264 7265 /* 7266 * Initialize cam_index to 0 7267 * index will auto-inc after each data writing 7268 */ 7269 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 7270 7271 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7272 case IP_VERSION(10, 3, 0): 7273 case IP_VERSION(10, 3, 2): 7274 case IP_VERSION(10, 3, 1): 7275 case IP_VERSION(10, 3, 4): 7276 case IP_VERSION(10, 3, 5): 7277 case IP_VERSION(10, 3, 6): 7278 case IP_VERSION(10, 3, 3): 7279 case IP_VERSION(10, 3, 7): 7280 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7281 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7282 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7283 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 7284 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7285 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7286 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7287 7288 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7289 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7290 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7291 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 7292 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7293 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7294 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7295 7296 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7297 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7298 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7299 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7300 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7301 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7302 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7303 7304 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7305 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7306 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7307 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7308 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7309 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7310 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7311 7312 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7313 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7314 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7315 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7316 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7317 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7318 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7319 7320 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7321 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7322 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7323 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7324 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7325 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7326 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7327 7328 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7329 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7330 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7331 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7332 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7333 break; 7334 default: 7335 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7336 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7337 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7338 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7339 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7340 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7341 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7342 7343 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7344 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7345 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7346 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7347 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7348 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7349 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7350 7351 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7352 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7353 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7354 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7355 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7356 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7357 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7358 7359 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7360 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7361 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7362 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7363 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7364 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7365 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7366 7367 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7368 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7369 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7370 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7371 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7372 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7373 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7374 7375 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7376 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7377 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7378 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7379 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7380 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7381 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7382 7383 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7384 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7385 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7386 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7387 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7388 break; 7389 } 7390 7391 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7392 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7393 } 7394 7395 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7396 { 7397 uint32_t data; 7398 7399 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7400 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7401 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7402 7403 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7404 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7405 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7406 } 7407 7408 static int gfx_v10_0_hw_init(struct amdgpu_ip_block *ip_block) 7409 { 7410 int r; 7411 struct amdgpu_device *adev = ip_block->adev; 7412 7413 if (!amdgpu_emu_mode) 7414 gfx_v10_0_init_golden_registers(adev); 7415 7416 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 7417 adev->gfx.cleaner_shader_ptr); 7418 7419 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7420 /** 7421 * For gfx 10, rlc firmware loading relies on smu firmware is 7422 * loaded firstly, so in direct type, it has to load smc ucode 7423 * here before rlc. 7424 */ 7425 r = amdgpu_pm_load_smu_firmware(adev, NULL); 7426 if (r) 7427 return r; 7428 gfx_v10_0_disable_gpa_mode(adev); 7429 } 7430 7431 /* if GRBM CAM not remapped, set up the remapping */ 7432 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7433 gfx_v10_0_setup_grbm_cam_remapping(adev); 7434 7435 gfx_v10_0_constants_init(adev); 7436 7437 r = gfx_v10_0_rlc_resume(adev); 7438 if (r) 7439 return r; 7440 7441 /* 7442 * init golden registers and rlc resume may override some registers, 7443 * reconfig them here 7444 */ 7445 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 10) || 7446 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) || 7447 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) 7448 gfx_v10_0_tcp_harvest(adev); 7449 7450 r = gfx_v10_0_cp_resume(adev); 7451 if (r) 7452 return r; 7453 7454 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0)) 7455 gfx_v10_3_program_pbb_mode(adev); 7456 7457 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0) && !amdgpu_sriov_vf(adev)) 7458 gfx_v10_3_set_power_brake_sequence(adev); 7459 7460 return r; 7461 } 7462 7463 static int gfx_v10_0_hw_fini(struct amdgpu_ip_block *ip_block) 7464 { 7465 struct amdgpu_device *adev = ip_block->adev; 7466 7467 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7468 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7469 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 7470 7471 /* WA added for Vangogh asic fixing the SMU suspend failure 7472 * It needs to set power gating again during gfxoff control 7473 * otherwise the gfxoff disallowing will be failed to set. 7474 */ 7475 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1)) 7476 gfx_v10_0_set_powergating_state(ip_block, AMD_PG_STATE_UNGATE); 7477 7478 if (!adev->no_hw_access) { 7479 if (amdgpu_async_gfx_ring) { 7480 if (amdgpu_gfx_disable_kgq(adev, 0)) 7481 DRM_ERROR("KGQ disable failed\n"); 7482 } 7483 7484 if (amdgpu_gfx_disable_kcq(adev, 0)) 7485 DRM_ERROR("KCQ disable failed\n"); 7486 } 7487 7488 if (amdgpu_sriov_vf(adev)) { 7489 gfx_v10_0_cp_gfx_enable(adev, false); 7490 /* Remove the steps of clearing KIQ position. 7491 * It causes GFX hang when another Win guest is rendering. 7492 */ 7493 return 0; 7494 } 7495 gfx_v10_0_cp_enable(adev, false); 7496 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7497 7498 return 0; 7499 } 7500 7501 static int gfx_v10_0_suspend(struct amdgpu_ip_block *ip_block) 7502 { 7503 return gfx_v10_0_hw_fini(ip_block); 7504 } 7505 7506 static int gfx_v10_0_resume(struct amdgpu_ip_block *ip_block) 7507 { 7508 return gfx_v10_0_hw_init(ip_block); 7509 } 7510 7511 static bool gfx_v10_0_is_idle(void *handle) 7512 { 7513 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7514 7515 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7516 GRBM_STATUS, GUI_ACTIVE)) 7517 return false; 7518 else 7519 return true; 7520 } 7521 7522 static int gfx_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 7523 { 7524 unsigned int i; 7525 u32 tmp; 7526 struct amdgpu_device *adev = ip_block->adev; 7527 7528 for (i = 0; i < adev->usec_timeout; i++) { 7529 /* read MC_STATUS */ 7530 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7531 GRBM_STATUS__GUI_ACTIVE_MASK; 7532 7533 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7534 return 0; 7535 udelay(1); 7536 } 7537 return -ETIMEDOUT; 7538 } 7539 7540 static int gfx_v10_0_soft_reset(struct amdgpu_ip_block *ip_block) 7541 { 7542 u32 grbm_soft_reset = 0; 7543 u32 tmp; 7544 struct amdgpu_device *adev = ip_block->adev; 7545 7546 /* GRBM_STATUS */ 7547 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7548 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7549 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7550 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7551 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7552 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7553 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7554 GRBM_SOFT_RESET, SOFT_RESET_CP, 7555 1); 7556 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7557 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7558 1); 7559 } 7560 7561 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7562 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7563 GRBM_SOFT_RESET, SOFT_RESET_CP, 7564 1); 7565 } 7566 7567 /* GRBM_STATUS2 */ 7568 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7569 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7570 case IP_VERSION(10, 3, 0): 7571 case IP_VERSION(10, 3, 2): 7572 case IP_VERSION(10, 3, 1): 7573 case IP_VERSION(10, 3, 4): 7574 case IP_VERSION(10, 3, 5): 7575 case IP_VERSION(10, 3, 6): 7576 case IP_VERSION(10, 3, 3): 7577 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7578 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7579 GRBM_SOFT_RESET, 7580 SOFT_RESET_RLC, 7581 1); 7582 break; 7583 default: 7584 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7585 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7586 GRBM_SOFT_RESET, 7587 SOFT_RESET_RLC, 7588 1); 7589 break; 7590 } 7591 7592 if (grbm_soft_reset) { 7593 /* stop the rlc */ 7594 gfx_v10_0_rlc_stop(adev); 7595 7596 /* Disable GFX parsing/prefetching */ 7597 gfx_v10_0_cp_gfx_enable(adev, false); 7598 7599 /* Disable MEC parsing/prefetching */ 7600 gfx_v10_0_cp_compute_enable(adev, false); 7601 7602 if (grbm_soft_reset) { 7603 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7604 tmp |= grbm_soft_reset; 7605 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7606 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7607 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7608 7609 udelay(50); 7610 7611 tmp &= ~grbm_soft_reset; 7612 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7613 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7614 } 7615 7616 /* Wait a little for things to settle down */ 7617 udelay(50); 7618 } 7619 return 0; 7620 } 7621 7622 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7623 { 7624 uint64_t clock, clock_lo, clock_hi, hi_check; 7625 7626 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7627 case IP_VERSION(10, 1, 3): 7628 case IP_VERSION(10, 1, 4): 7629 preempt_disable(); 7630 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish); 7631 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish); 7632 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish); 7633 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7634 * roughly every 42 seconds. 7635 */ 7636 if (hi_check != clock_hi) { 7637 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish); 7638 clock_hi = hi_check; 7639 } 7640 preempt_enable(); 7641 clock = clock_lo | (clock_hi << 32ULL); 7642 break; 7643 case IP_VERSION(10, 3, 1): 7644 case IP_VERSION(10, 3, 3): 7645 case IP_VERSION(10, 3, 7): 7646 preempt_disable(); 7647 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7648 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7649 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7650 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7651 * roughly every 42 seconds. 7652 */ 7653 if (hi_check != clock_hi) { 7654 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7655 clock_hi = hi_check; 7656 } 7657 preempt_enable(); 7658 clock = clock_lo | (clock_hi << 32ULL); 7659 break; 7660 case IP_VERSION(10, 3, 6): 7661 preempt_disable(); 7662 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7663 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7664 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7665 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7666 * roughly every 42 seconds. 7667 */ 7668 if (hi_check != clock_hi) { 7669 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7670 clock_hi = hi_check; 7671 } 7672 preempt_enable(); 7673 clock = clock_lo | (clock_hi << 32ULL); 7674 break; 7675 default: 7676 preempt_disable(); 7677 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7678 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7679 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7680 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7681 * roughly every 42 seconds. 7682 */ 7683 if (hi_check != clock_hi) { 7684 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7685 clock_hi = hi_check; 7686 } 7687 preempt_enable(); 7688 clock = clock_lo | (clock_hi << 32ULL); 7689 break; 7690 } 7691 return clock; 7692 } 7693 7694 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7695 uint32_t vmid, 7696 uint32_t gds_base, uint32_t gds_size, 7697 uint32_t gws_base, uint32_t gws_size, 7698 uint32_t oa_base, uint32_t oa_size) 7699 { 7700 struct amdgpu_device *adev = ring->adev; 7701 7702 /* GDS Base */ 7703 gfx_v10_0_write_data_to_reg(ring, 0, false, 7704 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7705 gds_base); 7706 7707 /* GDS Size */ 7708 gfx_v10_0_write_data_to_reg(ring, 0, false, 7709 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7710 gds_size); 7711 7712 /* GWS */ 7713 gfx_v10_0_write_data_to_reg(ring, 0, false, 7714 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7715 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7716 7717 /* OA */ 7718 gfx_v10_0_write_data_to_reg(ring, 0, false, 7719 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7720 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7721 } 7722 7723 static int gfx_v10_0_early_init(struct amdgpu_ip_block *ip_block) 7724 { 7725 struct amdgpu_device *adev = ip_block->adev; 7726 7727 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 7728 7729 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7730 case IP_VERSION(10, 1, 10): 7731 case IP_VERSION(10, 1, 1): 7732 case IP_VERSION(10, 1, 2): 7733 case IP_VERSION(10, 1, 3): 7734 case IP_VERSION(10, 1, 4): 7735 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7736 break; 7737 case IP_VERSION(10, 3, 0): 7738 case IP_VERSION(10, 3, 2): 7739 case IP_VERSION(10, 3, 1): 7740 case IP_VERSION(10, 3, 4): 7741 case IP_VERSION(10, 3, 5): 7742 case IP_VERSION(10, 3, 6): 7743 case IP_VERSION(10, 3, 3): 7744 case IP_VERSION(10, 3, 7): 7745 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7746 break; 7747 default: 7748 break; 7749 } 7750 7751 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7752 AMDGPU_MAX_COMPUTE_RINGS); 7753 7754 gfx_v10_0_set_kiq_pm4_funcs(adev); 7755 gfx_v10_0_set_ring_funcs(adev); 7756 gfx_v10_0_set_irq_funcs(adev); 7757 gfx_v10_0_set_gds_init(adev); 7758 gfx_v10_0_set_rlc_funcs(adev); 7759 gfx_v10_0_set_mqd_funcs(adev); 7760 7761 /* init rlcg reg access ctrl */ 7762 gfx_v10_0_init_rlcg_reg_access_ctrl(adev); 7763 7764 return gfx_v10_0_init_microcode(adev); 7765 } 7766 7767 static int gfx_v10_0_late_init(struct amdgpu_ip_block *ip_block) 7768 { 7769 struct amdgpu_device *adev = ip_block->adev; 7770 int r; 7771 7772 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7773 if (r) 7774 return r; 7775 7776 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7777 if (r) 7778 return r; 7779 7780 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 7781 if (r) 7782 return r; 7783 7784 return 0; 7785 } 7786 7787 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7788 { 7789 uint32_t rlc_cntl; 7790 7791 /* if RLC is not enabled, do nothing */ 7792 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7793 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7794 } 7795 7796 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 7797 { 7798 uint32_t data; 7799 unsigned int i; 7800 7801 data = RLC_SAFE_MODE__CMD_MASK; 7802 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7803 7804 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7805 case IP_VERSION(10, 3, 0): 7806 case IP_VERSION(10, 3, 2): 7807 case IP_VERSION(10, 3, 1): 7808 case IP_VERSION(10, 3, 4): 7809 case IP_VERSION(10, 3, 5): 7810 case IP_VERSION(10, 3, 6): 7811 case IP_VERSION(10, 3, 3): 7812 case IP_VERSION(10, 3, 7): 7813 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7814 7815 /* wait for RLC_SAFE_MODE */ 7816 for (i = 0; i < adev->usec_timeout; i++) { 7817 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7818 RLC_SAFE_MODE, CMD)) 7819 break; 7820 udelay(1); 7821 } 7822 break; 7823 default: 7824 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7825 7826 /* wait for RLC_SAFE_MODE */ 7827 for (i = 0; i < adev->usec_timeout; i++) { 7828 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7829 RLC_SAFE_MODE, CMD)) 7830 break; 7831 udelay(1); 7832 } 7833 break; 7834 } 7835 } 7836 7837 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 7838 { 7839 uint32_t data; 7840 7841 data = RLC_SAFE_MODE__CMD_MASK; 7842 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7843 case IP_VERSION(10, 3, 0): 7844 case IP_VERSION(10, 3, 2): 7845 case IP_VERSION(10, 3, 1): 7846 case IP_VERSION(10, 3, 4): 7847 case IP_VERSION(10, 3, 5): 7848 case IP_VERSION(10, 3, 6): 7849 case IP_VERSION(10, 3, 3): 7850 case IP_VERSION(10, 3, 7): 7851 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7852 break; 7853 default: 7854 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7855 break; 7856 } 7857 } 7858 7859 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7860 bool enable) 7861 { 7862 uint32_t data, def; 7863 7864 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 7865 return; 7866 7867 /* It is disabled by HW by default */ 7868 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7869 /* 0 - Disable some blocks' MGCG */ 7870 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7871 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7872 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7873 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7874 7875 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7876 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7877 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7878 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7879 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7880 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7881 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7882 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7883 7884 if (def != data) 7885 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7886 7887 /* MGLS is a global flag to control all MGLS in GFX */ 7888 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7889 /* 2 - RLC memory Light sleep */ 7890 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7891 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7892 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7893 if (def != data) 7894 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7895 } 7896 /* 3 - CP memory Light sleep */ 7897 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7898 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7899 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7900 if (def != data) 7901 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7902 } 7903 } 7904 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7905 /* 1 - MGCG_OVERRIDE */ 7906 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7907 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7908 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7909 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7910 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7911 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7912 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7913 if (def != data) 7914 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7915 7916 /* 2 - disable MGLS in CP */ 7917 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7918 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7919 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7920 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7921 } 7922 7923 /* 3 - disable MGLS in RLC */ 7924 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7925 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7926 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7927 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7928 } 7929 7930 } 7931 } 7932 7933 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7934 bool enable) 7935 { 7936 uint32_t data, def; 7937 7938 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS))) 7939 return; 7940 7941 /* Enable 3D CGCG/CGLS */ 7942 if (enable) { 7943 /* write cmd to clear cgcg/cgls ov */ 7944 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7945 7946 /* unset CGCG override */ 7947 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7948 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7949 7950 /* update CGCG and CGLS override bits */ 7951 if (def != data) 7952 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7953 7954 /* enable 3Dcgcg FSM(0x0000363f) */ 7955 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7956 data = 0; 7957 7958 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7959 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7960 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7961 7962 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7963 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7964 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7965 7966 if (def != data) 7967 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7968 7969 /* set IDLE_POLL_COUNT(0x00900100) */ 7970 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7971 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7972 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7973 if (def != data) 7974 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7975 } else { 7976 /* Disable CGCG/CGLS */ 7977 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7978 7979 /* disable cgcg, cgls should be disabled */ 7980 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7981 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7982 7983 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7984 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7985 7986 /* disable cgcg and cgls in FSM */ 7987 if (def != data) 7988 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7989 } 7990 } 7991 7992 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 7993 bool enable) 7994 { 7995 uint32_t def, data; 7996 7997 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS))) 7998 return; 7999 8000 if (enable) { 8001 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8002 8003 /* unset CGCG override */ 8004 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 8005 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 8006 8007 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 8008 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 8009 8010 /* update CGCG and CGLS override bits */ 8011 if (def != data) 8012 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8013 8014 /* enable cgcg FSM(0x0000363F) */ 8015 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 8016 data = 0; 8017 8018 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 8019 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 8020 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 8021 8022 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 8023 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 8024 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 8025 8026 if (def != data) 8027 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 8028 8029 /* set IDLE_POLL_COUNT(0x00900100) */ 8030 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 8031 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 8032 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 8033 if (def != data) 8034 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 8035 } else { 8036 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 8037 8038 /* reset CGCG/CGLS bits */ 8039 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 8040 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 8041 8042 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 8043 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 8044 8045 /* disable cgcg and cgls in FSM */ 8046 if (def != data) 8047 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 8048 } 8049 } 8050 8051 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 8052 bool enable) 8053 { 8054 uint32_t def, data; 8055 8056 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 8057 return; 8058 8059 if (enable) { 8060 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8061 /* unset FGCG override */ 8062 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 8063 /* update FGCG override bits */ 8064 if (def != data) 8065 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8066 8067 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 8068 /* unset RLC SRAM CLK GATER override */ 8069 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 8070 /* update RLC SRAM CLK GATER override bits */ 8071 if (def != data) 8072 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 8073 } else { 8074 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8075 /* reset FGCG bits */ 8076 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 8077 /* disable FGCG*/ 8078 if (def != data) 8079 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8080 8081 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 8082 /* reset RLC SRAM CLK GATER bits */ 8083 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 8084 /* disable RLC SRAM CLK*/ 8085 if (def != data) 8086 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 8087 } 8088 } 8089 8090 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev) 8091 { 8092 uint32_t reg_data = 0; 8093 uint32_t reg_idx = 0; 8094 uint32_t i; 8095 8096 const uint32_t tcp_ctrl_regs[] = { 8097 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 8098 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 8099 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 8100 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 8101 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 8102 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 8103 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 8104 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 8105 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 8106 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 8107 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG, 8108 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG, 8109 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 8110 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 8111 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 8112 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 8113 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 8114 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 8115 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 8116 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 8117 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 8118 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 8119 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG, 8120 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG 8121 }; 8122 8123 const uint32_t tcp_ctrl_regs_nv12[] = { 8124 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 8125 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 8126 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 8127 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 8128 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 8129 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 8130 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 8131 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 8132 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 8133 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 8134 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 8135 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 8136 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 8137 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 8138 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 8139 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 8140 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 8141 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 8142 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 8143 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 8144 }; 8145 8146 const uint32_t sm_ctlr_regs[] = { 8147 mmCGTS_SA0_QUAD0_SM_CTRL_REG, 8148 mmCGTS_SA0_QUAD1_SM_CTRL_REG, 8149 mmCGTS_SA1_QUAD0_SM_CTRL_REG, 8150 mmCGTS_SA1_QUAD1_SM_CTRL_REG 8151 }; 8152 8153 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) { 8154 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) { 8155 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 8156 tcp_ctrl_regs_nv12[i]; 8157 reg_data = RREG32(reg_idx); 8158 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 8159 WREG32(reg_idx, reg_data); 8160 } 8161 } else { 8162 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) { 8163 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 8164 tcp_ctrl_regs[i]; 8165 reg_data = RREG32(reg_idx); 8166 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 8167 WREG32(reg_idx, reg_data); 8168 } 8169 } 8170 8171 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) { 8172 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] + 8173 sm_ctlr_regs[i]; 8174 reg_data = RREG32(reg_idx); 8175 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK; 8176 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT; 8177 WREG32(reg_idx, reg_data); 8178 } 8179 } 8180 8181 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 8182 bool enable) 8183 { 8184 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 8185 8186 if (enable) { 8187 /* enable FGCG firstly*/ 8188 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8189 /* CGCG/CGLS should be enabled after MGCG/MGLS 8190 * === MGCG + MGLS === 8191 */ 8192 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8193 /* === CGCG /CGLS for GFX 3D Only === */ 8194 gfx_v10_0_update_3d_clock_gating(adev, enable); 8195 /* === CGCG + CGLS === */ 8196 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8197 8198 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == 8199 IP_VERSION(10, 1, 10)) || 8200 (amdgpu_ip_version(adev, GC_HWIP, 0) == 8201 IP_VERSION(10, 1, 1)) || 8202 (amdgpu_ip_version(adev, GC_HWIP, 0) == 8203 IP_VERSION(10, 1, 2))) 8204 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev); 8205 } else { 8206 /* CGCG/CGLS should be disabled before MGCG/MGLS 8207 * === CGCG + CGLS === 8208 */ 8209 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8210 /* === CGCG /CGLS for GFX 3D Only === */ 8211 gfx_v10_0_update_3d_clock_gating(adev, enable); 8212 /* === MGCG + MGLS === */ 8213 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8214 /* disable fgcg at last*/ 8215 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8216 } 8217 8218 if (adev->cg_flags & 8219 (AMD_CG_SUPPORT_GFX_MGCG | 8220 AMD_CG_SUPPORT_GFX_CGLS | 8221 AMD_CG_SUPPORT_GFX_CGCG | 8222 AMD_CG_SUPPORT_GFX_3D_CGCG | 8223 AMD_CG_SUPPORT_GFX_3D_CGLS)) 8224 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 8225 8226 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 8227 8228 return 0; 8229 } 8230 8231 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 8232 unsigned int vmid) 8233 { 8234 u32 reg, pre_data, data; 8235 8236 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 8237 /* not for *_SOC15 */ 8238 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 8239 pre_data = RREG32_NO_KIQ(reg); 8240 else 8241 pre_data = RREG32(reg); 8242 8243 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 8244 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 8245 8246 if (pre_data != data) { 8247 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 8248 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 8249 } else 8250 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 8251 } 8252 } 8253 8254 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid) 8255 { 8256 amdgpu_gfx_off_ctrl(adev, false); 8257 8258 gfx_v10_0_update_spm_vmid_internal(adev, vmid); 8259 8260 amdgpu_gfx_off_ctrl(adev, true); 8261 } 8262 8263 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 8264 uint32_t offset, 8265 struct soc15_reg_rlcg *entries, int arr_size) 8266 { 8267 int i; 8268 uint32_t reg; 8269 8270 if (!entries) 8271 return false; 8272 8273 for (i = 0; i < arr_size; i++) { 8274 const struct soc15_reg_rlcg *entry; 8275 8276 entry = &entries[i]; 8277 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 8278 if (offset == reg) 8279 return true; 8280 } 8281 8282 return false; 8283 } 8284 8285 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 8286 { 8287 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 8288 } 8289 8290 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 8291 { 8292 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 8293 8294 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 8295 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8296 else 8297 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8298 8299 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 8300 8301 /* 8302 * CGPG enablement required and the register to program the hysteresis value 8303 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value 8304 * in refclk count. Note that RLC FW is modified to take 16 bits from 8305 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits. 8306 * 8307 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part) 8308 * of CGPG enablement starting point. 8309 * Power/performance team will optimize it and might give a new value later. 8310 */ 8311 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 8312 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8313 case IP_VERSION(10, 3, 1): 8314 case IP_VERSION(10, 3, 3): 8315 case IP_VERSION(10, 3, 6): 8316 case IP_VERSION(10, 3, 7): 8317 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; 8318 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); 8319 break; 8320 default: 8321 break; 8322 } 8323 } 8324 } 8325 8326 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 8327 { 8328 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 8329 8330 gfx_v10_cntl_power_gating(adev, enable); 8331 8332 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 8333 } 8334 8335 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 8336 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8337 .set_safe_mode = gfx_v10_0_set_safe_mode, 8338 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8339 .init = gfx_v10_0_rlc_init, 8340 .get_csb_size = gfx_v10_0_get_csb_size, 8341 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8342 .resume = gfx_v10_0_rlc_resume, 8343 .stop = gfx_v10_0_rlc_stop, 8344 .reset = gfx_v10_0_rlc_reset, 8345 .start = gfx_v10_0_rlc_start, 8346 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8347 }; 8348 8349 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 8350 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8351 .set_safe_mode = gfx_v10_0_set_safe_mode, 8352 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8353 .init = gfx_v10_0_rlc_init, 8354 .get_csb_size = gfx_v10_0_get_csb_size, 8355 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8356 .resume = gfx_v10_0_rlc_resume, 8357 .stop = gfx_v10_0_rlc_stop, 8358 .reset = gfx_v10_0_rlc_reset, 8359 .start = gfx_v10_0_rlc_start, 8360 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8361 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 8362 }; 8363 8364 static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 8365 enum amd_powergating_state state) 8366 { 8367 struct amdgpu_device *adev = ip_block->adev; 8368 bool enable = (state == AMD_PG_STATE_GATE); 8369 8370 if (amdgpu_sriov_vf(adev)) 8371 return 0; 8372 8373 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8374 case IP_VERSION(10, 1, 10): 8375 case IP_VERSION(10, 1, 1): 8376 case IP_VERSION(10, 1, 2): 8377 case IP_VERSION(10, 3, 0): 8378 case IP_VERSION(10, 3, 2): 8379 case IP_VERSION(10, 3, 4): 8380 case IP_VERSION(10, 3, 5): 8381 amdgpu_gfx_off_ctrl(adev, enable); 8382 break; 8383 case IP_VERSION(10, 3, 1): 8384 case IP_VERSION(10, 3, 3): 8385 case IP_VERSION(10, 3, 6): 8386 case IP_VERSION(10, 3, 7): 8387 if (!enable) 8388 amdgpu_gfx_off_ctrl(adev, false); 8389 8390 gfx_v10_cntl_pg(adev, enable); 8391 8392 if (enable) 8393 amdgpu_gfx_off_ctrl(adev, true); 8394 8395 break; 8396 default: 8397 break; 8398 } 8399 return 0; 8400 } 8401 8402 static int gfx_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 8403 enum amd_clockgating_state state) 8404 { 8405 struct amdgpu_device *adev = ip_block->adev; 8406 8407 if (amdgpu_sriov_vf(adev)) 8408 return 0; 8409 8410 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8411 case IP_VERSION(10, 1, 10): 8412 case IP_VERSION(10, 1, 1): 8413 case IP_VERSION(10, 1, 2): 8414 case IP_VERSION(10, 3, 0): 8415 case IP_VERSION(10, 3, 2): 8416 case IP_VERSION(10, 3, 1): 8417 case IP_VERSION(10, 3, 4): 8418 case IP_VERSION(10, 3, 5): 8419 case IP_VERSION(10, 3, 6): 8420 case IP_VERSION(10, 3, 3): 8421 case IP_VERSION(10, 3, 7): 8422 gfx_v10_0_update_gfx_clock_gating(adev, 8423 state == AMD_CG_STATE_GATE); 8424 break; 8425 default: 8426 break; 8427 } 8428 return 0; 8429 } 8430 8431 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags) 8432 { 8433 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8434 int data; 8435 8436 /* AMD_CG_SUPPORT_GFX_FGCG */ 8437 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8438 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 8439 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 8440 8441 /* AMD_CG_SUPPORT_GFX_MGCG */ 8442 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8443 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 8444 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 8445 8446 /* AMD_CG_SUPPORT_GFX_CGCG */ 8447 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 8448 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 8449 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 8450 8451 /* AMD_CG_SUPPORT_GFX_CGLS */ 8452 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 8453 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 8454 8455 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 8456 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 8457 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 8458 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 8459 8460 /* AMD_CG_SUPPORT_GFX_CP_LS */ 8461 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 8462 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 8463 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 8464 8465 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 8466 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 8467 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 8468 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 8469 8470 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 8471 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 8472 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 8473 } 8474 8475 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 8476 { 8477 /* gfx10 is 32bit rptr*/ 8478 return *(uint32_t *)ring->rptr_cpu_addr; 8479 } 8480 8481 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 8482 { 8483 struct amdgpu_device *adev = ring->adev; 8484 u64 wptr; 8485 8486 /* XXX check if swapping is necessary on BE */ 8487 if (ring->use_doorbell) { 8488 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8489 } else { 8490 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 8491 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 8492 } 8493 8494 return wptr; 8495 } 8496 8497 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 8498 { 8499 struct amdgpu_device *adev = ring->adev; 8500 8501 if (ring->use_doorbell) { 8502 /* XXX check if swapping is necessary on BE */ 8503 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8504 ring->wptr); 8505 WDOORBELL64(ring->doorbell_index, ring->wptr); 8506 } else { 8507 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, 8508 lower_32_bits(ring->wptr)); 8509 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, 8510 upper_32_bits(ring->wptr)); 8511 } 8512 } 8513 8514 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 8515 { 8516 /* gfx10 hardware is 32bit rptr */ 8517 return *(uint32_t *)ring->rptr_cpu_addr; 8518 } 8519 8520 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 8521 { 8522 u64 wptr; 8523 8524 /* XXX check if swapping is necessary on BE */ 8525 if (ring->use_doorbell) 8526 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8527 else 8528 BUG(); 8529 return wptr; 8530 } 8531 8532 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8533 { 8534 struct amdgpu_device *adev = ring->adev; 8535 8536 if (ring->use_doorbell) { 8537 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8538 ring->wptr); 8539 WDOORBELL64(ring->doorbell_index, ring->wptr); 8540 } else { 8541 BUG(); /* only DOORBELL method supported on gfx10 now */ 8542 } 8543 } 8544 8545 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8546 { 8547 struct amdgpu_device *adev = ring->adev; 8548 u32 ref_and_mask, reg_mem_engine; 8549 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8550 8551 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8552 switch (ring->me) { 8553 case 1: 8554 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8555 break; 8556 case 2: 8557 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8558 break; 8559 default: 8560 return; 8561 } 8562 reg_mem_engine = 0; 8563 } else { 8564 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; 8565 reg_mem_engine = 1; /* pfp */ 8566 } 8567 8568 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8569 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8570 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8571 ref_and_mask, ref_and_mask, 0x20); 8572 } 8573 8574 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8575 struct amdgpu_job *job, 8576 struct amdgpu_ib *ib, 8577 uint32_t flags) 8578 { 8579 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8580 u32 header, control = 0; 8581 8582 if (ib->flags & AMDGPU_IB_FLAG_CE) 8583 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8584 else 8585 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8586 8587 control |= ib->length_dw | (vmid << 24); 8588 8589 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8590 control |= INDIRECT_BUFFER_PRE_ENB(1); 8591 8592 if (flags & AMDGPU_IB_PREEMPTED) 8593 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8594 8595 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8596 gfx_v10_0_ring_emit_de_meta(ring, 8597 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8598 } 8599 8600 amdgpu_ring_write(ring, header); 8601 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8602 amdgpu_ring_write(ring, 8603 #ifdef __BIG_ENDIAN 8604 (2 << 0) | 8605 #endif 8606 lower_32_bits(ib->gpu_addr)); 8607 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8608 amdgpu_ring_write(ring, control); 8609 } 8610 8611 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8612 struct amdgpu_job *job, 8613 struct amdgpu_ib *ib, 8614 uint32_t flags) 8615 { 8616 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8617 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8618 8619 /* Currently, there is a high possibility to get wave ID mismatch 8620 * between ME and GDS, leading to a hw deadlock, because ME generates 8621 * different wave IDs than the GDS expects. This situation happens 8622 * randomly when at least 5 compute pipes use GDS ordered append. 8623 * The wave IDs generated by ME are also wrong after suspend/resume. 8624 * Those are probably bugs somewhere else in the kernel driver. 8625 * 8626 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8627 * GDS to 0 for this ring (me/pipe). 8628 */ 8629 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8630 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8631 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8632 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8633 } 8634 8635 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8636 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8637 amdgpu_ring_write(ring, 8638 #ifdef __BIG_ENDIAN 8639 (2 << 0) | 8640 #endif 8641 lower_32_bits(ib->gpu_addr)); 8642 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8643 amdgpu_ring_write(ring, control); 8644 } 8645 8646 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8647 u64 seq, unsigned int flags) 8648 { 8649 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8650 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8651 8652 /* RELEASE_MEM - flush caches, send int */ 8653 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8654 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8655 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8656 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8657 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8658 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8659 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8660 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8661 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8662 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8663 8664 /* 8665 * the address should be Qword aligned if 64bit write, Dword 8666 * aligned if only send 32bit data low (discard data high) 8667 */ 8668 if (write64bit) 8669 BUG_ON(addr & 0x7); 8670 else 8671 BUG_ON(addr & 0x3); 8672 amdgpu_ring_write(ring, lower_32_bits(addr)); 8673 amdgpu_ring_write(ring, upper_32_bits(addr)); 8674 amdgpu_ring_write(ring, lower_32_bits(seq)); 8675 amdgpu_ring_write(ring, upper_32_bits(seq)); 8676 amdgpu_ring_write(ring, 0); 8677 } 8678 8679 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8680 { 8681 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8682 uint32_t seq = ring->fence_drv.sync_seq; 8683 uint64_t addr = ring->fence_drv.gpu_addr; 8684 8685 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8686 upper_32_bits(addr), seq, 0xffffffff, 4); 8687 } 8688 8689 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 8690 uint16_t pasid, uint32_t flush_type, 8691 bool all_hub, uint8_t dst_sel) 8692 { 8693 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 8694 amdgpu_ring_write(ring, 8695 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 8696 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 8697 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 8698 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 8699 } 8700 8701 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8702 unsigned int vmid, uint64_t pd_addr) 8703 { 8704 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8705 8706 /* compute doesn't have PFP */ 8707 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8708 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8709 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8710 amdgpu_ring_write(ring, 0x0); 8711 } 8712 } 8713 8714 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8715 u64 seq, unsigned int flags) 8716 { 8717 struct amdgpu_device *adev = ring->adev; 8718 8719 /* we only allocate 32bit for each seq wb address */ 8720 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8721 8722 /* write fence seq to the "addr" */ 8723 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8724 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8725 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8726 amdgpu_ring_write(ring, lower_32_bits(addr)); 8727 amdgpu_ring_write(ring, upper_32_bits(addr)); 8728 amdgpu_ring_write(ring, lower_32_bits(seq)); 8729 8730 if (flags & AMDGPU_FENCE_FLAG_INT) { 8731 /* set register to trigger INT */ 8732 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8733 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8734 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8735 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8736 amdgpu_ring_write(ring, 0); 8737 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8738 } 8739 } 8740 8741 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8742 { 8743 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8744 amdgpu_ring_write(ring, 0); 8745 } 8746 8747 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8748 uint32_t flags) 8749 { 8750 uint32_t dw2 = 0; 8751 8752 if (ring->adev->gfx.mcbp) 8753 gfx_v10_0_ring_emit_ce_meta(ring, 8754 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8755 8756 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8757 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8758 /* set load_global_config & load_global_uconfig */ 8759 dw2 |= 0x8001; 8760 /* set load_cs_sh_regs */ 8761 dw2 |= 0x01000000; 8762 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8763 dw2 |= 0x10002; 8764 8765 /* set load_ce_ram if preamble presented */ 8766 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8767 dw2 |= 0x10000000; 8768 } else { 8769 /* still load_ce_ram if this is the first time preamble presented 8770 * although there is no context switch happens. 8771 */ 8772 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8773 dw2 |= 0x10000000; 8774 } 8775 8776 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8777 amdgpu_ring_write(ring, dw2); 8778 amdgpu_ring_write(ring, 0); 8779 } 8780 8781 static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 8782 uint64_t addr) 8783 { 8784 unsigned int ret; 8785 8786 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8787 amdgpu_ring_write(ring, lower_32_bits(addr)); 8788 amdgpu_ring_write(ring, upper_32_bits(addr)); 8789 /* discard following DWs if *cond_exec_gpu_addr==0 */ 8790 amdgpu_ring_write(ring, 0); 8791 ret = ring->wptr & ring->buf_mask; 8792 /* patch dummy value later */ 8793 amdgpu_ring_write(ring, 0); 8794 8795 return ret; 8796 } 8797 8798 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8799 { 8800 int i, r = 0; 8801 struct amdgpu_device *adev = ring->adev; 8802 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 8803 struct amdgpu_ring *kiq_ring = &kiq->ring; 8804 unsigned long flags; 8805 8806 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8807 return -EINVAL; 8808 8809 spin_lock_irqsave(&kiq->ring_lock, flags); 8810 8811 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8812 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8813 return -ENOMEM; 8814 } 8815 8816 /* assert preemption condition */ 8817 amdgpu_ring_set_preempt_cond_exec(ring, false); 8818 8819 /* assert IB preemption, emit the trailing fence */ 8820 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8821 ring->trail_fence_gpu_addr, 8822 ++ring->trail_seq); 8823 amdgpu_ring_commit(kiq_ring); 8824 8825 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8826 8827 /* poll the trailing fence */ 8828 for (i = 0; i < adev->usec_timeout; i++) { 8829 if (ring->trail_seq == 8830 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8831 break; 8832 udelay(1); 8833 } 8834 8835 if (i >= adev->usec_timeout) { 8836 r = -EINVAL; 8837 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8838 } 8839 8840 /* deassert preemption condition */ 8841 amdgpu_ring_set_preempt_cond_exec(ring, true); 8842 return r; 8843 } 8844 8845 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8846 { 8847 struct amdgpu_device *adev = ring->adev; 8848 struct v10_ce_ib_state ce_payload = {0}; 8849 uint64_t offset, ce_payload_gpu_addr; 8850 void *ce_payload_cpu_addr; 8851 int cnt; 8852 8853 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8854 8855 offset = offsetof(struct v10_gfx_meta_data, ce_payload); 8856 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8857 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8858 8859 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8860 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8861 WRITE_DATA_DST_SEL(8) | 8862 WR_CONFIRM) | 8863 WRITE_DATA_CACHE_POLICY(0)); 8864 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)); 8865 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)); 8866 8867 if (resume) 8868 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr, 8869 sizeof(ce_payload) >> 2); 8870 else 8871 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8872 sizeof(ce_payload) >> 2); 8873 } 8874 8875 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8876 { 8877 struct amdgpu_device *adev = ring->adev; 8878 struct v10_de_ib_state de_payload = {0}; 8879 uint64_t offset, gds_addr, de_payload_gpu_addr; 8880 void *de_payload_cpu_addr; 8881 int cnt; 8882 8883 offset = offsetof(struct v10_gfx_meta_data, de_payload); 8884 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8885 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8886 8887 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 8888 AMDGPU_CSA_SIZE - adev->gds.gds_size, 8889 PAGE_SIZE); 8890 8891 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8892 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8893 8894 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8895 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8896 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8897 WRITE_DATA_DST_SEL(8) | 8898 WR_CONFIRM) | 8899 WRITE_DATA_CACHE_POLICY(0)); 8900 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 8901 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 8902 8903 if (resume) 8904 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 8905 sizeof(de_payload) >> 2); 8906 else 8907 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8908 sizeof(de_payload) >> 2); 8909 } 8910 8911 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8912 bool secure) 8913 { 8914 uint32_t v = secure ? FRAME_TMZ : 0; 8915 8916 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8917 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8918 } 8919 8920 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8921 uint32_t reg_val_offs) 8922 { 8923 struct amdgpu_device *adev = ring->adev; 8924 8925 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8926 amdgpu_ring_write(ring, 0 | /* src: register*/ 8927 (5 << 8) | /* dst: memory */ 8928 (1 << 20)); /* write confirm */ 8929 amdgpu_ring_write(ring, reg); 8930 amdgpu_ring_write(ring, 0); 8931 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8932 reg_val_offs * 4)); 8933 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8934 reg_val_offs * 4)); 8935 } 8936 8937 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8938 uint32_t val) 8939 { 8940 uint32_t cmd = 0; 8941 8942 switch (ring->funcs->type) { 8943 case AMDGPU_RING_TYPE_GFX: 8944 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8945 break; 8946 case AMDGPU_RING_TYPE_KIQ: 8947 cmd = (1 << 16); /* no inc addr */ 8948 break; 8949 default: 8950 cmd = WR_CONFIRM; 8951 break; 8952 } 8953 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8954 amdgpu_ring_write(ring, cmd); 8955 amdgpu_ring_write(ring, reg); 8956 amdgpu_ring_write(ring, 0); 8957 amdgpu_ring_write(ring, val); 8958 } 8959 8960 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8961 uint32_t val, uint32_t mask) 8962 { 8963 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8964 } 8965 8966 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8967 uint32_t reg0, uint32_t reg1, 8968 uint32_t ref, uint32_t mask) 8969 { 8970 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8971 struct amdgpu_device *adev = ring->adev; 8972 bool fw_version_ok = false; 8973 8974 fw_version_ok = adev->gfx.cp_fw_write_wait; 8975 8976 if (fw_version_ok) 8977 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8978 ref, mask, 0x20); 8979 else 8980 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8981 ref, mask); 8982 } 8983 8984 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 8985 unsigned int vmid) 8986 { 8987 struct amdgpu_device *adev = ring->adev; 8988 uint32_t value = 0; 8989 8990 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 8991 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 8992 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 8993 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 8994 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 8995 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 8996 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 8997 } 8998 8999 static void 9000 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 9001 uint32_t me, uint32_t pipe, 9002 enum amdgpu_interrupt_state state) 9003 { 9004 uint32_t cp_int_cntl, cp_int_cntl_reg; 9005 9006 if (!me) { 9007 switch (pipe) { 9008 case 0: 9009 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 9010 break; 9011 case 1: 9012 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 9013 break; 9014 default: 9015 DRM_DEBUG("invalid pipe %d\n", pipe); 9016 return; 9017 } 9018 } else { 9019 DRM_DEBUG("invalid me %d\n", me); 9020 return; 9021 } 9022 9023 switch (state) { 9024 case AMDGPU_IRQ_STATE_DISABLE: 9025 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9026 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9027 TIME_STAMP_INT_ENABLE, 0); 9028 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9029 break; 9030 case AMDGPU_IRQ_STATE_ENABLE: 9031 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9032 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9033 TIME_STAMP_INT_ENABLE, 1); 9034 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9035 break; 9036 default: 9037 break; 9038 } 9039 } 9040 9041 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 9042 int me, int pipe, 9043 enum amdgpu_interrupt_state state) 9044 { 9045 u32 mec_int_cntl, mec_int_cntl_reg; 9046 9047 /* 9048 * amdgpu controls only the first MEC. That's why this function only 9049 * handles the setting of interrupts for this specific MEC. All other 9050 * pipes' interrupts are set by amdkfd. 9051 */ 9052 9053 if (me == 1) { 9054 switch (pipe) { 9055 case 0: 9056 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9057 break; 9058 case 1: 9059 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 9060 break; 9061 case 2: 9062 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 9063 break; 9064 case 3: 9065 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 9066 break; 9067 default: 9068 DRM_DEBUG("invalid pipe %d\n", pipe); 9069 return; 9070 } 9071 } else { 9072 DRM_DEBUG("invalid me %d\n", me); 9073 return; 9074 } 9075 9076 switch (state) { 9077 case AMDGPU_IRQ_STATE_DISABLE: 9078 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 9079 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9080 TIME_STAMP_INT_ENABLE, 0); 9081 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 9082 break; 9083 case AMDGPU_IRQ_STATE_ENABLE: 9084 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 9085 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9086 TIME_STAMP_INT_ENABLE, 1); 9087 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 9088 break; 9089 default: 9090 break; 9091 } 9092 } 9093 9094 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 9095 struct amdgpu_irq_src *src, 9096 unsigned int type, 9097 enum amdgpu_interrupt_state state) 9098 { 9099 switch (type) { 9100 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 9101 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 9102 break; 9103 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 9104 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 9105 break; 9106 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 9107 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 9108 break; 9109 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 9110 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 9111 break; 9112 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 9113 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 9114 break; 9115 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 9116 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 9117 break; 9118 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 9119 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 9120 break; 9121 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 9122 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 9123 break; 9124 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 9125 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 9126 break; 9127 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 9128 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 9129 break; 9130 default: 9131 break; 9132 } 9133 return 0; 9134 } 9135 9136 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 9137 struct amdgpu_irq_src *source, 9138 struct amdgpu_iv_entry *entry) 9139 { 9140 int i; 9141 u8 me_id, pipe_id, queue_id; 9142 struct amdgpu_ring *ring; 9143 9144 DRM_DEBUG("IH: CP EOP\n"); 9145 9146 me_id = (entry->ring_id & 0x0c) >> 2; 9147 pipe_id = (entry->ring_id & 0x03) >> 0; 9148 queue_id = (entry->ring_id & 0x70) >> 4; 9149 9150 switch (me_id) { 9151 case 0: 9152 if (pipe_id == 0) 9153 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 9154 else 9155 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 9156 break; 9157 case 1: 9158 case 2: 9159 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9160 ring = &adev->gfx.compute_ring[i]; 9161 /* Per-queue interrupt is supported for MEC starting from VI. 9162 * The interrupt can only be enabled/disabled per pipe instead 9163 * of per queue. 9164 */ 9165 if ((ring->me == me_id) && 9166 (ring->pipe == pipe_id) && 9167 (ring->queue == queue_id)) 9168 amdgpu_fence_process(ring); 9169 } 9170 break; 9171 } 9172 9173 return 0; 9174 } 9175 9176 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 9177 struct amdgpu_irq_src *source, 9178 unsigned int type, 9179 enum amdgpu_interrupt_state state) 9180 { 9181 u32 cp_int_cntl_reg, cp_int_cntl; 9182 int i, j; 9183 9184 switch (state) { 9185 case AMDGPU_IRQ_STATE_DISABLE: 9186 case AMDGPU_IRQ_STATE_ENABLE: 9187 for (i = 0; i < adev->gfx.me.num_me; i++) { 9188 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9189 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); 9190 9191 if (cp_int_cntl_reg) { 9192 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9193 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9194 PRIV_REG_INT_ENABLE, 9195 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9196 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9197 } 9198 } 9199 } 9200 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9201 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9202 /* MECs start at 1 */ 9203 cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j); 9204 9205 if (cp_int_cntl_reg) { 9206 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9207 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9208 PRIV_REG_INT_ENABLE, 9209 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9210 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9211 } 9212 } 9213 } 9214 break; 9215 default: 9216 break; 9217 } 9218 9219 return 0; 9220 } 9221 9222 static int gfx_v10_0_set_bad_op_fault_state(struct amdgpu_device *adev, 9223 struct amdgpu_irq_src *source, 9224 unsigned type, 9225 enum amdgpu_interrupt_state state) 9226 { 9227 u32 cp_int_cntl_reg, cp_int_cntl; 9228 int i, j; 9229 9230 switch (state) { 9231 case AMDGPU_IRQ_STATE_DISABLE: 9232 case AMDGPU_IRQ_STATE_ENABLE: 9233 for (i = 0; i < adev->gfx.me.num_me; i++) { 9234 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9235 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); 9236 9237 if (cp_int_cntl_reg) { 9238 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9239 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9240 OPCODE_ERROR_INT_ENABLE, 9241 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9242 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9243 } 9244 } 9245 } 9246 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9247 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9248 /* MECs start at 1 */ 9249 cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j); 9250 9251 if (cp_int_cntl_reg) { 9252 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9253 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9254 OPCODE_ERROR_INT_ENABLE, 9255 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9256 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9257 } 9258 } 9259 } 9260 break; 9261 default: 9262 break; 9263 } 9264 return 0; 9265 } 9266 9267 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 9268 struct amdgpu_irq_src *source, 9269 unsigned int type, 9270 enum amdgpu_interrupt_state state) 9271 { 9272 u32 cp_int_cntl_reg, cp_int_cntl; 9273 int i, j; 9274 9275 switch (state) { 9276 case AMDGPU_IRQ_STATE_DISABLE: 9277 case AMDGPU_IRQ_STATE_ENABLE: 9278 for (i = 0; i < adev->gfx.me.num_me; i++) { 9279 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9280 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); 9281 9282 if (cp_int_cntl_reg) { 9283 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9284 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9285 PRIV_INSTR_INT_ENABLE, 9286 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9287 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9288 } 9289 } 9290 } 9291 break; 9292 default: 9293 break; 9294 } 9295 9296 return 0; 9297 } 9298 9299 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 9300 struct amdgpu_iv_entry *entry) 9301 { 9302 u8 me_id, pipe_id, queue_id; 9303 struct amdgpu_ring *ring; 9304 int i; 9305 9306 me_id = (entry->ring_id & 0x0c) >> 2; 9307 pipe_id = (entry->ring_id & 0x03) >> 0; 9308 queue_id = (entry->ring_id & 0x70) >> 4; 9309 9310 switch (me_id) { 9311 case 0: 9312 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 9313 ring = &adev->gfx.gfx_ring[i]; 9314 if (ring->me == me_id && ring->pipe == pipe_id && 9315 ring->queue == queue_id) 9316 drm_sched_fault(&ring->sched); 9317 } 9318 break; 9319 case 1: 9320 case 2: 9321 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9322 ring = &adev->gfx.compute_ring[i]; 9323 if (ring->me == me_id && ring->pipe == pipe_id && 9324 ring->queue == queue_id) 9325 drm_sched_fault(&ring->sched); 9326 } 9327 break; 9328 default: 9329 BUG(); 9330 } 9331 } 9332 9333 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 9334 struct amdgpu_irq_src *source, 9335 struct amdgpu_iv_entry *entry) 9336 { 9337 DRM_ERROR("Illegal register access in command stream\n"); 9338 gfx_v10_0_handle_priv_fault(adev, entry); 9339 return 0; 9340 } 9341 9342 static int gfx_v10_0_bad_op_irq(struct amdgpu_device *adev, 9343 struct amdgpu_irq_src *source, 9344 struct amdgpu_iv_entry *entry) 9345 { 9346 DRM_ERROR("Illegal opcode in command stream \n"); 9347 gfx_v10_0_handle_priv_fault(adev, entry); 9348 return 0; 9349 } 9350 9351 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 9352 struct amdgpu_irq_src *source, 9353 struct amdgpu_iv_entry *entry) 9354 { 9355 DRM_ERROR("Illegal instruction in command stream\n"); 9356 gfx_v10_0_handle_priv_fault(adev, entry); 9357 return 0; 9358 } 9359 9360 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 9361 struct amdgpu_irq_src *src, 9362 unsigned int type, 9363 enum amdgpu_interrupt_state state) 9364 { 9365 uint32_t tmp, target; 9366 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9367 9368 if (ring->me == 1) 9369 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9370 else 9371 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 9372 target += ring->pipe; 9373 9374 switch (type) { 9375 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 9376 if (state == AMDGPU_IRQ_STATE_DISABLE) { 9377 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9378 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9379 GENERIC2_INT_ENABLE, 0); 9380 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9381 9382 tmp = RREG32_SOC15_IP(GC, target); 9383 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9384 GENERIC2_INT_ENABLE, 0); 9385 WREG32_SOC15_IP(GC, target, tmp); 9386 } else { 9387 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9388 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9389 GENERIC2_INT_ENABLE, 1); 9390 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9391 9392 tmp = RREG32_SOC15_IP(GC, target); 9393 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9394 GENERIC2_INT_ENABLE, 1); 9395 WREG32_SOC15_IP(GC, target, tmp); 9396 } 9397 break; 9398 default: 9399 BUG(); /* kiq only support GENERIC2_INT now */ 9400 break; 9401 } 9402 return 0; 9403 } 9404 9405 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 9406 struct amdgpu_irq_src *source, 9407 struct amdgpu_iv_entry *entry) 9408 { 9409 u8 me_id, pipe_id, queue_id; 9410 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9411 9412 me_id = (entry->ring_id & 0x0c) >> 2; 9413 pipe_id = (entry->ring_id & 0x03) >> 0; 9414 queue_id = (entry->ring_id & 0x70) >> 4; 9415 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 9416 me_id, pipe_id, queue_id); 9417 9418 amdgpu_fence_process(ring); 9419 return 0; 9420 } 9421 9422 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 9423 { 9424 const unsigned int gcr_cntl = 9425 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 9426 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 9427 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 9428 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 9429 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 9430 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 9431 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 9432 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 9433 9434 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 9435 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 9436 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 9437 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 9438 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 9439 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 9440 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 9441 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 9442 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 9443 } 9444 9445 static void gfx_v10_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 9446 { 9447 /* Header itself is a NOP packet */ 9448 if (num_nop == 1) { 9449 amdgpu_ring_write(ring, ring->funcs->nop); 9450 return; 9451 } 9452 9453 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 9454 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 9455 9456 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 9457 amdgpu_ring_insert_nop(ring, num_nop - 1); 9458 } 9459 9460 static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) 9461 { 9462 struct amdgpu_device *adev = ring->adev; 9463 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 9464 struct amdgpu_ring *kiq_ring = &kiq->ring; 9465 unsigned long flags; 9466 u32 tmp; 9467 u64 addr; 9468 int r; 9469 9470 if (amdgpu_sriov_vf(adev)) 9471 return -EINVAL; 9472 9473 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 9474 return -EINVAL; 9475 9476 spin_lock_irqsave(&kiq->ring_lock, flags); 9477 9478 if (amdgpu_ring_alloc(kiq_ring, 5 + 7 + 7 + kiq->pmf->map_queues_size)) { 9479 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9480 return -ENOMEM; 9481 } 9482 9483 addr = amdgpu_bo_gpu_offset(ring->mqd_obj) + 9484 offsetof(struct v10_gfx_mqd, cp_gfx_hqd_active); 9485 tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 9486 if (ring->pipe == 0) 9487 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << ring->queue); 9488 else 9489 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << ring->queue); 9490 9491 gfx_v10_0_ring_emit_wreg(kiq_ring, 9492 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), tmp); 9493 gfx_v10_0_wait_reg_mem(kiq_ring, 0, 1, 0, 9494 lower_32_bits(addr), upper_32_bits(addr), 9495 0, 1, 0x20); 9496 gfx_v10_0_ring_emit_reg_wait(kiq_ring, 9497 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0, 0xffffffff); 9498 kiq->pmf->kiq_map_queues(kiq_ring, ring); 9499 amdgpu_ring_commit(kiq_ring); 9500 9501 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9502 9503 r = amdgpu_ring_test_ring(kiq_ring); 9504 if (r) 9505 return r; 9506 9507 r = amdgpu_bo_reserve(ring->mqd_obj, false); 9508 if (unlikely(r != 0)) { 9509 DRM_ERROR("fail to resv mqd_obj\n"); 9510 return r; 9511 } 9512 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 9513 if (!r) { 9514 r = gfx_v10_0_kgq_init_queue(ring, true); 9515 amdgpu_bo_kunmap(ring->mqd_obj); 9516 ring->mqd_ptr = NULL; 9517 } 9518 amdgpu_bo_unreserve(ring->mqd_obj); 9519 if (r) { 9520 DRM_ERROR("fail to unresv mqd_obj\n"); 9521 return r; 9522 } 9523 9524 return amdgpu_ring_test_ring(ring); 9525 } 9526 9527 static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring, 9528 unsigned int vmid) 9529 { 9530 struct amdgpu_device *adev = ring->adev; 9531 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 9532 struct amdgpu_ring *kiq_ring = &kiq->ring; 9533 unsigned long flags; 9534 int i, r; 9535 9536 if (amdgpu_sriov_vf(adev)) 9537 return -EINVAL; 9538 9539 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 9540 return -EINVAL; 9541 9542 spin_lock_irqsave(&kiq->ring_lock, flags); 9543 9544 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 9545 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9546 return -ENOMEM; 9547 } 9548 9549 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 9550 0, 0); 9551 amdgpu_ring_commit(kiq_ring); 9552 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9553 9554 r = amdgpu_ring_test_ring(kiq_ring); 9555 if (r) 9556 return r; 9557 9558 /* make sure dequeue is complete*/ 9559 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 9560 mutex_lock(&adev->srbm_mutex); 9561 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 9562 for (i = 0; i < adev->usec_timeout; i++) { 9563 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 9564 break; 9565 udelay(1); 9566 } 9567 if (i >= adev->usec_timeout) 9568 r = -ETIMEDOUT; 9569 nv_grbm_select(adev, 0, 0, 0, 0); 9570 mutex_unlock(&adev->srbm_mutex); 9571 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 9572 if (r) { 9573 dev_err(adev->dev, "fail to wait on hqd deactivate\n"); 9574 return r; 9575 } 9576 9577 r = amdgpu_bo_reserve(ring->mqd_obj, false); 9578 if (unlikely(r != 0)) { 9579 dev_err(adev->dev, "fail to resv mqd_obj\n"); 9580 return r; 9581 } 9582 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 9583 if (!r) { 9584 r = gfx_v10_0_kcq_init_queue(ring, true); 9585 amdgpu_bo_kunmap(ring->mqd_obj); 9586 ring->mqd_ptr = NULL; 9587 } 9588 amdgpu_bo_unreserve(ring->mqd_obj); 9589 if (r) { 9590 dev_err(adev->dev, "fail to unresv mqd_obj\n"); 9591 return r; 9592 } 9593 9594 spin_lock_irqsave(&kiq->ring_lock, flags); 9595 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size)) { 9596 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9597 return -ENOMEM; 9598 } 9599 kiq->pmf->kiq_map_queues(kiq_ring, ring); 9600 amdgpu_ring_commit(kiq_ring); 9601 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9602 9603 r = amdgpu_ring_test_ring(kiq_ring); 9604 if (r) 9605 return r; 9606 9607 return amdgpu_ring_test_ring(ring); 9608 } 9609 9610 static void gfx_v10_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 9611 { 9612 struct amdgpu_device *adev = ip_block->adev; 9613 uint32_t i, j, k, reg, index = 0; 9614 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 9615 9616 if (!adev->gfx.ip_dump_core) 9617 return; 9618 9619 for (i = 0; i < reg_count; i++) 9620 drm_printf(p, "%-50s \t 0x%08x\n", 9621 gc_reg_list_10_1[i].reg_name, 9622 adev->gfx.ip_dump_core[i]); 9623 9624 /* print compute queue registers for all instances */ 9625 if (!adev->gfx.ip_dump_compute_queues) 9626 return; 9627 9628 reg_count = ARRAY_SIZE(gc_cp_reg_list_10); 9629 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 9630 adev->gfx.mec.num_mec, 9631 adev->gfx.mec.num_pipe_per_mec, 9632 adev->gfx.mec.num_queue_per_pipe); 9633 9634 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9635 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9636 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 9637 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 9638 for (reg = 0; reg < reg_count; reg++) { 9639 drm_printf(p, "%-50s \t 0x%08x\n", 9640 gc_cp_reg_list_10[reg].reg_name, 9641 adev->gfx.ip_dump_compute_queues[index + reg]); 9642 } 9643 index += reg_count; 9644 } 9645 } 9646 } 9647 9648 /* print gfx queue registers for all instances */ 9649 if (!adev->gfx.ip_dump_gfx_queues) 9650 return; 9651 9652 index = 0; 9653 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10); 9654 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 9655 adev->gfx.me.num_me, 9656 adev->gfx.me.num_pipe_per_me, 9657 adev->gfx.me.num_queue_per_pipe); 9658 9659 for (i = 0; i < adev->gfx.me.num_me; i++) { 9660 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9661 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 9662 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 9663 for (reg = 0; reg < reg_count; reg++) { 9664 drm_printf(p, "%-50s \t 0x%08x\n", 9665 gc_gfx_queue_reg_list_10[reg].reg_name, 9666 adev->gfx.ip_dump_gfx_queues[index + reg]); 9667 } 9668 index += reg_count; 9669 } 9670 } 9671 } 9672 } 9673 9674 static void gfx_v10_ip_dump(struct amdgpu_ip_block *ip_block) 9675 { 9676 struct amdgpu_device *adev = ip_block->adev; 9677 uint32_t i, j, k, reg, index = 0; 9678 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 9679 9680 if (!adev->gfx.ip_dump_core) 9681 return; 9682 9683 amdgpu_gfx_off_ctrl(adev, false); 9684 for (i = 0; i < reg_count; i++) 9685 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i])); 9686 amdgpu_gfx_off_ctrl(adev, true); 9687 9688 /* dump compute queue registers for all instances */ 9689 if (!adev->gfx.ip_dump_compute_queues) 9690 return; 9691 9692 reg_count = ARRAY_SIZE(gc_cp_reg_list_10); 9693 amdgpu_gfx_off_ctrl(adev, false); 9694 mutex_lock(&adev->srbm_mutex); 9695 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9696 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9697 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 9698 /* ME0 is for GFX so start from 1 for CP */ 9699 nv_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 9700 9701 for (reg = 0; reg < reg_count; reg++) { 9702 adev->gfx.ip_dump_compute_queues[index + reg] = 9703 RREG32(SOC15_REG_ENTRY_OFFSET( 9704 gc_cp_reg_list_10[reg])); 9705 } 9706 index += reg_count; 9707 } 9708 } 9709 } 9710 nv_grbm_select(adev, 0, 0, 0, 0); 9711 mutex_unlock(&adev->srbm_mutex); 9712 amdgpu_gfx_off_ctrl(adev, true); 9713 9714 /* dump gfx queue registers for all instances */ 9715 if (!adev->gfx.ip_dump_gfx_queues) 9716 return; 9717 9718 index = 0; 9719 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10); 9720 amdgpu_gfx_off_ctrl(adev, false); 9721 mutex_lock(&adev->srbm_mutex); 9722 for (i = 0; i < adev->gfx.me.num_me; i++) { 9723 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9724 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 9725 nv_grbm_select(adev, i, j, k, 0); 9726 9727 for (reg = 0; reg < reg_count; reg++) { 9728 adev->gfx.ip_dump_gfx_queues[index + reg] = 9729 RREG32(SOC15_REG_ENTRY_OFFSET( 9730 gc_gfx_queue_reg_list_10[reg])); 9731 } 9732 index += reg_count; 9733 } 9734 } 9735 } 9736 nv_grbm_select(adev, 0, 0, 0, 0); 9737 mutex_unlock(&adev->srbm_mutex); 9738 amdgpu_gfx_off_ctrl(adev, true); 9739 } 9740 9741 static void gfx_v10_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 9742 { 9743 /* Emit the cleaner shader */ 9744 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 9745 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 9746 } 9747 9748 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 9749 .name = "gfx_v10_0", 9750 .early_init = gfx_v10_0_early_init, 9751 .late_init = gfx_v10_0_late_init, 9752 .sw_init = gfx_v10_0_sw_init, 9753 .sw_fini = gfx_v10_0_sw_fini, 9754 .hw_init = gfx_v10_0_hw_init, 9755 .hw_fini = gfx_v10_0_hw_fini, 9756 .suspend = gfx_v10_0_suspend, 9757 .resume = gfx_v10_0_resume, 9758 .is_idle = gfx_v10_0_is_idle, 9759 .wait_for_idle = gfx_v10_0_wait_for_idle, 9760 .soft_reset = gfx_v10_0_soft_reset, 9761 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 9762 .set_powergating_state = gfx_v10_0_set_powergating_state, 9763 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 9764 .dump_ip_state = gfx_v10_ip_dump, 9765 .print_ip_state = gfx_v10_ip_print, 9766 }; 9767 9768 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 9769 .type = AMDGPU_RING_TYPE_GFX, 9770 .align_mask = 0xff, 9771 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9772 .support_64bit_ptrs = true, 9773 .secure_submission_supported = true, 9774 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 9775 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 9776 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 9777 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 9778 5 + /* COND_EXEC */ 9779 7 + /* PIPELINE_SYNC */ 9780 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9781 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9782 4 + /* VM_FLUSH */ 9783 8 + /* FENCE for VM_FLUSH */ 9784 20 + /* GDS switch */ 9785 4 + /* double SWITCH_BUFFER, 9786 * the first COND_EXEC jump to the place 9787 * just prior to this double SWITCH_BUFFER 9788 */ 9789 5 + /* COND_EXEC */ 9790 7 + /* HDP_flush */ 9791 4 + /* VGT_flush */ 9792 14 + /* CE_META */ 9793 31 + /* DE_META */ 9794 3 + /* CNTX_CTRL */ 9795 5 + /* HDP_INVL */ 9796 8 + 8 + /* FENCE x2 */ 9797 2 + /* SWITCH_BUFFER */ 9798 8 + /* gfx_v10_0_emit_mem_sync */ 9799 2, /* gfx_v10_0_ring_emit_cleaner_shader */ 9800 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 9801 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 9802 .emit_fence = gfx_v10_0_ring_emit_fence, 9803 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9804 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9805 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9806 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9807 .test_ring = gfx_v10_0_ring_test_ring, 9808 .test_ib = gfx_v10_0_ring_test_ib, 9809 .insert_nop = gfx_v10_ring_insert_nop, 9810 .pad_ib = amdgpu_ring_generic_pad_ib, 9811 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 9812 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 9813 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 9814 .preempt_ib = gfx_v10_0_ring_preempt_ib, 9815 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 9816 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9817 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9818 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9819 .soft_recovery = gfx_v10_0_ring_soft_recovery, 9820 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9821 .reset = gfx_v10_0_reset_kgq, 9822 .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader, 9823 .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, 9824 .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, 9825 }; 9826 9827 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 9828 .type = AMDGPU_RING_TYPE_COMPUTE, 9829 .align_mask = 0xff, 9830 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9831 .support_64bit_ptrs = true, 9832 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9833 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9834 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9835 .emit_frame_size = 9836 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9837 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9838 5 + /* hdp invalidate */ 9839 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9840 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9841 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9842 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9843 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 9844 8 + /* gfx_v10_0_emit_mem_sync */ 9845 2, /* gfx_v10_0_ring_emit_cleaner_shader */ 9846 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9847 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9848 .emit_fence = gfx_v10_0_ring_emit_fence, 9849 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9850 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9851 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9852 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9853 .test_ring = gfx_v10_0_ring_test_ring, 9854 .test_ib = gfx_v10_0_ring_test_ib, 9855 .insert_nop = gfx_v10_ring_insert_nop, 9856 .pad_ib = amdgpu_ring_generic_pad_ib, 9857 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9858 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9859 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9860 .soft_recovery = gfx_v10_0_ring_soft_recovery, 9861 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9862 .reset = gfx_v10_0_reset_kcq, 9863 .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader, 9864 .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, 9865 .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, 9866 }; 9867 9868 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 9869 .type = AMDGPU_RING_TYPE_KIQ, 9870 .align_mask = 0xff, 9871 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9872 .support_64bit_ptrs = true, 9873 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9874 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9875 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9876 .emit_frame_size = 9877 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9878 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9879 5 + /*hdp invalidate */ 9880 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9881 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9882 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9883 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 9884 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9885 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9886 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 9887 .test_ring = gfx_v10_0_ring_test_ring, 9888 .test_ib = gfx_v10_0_ring_test_ib, 9889 .insert_nop = amdgpu_ring_insert_nop, 9890 .pad_ib = amdgpu_ring_generic_pad_ib, 9891 .emit_rreg = gfx_v10_0_ring_emit_rreg, 9892 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9893 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9894 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9895 }; 9896 9897 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 9898 { 9899 int i; 9900 9901 adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq; 9902 9903 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 9904 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 9905 9906 for (i = 0; i < adev->gfx.num_compute_rings; i++) 9907 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 9908 } 9909 9910 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 9911 .set = gfx_v10_0_set_eop_interrupt_state, 9912 .process = gfx_v10_0_eop_irq, 9913 }; 9914 9915 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 9916 .set = gfx_v10_0_set_priv_reg_fault_state, 9917 .process = gfx_v10_0_priv_reg_irq, 9918 }; 9919 9920 static const struct amdgpu_irq_src_funcs gfx_v10_0_bad_op_irq_funcs = { 9921 .set = gfx_v10_0_set_bad_op_fault_state, 9922 .process = gfx_v10_0_bad_op_irq, 9923 }; 9924 9925 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 9926 .set = gfx_v10_0_set_priv_inst_fault_state, 9927 .process = gfx_v10_0_priv_inst_irq, 9928 }; 9929 9930 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 9931 .set = gfx_v10_0_kiq_set_interrupt_state, 9932 .process = gfx_v10_0_kiq_irq, 9933 }; 9934 9935 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 9936 { 9937 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 9938 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 9939 9940 adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 9941 adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs; 9942 9943 adev->gfx.priv_reg_irq.num_types = 1; 9944 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 9945 9946 adev->gfx.bad_op_irq.num_types = 1; 9947 adev->gfx.bad_op_irq.funcs = &gfx_v10_0_bad_op_irq_funcs; 9948 9949 adev->gfx.priv_inst_irq.num_types = 1; 9950 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 9951 } 9952 9953 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 9954 { 9955 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 9956 case IP_VERSION(10, 1, 10): 9957 case IP_VERSION(10, 1, 1): 9958 case IP_VERSION(10, 1, 3): 9959 case IP_VERSION(10, 1, 4): 9960 case IP_VERSION(10, 3, 2): 9961 case IP_VERSION(10, 3, 1): 9962 case IP_VERSION(10, 3, 4): 9963 case IP_VERSION(10, 3, 5): 9964 case IP_VERSION(10, 3, 6): 9965 case IP_VERSION(10, 3, 3): 9966 case IP_VERSION(10, 3, 7): 9967 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 9968 break; 9969 case IP_VERSION(10, 1, 2): 9970 case IP_VERSION(10, 3, 0): 9971 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 9972 break; 9973 default: 9974 break; 9975 } 9976 } 9977 9978 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 9979 { 9980 unsigned int total_cu = adev->gfx.config.max_cu_per_sh * 9981 adev->gfx.config.max_sh_per_se * 9982 adev->gfx.config.max_shader_engines; 9983 9984 adev->gds.gds_size = 0x10000; 9985 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 9986 adev->gds.gws_size = 64; 9987 adev->gds.oa_size = 16; 9988 } 9989 9990 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev) 9991 { 9992 /* set gfx eng mqd */ 9993 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 9994 sizeof(struct v10_gfx_mqd); 9995 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 9996 gfx_v10_0_gfx_mqd_init; 9997 /* set compute eng mqd */ 9998 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 9999 sizeof(struct v10_compute_mqd); 10000 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 10001 gfx_v10_0_compute_mqd_init; 10002 } 10003 10004 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 10005 u32 bitmap) 10006 { 10007 u32 data; 10008 10009 if (!bitmap) 10010 return; 10011 10012 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 10013 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 10014 10015 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 10016 } 10017 10018 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 10019 { 10020 u32 disabled_mask = 10021 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 10022 u32 efuse_setting = 0; 10023 u32 vbios_setting = 0; 10024 10025 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 10026 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 10027 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 10028 10029 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 10030 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 10031 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 10032 10033 disabled_mask |= efuse_setting | vbios_setting; 10034 10035 return (~disabled_mask); 10036 } 10037 10038 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 10039 { 10040 u32 wgp_idx, wgp_active_bitmap; 10041 u32 cu_bitmap_per_wgp, cu_active_bitmap; 10042 10043 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 10044 cu_active_bitmap = 0; 10045 10046 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 10047 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 10048 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 10049 if (wgp_active_bitmap & (1 << wgp_idx)) 10050 cu_active_bitmap |= cu_bitmap_per_wgp; 10051 } 10052 10053 return cu_active_bitmap; 10054 } 10055 10056 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 10057 struct amdgpu_cu_info *cu_info) 10058 { 10059 int i, j, k, counter, active_cu_number = 0; 10060 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 10061 unsigned int disable_masks[4 * 2]; 10062 10063 if (!adev || !cu_info) 10064 return -EINVAL; 10065 10066 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 10067 10068 mutex_lock(&adev->grbm_idx_mutex); 10069 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 10070 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 10071 bitmap = i * adev->gfx.config.max_sh_per_se + j; 10072 if (((amdgpu_ip_version(adev, GC_HWIP, 0) == 10073 IP_VERSION(10, 3, 0)) || 10074 (amdgpu_ip_version(adev, GC_HWIP, 0) == 10075 IP_VERSION(10, 3, 3)) || 10076 (amdgpu_ip_version(adev, GC_HWIP, 0) == 10077 IP_VERSION(10, 3, 6)) || 10078 (amdgpu_ip_version(adev, GC_HWIP, 0) == 10079 IP_VERSION(10, 3, 7))) && 10080 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 10081 continue; 10082 mask = 1; 10083 ao_bitmap = 0; 10084 counter = 0; 10085 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 10086 if (i < 4 && j < 2) 10087 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 10088 adev, disable_masks[i * 2 + j]); 10089 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 10090 cu_info->bitmap[0][i][j] = bitmap; 10091 10092 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 10093 if (bitmap & mask) { 10094 if (counter < adev->gfx.config.max_cu_per_sh) 10095 ao_bitmap |= mask; 10096 counter++; 10097 } 10098 mask <<= 1; 10099 } 10100 active_cu_number += counter; 10101 if (i < 2 && j < 2) 10102 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 10103 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 10104 } 10105 } 10106 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 10107 mutex_unlock(&adev->grbm_idx_mutex); 10108 10109 cu_info->number = active_cu_number; 10110 cu_info->ao_cu_mask = ao_cu_mask; 10111 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 10112 10113 return 0; 10114 } 10115 10116 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 10117 { 10118 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 10119 10120 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 10121 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 10122 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 10123 10124 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 10125 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 10126 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 10127 10128 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 10129 adev->gfx.config.max_shader_engines); 10130 disabled_sa = efuse_setting | vbios_setting; 10131 disabled_sa &= max_sa_mask; 10132 10133 return disabled_sa; 10134 } 10135 10136 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 10137 { 10138 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 10139 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 10140 10141 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 10142 10143 max_sa_per_se = adev->gfx.config.max_sh_per_se; 10144 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 10145 max_shader_engines = adev->gfx.config.max_shader_engines; 10146 10147 for (se_index = 0; max_shader_engines > se_index; se_index++) { 10148 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 10149 disabled_sa_per_se &= max_sa_per_se_mask; 10150 if (disabled_sa_per_se == max_sa_per_se_mask) { 10151 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 10152 break; 10153 } 10154 } 10155 } 10156 10157 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) 10158 { 10159 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 10160 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) | 10161 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) | 10162 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 10163 10164 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); 10165 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, 10166 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) | 10167 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) | 10168 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) | 10169 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT)); 10170 10171 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid, 10172 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) | 10173 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) | 10174 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT)); 10175 10176 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); 10177 10178 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA, 10179 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT)); 10180 } 10181 10182 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = { 10183 .type = AMD_IP_BLOCK_TYPE_GFX, 10184 .major = 10, 10185 .minor = 0, 10186 .rev = 0, 10187 .funcs = &gfx_v10_0_ip_funcs, 10188 }; 10189