1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include <drm/drm_edid.h> 27 #include <drm/drm_fourcc.h> 28 #include <drm/drm_modeset_helper.h> 29 #include <drm/drm_modeset_helper_vtables.h> 30 #include <drm/drm_vblank.h> 31 32 #include "amdgpu.h" 33 #include "amdgpu_pm.h" 34 #include "amdgpu_i2c.h" 35 #include "atom.h" 36 #include "amdgpu_atombios.h" 37 #include "atombios_crtc.h" 38 #include "atombios_encoders.h" 39 #include "amdgpu_pll.h" 40 #include "amdgpu_connectors.h" 41 #include "amdgpu_display.h" 42 43 #include "bif/bif_3_0_d.h" 44 #include "bif/bif_3_0_sh_mask.h" 45 #include "oss/oss_1_0_d.h" 46 #include "oss/oss_1_0_sh_mask.h" 47 #include "gca/gfx_6_0_d.h" 48 #include "gca/gfx_6_0_sh_mask.h" 49 #include "gmc/gmc_6_0_d.h" 50 #include "gmc/gmc_6_0_sh_mask.h" 51 #include "dce/dce_6_0_d.h" 52 #include "dce/dce_6_0_sh_mask.h" 53 #include "gca/gfx_7_2_enum.h" 54 #include "dce_v6_0.h" 55 #include "si_enums.h" 56 57 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev); 58 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev); 59 60 static const u32 crtc_offsets[6] = 61 { 62 SI_CRTC0_REGISTER_OFFSET, 63 SI_CRTC1_REGISTER_OFFSET, 64 SI_CRTC2_REGISTER_OFFSET, 65 SI_CRTC3_REGISTER_OFFSET, 66 SI_CRTC4_REGISTER_OFFSET, 67 SI_CRTC5_REGISTER_OFFSET 68 }; 69 70 static const u32 hpd_offsets[] = 71 { 72 mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS, 73 mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS, 74 mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS, 75 mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS, 76 mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS, 77 mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS, 78 }; 79 80 static const uint32_t dig_offsets[] = { 81 SI_CRTC0_REGISTER_OFFSET, 82 SI_CRTC1_REGISTER_OFFSET, 83 SI_CRTC2_REGISTER_OFFSET, 84 SI_CRTC3_REGISTER_OFFSET, 85 SI_CRTC4_REGISTER_OFFSET, 86 SI_CRTC5_REGISTER_OFFSET, 87 (0x13830 - 0x7030) >> 2, 88 }; 89 90 static const struct { 91 uint32_t reg; 92 uint32_t vblank; 93 uint32_t vline; 94 uint32_t hpd; 95 96 } interrupt_status_offsets[6] = { { 97 .reg = mmDISP_INTERRUPT_STATUS, 98 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 99 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 100 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 101 }, { 102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 104 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 106 }, { 107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 109 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 111 }, { 112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 114 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 116 }, { 117 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 118 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 119 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 120 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 121 }, { 122 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 123 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 124 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 125 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 126 } }; 127 128 static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev, 129 u32 block_offset, u32 reg) 130 { 131 unsigned long flags; 132 u32 r; 133 134 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 135 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 136 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 137 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 138 139 return r; 140 } 141 142 static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev, 143 u32 block_offset, u32 reg, u32 v) 144 { 145 unsigned long flags; 146 147 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 148 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, 149 reg | AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK); 150 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 151 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 152 } 153 154 static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 155 { 156 if (crtc >= adev->mode_info.num_crtc) 157 return 0; 158 else 159 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 160 } 161 162 static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev) 163 { 164 unsigned i; 165 166 /* Enable pflip interrupts */ 167 for (i = 0; i < adev->mode_info.num_crtc; i++) 168 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 169 } 170 171 static void dce_v6_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 172 { 173 unsigned i; 174 175 /* Disable pflip interrupts */ 176 for (i = 0; i < adev->mode_info.num_crtc; i++) 177 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 178 } 179 180 /** 181 * dce_v6_0_page_flip - pageflip callback. 182 * 183 * @adev: amdgpu_device pointer 184 * @crtc_id: crtc to cleanup pageflip on 185 * @crtc_base: new address of the crtc (GPU MC address) 186 * @async: asynchronous flip 187 * 188 * Does the actual pageflip (evergreen+). 189 * During vblank we take the crtc lock and wait for the update_pending 190 * bit to go high, when it does, we release the lock, and allow the 191 * double buffered update to take place. 192 * Returns the current update pending status. 193 */ 194 static void dce_v6_0_page_flip(struct amdgpu_device *adev, 195 int crtc_id, u64 crtc_base, bool async) 196 { 197 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 198 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; 199 200 /* flip at hsync for async, default is vsync */ 201 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? 202 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); 203 /* update pitch */ 204 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, 205 fb->pitches[0] / fb->format->cpp[0]); 206 /* update the scanout addresses */ 207 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 208 upper_32_bits(crtc_base)); 209 /* writing to the low address triggers the update */ 210 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 211 (u32)crtc_base); 212 /* post the write */ 213 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 214 } 215 216 static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 217 u32 *vbl, u32 *position) 218 { 219 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 220 return -EINVAL; 221 222 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 223 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 224 225 return 0; 226 } 227 228 /** 229 * dce_v6_0_hpd_sense - hpd sense callback. 230 * 231 * @adev: amdgpu_device pointer 232 * @hpd: hpd (hotplug detect) pin 233 * 234 * Checks if a digital monitor is connected (evergreen+). 235 * Returns true if connected, false if not connected. 236 */ 237 static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev, 238 enum amdgpu_hpd_id hpd) 239 { 240 bool connected = false; 241 242 if (hpd >= adev->mode_info.num_hpd) 243 return connected; 244 245 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & 246 DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) 247 connected = true; 248 249 return connected; 250 } 251 252 /** 253 * dce_v6_0_hpd_set_polarity - hpd set polarity callback. 254 * 255 * @adev: amdgpu_device pointer 256 * @hpd: hpd (hotplug detect) pin 257 * 258 * Set the polarity of the hpd pin (evergreen+). 259 */ 260 static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev, 261 enum amdgpu_hpd_id hpd) 262 { 263 u32 tmp; 264 bool connected = dce_v6_0_hpd_sense(adev, hpd); 265 266 if (hpd >= adev->mode_info.num_hpd) 267 return; 268 269 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 270 if (connected) 271 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 272 else 273 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 274 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 275 } 276 277 static void dce_v6_0_hpd_int_ack(struct amdgpu_device *adev, 278 int hpd) 279 { 280 u32 tmp; 281 282 if (hpd >= adev->mode_info.num_hpd) { 283 DRM_DEBUG("invalid hdp %d\n", hpd); 284 return; 285 } 286 287 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 288 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; 289 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 290 } 291 292 /** 293 * dce_v6_0_hpd_init - hpd setup callback. 294 * 295 * @adev: amdgpu_device pointer 296 * 297 * Setup the hpd pins used by the card (evergreen+). 298 * Enable the pin, set the polarity, and enable the hpd interrupts. 299 */ 300 static void dce_v6_0_hpd_init(struct amdgpu_device *adev) 301 { 302 struct drm_device *dev = adev_to_drm(adev); 303 struct drm_connector *connector; 304 struct drm_connector_list_iter iter; 305 u32 tmp; 306 307 drm_connector_list_iter_begin(dev, &iter); 308 drm_for_each_connector_iter(connector, &iter) { 309 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 310 311 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 312 continue; 313 314 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 315 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK; 316 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 317 318 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 319 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 320 /* don't try to enable hpd on eDP or LVDS avoid breaking the 321 * aux dp channel on imac and help (but not completely fix) 322 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 323 * also avoid interrupt storms during dpms. 324 */ 325 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 326 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 327 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 328 continue; 329 } 330 331 dce_v6_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd); 332 dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 333 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 334 } 335 drm_connector_list_iter_end(&iter); 336 } 337 338 /** 339 * dce_v6_0_hpd_fini - hpd tear down callback. 340 * 341 * @adev: amdgpu_device pointer 342 * 343 * Tear down the hpd pins used by the card (evergreen+). 344 * Disable the hpd interrupts. 345 */ 346 static void dce_v6_0_hpd_fini(struct amdgpu_device *adev) 347 { 348 struct drm_device *dev = adev_to_drm(adev); 349 struct drm_connector *connector; 350 struct drm_connector_list_iter iter; 351 u32 tmp; 352 353 drm_connector_list_iter_begin(dev, &iter); 354 drm_for_each_connector_iter(connector, &iter) { 355 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 356 357 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 358 continue; 359 360 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 361 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK; 362 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 363 364 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 365 } 366 drm_connector_list_iter_end(&iter); 367 } 368 369 static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 370 { 371 return mmDC_GPIO_HPD_A; 372 } 373 374 static bool dce_v6_0_is_display_hung(struct amdgpu_device *adev) 375 { 376 u32 crtc_hung = 0; 377 u32 crtc_status[6]; 378 u32 i, j, tmp; 379 380 for (i = 0; i < adev->mode_info.num_crtc; i++) { 381 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) { 382 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 383 crtc_hung |= (1 << i); 384 } 385 } 386 387 for (j = 0; j < 10; j++) { 388 for (i = 0; i < adev->mode_info.num_crtc; i++) { 389 if (crtc_hung & (1 << i)) { 390 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 391 if (tmp != crtc_status[i]) 392 crtc_hung &= ~(1 << i); 393 } 394 } 395 if (crtc_hung == 0) 396 return false; 397 udelay(100); 398 } 399 400 return true; 401 } 402 403 static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev, 404 bool render) 405 { 406 if (!render) 407 WREG32(mmVGA_RENDER_CONTROL, 408 RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL); 409 } 410 411 static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev) 412 { 413 switch (adev->asic_type) { 414 case CHIP_TAHITI: 415 case CHIP_PITCAIRN: 416 case CHIP_VERDE: 417 return 6; 418 case CHIP_OLAND: 419 return 2; 420 default: 421 return 0; 422 } 423 } 424 425 void dce_v6_0_disable_dce(struct amdgpu_device *adev) 426 { 427 /*Disable VGA render and enabled crtc, if has DCE engine*/ 428 if (amdgpu_atombios_has_dce_engine_info(adev)) { 429 u32 tmp; 430 int crtc_enabled, i; 431 432 dce_v6_0_set_vga_render_state(adev, false); 433 434 /*Disable crtc*/ 435 for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) { 436 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & 437 CRTC_CONTROL__CRTC_MASTER_EN_MASK; 438 if (crtc_enabled) { 439 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 440 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 441 tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK; 442 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 443 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 444 } 445 } 446 } 447 } 448 449 static void dce_v6_0_program_fmt(struct drm_encoder *encoder) 450 { 451 struct drm_device *dev = encoder->dev; 452 struct amdgpu_device *adev = drm_to_adev(dev); 453 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 454 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 455 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 456 int bpc = 0; 457 u32 tmp = 0; 458 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 459 460 if (connector) { 461 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 462 bpc = amdgpu_connector_get_monitor_bpc(connector); 463 dither = amdgpu_connector->dither; 464 } 465 466 /* LVDS FMT is set up by atom */ 467 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 468 return; 469 470 if (bpc == 0) 471 return; 472 473 474 switch (bpc) { 475 case 6: 476 if (dither == AMDGPU_FMT_DITHER_ENABLE) 477 /* XXX sort out optimal dither settings */ 478 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 479 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 480 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK); 481 else 482 tmp |= FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK; 483 break; 484 case 8: 485 if (dither == AMDGPU_FMT_DITHER_ENABLE) 486 /* XXX sort out optimal dither settings */ 487 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 488 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 489 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK | 490 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | 491 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK); 492 else 493 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | 494 FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK); 495 break; 496 case 10: 497 default: 498 /* not needed */ 499 break; 500 } 501 502 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 503 } 504 505 /** 506 * si_get_number_of_dram_channels - get the number of dram channels 507 * 508 * @adev: amdgpu_device pointer 509 * 510 * Look up the number of video ram channels (CIK). 511 * Used for display watermark bandwidth calculations 512 * Returns the number of dram channels 513 */ 514 static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev) 515 { 516 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 517 518 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { 519 case 0: 520 default: 521 return 1; 522 case 1: 523 return 2; 524 case 2: 525 return 4; 526 case 3: 527 return 8; 528 case 4: 529 return 3; 530 case 5: 531 return 6; 532 case 6: 533 return 10; 534 case 7: 535 return 12; 536 case 8: 537 return 16; 538 } 539 } 540 541 struct dce6_wm_params { 542 u32 dram_channels; /* number of dram channels */ 543 u32 yclk; /* bandwidth per dram data pin in kHz */ 544 u32 sclk; /* engine clock in kHz */ 545 u32 disp_clk; /* display clock in kHz */ 546 u32 src_width; /* viewport width */ 547 u32 active_time; /* active display time in ns */ 548 u32 blank_time; /* blank time in ns */ 549 bool interlaced; /* mode is interlaced */ 550 fixed20_12 vsc; /* vertical scale ratio */ 551 u32 num_heads; /* number of active crtcs */ 552 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 553 u32 lb_size; /* line buffer allocated to pipe */ 554 u32 vtaps; /* vertical scaler taps */ 555 }; 556 557 /** 558 * dce_v6_0_dram_bandwidth - get the dram bandwidth 559 * 560 * @wm: watermark calculation data 561 * 562 * Calculate the raw dram bandwidth (CIK). 563 * Used for display watermark bandwidth calculations 564 * Returns the dram bandwidth in MBytes/s 565 */ 566 static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm) 567 { 568 /* Calculate raw DRAM Bandwidth */ 569 fixed20_12 dram_efficiency; /* 0.7 */ 570 fixed20_12 yclk, dram_channels, bandwidth; 571 fixed20_12 a; 572 573 a.full = dfixed_const(1000); 574 yclk.full = dfixed_const(wm->yclk); 575 yclk.full = dfixed_div(yclk, a); 576 dram_channels.full = dfixed_const(wm->dram_channels * 4); 577 a.full = dfixed_const(10); 578 dram_efficiency.full = dfixed_const(7); 579 dram_efficiency.full = dfixed_div(dram_efficiency, a); 580 bandwidth.full = dfixed_mul(dram_channels, yclk); 581 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 582 583 return dfixed_trunc(bandwidth); 584 } 585 586 /** 587 * dce_v6_0_dram_bandwidth_for_display - get the dram bandwidth for display 588 * 589 * @wm: watermark calculation data 590 * 591 * Calculate the dram bandwidth used for display (CIK). 592 * Used for display watermark bandwidth calculations 593 * Returns the dram bandwidth for display in MBytes/s 594 */ 595 static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm) 596 { 597 /* Calculate DRAM Bandwidth and the part allocated to display. */ 598 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 599 fixed20_12 yclk, dram_channels, bandwidth; 600 fixed20_12 a; 601 602 a.full = dfixed_const(1000); 603 yclk.full = dfixed_const(wm->yclk); 604 yclk.full = dfixed_div(yclk, a); 605 dram_channels.full = dfixed_const(wm->dram_channels * 4); 606 a.full = dfixed_const(10); 607 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 608 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 609 bandwidth.full = dfixed_mul(dram_channels, yclk); 610 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 611 612 return dfixed_trunc(bandwidth); 613 } 614 615 /** 616 * dce_v6_0_data_return_bandwidth - get the data return bandwidth 617 * 618 * @wm: watermark calculation data 619 * 620 * Calculate the data return bandwidth used for display (CIK). 621 * Used for display watermark bandwidth calculations 622 * Returns the data return bandwidth in MBytes/s 623 */ 624 static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm) 625 { 626 /* Calculate the display Data return Bandwidth */ 627 fixed20_12 return_efficiency; /* 0.8 */ 628 fixed20_12 sclk, bandwidth; 629 fixed20_12 a; 630 631 a.full = dfixed_const(1000); 632 sclk.full = dfixed_const(wm->sclk); 633 sclk.full = dfixed_div(sclk, a); 634 a.full = dfixed_const(10); 635 return_efficiency.full = dfixed_const(8); 636 return_efficiency.full = dfixed_div(return_efficiency, a); 637 a.full = dfixed_const(32); 638 bandwidth.full = dfixed_mul(a, sclk); 639 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 640 641 return dfixed_trunc(bandwidth); 642 } 643 644 /** 645 * dce_v6_0_dmif_request_bandwidth - get the dmif bandwidth 646 * 647 * @wm: watermark calculation data 648 * 649 * Calculate the dmif bandwidth used for display (CIK). 650 * Used for display watermark bandwidth calculations 651 * Returns the dmif bandwidth in MBytes/s 652 */ 653 static u32 dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params *wm) 654 { 655 /* Calculate the DMIF Request Bandwidth */ 656 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 657 fixed20_12 disp_clk, bandwidth; 658 fixed20_12 a, b; 659 660 a.full = dfixed_const(1000); 661 disp_clk.full = dfixed_const(wm->disp_clk); 662 disp_clk.full = dfixed_div(disp_clk, a); 663 a.full = dfixed_const(32); 664 b.full = dfixed_mul(a, disp_clk); 665 666 a.full = dfixed_const(10); 667 disp_clk_request_efficiency.full = dfixed_const(8); 668 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 669 670 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 671 672 return dfixed_trunc(bandwidth); 673 } 674 675 /** 676 * dce_v6_0_available_bandwidth - get the min available bandwidth 677 * 678 * @wm: watermark calculation data 679 * 680 * Calculate the min available bandwidth used for display (CIK). 681 * Used for display watermark bandwidth calculations 682 * Returns the min available bandwidth in MBytes/s 683 */ 684 static u32 dce_v6_0_available_bandwidth(struct dce6_wm_params *wm) 685 { 686 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 687 u32 dram_bandwidth = dce_v6_0_dram_bandwidth(wm); 688 u32 data_return_bandwidth = dce_v6_0_data_return_bandwidth(wm); 689 u32 dmif_req_bandwidth = dce_v6_0_dmif_request_bandwidth(wm); 690 691 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 692 } 693 694 /** 695 * dce_v6_0_average_bandwidth - get the average available bandwidth 696 * 697 * @wm: watermark calculation data 698 * 699 * Calculate the average available bandwidth used for display (CIK). 700 * Used for display watermark bandwidth calculations 701 * Returns the average available bandwidth in MBytes/s 702 */ 703 static u32 dce_v6_0_average_bandwidth(struct dce6_wm_params *wm) 704 { 705 /* Calculate the display mode Average Bandwidth 706 * DisplayMode should contain the source and destination dimensions, 707 * timing, etc. 708 */ 709 fixed20_12 bpp; 710 fixed20_12 line_time; 711 fixed20_12 src_width; 712 fixed20_12 bandwidth; 713 fixed20_12 a; 714 715 a.full = dfixed_const(1000); 716 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 717 line_time.full = dfixed_div(line_time, a); 718 bpp.full = dfixed_const(wm->bytes_per_pixel); 719 src_width.full = dfixed_const(wm->src_width); 720 bandwidth.full = dfixed_mul(src_width, bpp); 721 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 722 bandwidth.full = dfixed_div(bandwidth, line_time); 723 724 return dfixed_trunc(bandwidth); 725 } 726 727 /** 728 * dce_v6_0_latency_watermark - get the latency watermark 729 * 730 * @wm: watermark calculation data 731 * 732 * Calculate the latency watermark (CIK). 733 * Used for display watermark bandwidth calculations 734 * Returns the latency watermark in ns 735 */ 736 static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm) 737 { 738 /* First calculate the latency in ns */ 739 u32 mc_latency = 2000; /* 2000 ns. */ 740 u32 available_bandwidth = dce_v6_0_available_bandwidth(wm); 741 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 742 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 743 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 744 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 745 (wm->num_heads * cursor_line_pair_return_time); 746 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 747 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 748 u32 tmp, dmif_size = 12288; 749 fixed20_12 a, b, c; 750 751 if (wm->num_heads == 0) 752 return 0; 753 754 a.full = dfixed_const(2); 755 b.full = dfixed_const(1); 756 if ((wm->vsc.full > a.full) || 757 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 758 (wm->vtaps >= 5) || 759 ((wm->vsc.full >= a.full) && wm->interlaced)) 760 max_src_lines_per_dst_line = 4; 761 else 762 max_src_lines_per_dst_line = 2; 763 764 a.full = dfixed_const(available_bandwidth); 765 b.full = dfixed_const(wm->num_heads); 766 a.full = dfixed_div(a, b); 767 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); 768 tmp = min(dfixed_trunc(a), tmp); 769 770 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); 771 772 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 773 b.full = dfixed_const(1000); 774 c.full = dfixed_const(lb_fill_bw); 775 b.full = dfixed_div(c, b); 776 a.full = dfixed_div(a, b); 777 line_fill_time = dfixed_trunc(a); 778 779 if (line_fill_time < wm->active_time) 780 return latency; 781 else 782 return latency + (line_fill_time - wm->active_time); 783 784 } 785 786 /** 787 * dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display - check 788 * average and available dram bandwidth 789 * 790 * @wm: watermark calculation data 791 * 792 * Check if the display average bandwidth fits in the display 793 * dram bandwidth (CIK). 794 * Used for display watermark bandwidth calculations 795 * Returns true if the display fits, false if not. 796 */ 797 static bool dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm) 798 { 799 if (dce_v6_0_average_bandwidth(wm) <= 800 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 801 return true; 802 else 803 return false; 804 } 805 806 /** 807 * dce_v6_0_average_bandwidth_vs_available_bandwidth - check 808 * average and available bandwidth 809 * 810 * @wm: watermark calculation data 811 * 812 * Check if the display average bandwidth fits in the display 813 * available bandwidth (CIK). 814 * Used for display watermark bandwidth calculations 815 * Returns true if the display fits, false if not. 816 */ 817 static bool dce_v6_0_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm) 818 { 819 if (dce_v6_0_average_bandwidth(wm) <= 820 (dce_v6_0_available_bandwidth(wm) / wm->num_heads)) 821 return true; 822 else 823 return false; 824 } 825 826 /** 827 * dce_v6_0_check_latency_hiding - check latency hiding 828 * 829 * @wm: watermark calculation data 830 * 831 * Check latency hiding (CIK). 832 * Used for display watermark bandwidth calculations 833 * Returns true if the display fits, false if not. 834 */ 835 static bool dce_v6_0_check_latency_hiding(struct dce6_wm_params *wm) 836 { 837 u32 lb_partitions = wm->lb_size / wm->src_width; 838 u32 line_time = wm->active_time + wm->blank_time; 839 u32 latency_tolerant_lines; 840 u32 latency_hiding; 841 fixed20_12 a; 842 843 a.full = dfixed_const(1); 844 if (wm->vsc.full > a.full) 845 latency_tolerant_lines = 1; 846 else { 847 if (lb_partitions <= (wm->vtaps + 1)) 848 latency_tolerant_lines = 1; 849 else 850 latency_tolerant_lines = 2; 851 } 852 853 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 854 855 if (dce_v6_0_latency_watermark(wm) <= latency_hiding) 856 return true; 857 else 858 return false; 859 } 860 861 /** 862 * dce_v6_0_program_watermarks - program display watermarks 863 * 864 * @adev: amdgpu_device pointer 865 * @amdgpu_crtc: the selected display controller 866 * @lb_size: line buffer size 867 * @num_heads: number of display controllers in use 868 * 869 * Calculate and program the display watermarks for the 870 * selected display controller (CIK). 871 */ 872 static void dce_v6_0_program_watermarks(struct amdgpu_device *adev, 873 struct amdgpu_crtc *amdgpu_crtc, 874 u32 lb_size, u32 num_heads) 875 { 876 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 877 struct dce6_wm_params wm_low, wm_high; 878 u32 dram_channels; 879 u32 active_time; 880 u32 line_time = 0; 881 u32 latency_watermark_a = 0, latency_watermark_b = 0; 882 u32 priority_a_mark = 0, priority_b_mark = 0; 883 u32 priority_a_cnt = PRIORITY_OFF; 884 u32 priority_b_cnt = PRIORITY_OFF; 885 u32 tmp, arb_control3, lb_vblank_lead_lines = 0; 886 fixed20_12 a, b, c; 887 888 if (amdgpu_crtc->base.enabled && num_heads && mode) { 889 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, 890 (u32)mode->clock); 891 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, 892 (u32)mode->clock); 893 line_time = min_t(u32, line_time, 65535); 894 priority_a_cnt = 0; 895 priority_b_cnt = 0; 896 897 dram_channels = si_get_number_of_dram_channels(adev); 898 899 /* watermark for high clocks */ 900 if (adev->pm.dpm_enabled) { 901 wm_high.yclk = 902 amdgpu_dpm_get_mclk(adev, false) * 10; 903 wm_high.sclk = 904 amdgpu_dpm_get_sclk(adev, false) * 10; 905 } else { 906 wm_high.yclk = adev->pm.current_mclk * 10; 907 wm_high.sclk = adev->pm.current_sclk * 10; 908 } 909 910 wm_high.disp_clk = mode->clock; 911 wm_high.src_width = mode->crtc_hdisplay; 912 wm_high.active_time = active_time; 913 wm_high.blank_time = line_time - wm_high.active_time; 914 wm_high.interlaced = false; 915 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 916 wm_high.interlaced = true; 917 wm_high.vsc = amdgpu_crtc->vsc; 918 wm_high.vtaps = 1; 919 if (amdgpu_crtc->rmx_type != RMX_OFF) 920 wm_high.vtaps = 2; 921 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 922 wm_high.lb_size = lb_size; 923 wm_high.dram_channels = dram_channels; 924 wm_high.num_heads = num_heads; 925 926 /* watermark for low clocks */ 927 if (adev->pm.dpm_enabled) { 928 wm_low.yclk = 929 amdgpu_dpm_get_mclk(adev, true) * 10; 930 wm_low.sclk = 931 amdgpu_dpm_get_sclk(adev, true) * 10; 932 } else { 933 wm_low.yclk = adev->pm.current_mclk * 10; 934 wm_low.sclk = adev->pm.current_sclk * 10; 935 } 936 937 wm_low.disp_clk = mode->clock; 938 wm_low.src_width = mode->crtc_hdisplay; 939 wm_low.active_time = active_time; 940 wm_low.blank_time = line_time - wm_low.active_time; 941 wm_low.interlaced = false; 942 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 943 wm_low.interlaced = true; 944 wm_low.vsc = amdgpu_crtc->vsc; 945 wm_low.vtaps = 1; 946 if (amdgpu_crtc->rmx_type != RMX_OFF) 947 wm_low.vtaps = 2; 948 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 949 wm_low.lb_size = lb_size; 950 wm_low.dram_channels = dram_channels; 951 wm_low.num_heads = num_heads; 952 953 /* set for high clocks */ 954 latency_watermark_a = min_t(u32, dce_v6_0_latency_watermark(&wm_high), 65535); 955 /* set for low clocks */ 956 latency_watermark_b = min_t(u32, dce_v6_0_latency_watermark(&wm_low), 65535); 957 958 /* possibly force display priority to high */ 959 /* should really do this at mode validation time... */ 960 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 961 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 962 !dce_v6_0_check_latency_hiding(&wm_high) || 963 (adev->mode_info.disp_priority == 2)) { 964 DRM_DEBUG_KMS("force priority to high\n"); 965 priority_a_cnt |= PRIORITY_ALWAYS_ON; 966 priority_b_cnt |= PRIORITY_ALWAYS_ON; 967 } 968 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 969 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 970 !dce_v6_0_check_latency_hiding(&wm_low) || 971 (adev->mode_info.disp_priority == 2)) { 972 DRM_DEBUG_KMS("force priority to high\n"); 973 priority_a_cnt |= PRIORITY_ALWAYS_ON; 974 priority_b_cnt |= PRIORITY_ALWAYS_ON; 975 } 976 977 a.full = dfixed_const(1000); 978 b.full = dfixed_const(mode->clock); 979 b.full = dfixed_div(b, a); 980 c.full = dfixed_const(latency_watermark_a); 981 c.full = dfixed_mul(c, b); 982 c.full = dfixed_mul(c, amdgpu_crtc->hsc); 983 c.full = dfixed_div(c, a); 984 a.full = dfixed_const(16); 985 c.full = dfixed_div(c, a); 986 priority_a_mark = dfixed_trunc(c); 987 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK; 988 989 a.full = dfixed_const(1000); 990 b.full = dfixed_const(mode->clock); 991 b.full = dfixed_div(b, a); 992 c.full = dfixed_const(latency_watermark_b); 993 c.full = dfixed_mul(c, b); 994 c.full = dfixed_mul(c, amdgpu_crtc->hsc); 995 c.full = dfixed_div(c, a); 996 a.full = dfixed_const(16); 997 c.full = dfixed_div(c, a); 998 priority_b_mark = dfixed_trunc(c); 999 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; 1000 1001 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1002 } 1003 1004 /* select wm A */ 1005 arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); 1006 tmp = arb_control3; 1007 tmp &= ~LATENCY_WATERMARK_MASK(3); 1008 tmp |= LATENCY_WATERMARK_MASK(1); 1009 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); 1010 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 1011 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 1012 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 1013 /* select wm B */ 1014 tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); 1015 tmp &= ~LATENCY_WATERMARK_MASK(3); 1016 tmp |= LATENCY_WATERMARK_MASK(2); 1017 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); 1018 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 1019 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 1020 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 1021 /* restore original selection */ 1022 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3); 1023 1024 /* write the priority marks */ 1025 WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt); 1026 WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt); 1027 1028 /* save values for DPM */ 1029 amdgpu_crtc->line_time = line_time; 1030 amdgpu_crtc->wm_high = latency_watermark_a; 1031 1032 /* Save number of lines the linebuffer leads before the scanout */ 1033 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1034 } 1035 1036 /* watermark setup */ 1037 /** 1038 * dce_v6_0_line_buffer_adjust - Set up the line buffer 1039 * 1040 * @adev: amdgpu_device pointer 1041 * @amdgpu_crtc: the selected display controller 1042 * @mode: the current display mode on the selected display 1043 * controller 1044 * 1045 * Setup up the line buffer allocation for 1046 * the selected display controller (CIK). 1047 * Returns the line buffer size in pixels. 1048 */ 1049 static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev, 1050 struct amdgpu_crtc *amdgpu_crtc, 1051 struct drm_display_mode *mode, 1052 struct drm_display_mode *other_mode) 1053 { 1054 u32 tmp, buffer_alloc, i; 1055 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; 1056 /* 1057 * Line Buffer Setup 1058 * There are 3 line buffers, each one shared by 2 display controllers. 1059 * mmDC_LB_MEMORY_SPLIT controls how that line buffer is shared between 1060 * the display controllers. The paritioning is done via one of four 1061 * preset allocations specified in bits 21:20: 1062 * 0 - half lb 1063 * 2 - whole lb, other crtc must be disabled 1064 */ 1065 /* this can get tricky if we have two large displays on a paired group 1066 * of crtcs. Ideally for multiple large displays we'd assign them to 1067 * non-linked crtcs for maximum line buffer allocation. 1068 */ 1069 if (amdgpu_crtc->base.enabled && mode) { 1070 if (other_mode) { 1071 tmp = 0; /* 1/2 */ 1072 buffer_alloc = 1; 1073 } else { 1074 tmp = 2; /* whole */ 1075 buffer_alloc = 2; 1076 } 1077 } else { 1078 tmp = 0; 1079 buffer_alloc = 0; 1080 } 1081 1082 WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset, 1083 DC_LB_MEMORY_CONFIG(tmp)); 1084 1085 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, 1086 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT)); 1087 for (i = 0; i < adev->usec_timeout; i++) { 1088 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & 1089 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK) 1090 break; 1091 udelay(1); 1092 } 1093 1094 if (amdgpu_crtc->base.enabled && mode) { 1095 switch (tmp) { 1096 case 0: 1097 default: 1098 return 4096 * 2; 1099 case 2: 1100 return 8192 * 2; 1101 } 1102 } 1103 1104 /* controller not enabled, so no lb used */ 1105 return 0; 1106 } 1107 1108 1109 /** 1110 * dce_v6_0_bandwidth_update - program display watermarks 1111 * 1112 * @adev: amdgpu_device pointer 1113 * 1114 * Calculate and program the display watermarks and line 1115 * buffer allocation (CIK). 1116 */ 1117 static void dce_v6_0_bandwidth_update(struct amdgpu_device *adev) 1118 { 1119 struct drm_display_mode *mode0 = NULL; 1120 struct drm_display_mode *mode1 = NULL; 1121 u32 num_heads = 0, lb_size; 1122 int i; 1123 1124 if (!adev->mode_info.mode_config_initialized) 1125 return; 1126 1127 amdgpu_display_update_priority(adev); 1128 1129 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1130 if (adev->mode_info.crtcs[i]->base.enabled) 1131 num_heads++; 1132 } 1133 for (i = 0; i < adev->mode_info.num_crtc; i += 2) { 1134 mode0 = &adev->mode_info.crtcs[i]->base.mode; 1135 mode1 = &adev->mode_info.crtcs[i+1]->base.mode; 1136 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1); 1137 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads); 1138 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0); 1139 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads); 1140 } 1141 } 1142 1143 static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device *adev) 1144 { 1145 int i; 1146 u32 tmp; 1147 1148 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1149 tmp = RREG32_AUDIO_ENDPT(adev->mode_info.audio.pin[i].offset, 1150 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1151 if (REG_GET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT, 1152 PORT_CONNECTIVITY)) 1153 adev->mode_info.audio.pin[i].connected = false; 1154 else 1155 adev->mode_info.audio.pin[i].connected = true; 1156 } 1157 1158 } 1159 1160 static struct amdgpu_audio_pin *dce_v6_0_audio_get_pin(struct amdgpu_device *adev) 1161 { 1162 int i; 1163 1164 dce_v6_0_audio_get_connected_pins(adev); 1165 1166 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1167 if (adev->mode_info.audio.pin[i].connected) 1168 return &adev->mode_info.audio.pin[i]; 1169 } 1170 DRM_ERROR("No connected audio pins found!\n"); 1171 return NULL; 1172 } 1173 1174 static void dce_v6_0_audio_select_pin(struct drm_encoder *encoder) 1175 { 1176 struct amdgpu_device *adev = drm_to_adev(encoder->dev); 1177 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1178 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1179 1180 if (!dig || !dig->afmt || !dig->afmt->pin) 1181 return; 1182 1183 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, 1184 REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, 1185 dig->afmt->pin->id)); 1186 } 1187 1188 static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder, 1189 struct drm_display_mode *mode) 1190 { 1191 struct drm_device *dev = encoder->dev; 1192 struct amdgpu_device *adev = drm_to_adev(dev); 1193 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1194 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1195 struct drm_connector *connector; 1196 struct drm_connector_list_iter iter; 1197 struct amdgpu_connector *amdgpu_connector = NULL; 1198 int interlace = 0; 1199 u32 tmp; 1200 1201 drm_connector_list_iter_begin(dev, &iter); 1202 drm_for_each_connector_iter(connector, &iter) { 1203 if (connector->encoder == encoder) { 1204 amdgpu_connector = to_amdgpu_connector(connector); 1205 break; 1206 } 1207 } 1208 drm_connector_list_iter_end(&iter); 1209 1210 if (!amdgpu_connector) { 1211 DRM_ERROR("Couldn't find encoder's connector\n"); 1212 return; 1213 } 1214 1215 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1216 interlace = 1; 1217 1218 if (connector->latency_present[interlace]) { 1219 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1220 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1221 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1222 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1223 } else { 1224 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1225 VIDEO_LIPSYNC, 0); 1226 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1227 AUDIO_LIPSYNC, 0); 1228 } 1229 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1230 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1231 } 1232 1233 static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1234 { 1235 struct drm_device *dev = encoder->dev; 1236 struct amdgpu_device *adev = drm_to_adev(dev); 1237 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1238 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1239 struct drm_connector *connector; 1240 struct drm_connector_list_iter iter; 1241 struct amdgpu_connector *amdgpu_connector = NULL; 1242 u8 *sadb = NULL; 1243 int sad_count; 1244 u32 tmp; 1245 1246 drm_connector_list_iter_begin(dev, &iter); 1247 drm_for_each_connector_iter(connector, &iter) { 1248 if (connector->encoder == encoder) { 1249 amdgpu_connector = to_amdgpu_connector(connector); 1250 break; 1251 } 1252 } 1253 drm_connector_list_iter_end(&iter); 1254 1255 if (!amdgpu_connector) { 1256 DRM_ERROR("Couldn't find encoder's connector\n"); 1257 return; 1258 } 1259 1260 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb); 1261 if (sad_count < 0) { 1262 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1263 sad_count = 0; 1264 } 1265 1266 /* program the speaker allocation */ 1267 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1268 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1269 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1270 HDMI_CONNECTION, 0); 1271 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1272 DP_CONNECTION, 0); 1273 1274 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) 1275 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1276 DP_CONNECTION, 1); 1277 else 1278 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1279 HDMI_CONNECTION, 1); 1280 1281 if (sad_count) 1282 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1283 SPEAKER_ALLOCATION, sadb[0]); 1284 else 1285 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1286 SPEAKER_ALLOCATION, 5); /* stereo */ 1287 1288 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1289 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1290 1291 kfree(sadb); 1292 } 1293 1294 static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder) 1295 { 1296 struct drm_device *dev = encoder->dev; 1297 struct amdgpu_device *adev = drm_to_adev(dev); 1298 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1299 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1300 struct drm_connector *connector; 1301 struct drm_connector_list_iter iter; 1302 struct amdgpu_connector *amdgpu_connector = NULL; 1303 struct cea_sad *sads; 1304 int i, sad_count; 1305 1306 static const u16 eld_reg_to_type[][2] = { 1307 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1308 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1309 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1310 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1311 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1312 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1313 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1314 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1315 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1316 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1317 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1318 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1319 }; 1320 1321 drm_connector_list_iter_begin(dev, &iter); 1322 drm_for_each_connector_iter(connector, &iter) { 1323 if (connector->encoder == encoder) { 1324 amdgpu_connector = to_amdgpu_connector(connector); 1325 break; 1326 } 1327 } 1328 drm_connector_list_iter_end(&iter); 1329 1330 if (!amdgpu_connector) { 1331 DRM_ERROR("Couldn't find encoder's connector\n"); 1332 return; 1333 } 1334 1335 sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads); 1336 if (sad_count < 0) 1337 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1338 if (sad_count <= 0) 1339 return; 1340 1341 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1342 u32 tmp = 0; 1343 u8 stereo_freqs = 0; 1344 int max_channels = -1; 1345 int j; 1346 1347 for (j = 0; j < sad_count; j++) { 1348 struct cea_sad *sad = &sads[j]; 1349 1350 if (sad->format == eld_reg_to_type[i][1]) { 1351 if (sad->channels > max_channels) { 1352 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1353 MAX_CHANNELS, sad->channels); 1354 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1355 DESCRIPTOR_BYTE_2, sad->byte2); 1356 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1357 SUPPORTED_FREQUENCIES, sad->freq); 1358 max_channels = sad->channels; 1359 } 1360 1361 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1362 stereo_freqs |= sad->freq; 1363 else 1364 break; 1365 } 1366 } 1367 1368 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1369 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); 1370 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); 1371 } 1372 1373 kfree(sads); 1374 1375 } 1376 1377 static void dce_v6_0_audio_enable(struct amdgpu_device *adev, 1378 struct amdgpu_audio_pin *pin, 1379 bool enable) 1380 { 1381 if (!pin) 1382 return; 1383 1384 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1385 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1386 } 1387 1388 static const u32 pin_offsets[7] = 1389 { 1390 (0x1780 - 0x1780), 1391 (0x1786 - 0x1780), 1392 (0x178c - 0x1780), 1393 (0x1792 - 0x1780), 1394 (0x1798 - 0x1780), 1395 (0x179d - 0x1780), 1396 (0x17a4 - 0x1780), 1397 }; 1398 1399 static int dce_v6_0_audio_init(struct amdgpu_device *adev) 1400 { 1401 int i; 1402 1403 if (!amdgpu_audio) 1404 return 0; 1405 1406 adev->mode_info.audio.enabled = true; 1407 1408 switch (adev->asic_type) { 1409 case CHIP_TAHITI: 1410 case CHIP_PITCAIRN: 1411 case CHIP_VERDE: 1412 default: 1413 adev->mode_info.audio.num_pins = 6; 1414 break; 1415 case CHIP_OLAND: 1416 adev->mode_info.audio.num_pins = 2; 1417 break; 1418 } 1419 1420 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1421 adev->mode_info.audio.pin[i].channels = -1; 1422 adev->mode_info.audio.pin[i].rate = -1; 1423 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1424 adev->mode_info.audio.pin[i].status_bits = 0; 1425 adev->mode_info.audio.pin[i].category_code = 0; 1426 adev->mode_info.audio.pin[i].connected = false; 1427 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1428 adev->mode_info.audio.pin[i].id = i; 1429 /* disable audio. it will be set up later */ 1430 /* XXX remove once we switch to ip funcs */ 1431 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1432 } 1433 1434 return 0; 1435 } 1436 1437 static void dce_v6_0_audio_fini(struct amdgpu_device *adev) 1438 { 1439 int i; 1440 1441 if (!amdgpu_audio) 1442 return; 1443 1444 if (!adev->mode_info.audio.enabled) 1445 return; 1446 1447 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1448 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1449 1450 adev->mode_info.audio.enabled = false; 1451 } 1452 1453 static void dce_v6_0_audio_set_vbi_packet(struct drm_encoder *encoder) 1454 { 1455 struct drm_device *dev = encoder->dev; 1456 struct amdgpu_device *adev = drm_to_adev(dev); 1457 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1458 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1459 u32 tmp; 1460 1461 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1462 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1463 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); 1464 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); 1465 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1466 } 1467 1468 static void dce_v6_0_audio_set_acr(struct drm_encoder *encoder, 1469 uint32_t clock, int bpc) 1470 { 1471 struct drm_device *dev = encoder->dev; 1472 struct amdgpu_device *adev = drm_to_adev(dev); 1473 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1474 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1475 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1476 u32 tmp; 1477 1478 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1479 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1480 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1481 bpc > 8 ? 0 : 1); 1482 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1483 1484 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1485 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1486 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1487 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1488 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1489 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1490 1491 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1492 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1493 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1494 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1495 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1496 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1497 1498 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1499 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1500 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1501 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1502 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1503 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1504 } 1505 1506 static void dce_v6_0_audio_set_avi_infoframe(struct drm_encoder *encoder, 1507 struct drm_display_mode *mode) 1508 { 1509 struct drm_device *dev = encoder->dev; 1510 struct amdgpu_device *adev = drm_to_adev(dev); 1511 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1512 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1513 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1514 struct hdmi_avi_infoframe frame; 1515 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1516 uint8_t *payload = buffer + 3; 1517 uint8_t *header = buffer; 1518 ssize_t err; 1519 u32 tmp; 1520 1521 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); 1522 if (err < 0) { 1523 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1524 return; 1525 } 1526 1527 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1528 if (err < 0) { 1529 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1530 return; 1531 } 1532 1533 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1534 payload[0x0] | (payload[0x1] << 8) | (payload[0x2] << 16) | (payload[0x3] << 24)); 1535 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1536 payload[0x4] | (payload[0x5] << 8) | (payload[0x6] << 16) | (payload[0x7] << 24)); 1537 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1538 payload[0x8] | (payload[0x9] << 8) | (payload[0xA] << 16) | (payload[0xB] << 24)); 1539 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1540 payload[0xC] | (payload[0xD] << 8) | (header[1] << 24)); 1541 1542 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1543 /* anything other than 0 */ 1544 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, 1545 HDMI_AUDIO_INFO_LINE, 2); 1546 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1547 } 1548 1549 static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1550 { 1551 struct drm_device *dev = encoder->dev; 1552 struct amdgpu_device *adev = drm_to_adev(dev); 1553 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1554 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 1555 u32 tmp; 1556 1557 /* 1558 * Two dtos: generally use dto0 for hdmi, dto1 for dp. 1559 * Express [24MHz / target pixel clock] as an exact rational 1560 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1561 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1562 */ 1563 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1564 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, 1565 DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id); 1566 if (em == ATOM_ENCODER_MODE_HDMI) { 1567 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, 1568 DCCG_AUDIO_DTO_SEL, 0); 1569 } else if (ENCODER_MODE_IS_DP(em)) { 1570 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, 1571 DCCG_AUDIO_DTO_SEL, 1); 1572 } 1573 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1574 if (em == ATOM_ENCODER_MODE_HDMI) { 1575 WREG32(mmDCCG_AUDIO_DTO0_PHASE, 24000); 1576 WREG32(mmDCCG_AUDIO_DTO0_MODULE, clock); 1577 } else if (ENCODER_MODE_IS_DP(em)) { 1578 WREG32(mmDCCG_AUDIO_DTO1_PHASE, 24000); 1579 WREG32(mmDCCG_AUDIO_DTO1_MODULE, clock); 1580 } 1581 } 1582 1583 static void dce_v6_0_audio_set_packet(struct drm_encoder *encoder) 1584 { 1585 struct drm_device *dev = encoder->dev; 1586 struct amdgpu_device *adev = drm_to_adev(dev); 1587 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1588 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1589 u32 tmp; 1590 1591 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1592 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1593 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1594 1595 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1596 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1597 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1598 1599 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1600 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1601 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1602 1603 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1604 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1605 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1606 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1607 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1608 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1609 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1610 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1611 1612 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset); 1613 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, 0xff); 1614 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, tmp); 1615 1616 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1617 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1618 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1619 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1620 1621 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1622 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_RESET_FIFO_WHEN_AUDIO_DIS, 1); 1623 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1624 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1625 } 1626 1627 static void dce_v6_0_audio_set_mute(struct drm_encoder *encoder, bool mute) 1628 { 1629 struct drm_device *dev = encoder->dev; 1630 struct amdgpu_device *adev = drm_to_adev(dev); 1631 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1632 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1633 u32 tmp; 1634 1635 tmp = RREG32(mmHDMI_GC + dig->afmt->offset); 1636 tmp = REG_SET_FIELD(tmp, HDMI_GC, HDMI_GC_AVMUTE, mute ? 1 : 0); 1637 WREG32(mmHDMI_GC + dig->afmt->offset, tmp); 1638 } 1639 1640 static void dce_v6_0_audio_hdmi_enable(struct drm_encoder *encoder, bool enable) 1641 { 1642 struct drm_device *dev = encoder->dev; 1643 struct amdgpu_device *adev = drm_to_adev(dev); 1644 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1645 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1646 u32 tmp; 1647 1648 if (enable) { 1649 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1650 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1651 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1652 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1653 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1654 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1655 1656 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1657 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1658 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1659 1660 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1661 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1662 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1663 } else { 1664 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1665 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 0); 1666 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 0); 1667 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 0); 1668 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 0); 1669 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1670 1671 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1672 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 0); 1673 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1674 } 1675 } 1676 1677 static void dce_v6_0_audio_dp_enable(struct drm_encoder *encoder, bool enable) 1678 { 1679 struct drm_device *dev = encoder->dev; 1680 struct amdgpu_device *adev = drm_to_adev(dev); 1681 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1682 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1683 u32 tmp; 1684 1685 if (enable) { 1686 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1687 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1688 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1689 1690 tmp = RREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset); 1691 tmp = REG_SET_FIELD(tmp, DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, 1); 1692 WREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset, tmp); 1693 1694 tmp = RREG32(mmDP_SEC_CNTL + dig->afmt->offset); 1695 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); 1696 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ATP_ENABLE, 1); 1697 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_AIP_ENABLE, 1); 1698 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1699 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, tmp); 1700 } else { 1701 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, 0); 1702 } 1703 } 1704 1705 static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder, 1706 struct drm_display_mode *mode) 1707 { 1708 struct drm_device *dev = encoder->dev; 1709 struct amdgpu_device *adev = drm_to_adev(dev); 1710 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1711 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1712 struct drm_connector *connector; 1713 struct drm_connector_list_iter iter; 1714 struct amdgpu_connector *amdgpu_connector = NULL; 1715 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 1716 int bpc = 8; 1717 1718 if (!dig || !dig->afmt) 1719 return; 1720 1721 drm_connector_list_iter_begin(dev, &iter); 1722 drm_for_each_connector_iter(connector, &iter) { 1723 if (connector->encoder == encoder) { 1724 amdgpu_connector = to_amdgpu_connector(connector); 1725 break; 1726 } 1727 } 1728 drm_connector_list_iter_end(&iter); 1729 1730 if (!amdgpu_connector) { 1731 DRM_ERROR("Couldn't find encoder's connector\n"); 1732 return; 1733 } 1734 1735 if (!dig->afmt->enabled) 1736 return; 1737 1738 dig->afmt->pin = dce_v6_0_audio_get_pin(adev); 1739 if (!dig->afmt->pin) 1740 return; 1741 1742 if (encoder->crtc) { 1743 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1744 bpc = amdgpu_crtc->bpc; 1745 } 1746 1747 /* disable audio before setting up hw */ 1748 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); 1749 1750 dce_v6_0_audio_set_mute(encoder, true); 1751 dce_v6_0_audio_write_speaker_allocation(encoder); 1752 dce_v6_0_audio_write_sad_regs(encoder); 1753 dce_v6_0_audio_write_latency_fields(encoder, mode); 1754 if (em == ATOM_ENCODER_MODE_HDMI) { 1755 dce_v6_0_audio_set_dto(encoder, mode->clock); 1756 dce_v6_0_audio_set_vbi_packet(encoder); 1757 dce_v6_0_audio_set_acr(encoder, mode->clock, bpc); 1758 } else if (ENCODER_MODE_IS_DP(em)) { 1759 dce_v6_0_audio_set_dto(encoder, adev->clock.default_dispclk * 10); 1760 } 1761 dce_v6_0_audio_set_packet(encoder); 1762 dce_v6_0_audio_select_pin(encoder); 1763 dce_v6_0_audio_set_avi_infoframe(encoder, mode); 1764 dce_v6_0_audio_set_mute(encoder, false); 1765 if (em == ATOM_ENCODER_MODE_HDMI) { 1766 dce_v6_0_audio_hdmi_enable(encoder, 1); 1767 } else if (ENCODER_MODE_IS_DP(em)) { 1768 dce_v6_0_audio_dp_enable(encoder, 1); 1769 } 1770 1771 /* enable audio after setting up hw */ 1772 dce_v6_0_audio_enable(adev, dig->afmt->pin, true); 1773 } 1774 1775 static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1776 { 1777 struct drm_device *dev = encoder->dev; 1778 struct amdgpu_device *adev = drm_to_adev(dev); 1779 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1780 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1781 1782 if (!dig || !dig->afmt) 1783 return; 1784 1785 /* Silent, r600_hdmi_enable will raise WARN for us */ 1786 if (enable && dig->afmt->enabled) 1787 return; 1788 1789 if (!enable && !dig->afmt->enabled) 1790 return; 1791 1792 if (!enable && dig->afmt->pin) { 1793 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); 1794 dig->afmt->pin = NULL; 1795 } 1796 1797 dig->afmt->enabled = enable; 1798 1799 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1800 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1801 } 1802 1803 static int dce_v6_0_afmt_init(struct amdgpu_device *adev) 1804 { 1805 int i, j; 1806 1807 for (i = 0; i < adev->mode_info.num_dig; i++) 1808 adev->mode_info.afmt[i] = NULL; 1809 1810 /* DCE6 has audio blocks tied to DIG encoders */ 1811 for (i = 0; i < adev->mode_info.num_dig; i++) { 1812 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1813 if (adev->mode_info.afmt[i]) { 1814 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1815 adev->mode_info.afmt[i]->id = i; 1816 } else { 1817 for (j = 0; j < i; j++) { 1818 kfree(adev->mode_info.afmt[j]); 1819 adev->mode_info.afmt[j] = NULL; 1820 } 1821 DRM_ERROR("Out of memory allocating afmt table\n"); 1822 return -ENOMEM; 1823 } 1824 } 1825 return 0; 1826 } 1827 1828 static void dce_v6_0_afmt_fini(struct amdgpu_device *adev) 1829 { 1830 int i; 1831 1832 for (i = 0; i < adev->mode_info.num_dig; i++) { 1833 kfree(adev->mode_info.afmt[i]); 1834 adev->mode_info.afmt[i] = NULL; 1835 } 1836 } 1837 1838 static const u32 vga_control_regs[6] = 1839 { 1840 mmD1VGA_CONTROL, 1841 mmD2VGA_CONTROL, 1842 mmD3VGA_CONTROL, 1843 mmD4VGA_CONTROL, 1844 mmD5VGA_CONTROL, 1845 mmD6VGA_CONTROL, 1846 }; 1847 1848 static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable) 1849 { 1850 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1851 struct drm_device *dev = crtc->dev; 1852 struct amdgpu_device *adev = drm_to_adev(dev); 1853 u32 vga_control; 1854 1855 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 1856 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0)); 1857 } 1858 1859 static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable) 1860 { 1861 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1862 struct drm_device *dev = crtc->dev; 1863 struct amdgpu_device *adev = drm_to_adev(dev); 1864 1865 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); 1866 } 1867 1868 static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, 1869 struct drm_framebuffer *fb, 1870 int x, int y, int atomic) 1871 { 1872 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1873 struct drm_device *dev = crtc->dev; 1874 struct amdgpu_device *adev = drm_to_adev(dev); 1875 struct drm_framebuffer *target_fb; 1876 struct drm_gem_object *obj; 1877 struct amdgpu_bo *abo; 1878 uint64_t fb_location, tiling_flags; 1879 uint32_t fb_format, fb_pitch_pixels, pipe_config; 1880 u32 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_NONE); 1881 u32 viewport_w, viewport_h; 1882 int r; 1883 bool bypass_lut = false; 1884 1885 /* no fb bound */ 1886 if (!atomic && !crtc->primary->fb) { 1887 DRM_DEBUG_KMS("No FB bound\n"); 1888 return 0; 1889 } 1890 1891 if (atomic) 1892 target_fb = fb; 1893 else 1894 target_fb = crtc->primary->fb; 1895 1896 /* If atomic, assume fb object is pinned & idle & fenced and 1897 * just update base pointers 1898 */ 1899 obj = target_fb->obj[0]; 1900 abo = gem_to_amdgpu_bo(obj); 1901 r = amdgpu_bo_reserve(abo, false); 1902 if (unlikely(r != 0)) 1903 return r; 1904 1905 if (!atomic) { 1906 abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 1907 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); 1908 if (unlikely(r != 0)) { 1909 amdgpu_bo_unreserve(abo); 1910 return -EINVAL; 1911 } 1912 } 1913 fb_location = amdgpu_bo_gpu_offset(abo); 1914 1915 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1916 amdgpu_bo_unreserve(abo); 1917 1918 switch (target_fb->format->format) { 1919 case DRM_FORMAT_C8: 1920 fb_format = (GRPH_DEPTH(GRPH_DEPTH_8BPP) | 1921 GRPH_FORMAT(GRPH_FORMAT_INDEXED)); 1922 break; 1923 case DRM_FORMAT_XRGB4444: 1924 case DRM_FORMAT_ARGB4444: 1925 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 1926 GRPH_FORMAT(GRPH_FORMAT_ARGB4444)); 1927 #ifdef __BIG_ENDIAN 1928 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 1929 #endif 1930 break; 1931 case DRM_FORMAT_XRGB1555: 1932 case DRM_FORMAT_ARGB1555: 1933 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 1934 GRPH_FORMAT(GRPH_FORMAT_ARGB1555)); 1935 #ifdef __BIG_ENDIAN 1936 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 1937 #endif 1938 break; 1939 case DRM_FORMAT_BGRX5551: 1940 case DRM_FORMAT_BGRA5551: 1941 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 1942 GRPH_FORMAT(GRPH_FORMAT_BGRA5551)); 1943 #ifdef __BIG_ENDIAN 1944 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 1945 #endif 1946 break; 1947 case DRM_FORMAT_RGB565: 1948 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 1949 GRPH_FORMAT(GRPH_FORMAT_ARGB565)); 1950 #ifdef __BIG_ENDIAN 1951 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 1952 #endif 1953 break; 1954 case DRM_FORMAT_XRGB8888: 1955 case DRM_FORMAT_ARGB8888: 1956 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 1957 GRPH_FORMAT(GRPH_FORMAT_ARGB8888)); 1958 #ifdef __BIG_ENDIAN 1959 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 1960 #endif 1961 break; 1962 case DRM_FORMAT_XRGB2101010: 1963 case DRM_FORMAT_ARGB2101010: 1964 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 1965 GRPH_FORMAT(GRPH_FORMAT_ARGB2101010)); 1966 #ifdef __BIG_ENDIAN 1967 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 1968 #endif 1969 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1970 bypass_lut = true; 1971 break; 1972 case DRM_FORMAT_BGRX1010102: 1973 case DRM_FORMAT_BGRA1010102: 1974 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 1975 GRPH_FORMAT(GRPH_FORMAT_BGRA1010102)); 1976 #ifdef __BIG_ENDIAN 1977 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 1978 #endif 1979 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1980 bypass_lut = true; 1981 break; 1982 case DRM_FORMAT_XBGR8888: 1983 case DRM_FORMAT_ABGR8888: 1984 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 1985 GRPH_FORMAT(GRPH_FORMAT_ARGB8888)); 1986 fb_swap = (GRPH_RED_CROSSBAR(GRPH_RED_SEL_B) | 1987 GRPH_BLUE_CROSSBAR(GRPH_BLUE_SEL_R)); 1988 #ifdef __BIG_ENDIAN 1989 fb_swap |= GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 1990 #endif 1991 break; 1992 default: 1993 DRM_ERROR("Unsupported screen format %p4cc\n", 1994 &target_fb->format->format); 1995 return -EINVAL; 1996 } 1997 1998 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 1999 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 2000 2001 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2002 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2003 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2004 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2005 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2006 2007 fb_format |= GRPH_NUM_BANKS(num_banks); 2008 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_2D_TILED_THIN1); 2009 fb_format |= GRPH_TILE_SPLIT(tile_split); 2010 fb_format |= GRPH_BANK_WIDTH(bankw); 2011 fb_format |= GRPH_BANK_HEIGHT(bankh); 2012 fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect); 2013 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 2014 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_1D_TILED_THIN1); 2015 } 2016 2017 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2018 fb_format |= GRPH_PIPE_CONFIG(pipe_config); 2019 2020 dce_v6_0_vga_enable(crtc, false); 2021 2022 /* Make sure surface address is updated at vertical blank rather than 2023 * horizontal blank 2024 */ 2025 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); 2026 2027 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2028 upper_32_bits(fb_location)); 2029 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2030 upper_32_bits(fb_location)); 2031 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2032 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2033 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2034 (u32) fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2035 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2036 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2037 2038 /* 2039 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2040 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2041 * retain the full precision throughout the pipeline. 2042 */ 2043 WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, 2044 (bypass_lut ? GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK : 0), 2045 ~GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK); 2046 2047 if (bypass_lut) 2048 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2049 2050 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2051 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2052 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2053 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2054 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2055 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2056 2057 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 2058 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2059 2060 dce_v6_0_grph_enable(crtc, true); 2061 2062 WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2063 target_fb->height); 2064 x &= ~3; 2065 y &= ~1; 2066 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2067 (x << 16) | y); 2068 viewport_w = crtc->mode.hdisplay; 2069 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2070 2071 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2072 (viewport_w << 16) | viewport_h); 2073 2074 /* set pageflip to happen anywhere in vblank interval */ 2075 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); 2076 2077 if (!atomic && fb && fb != crtc->primary->fb) { 2078 abo = gem_to_amdgpu_bo(fb->obj[0]); 2079 r = amdgpu_bo_reserve(abo, true); 2080 if (unlikely(r != 0)) 2081 return r; 2082 amdgpu_bo_unpin(abo); 2083 amdgpu_bo_unreserve(abo); 2084 } 2085 2086 /* Bytes per pixel may have changed */ 2087 dce_v6_0_bandwidth_update(adev); 2088 2089 return 0; 2090 2091 } 2092 2093 static void dce_v6_0_set_interleave(struct drm_crtc *crtc, 2094 struct drm_display_mode *mode) 2095 { 2096 struct drm_device *dev = crtc->dev; 2097 struct amdgpu_device *adev = drm_to_adev(dev); 2098 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2099 2100 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2101 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 2102 INTERLEAVE_EN); 2103 else 2104 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0); 2105 } 2106 2107 static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc) 2108 { 2109 2110 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2111 struct drm_device *dev = crtc->dev; 2112 struct amdgpu_device *adev = drm_to_adev(dev); 2113 u16 *r, *g, *b; 2114 int i; 2115 2116 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2117 2118 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 2119 ((0 << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) | 2120 (0 << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT))); 2121 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, 2122 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK); 2123 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, 2124 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK); 2125 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2126 ((0 << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) | 2127 (0 << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT))); 2128 2129 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2130 2131 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2132 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2133 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2134 2135 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2136 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2137 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2138 2139 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2140 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2141 2142 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2143 r = crtc->gamma_store; 2144 g = r + crtc->gamma_size; 2145 b = g + crtc->gamma_size; 2146 for (i = 0; i < 256; i++) { 2147 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2148 ((*r++ & 0xffc0) << 14) | 2149 ((*g++ & 0xffc0) << 4) | 2150 (*b++ >> 6)); 2151 } 2152 2153 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2154 ((0 << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) | 2155 (0 << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) | 2156 ICON_DEGAMMA_MODE(0) | 2157 (0 << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT))); 2158 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, 2159 ((0 << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) | 2160 (0 << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT))); 2161 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2162 ((0 << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) | 2163 (0 << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT))); 2164 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 2165 ((0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) | 2166 (0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT))); 2167 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2168 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); 2169 2170 2171 } 2172 2173 static int dce_v6_0_pick_dig_encoder(struct drm_encoder *encoder) 2174 { 2175 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2176 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2177 2178 switch (amdgpu_encoder->encoder_id) { 2179 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2180 return dig->linkb ? 1 : 0; 2181 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2182 return dig->linkb ? 3 : 2; 2183 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2184 return dig->linkb ? 5 : 4; 2185 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2186 return 6; 2187 default: 2188 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2189 return 0; 2190 } 2191 } 2192 2193 /** 2194 * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc. 2195 * 2196 * @crtc: drm crtc 2197 * 2198 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2199 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2200 * monitors a dedicated PPLL must be used. If a particular board has 2201 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2202 * as there is no need to program the PLL itself. If we are not able to 2203 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2204 * avoid messing up an existing monitor. 2205 * 2206 * 2207 */ 2208 static u32 dce_v6_0_pick_pll(struct drm_crtc *crtc) 2209 { 2210 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2211 struct drm_device *dev = crtc->dev; 2212 struct amdgpu_device *adev = drm_to_adev(dev); 2213 u32 pll_in_use; 2214 int pll; 2215 2216 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2217 if (adev->clock.dp_extclk) 2218 /* skip PPLL programming if using ext clock */ 2219 return ATOM_PPLL_INVALID; 2220 else 2221 return ATOM_PPLL0; 2222 } else { 2223 /* use the same PPLL for all monitors with the same clock */ 2224 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2225 if (pll != ATOM_PPLL_INVALID) 2226 return pll; 2227 } 2228 2229 /* PPLL1, and PPLL2 */ 2230 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2231 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2232 return ATOM_PPLL2; 2233 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2234 return ATOM_PPLL1; 2235 DRM_ERROR("unable to allocate a PPLL\n"); 2236 return ATOM_PPLL_INVALID; 2237 } 2238 2239 static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2240 { 2241 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2242 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2243 uint32_t cur_lock; 2244 2245 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2246 if (lock) 2247 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 2248 else 2249 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 2250 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2251 } 2252 2253 static void dce_v6_0_hide_cursor(struct drm_crtc *crtc) 2254 { 2255 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2256 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2257 2258 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 2259 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 2260 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 2261 2262 2263 } 2264 2265 static void dce_v6_0_show_cursor(struct drm_crtc *crtc) 2266 { 2267 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2268 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2269 2270 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2271 upper_32_bits(amdgpu_crtc->cursor_addr)); 2272 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2273 lower_32_bits(amdgpu_crtc->cursor_addr)); 2274 2275 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 2276 CUR_CONTROL__CURSOR_EN_MASK | 2277 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 2278 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 2279 2280 } 2281 2282 static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc, 2283 int x, int y) 2284 { 2285 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2286 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2287 int xorigin = 0, yorigin = 0; 2288 2289 int w = amdgpu_crtc->cursor_width; 2290 2291 amdgpu_crtc->cursor_x = x; 2292 amdgpu_crtc->cursor_y = y; 2293 2294 /* avivo cursor are offset into the total surface */ 2295 x += crtc->x; 2296 y += crtc->y; 2297 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2298 2299 if (x < 0) { 2300 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2301 x = 0; 2302 } 2303 if (y < 0) { 2304 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2305 y = 0; 2306 } 2307 2308 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2309 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2310 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2311 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2312 2313 return 0; 2314 } 2315 2316 static int dce_v6_0_crtc_cursor_move(struct drm_crtc *crtc, 2317 int x, int y) 2318 { 2319 int ret; 2320 2321 dce_v6_0_lock_cursor(crtc, true); 2322 ret = dce_v6_0_cursor_move_locked(crtc, x, y); 2323 dce_v6_0_lock_cursor(crtc, false); 2324 2325 return ret; 2326 } 2327 2328 static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, 2329 struct drm_file *file_priv, 2330 uint32_t handle, 2331 uint32_t width, 2332 uint32_t height, 2333 int32_t hot_x, 2334 int32_t hot_y) 2335 { 2336 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2337 struct drm_gem_object *obj; 2338 struct amdgpu_bo *aobj; 2339 int ret; 2340 2341 if (!handle) { 2342 /* turn off cursor */ 2343 dce_v6_0_hide_cursor(crtc); 2344 obj = NULL; 2345 goto unpin; 2346 } 2347 2348 if ((width > amdgpu_crtc->max_cursor_width) || 2349 (height > amdgpu_crtc->max_cursor_height)) { 2350 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2351 return -EINVAL; 2352 } 2353 2354 obj = drm_gem_object_lookup(file_priv, handle); 2355 if (!obj) { 2356 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2357 return -ENOENT; 2358 } 2359 2360 aobj = gem_to_amdgpu_bo(obj); 2361 ret = amdgpu_bo_reserve(aobj, false); 2362 if (ret != 0) { 2363 drm_gem_object_put(obj); 2364 return ret; 2365 } 2366 2367 aobj->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 2368 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); 2369 amdgpu_bo_unreserve(aobj); 2370 if (ret) { 2371 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2372 drm_gem_object_put(obj); 2373 return ret; 2374 } 2375 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); 2376 2377 dce_v6_0_lock_cursor(crtc, true); 2378 2379 if (width != amdgpu_crtc->cursor_width || 2380 height != amdgpu_crtc->cursor_height || 2381 hot_x != amdgpu_crtc->cursor_hot_x || 2382 hot_y != amdgpu_crtc->cursor_hot_y) { 2383 int x, y; 2384 2385 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2386 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2387 2388 dce_v6_0_cursor_move_locked(crtc, x, y); 2389 2390 amdgpu_crtc->cursor_width = width; 2391 amdgpu_crtc->cursor_height = height; 2392 amdgpu_crtc->cursor_hot_x = hot_x; 2393 amdgpu_crtc->cursor_hot_y = hot_y; 2394 } 2395 2396 dce_v6_0_show_cursor(crtc); 2397 dce_v6_0_lock_cursor(crtc, false); 2398 2399 unpin: 2400 if (amdgpu_crtc->cursor_bo) { 2401 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2402 ret = amdgpu_bo_reserve(aobj, true); 2403 if (likely(ret == 0)) { 2404 amdgpu_bo_unpin(aobj); 2405 amdgpu_bo_unreserve(aobj); 2406 } 2407 drm_gem_object_put(amdgpu_crtc->cursor_bo); 2408 } 2409 2410 amdgpu_crtc->cursor_bo = obj; 2411 return 0; 2412 } 2413 2414 static void dce_v6_0_cursor_reset(struct drm_crtc *crtc) 2415 { 2416 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2417 2418 if (amdgpu_crtc->cursor_bo) { 2419 dce_v6_0_lock_cursor(crtc, true); 2420 2421 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2422 amdgpu_crtc->cursor_y); 2423 2424 dce_v6_0_show_cursor(crtc); 2425 dce_v6_0_lock_cursor(crtc, false); 2426 } 2427 } 2428 2429 static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2430 u16 *blue, uint32_t size, 2431 struct drm_modeset_acquire_ctx *ctx) 2432 { 2433 dce_v6_0_crtc_load_lut(crtc); 2434 2435 return 0; 2436 } 2437 2438 static void dce_v6_0_crtc_destroy(struct drm_crtc *crtc) 2439 { 2440 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2441 2442 drm_crtc_cleanup(crtc); 2443 kfree(amdgpu_crtc); 2444 } 2445 2446 static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = { 2447 .cursor_set2 = dce_v6_0_crtc_cursor_set2, 2448 .cursor_move = dce_v6_0_crtc_cursor_move, 2449 .gamma_set = dce_v6_0_crtc_gamma_set, 2450 .set_config = amdgpu_display_crtc_set_config, 2451 .destroy = dce_v6_0_crtc_destroy, 2452 .page_flip_target = amdgpu_display_crtc_page_flip_target, 2453 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 2454 .enable_vblank = amdgpu_enable_vblank_kms, 2455 .disable_vblank = amdgpu_disable_vblank_kms, 2456 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 2457 }; 2458 2459 static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2460 { 2461 struct drm_device *dev = crtc->dev; 2462 struct amdgpu_device *adev = drm_to_adev(dev); 2463 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2464 unsigned type; 2465 2466 switch (mode) { 2467 case DRM_MODE_DPMS_ON: 2468 amdgpu_crtc->enabled = true; 2469 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2470 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2471 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2472 type = amdgpu_display_crtc_idx_to_irq_type(adev, 2473 amdgpu_crtc->crtc_id); 2474 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2475 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2476 drm_crtc_vblank_on(crtc); 2477 dce_v6_0_crtc_load_lut(crtc); 2478 break; 2479 case DRM_MODE_DPMS_STANDBY: 2480 case DRM_MODE_DPMS_SUSPEND: 2481 case DRM_MODE_DPMS_OFF: 2482 drm_crtc_vblank_off(crtc); 2483 if (amdgpu_crtc->enabled) 2484 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2485 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2486 amdgpu_crtc->enabled = false; 2487 break; 2488 } 2489 /* adjust pm to dpms */ 2490 amdgpu_dpm_compute_clocks(adev); 2491 } 2492 2493 static void dce_v6_0_crtc_prepare(struct drm_crtc *crtc) 2494 { 2495 /* disable crtc pair power gating before programming */ 2496 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2497 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2498 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2499 } 2500 2501 static void dce_v6_0_crtc_commit(struct drm_crtc *crtc) 2502 { 2503 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2504 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2505 } 2506 2507 static void dce_v6_0_crtc_disable(struct drm_crtc *crtc) 2508 { 2509 2510 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2511 struct drm_device *dev = crtc->dev; 2512 struct amdgpu_device *adev = drm_to_adev(dev); 2513 struct amdgpu_atom_ss ss; 2514 int i; 2515 2516 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2517 if (crtc->primary->fb) { 2518 int r; 2519 struct amdgpu_bo *abo; 2520 2521 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); 2522 r = amdgpu_bo_reserve(abo, true); 2523 if (unlikely(r)) 2524 DRM_ERROR("failed to reserve abo before unpin\n"); 2525 else { 2526 amdgpu_bo_unpin(abo); 2527 amdgpu_bo_unreserve(abo); 2528 } 2529 } 2530 /* disable the GRPH */ 2531 dce_v6_0_grph_enable(crtc, false); 2532 2533 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2534 2535 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2536 if (adev->mode_info.crtcs[i] && 2537 adev->mode_info.crtcs[i]->enabled && 2538 i != amdgpu_crtc->crtc_id && 2539 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2540 /* one other crtc is using this pll don't turn 2541 * off the pll 2542 */ 2543 goto done; 2544 } 2545 } 2546 2547 switch (amdgpu_crtc->pll_id) { 2548 case ATOM_PPLL1: 2549 case ATOM_PPLL2: 2550 /* disable the ppll */ 2551 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2552 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2553 break; 2554 default: 2555 break; 2556 } 2557 done: 2558 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2559 amdgpu_crtc->adjusted_clock = 0; 2560 amdgpu_crtc->encoder = NULL; 2561 amdgpu_crtc->connector = NULL; 2562 } 2563 2564 static int dce_v6_0_crtc_mode_set(struct drm_crtc *crtc, 2565 struct drm_display_mode *mode, 2566 struct drm_display_mode *adjusted_mode, 2567 int x, int y, struct drm_framebuffer *old_fb) 2568 { 2569 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2570 2571 if (!amdgpu_crtc->adjusted_clock) 2572 return -EINVAL; 2573 2574 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2575 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2576 dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2577 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2578 amdgpu_atombios_crtc_scaler_setup(crtc); 2579 dce_v6_0_cursor_reset(crtc); 2580 /* update the hw version fpr dpm */ 2581 amdgpu_crtc->hw_mode = *adjusted_mode; 2582 2583 return 0; 2584 } 2585 2586 static bool dce_v6_0_crtc_mode_fixup(struct drm_crtc *crtc, 2587 const struct drm_display_mode *mode, 2588 struct drm_display_mode *adjusted_mode) 2589 { 2590 2591 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2592 struct drm_device *dev = crtc->dev; 2593 struct drm_encoder *encoder; 2594 2595 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2596 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2597 if (encoder->crtc == crtc) { 2598 amdgpu_crtc->encoder = encoder; 2599 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2600 break; 2601 } 2602 } 2603 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2604 amdgpu_crtc->encoder = NULL; 2605 amdgpu_crtc->connector = NULL; 2606 return false; 2607 } 2608 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2609 return false; 2610 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2611 return false; 2612 /* pick pll */ 2613 amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc); 2614 /* if we can't get a PPLL for a non-DP encoder, fail */ 2615 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2616 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2617 return false; 2618 2619 return true; 2620 } 2621 2622 static int dce_v6_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2623 struct drm_framebuffer *old_fb) 2624 { 2625 return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2626 } 2627 2628 static int dce_v6_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2629 struct drm_framebuffer *fb, 2630 int x, int y, enum mode_set_atomic state) 2631 { 2632 return dce_v6_0_crtc_do_set_base(crtc, fb, x, y, 1); 2633 } 2634 2635 static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = { 2636 .dpms = dce_v6_0_crtc_dpms, 2637 .mode_fixup = dce_v6_0_crtc_mode_fixup, 2638 .mode_set = dce_v6_0_crtc_mode_set, 2639 .mode_set_base = dce_v6_0_crtc_set_base, 2640 .mode_set_base_atomic = dce_v6_0_crtc_set_base_atomic, 2641 .prepare = dce_v6_0_crtc_prepare, 2642 .commit = dce_v6_0_crtc_commit, 2643 .disable = dce_v6_0_crtc_disable, 2644 .get_scanout_position = amdgpu_crtc_get_scanout_position, 2645 }; 2646 2647 static void dce_v6_0_panic_flush(struct drm_plane *plane) 2648 { 2649 struct drm_framebuffer *fb; 2650 struct amdgpu_crtc *amdgpu_crtc; 2651 struct amdgpu_device *adev; 2652 uint32_t fb_format; 2653 2654 if (!plane->fb) 2655 return; 2656 2657 fb = plane->fb; 2658 amdgpu_crtc = to_amdgpu_crtc(plane->crtc); 2659 adev = drm_to_adev(fb->dev); 2660 2661 /* Disable DC tiling */ 2662 fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset); 2663 fb_format &= ~GRPH_ARRAY_MODE(0x7); 2664 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2665 2666 } 2667 2668 static const struct drm_plane_helper_funcs dce_v6_0_drm_primary_plane_helper_funcs = { 2669 .get_scanout_buffer = amdgpu_display_get_scanout_buffer, 2670 .panic_flush = dce_v6_0_panic_flush, 2671 }; 2672 2673 static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index) 2674 { 2675 struct amdgpu_crtc *amdgpu_crtc; 2676 2677 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2678 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2679 if (amdgpu_crtc == NULL) 2680 return -ENOMEM; 2681 2682 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v6_0_crtc_funcs); 2683 2684 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2685 amdgpu_crtc->crtc_id = index; 2686 adev->mode_info.crtcs[index] = amdgpu_crtc; 2687 2688 amdgpu_crtc->max_cursor_width = CURSOR_WIDTH; 2689 amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT; 2690 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2691 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2692 2693 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; 2694 2695 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2696 amdgpu_crtc->adjusted_clock = 0; 2697 amdgpu_crtc->encoder = NULL; 2698 amdgpu_crtc->connector = NULL; 2699 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs); 2700 drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v6_0_drm_primary_plane_helper_funcs); 2701 2702 return 0; 2703 } 2704 2705 static int dce_v6_0_early_init(struct amdgpu_ip_block *ip_block) 2706 { 2707 struct amdgpu_device *adev = ip_block->adev; 2708 2709 adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg; 2710 adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg; 2711 2712 dce_v6_0_set_display_funcs(adev); 2713 2714 adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev); 2715 2716 switch (adev->asic_type) { 2717 case CHIP_TAHITI: 2718 case CHIP_PITCAIRN: 2719 case CHIP_VERDE: 2720 adev->mode_info.num_hpd = 6; 2721 adev->mode_info.num_dig = 6; 2722 break; 2723 case CHIP_OLAND: 2724 adev->mode_info.num_hpd = 2; 2725 adev->mode_info.num_dig = 2; 2726 break; 2727 default: 2728 return -EINVAL; 2729 } 2730 2731 dce_v6_0_set_irq_funcs(adev); 2732 2733 return 0; 2734 } 2735 2736 static int dce_v6_0_sw_init(struct amdgpu_ip_block *ip_block) 2737 { 2738 int r, i; 2739 bool ret; 2740 struct amdgpu_device *adev = ip_block->adev; 2741 2742 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2743 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); 2744 if (r) 2745 return r; 2746 } 2747 2748 for (i = 8; i < 20; i += 2) { 2749 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq); 2750 if (r) 2751 return r; 2752 } 2753 2754 /* HPD hotplug */ 2755 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq); 2756 if (r) 2757 return r; 2758 2759 adev->mode_info.mode_config_initialized = true; 2760 2761 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs; 2762 adev_to_drm(adev)->mode_config.async_page_flip = true; 2763 adev_to_drm(adev)->mode_config.max_width = 16384; 2764 adev_to_drm(adev)->mode_config.max_height = 16384; 2765 adev_to_drm(adev)->mode_config.preferred_depth = 24; 2766 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 2767 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; 2768 2769 r = amdgpu_display_modeset_create_props(adev); 2770 if (r) 2771 return r; 2772 2773 adev_to_drm(adev)->mode_config.max_width = 16384; 2774 adev_to_drm(adev)->mode_config.max_height = 16384; 2775 2776 /* allocate crtcs */ 2777 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2778 r = dce_v6_0_crtc_init(adev, i); 2779 if (r) 2780 return r; 2781 } 2782 2783 ret = amdgpu_atombios_get_connector_info_from_object_table(adev); 2784 if (ret) 2785 amdgpu_display_print_display_setup(adev_to_drm(adev)); 2786 else 2787 return -EINVAL; 2788 2789 /* setup afmt */ 2790 r = dce_v6_0_afmt_init(adev); 2791 if (r) 2792 return r; 2793 2794 r = dce_v6_0_audio_init(adev); 2795 if (r) 2796 return r; 2797 2798 /* Disable vblank IRQs aggressively for power-saving */ 2799 /* XXX: can this be enabled for DC? */ 2800 adev_to_drm(adev)->vblank_disable_immediate = true; 2801 2802 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc); 2803 if (r) 2804 return r; 2805 2806 /* Pre-DCE11 */ 2807 INIT_DELAYED_WORK(&adev->hotplug_work, 2808 amdgpu_display_hotplug_work_func); 2809 2810 drm_kms_helper_poll_init(adev_to_drm(adev)); 2811 2812 return r; 2813 } 2814 2815 static int dce_v6_0_sw_fini(struct amdgpu_ip_block *ip_block) 2816 { 2817 struct amdgpu_device *adev = ip_block->adev; 2818 2819 drm_edid_free(adev->mode_info.bios_hardcoded_edid); 2820 2821 drm_kms_helper_poll_fini(adev_to_drm(adev)); 2822 2823 dce_v6_0_audio_fini(adev); 2824 dce_v6_0_afmt_fini(adev); 2825 2826 drm_mode_config_cleanup(adev_to_drm(adev)); 2827 adev->mode_info.mode_config_initialized = false; 2828 2829 return 0; 2830 } 2831 2832 static int dce_v6_0_hw_init(struct amdgpu_ip_block *ip_block) 2833 { 2834 int i; 2835 struct amdgpu_device *adev = ip_block->adev; 2836 2837 /* disable vga render */ 2838 dce_v6_0_set_vga_render_state(adev, false); 2839 /* init dig PHYs, disp eng pll */ 2840 amdgpu_atombios_encoder_init_dig(adev); 2841 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 2842 2843 /* initialize hpd */ 2844 dce_v6_0_hpd_init(adev); 2845 2846 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2847 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2848 } 2849 2850 dce_v6_0_pageflip_interrupt_init(adev); 2851 2852 return 0; 2853 } 2854 2855 static int dce_v6_0_hw_fini(struct amdgpu_ip_block *ip_block) 2856 { 2857 int i; 2858 struct amdgpu_device *adev = ip_block->adev; 2859 2860 dce_v6_0_hpd_fini(adev); 2861 2862 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2863 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2864 } 2865 2866 dce_v6_0_pageflip_interrupt_fini(adev); 2867 2868 flush_delayed_work(&adev->hotplug_work); 2869 2870 return 0; 2871 } 2872 2873 static int dce_v6_0_suspend(struct amdgpu_ip_block *ip_block) 2874 { 2875 struct amdgpu_device *adev = ip_block->adev; 2876 int r; 2877 2878 r = amdgpu_display_suspend_helper(adev); 2879 if (r) 2880 return r; 2881 adev->mode_info.bl_level = 2882 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); 2883 2884 return dce_v6_0_hw_fini(ip_block); 2885 } 2886 2887 static int dce_v6_0_resume(struct amdgpu_ip_block *ip_block) 2888 { 2889 struct amdgpu_device *adev = ip_block->adev; 2890 int ret; 2891 2892 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, 2893 adev->mode_info.bl_level); 2894 2895 ret = dce_v6_0_hw_init(ip_block); 2896 2897 /* turn on the BL */ 2898 if (adev->mode_info.bl_encoder) { 2899 u8 bl_level = amdgpu_display_backlight_get_level(adev, 2900 adev->mode_info.bl_encoder); 2901 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 2902 bl_level); 2903 } 2904 if (ret) 2905 return ret; 2906 2907 return amdgpu_display_resume_helper(adev); 2908 } 2909 2910 static bool dce_v6_0_is_idle(struct amdgpu_ip_block *ip_block) 2911 { 2912 return true; 2913 } 2914 2915 static int dce_v6_0_soft_reset(struct amdgpu_ip_block *ip_block) 2916 { 2917 u32 srbm_soft_reset = 0, tmp; 2918 struct amdgpu_device *adev = ip_block->adev; 2919 2920 if (dce_v6_0_is_display_hung(adev)) 2921 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 2922 2923 if (srbm_soft_reset) { 2924 tmp = RREG32(mmSRBM_SOFT_RESET); 2925 tmp |= srbm_soft_reset; 2926 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 2927 WREG32(mmSRBM_SOFT_RESET, tmp); 2928 tmp = RREG32(mmSRBM_SOFT_RESET); 2929 2930 udelay(50); 2931 2932 tmp &= ~srbm_soft_reset; 2933 WREG32(mmSRBM_SOFT_RESET, tmp); 2934 tmp = RREG32(mmSRBM_SOFT_RESET); 2935 2936 /* Wait a little for things to settle down */ 2937 udelay(50); 2938 } 2939 return 0; 2940 } 2941 2942 static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 2943 int crtc, 2944 enum amdgpu_interrupt_state state) 2945 { 2946 u32 reg_block, interrupt_mask; 2947 2948 if (crtc >= adev->mode_info.num_crtc) { 2949 DRM_DEBUG("invalid crtc %d\n", crtc); 2950 return; 2951 } 2952 2953 switch (crtc) { 2954 case 0: 2955 reg_block = SI_CRTC0_REGISTER_OFFSET; 2956 break; 2957 case 1: 2958 reg_block = SI_CRTC1_REGISTER_OFFSET; 2959 break; 2960 case 2: 2961 reg_block = SI_CRTC2_REGISTER_OFFSET; 2962 break; 2963 case 3: 2964 reg_block = SI_CRTC3_REGISTER_OFFSET; 2965 break; 2966 case 4: 2967 reg_block = SI_CRTC4_REGISTER_OFFSET; 2968 break; 2969 case 5: 2970 reg_block = SI_CRTC5_REGISTER_OFFSET; 2971 break; 2972 default: 2973 DRM_DEBUG("invalid crtc %d\n", crtc); 2974 return; 2975 } 2976 2977 switch (state) { 2978 case AMDGPU_IRQ_STATE_DISABLE: 2979 interrupt_mask = RREG32(mmINT_MASK + reg_block); 2980 interrupt_mask &= ~VBLANK_INT_MASK; 2981 WREG32(mmINT_MASK + reg_block, interrupt_mask); 2982 break; 2983 case AMDGPU_IRQ_STATE_ENABLE: 2984 interrupt_mask = RREG32(mmINT_MASK + reg_block); 2985 interrupt_mask |= VBLANK_INT_MASK; 2986 WREG32(mmINT_MASK + reg_block, interrupt_mask); 2987 break; 2988 default: 2989 break; 2990 } 2991 } 2992 2993 static void dce_v6_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 2994 int crtc, 2995 enum amdgpu_interrupt_state state) 2996 { 2997 2998 } 2999 3000 static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev, 3001 struct amdgpu_irq_src *src, 3002 unsigned type, 3003 enum amdgpu_interrupt_state state) 3004 { 3005 u32 dc_hpd_int_cntl; 3006 3007 if (type >= adev->mode_info.num_hpd) { 3008 DRM_DEBUG("invalid hdp %d\n", type); 3009 return 0; 3010 } 3011 3012 switch (state) { 3013 case AMDGPU_IRQ_STATE_DISABLE: 3014 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); 3015 dc_hpd_int_cntl &= ~DC_HPDx_INT_EN; 3016 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 3017 break; 3018 case AMDGPU_IRQ_STATE_ENABLE: 3019 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); 3020 dc_hpd_int_cntl |= DC_HPDx_INT_EN; 3021 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 3022 break; 3023 default: 3024 break; 3025 } 3026 3027 return 0; 3028 } 3029 3030 static int dce_v6_0_set_crtc_interrupt_state(struct amdgpu_device *adev, 3031 struct amdgpu_irq_src *src, 3032 unsigned type, 3033 enum amdgpu_interrupt_state state) 3034 { 3035 switch (type) { 3036 case AMDGPU_CRTC_IRQ_VBLANK1: 3037 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3038 break; 3039 case AMDGPU_CRTC_IRQ_VBLANK2: 3040 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3041 break; 3042 case AMDGPU_CRTC_IRQ_VBLANK3: 3043 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3044 break; 3045 case AMDGPU_CRTC_IRQ_VBLANK4: 3046 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3047 break; 3048 case AMDGPU_CRTC_IRQ_VBLANK5: 3049 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3050 break; 3051 case AMDGPU_CRTC_IRQ_VBLANK6: 3052 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3053 break; 3054 case AMDGPU_CRTC_IRQ_VLINE1: 3055 dce_v6_0_set_crtc_vline_interrupt_state(adev, 0, state); 3056 break; 3057 case AMDGPU_CRTC_IRQ_VLINE2: 3058 dce_v6_0_set_crtc_vline_interrupt_state(adev, 1, state); 3059 break; 3060 case AMDGPU_CRTC_IRQ_VLINE3: 3061 dce_v6_0_set_crtc_vline_interrupt_state(adev, 2, state); 3062 break; 3063 case AMDGPU_CRTC_IRQ_VLINE4: 3064 dce_v6_0_set_crtc_vline_interrupt_state(adev, 3, state); 3065 break; 3066 case AMDGPU_CRTC_IRQ_VLINE5: 3067 dce_v6_0_set_crtc_vline_interrupt_state(adev, 4, state); 3068 break; 3069 case AMDGPU_CRTC_IRQ_VLINE6: 3070 dce_v6_0_set_crtc_vline_interrupt_state(adev, 5, state); 3071 break; 3072 default: 3073 break; 3074 } 3075 return 0; 3076 } 3077 3078 static int dce_v6_0_crtc_irq(struct amdgpu_device *adev, 3079 struct amdgpu_irq_src *source, 3080 struct amdgpu_iv_entry *entry) 3081 { 3082 unsigned crtc = entry->src_id - 1; 3083 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3084 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, 3085 crtc); 3086 3087 switch (entry->src_data[0]) { 3088 case 0: /* vblank */ 3089 if (disp_int & interrupt_status_offsets[crtc].vblank) 3090 WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK); 3091 else 3092 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3093 3094 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3095 drm_handle_vblank(adev_to_drm(adev), crtc); 3096 } 3097 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3098 break; 3099 case 1: /* vline */ 3100 if (disp_int & interrupt_status_offsets[crtc].vline) 3101 WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK); 3102 else 3103 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3104 3105 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3106 break; 3107 default: 3108 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3109 break; 3110 } 3111 3112 return 0; 3113 } 3114 3115 static int dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device *adev, 3116 struct amdgpu_irq_src *src, 3117 unsigned type, 3118 enum amdgpu_interrupt_state state) 3119 { 3120 u32 reg; 3121 3122 if (type >= adev->mode_info.num_crtc) { 3123 DRM_ERROR("invalid pageflip crtc %d\n", type); 3124 return -EINVAL; 3125 } 3126 3127 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3128 if (state == AMDGPU_IRQ_STATE_DISABLE) 3129 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3130 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3131 else 3132 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3133 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3134 3135 return 0; 3136 } 3137 3138 static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev, 3139 struct amdgpu_irq_src *source, 3140 struct amdgpu_iv_entry *entry) 3141 { 3142 unsigned long flags; 3143 unsigned crtc_id; 3144 struct amdgpu_crtc *amdgpu_crtc; 3145 struct amdgpu_flip_work *works; 3146 3147 crtc_id = (entry->src_id - 8) >> 1; 3148 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3149 3150 if (crtc_id >= adev->mode_info.num_crtc) { 3151 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3152 return -EINVAL; 3153 } 3154 3155 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3156 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3157 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3158 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3159 3160 /* IRQ could occur when in initial stage */ 3161 if (amdgpu_crtc == NULL) 3162 return 0; 3163 3164 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 3165 works = amdgpu_crtc->pflip_works; 3166 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 3167 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3168 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3169 amdgpu_crtc->pflip_status, 3170 AMDGPU_FLIP_SUBMITTED); 3171 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3172 return 0; 3173 } 3174 3175 /* page flip completed. clean up */ 3176 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3177 amdgpu_crtc->pflip_works = NULL; 3178 3179 /* wakeup usersapce */ 3180 if (works->event) 3181 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); 3182 3183 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3184 3185 drm_crtc_vblank_put(&amdgpu_crtc->base); 3186 schedule_work(&works->unpin_work); 3187 3188 return 0; 3189 } 3190 3191 static int dce_v6_0_hpd_irq(struct amdgpu_device *adev, 3192 struct amdgpu_irq_src *source, 3193 struct amdgpu_iv_entry *entry) 3194 { 3195 uint32_t disp_int, mask; 3196 unsigned hpd; 3197 3198 if (entry->src_data[0] >= adev->mode_info.num_hpd) { 3199 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3200 return 0; 3201 } 3202 3203 hpd = entry->src_data[0]; 3204 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3205 mask = interrupt_status_offsets[hpd].hpd; 3206 3207 if (disp_int & mask) { 3208 dce_v6_0_hpd_int_ack(adev, hpd); 3209 schedule_delayed_work(&adev->hotplug_work, 0); 3210 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3211 } 3212 3213 return 0; 3214 } 3215 3216 static int dce_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 3217 enum amd_clockgating_state state) 3218 { 3219 return 0; 3220 } 3221 3222 static int dce_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 3223 enum amd_powergating_state state) 3224 { 3225 return 0; 3226 } 3227 3228 static const struct amd_ip_funcs dce_v6_0_ip_funcs = { 3229 .name = "dce_v6_0", 3230 .early_init = dce_v6_0_early_init, 3231 .sw_init = dce_v6_0_sw_init, 3232 .sw_fini = dce_v6_0_sw_fini, 3233 .hw_init = dce_v6_0_hw_init, 3234 .hw_fini = dce_v6_0_hw_fini, 3235 .suspend = dce_v6_0_suspend, 3236 .resume = dce_v6_0_resume, 3237 .is_idle = dce_v6_0_is_idle, 3238 .soft_reset = dce_v6_0_soft_reset, 3239 .set_clockgating_state = dce_v6_0_set_clockgating_state, 3240 .set_powergating_state = dce_v6_0_set_powergating_state, 3241 }; 3242 3243 static void 3244 dce_v6_0_encoder_mode_set(struct drm_encoder *encoder, 3245 struct drm_display_mode *mode, 3246 struct drm_display_mode *adjusted_mode) 3247 { 3248 3249 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3250 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 3251 3252 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3253 3254 /* need to call this here rather than in prepare() since we need some crtc info */ 3255 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3256 3257 /* set scaler clears this on some chips */ 3258 dce_v6_0_set_interleave(encoder->crtc, mode); 3259 3260 if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em)) { 3261 dce_v6_0_afmt_enable(encoder, true); 3262 dce_v6_0_afmt_setmode(encoder, adjusted_mode); 3263 } 3264 } 3265 3266 static void dce_v6_0_encoder_prepare(struct drm_encoder *encoder) 3267 { 3268 3269 struct amdgpu_device *adev = drm_to_adev(encoder->dev); 3270 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3271 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3272 3273 if ((amdgpu_encoder->active_device & 3274 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3275 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3276 ENCODER_OBJECT_ID_NONE)) { 3277 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3278 if (dig) { 3279 dig->dig_encoder = dce_v6_0_pick_dig_encoder(encoder); 3280 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3281 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3282 } 3283 } 3284 3285 amdgpu_atombios_scratch_regs_lock(adev, true); 3286 3287 if (connector) { 3288 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3289 3290 /* select the clock/data port if it uses a router */ 3291 if (amdgpu_connector->router.cd_valid) 3292 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3293 3294 /* turn eDP panel on for mode set */ 3295 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3296 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3297 ATOM_TRANSMITTER_ACTION_POWER_ON); 3298 } 3299 3300 /* this is needed for the pll/ss setup to work correctly in some cases */ 3301 amdgpu_atombios_encoder_set_crtc_source(encoder); 3302 /* set up the FMT blocks */ 3303 dce_v6_0_program_fmt(encoder); 3304 } 3305 3306 static void dce_v6_0_encoder_commit(struct drm_encoder *encoder) 3307 { 3308 3309 struct drm_device *dev = encoder->dev; 3310 struct amdgpu_device *adev = drm_to_adev(dev); 3311 3312 /* need to call this here as we need the crtc set up */ 3313 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3314 amdgpu_atombios_scratch_regs_lock(adev, false); 3315 } 3316 3317 static void dce_v6_0_encoder_disable(struct drm_encoder *encoder) 3318 { 3319 3320 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3321 struct amdgpu_encoder_atom_dig *dig; 3322 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 3323 3324 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3325 3326 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3327 if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em)) 3328 dce_v6_0_afmt_enable(encoder, false); 3329 dig = amdgpu_encoder->enc_priv; 3330 dig->dig_encoder = -1; 3331 } 3332 amdgpu_encoder->active_device = 0; 3333 } 3334 3335 /* these are handled by the primary encoders */ 3336 static void dce_v6_0_ext_prepare(struct drm_encoder *encoder) 3337 { 3338 3339 } 3340 3341 static void dce_v6_0_ext_commit(struct drm_encoder *encoder) 3342 { 3343 3344 } 3345 3346 static void dce_v6_0_ext_mode_set(struct drm_encoder *encoder, 3347 struct drm_display_mode *mode, 3348 struct drm_display_mode *adjusted_mode) 3349 { 3350 3351 } 3352 3353 static void dce_v6_0_ext_disable(struct drm_encoder *encoder) 3354 { 3355 3356 } 3357 3358 static void dce_v6_0_ext_dpms(struct drm_encoder *encoder, int mode) 3359 { 3360 3361 } 3362 3363 static bool dce_v6_0_ext_mode_fixup(struct drm_encoder *encoder, 3364 const struct drm_display_mode *mode, 3365 struct drm_display_mode *adjusted_mode) 3366 { 3367 return true; 3368 } 3369 3370 static const struct drm_encoder_helper_funcs dce_v6_0_ext_helper_funcs = { 3371 .dpms = dce_v6_0_ext_dpms, 3372 .mode_fixup = dce_v6_0_ext_mode_fixup, 3373 .prepare = dce_v6_0_ext_prepare, 3374 .mode_set = dce_v6_0_ext_mode_set, 3375 .commit = dce_v6_0_ext_commit, 3376 .disable = dce_v6_0_ext_disable, 3377 /* no detect for TMDS/LVDS yet */ 3378 }; 3379 3380 static const struct drm_encoder_helper_funcs dce_v6_0_dig_helper_funcs = { 3381 .dpms = amdgpu_atombios_encoder_dpms, 3382 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3383 .prepare = dce_v6_0_encoder_prepare, 3384 .mode_set = dce_v6_0_encoder_mode_set, 3385 .commit = dce_v6_0_encoder_commit, 3386 .disable = dce_v6_0_encoder_disable, 3387 .detect = amdgpu_atombios_encoder_dig_detect, 3388 }; 3389 3390 static const struct drm_encoder_helper_funcs dce_v6_0_dac_helper_funcs = { 3391 .dpms = amdgpu_atombios_encoder_dpms, 3392 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3393 .prepare = dce_v6_0_encoder_prepare, 3394 .mode_set = dce_v6_0_encoder_mode_set, 3395 .commit = dce_v6_0_encoder_commit, 3396 .detect = amdgpu_atombios_encoder_dac_detect, 3397 }; 3398 3399 static void dce_v6_0_encoder_destroy(struct drm_encoder *encoder) 3400 { 3401 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3402 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3403 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3404 kfree(amdgpu_encoder->enc_priv); 3405 drm_encoder_cleanup(encoder); 3406 kfree(amdgpu_encoder); 3407 } 3408 3409 static const struct drm_encoder_funcs dce_v6_0_encoder_funcs = { 3410 .destroy = dce_v6_0_encoder_destroy, 3411 }; 3412 3413 static void dce_v6_0_encoder_add(struct amdgpu_device *adev, 3414 uint32_t encoder_enum, 3415 uint32_t supported_device, 3416 u16 caps) 3417 { 3418 struct drm_device *dev = adev_to_drm(adev); 3419 struct drm_encoder *encoder; 3420 struct amdgpu_encoder *amdgpu_encoder; 3421 3422 /* see if we already added it */ 3423 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3424 amdgpu_encoder = to_amdgpu_encoder(encoder); 3425 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3426 amdgpu_encoder->devices |= supported_device; 3427 return; 3428 } 3429 } 3430 3431 /* add a new one */ 3432 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3433 if (!amdgpu_encoder) 3434 return; 3435 3436 encoder = &amdgpu_encoder->base; 3437 switch (adev->mode_info.num_crtc) { 3438 case 1: 3439 encoder->possible_crtcs = 0x1; 3440 break; 3441 case 2: 3442 default: 3443 encoder->possible_crtcs = 0x3; 3444 break; 3445 case 4: 3446 encoder->possible_crtcs = 0xf; 3447 break; 3448 case 6: 3449 encoder->possible_crtcs = 0x3f; 3450 break; 3451 } 3452 3453 amdgpu_encoder->enc_priv = NULL; 3454 amdgpu_encoder->encoder_enum = encoder_enum; 3455 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3456 amdgpu_encoder->devices = supported_device; 3457 amdgpu_encoder->rmx_type = RMX_OFF; 3458 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3459 amdgpu_encoder->is_ext_encoder = false; 3460 amdgpu_encoder->caps = caps; 3461 3462 switch (amdgpu_encoder->encoder_id) { 3463 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3464 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3465 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3466 DRM_MODE_ENCODER_DAC, NULL); 3467 drm_encoder_helper_add(encoder, &dce_v6_0_dac_helper_funcs); 3468 break; 3469 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3470 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3471 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3472 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3473 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3474 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3475 amdgpu_encoder->rmx_type = RMX_FULL; 3476 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3477 DRM_MODE_ENCODER_LVDS, NULL); 3478 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3479 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3480 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3481 DRM_MODE_ENCODER_DAC, NULL); 3482 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3483 } else { 3484 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3485 DRM_MODE_ENCODER_TMDS, NULL); 3486 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3487 } 3488 drm_encoder_helper_add(encoder, &dce_v6_0_dig_helper_funcs); 3489 break; 3490 case ENCODER_OBJECT_ID_SI170B: 3491 case ENCODER_OBJECT_ID_CH7303: 3492 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3493 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3494 case ENCODER_OBJECT_ID_TITFP513: 3495 case ENCODER_OBJECT_ID_VT1623: 3496 case ENCODER_OBJECT_ID_HDMI_SI1930: 3497 case ENCODER_OBJECT_ID_TRAVIS: 3498 case ENCODER_OBJECT_ID_NUTMEG: 3499 /* these are handled by the primary encoders */ 3500 amdgpu_encoder->is_ext_encoder = true; 3501 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3502 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3503 DRM_MODE_ENCODER_LVDS, NULL); 3504 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3505 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3506 DRM_MODE_ENCODER_DAC, NULL); 3507 else 3508 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3509 DRM_MODE_ENCODER_TMDS, NULL); 3510 drm_encoder_helper_add(encoder, &dce_v6_0_ext_helper_funcs); 3511 break; 3512 } 3513 } 3514 3515 static const struct amdgpu_display_funcs dce_v6_0_display_funcs = { 3516 .bandwidth_update = &dce_v6_0_bandwidth_update, 3517 .vblank_get_counter = &dce_v6_0_vblank_get_counter, 3518 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3519 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3520 .hpd_sense = &dce_v6_0_hpd_sense, 3521 .hpd_set_polarity = &dce_v6_0_hpd_set_polarity, 3522 .hpd_get_gpio_reg = &dce_v6_0_hpd_get_gpio_reg, 3523 .page_flip = &dce_v6_0_page_flip, 3524 .page_flip_get_scanoutpos = &dce_v6_0_crtc_get_scanoutpos, 3525 .add_encoder = &dce_v6_0_encoder_add, 3526 .add_connector = &amdgpu_connector_add, 3527 }; 3528 3529 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev) 3530 { 3531 adev->mode_info.funcs = &dce_v6_0_display_funcs; 3532 } 3533 3534 static const struct amdgpu_irq_src_funcs dce_v6_0_crtc_irq_funcs = { 3535 .set = dce_v6_0_set_crtc_interrupt_state, 3536 .process = dce_v6_0_crtc_irq, 3537 }; 3538 3539 static const struct amdgpu_irq_src_funcs dce_v6_0_pageflip_irq_funcs = { 3540 .set = dce_v6_0_set_pageflip_interrupt_state, 3541 .process = dce_v6_0_pageflip_irq, 3542 }; 3543 3544 static const struct amdgpu_irq_src_funcs dce_v6_0_hpd_irq_funcs = { 3545 .set = dce_v6_0_set_hpd_interrupt_state, 3546 .process = dce_v6_0_hpd_irq, 3547 }; 3548 3549 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev) 3550 { 3551 if (adev->mode_info.num_crtc > 0) 3552 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; 3553 else 3554 adev->crtc_irq.num_types = 0; 3555 adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs; 3556 3557 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; 3558 adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs; 3559 3560 adev->hpd_irq.num_types = adev->mode_info.num_hpd; 3561 adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs; 3562 } 3563 3564 const struct amdgpu_ip_block_version dce_v6_0_ip_block = 3565 { 3566 .type = AMD_IP_BLOCK_TYPE_DCE, 3567 .major = 6, 3568 .minor = 0, 3569 .rev = 0, 3570 .funcs = &dce_v6_0_ip_funcs, 3571 }; 3572 3573 const struct amdgpu_ip_block_version dce_v6_4_ip_block = 3574 { 3575 .type = AMD_IP_BLOCK_TYPE_DCE, 3576 .major = 6, 3577 .minor = 4, 3578 .rev = 0, 3579 .funcs = &dce_v6_0_ip_funcs, 3580 }; 3581