1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include <drm/drm_edid.h> 27 #include <drm/drm_fourcc.h> 28 #include <drm/drm_modeset_helper.h> 29 #include <drm/drm_modeset_helper_vtables.h> 30 #include <drm/drm_vblank.h> 31 32 #include "amdgpu.h" 33 #include "amdgpu_pm.h" 34 #include "amdgpu_i2c.h" 35 #include "atom.h" 36 #include "amdgpu_atombios.h" 37 #include "atombios_crtc.h" 38 #include "atombios_encoders.h" 39 #include "amdgpu_pll.h" 40 #include "amdgpu_connectors.h" 41 #include "amdgpu_display.h" 42 43 #include "dce_v6_0.h" 44 45 #include "bif/bif_3_0_d.h" 46 #include "bif/bif_3_0_sh_mask.h" 47 48 #include "oss/oss_1_0_d.h" 49 #include "oss/oss_1_0_sh_mask.h" 50 51 #include "gca/gfx_6_0_d.h" 52 #include "gca/gfx_6_0_sh_mask.h" 53 #include "gca/gfx_7_2_enum.h" 54 55 #include "gmc/gmc_6_0_d.h" 56 #include "gmc/gmc_6_0_sh_mask.h" 57 58 #include "dce/dce_6_0_d.h" 59 #include "dce/dce_6_0_sh_mask.h" 60 61 #include "si_enums.h" 62 63 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev); 64 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev); 65 66 static const u32 crtc_offsets[6] = 67 { 68 SI_CRTC0_REGISTER_OFFSET, 69 SI_CRTC1_REGISTER_OFFSET, 70 SI_CRTC2_REGISTER_OFFSET, 71 SI_CRTC3_REGISTER_OFFSET, 72 SI_CRTC4_REGISTER_OFFSET, 73 SI_CRTC5_REGISTER_OFFSET 74 }; 75 76 static const u32 hpd_offsets[] = 77 { 78 mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS, 79 mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS, 80 mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS, 81 mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS, 82 mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS, 83 mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS, 84 }; 85 86 static const uint32_t dig_offsets[] = { 87 SI_CRTC0_REGISTER_OFFSET, 88 SI_CRTC1_REGISTER_OFFSET, 89 SI_CRTC2_REGISTER_OFFSET, 90 SI_CRTC3_REGISTER_OFFSET, 91 SI_CRTC4_REGISTER_OFFSET, 92 SI_CRTC5_REGISTER_OFFSET, 93 (0x13830 - 0x7030) >> 2, 94 }; 95 96 static const struct { 97 uint32_t reg; 98 uint32_t vblank; 99 uint32_t vline; 100 uint32_t hpd; 101 102 } interrupt_status_offsets[6] = { { 103 .reg = mmDISP_INTERRUPT_STATUS, 104 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 105 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 106 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 107 }, { 108 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 109 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 110 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 111 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 112 }, { 113 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 114 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 115 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 116 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 117 }, { 118 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 119 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 120 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 121 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 122 }, { 123 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 124 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 125 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 126 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 127 }, { 128 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 129 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 130 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 131 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 132 } }; 133 134 static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev, 135 u32 block_offset, u32 reg) 136 { 137 unsigned long flags; 138 u32 r; 139 140 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 141 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 142 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 143 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 144 145 return r; 146 } 147 148 static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev, 149 u32 block_offset, u32 reg, u32 v) 150 { 151 unsigned long flags; 152 153 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 154 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, 155 reg | AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK); 156 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 157 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 158 } 159 160 static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 161 { 162 if (crtc >= adev->mode_info.num_crtc) 163 return 0; 164 else 165 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 166 } 167 168 static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev) 169 { 170 unsigned i; 171 172 /* Enable pflip interrupts */ 173 for (i = 0; i < adev->mode_info.num_crtc; i++) 174 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 175 } 176 177 static void dce_v6_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 178 { 179 unsigned i; 180 181 /* Disable pflip interrupts */ 182 for (i = 0; i < adev->mode_info.num_crtc; i++) 183 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 184 } 185 186 /** 187 * dce_v6_0_page_flip - pageflip callback. 188 * 189 * @adev: amdgpu_device pointer 190 * @crtc_id: crtc to cleanup pageflip on 191 * @crtc_base: new address of the crtc (GPU MC address) 192 * @async: asynchronous flip 193 * 194 * Does the actual pageflip (evergreen+). 195 * During vblank we take the crtc lock and wait for the update_pending 196 * bit to go high, when it does, we release the lock, and allow the 197 * double buffered update to take place. 198 * Returns the current update pending status. 199 */ 200 static void dce_v6_0_page_flip(struct amdgpu_device *adev, 201 int crtc_id, u64 crtc_base, bool async) 202 { 203 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 204 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; 205 206 /* flip at hsync for async, default is vsync */ 207 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? 208 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); 209 /* update pitch */ 210 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, 211 fb->pitches[0] / fb->format->cpp[0]); 212 /* update the scanout addresses */ 213 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 214 upper_32_bits(crtc_base)); 215 /* writing to the low address triggers the update */ 216 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 217 (u32)crtc_base); 218 /* post the write */ 219 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 220 } 221 222 static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 223 u32 *vbl, u32 *position) 224 { 225 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 226 return -EINVAL; 227 228 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 229 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 230 231 return 0; 232 } 233 234 /** 235 * dce_v6_0_hpd_sense - hpd sense callback. 236 * 237 * @adev: amdgpu_device pointer 238 * @hpd: hpd (hotplug detect) pin 239 * 240 * Checks if a digital monitor is connected (evergreen+). 241 * Returns true if connected, false if not connected. 242 */ 243 static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev, 244 enum amdgpu_hpd_id hpd) 245 { 246 bool connected = false; 247 248 if (hpd >= adev->mode_info.num_hpd) 249 return connected; 250 251 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & 252 DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) 253 connected = true; 254 255 return connected; 256 } 257 258 /** 259 * dce_v6_0_hpd_set_polarity - hpd set polarity callback. 260 * 261 * @adev: amdgpu_device pointer 262 * @hpd: hpd (hotplug detect) pin 263 * 264 * Set the polarity of the hpd pin (evergreen+). 265 */ 266 static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev, 267 enum amdgpu_hpd_id hpd) 268 { 269 u32 tmp; 270 bool connected = dce_v6_0_hpd_sense(adev, hpd); 271 272 if (hpd >= adev->mode_info.num_hpd) 273 return; 274 275 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 276 if (connected) 277 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 278 else 279 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 280 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 281 } 282 283 static void dce_v6_0_hpd_int_ack(struct amdgpu_device *adev, 284 int hpd) 285 { 286 u32 tmp; 287 288 if (hpd >= adev->mode_info.num_hpd) { 289 DRM_DEBUG("invalid hdp %d\n", hpd); 290 return; 291 } 292 293 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 294 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; 295 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 296 } 297 298 /** 299 * dce_v6_0_hpd_init - hpd setup callback. 300 * 301 * @adev: amdgpu_device pointer 302 * 303 * Setup the hpd pins used by the card (evergreen+). 304 * Enable the pin, set the polarity, and enable the hpd interrupts. 305 */ 306 static void dce_v6_0_hpd_init(struct amdgpu_device *adev) 307 { 308 struct drm_device *dev = adev_to_drm(adev); 309 struct drm_connector *connector; 310 struct drm_connector_list_iter iter; 311 u32 tmp; 312 313 drm_connector_list_iter_begin(dev, &iter); 314 drm_for_each_connector_iter(connector, &iter) { 315 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 316 317 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 318 continue; 319 320 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 321 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK; 322 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 323 324 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 325 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 326 /* don't try to enable hpd on eDP or LVDS avoid breaking the 327 * aux dp channel on imac and help (but not completely fix) 328 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 329 * also avoid interrupt storms during dpms. 330 */ 331 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 332 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 333 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 334 continue; 335 } 336 337 dce_v6_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd); 338 dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 339 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 340 } 341 drm_connector_list_iter_end(&iter); 342 } 343 344 /** 345 * dce_v6_0_hpd_fini - hpd tear down callback. 346 * 347 * @adev: amdgpu_device pointer 348 * 349 * Tear down the hpd pins used by the card (evergreen+). 350 * Disable the hpd interrupts. 351 */ 352 static void dce_v6_0_hpd_fini(struct amdgpu_device *adev) 353 { 354 struct drm_device *dev = adev_to_drm(adev); 355 struct drm_connector *connector; 356 struct drm_connector_list_iter iter; 357 u32 tmp; 358 359 drm_connector_list_iter_begin(dev, &iter); 360 drm_for_each_connector_iter(connector, &iter) { 361 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 362 363 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 364 continue; 365 366 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 367 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK; 368 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 369 370 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 371 } 372 drm_connector_list_iter_end(&iter); 373 } 374 375 static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 376 { 377 return mmDC_GPIO_HPD_A; 378 } 379 380 static bool dce_v6_0_is_display_hung(struct amdgpu_device *adev) 381 { 382 u32 crtc_hung = 0; 383 u32 crtc_status[6]; 384 u32 i, j, tmp; 385 386 for (i = 0; i < adev->mode_info.num_crtc; i++) { 387 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) { 388 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 389 crtc_hung |= (1 << i); 390 } 391 } 392 393 for (j = 0; j < 10; j++) { 394 for (i = 0; i < adev->mode_info.num_crtc; i++) { 395 if (crtc_hung & (1 << i)) { 396 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 397 if (tmp != crtc_status[i]) 398 crtc_hung &= ~(1 << i); 399 } 400 } 401 if (crtc_hung == 0) 402 return false; 403 udelay(100); 404 } 405 406 return true; 407 } 408 409 static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev, 410 bool render) 411 { 412 if (!render) 413 WREG32(mmVGA_RENDER_CONTROL, 414 RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL); 415 } 416 417 static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev) 418 { 419 switch (adev->asic_type) { 420 case CHIP_TAHITI: 421 case CHIP_PITCAIRN: 422 case CHIP_VERDE: 423 return 6; 424 case CHIP_OLAND: 425 return 2; 426 default: 427 return 0; 428 } 429 } 430 431 void dce_v6_0_disable_dce(struct amdgpu_device *adev) 432 { 433 /*Disable VGA render and enabled crtc, if has DCE engine*/ 434 if (amdgpu_atombios_has_dce_engine_info(adev)) { 435 u32 tmp; 436 int crtc_enabled, i; 437 438 dce_v6_0_set_vga_render_state(adev, false); 439 440 /*Disable crtc*/ 441 for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) { 442 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & 443 CRTC_CONTROL__CRTC_MASTER_EN_MASK; 444 if (crtc_enabled) { 445 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 446 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 447 tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK; 448 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 449 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 450 } 451 } 452 } 453 } 454 455 static void dce_v6_0_program_fmt(struct drm_encoder *encoder) 456 { 457 struct drm_device *dev = encoder->dev; 458 struct amdgpu_device *adev = drm_to_adev(dev); 459 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 460 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 461 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 462 int bpc = 0; 463 u32 tmp = 0; 464 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 465 466 if (connector) { 467 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 468 bpc = amdgpu_connector_get_monitor_bpc(connector); 469 dither = amdgpu_connector->dither; 470 } 471 472 /* LVDS FMT is set up by atom */ 473 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 474 return; 475 476 if (bpc == 0) 477 return; 478 479 480 switch (bpc) { 481 case 6: 482 if (dither == AMDGPU_FMT_DITHER_ENABLE) 483 /* XXX sort out optimal dither settings */ 484 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 485 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 486 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK); 487 else 488 tmp |= FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK; 489 break; 490 case 8: 491 if (dither == AMDGPU_FMT_DITHER_ENABLE) 492 /* XXX sort out optimal dither settings */ 493 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 494 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 495 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK | 496 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | 497 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK); 498 else 499 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | 500 FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK); 501 break; 502 case 10: 503 default: 504 /* not needed */ 505 break; 506 } 507 508 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 509 } 510 511 /** 512 * si_get_number_of_dram_channels - get the number of dram channels 513 * 514 * @adev: amdgpu_device pointer 515 * 516 * Look up the number of video ram channels (CIK). 517 * Used for display watermark bandwidth calculations 518 * Returns the number of dram channels 519 */ 520 static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev) 521 { 522 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 523 524 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { 525 case 0: 526 default: 527 return 1; 528 case 1: 529 return 2; 530 case 2: 531 return 4; 532 case 3: 533 return 8; 534 case 4: 535 return 3; 536 case 5: 537 return 6; 538 case 6: 539 return 10; 540 case 7: 541 return 12; 542 case 8: 543 return 16; 544 } 545 } 546 547 struct dce6_wm_params { 548 u32 dram_channels; /* number of dram channels */ 549 u32 yclk; /* bandwidth per dram data pin in kHz */ 550 u32 sclk; /* engine clock in kHz */ 551 u32 disp_clk; /* display clock in kHz */ 552 u32 src_width; /* viewport width */ 553 u32 active_time; /* active display time in ns */ 554 u32 blank_time; /* blank time in ns */ 555 bool interlaced; /* mode is interlaced */ 556 fixed20_12 vsc; /* vertical scale ratio */ 557 u32 num_heads; /* number of active crtcs */ 558 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 559 u32 lb_size; /* line buffer allocated to pipe */ 560 u32 vtaps; /* vertical scaler taps */ 561 }; 562 563 /** 564 * dce_v6_0_dram_bandwidth - get the dram bandwidth 565 * 566 * @wm: watermark calculation data 567 * 568 * Calculate the raw dram bandwidth (CIK). 569 * Used for display watermark bandwidth calculations 570 * Returns the dram bandwidth in MBytes/s 571 */ 572 static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm) 573 { 574 /* Calculate raw DRAM Bandwidth */ 575 fixed20_12 dram_efficiency; /* 0.7 */ 576 fixed20_12 yclk, dram_channels, bandwidth; 577 fixed20_12 a; 578 579 a.full = dfixed_const(1000); 580 yclk.full = dfixed_const(wm->yclk); 581 yclk.full = dfixed_div(yclk, a); 582 dram_channels.full = dfixed_const(wm->dram_channels * 4); 583 a.full = dfixed_const(10); 584 dram_efficiency.full = dfixed_const(7); 585 dram_efficiency.full = dfixed_div(dram_efficiency, a); 586 bandwidth.full = dfixed_mul(dram_channels, yclk); 587 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 588 589 return dfixed_trunc(bandwidth); 590 } 591 592 /** 593 * dce_v6_0_dram_bandwidth_for_display - get the dram bandwidth for display 594 * 595 * @wm: watermark calculation data 596 * 597 * Calculate the dram bandwidth used for display (CIK). 598 * Used for display watermark bandwidth calculations 599 * Returns the dram bandwidth for display in MBytes/s 600 */ 601 static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm) 602 { 603 /* Calculate DRAM Bandwidth and the part allocated to display. */ 604 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 605 fixed20_12 yclk, dram_channels, bandwidth; 606 fixed20_12 a; 607 608 a.full = dfixed_const(1000); 609 yclk.full = dfixed_const(wm->yclk); 610 yclk.full = dfixed_div(yclk, a); 611 dram_channels.full = dfixed_const(wm->dram_channels * 4); 612 a.full = dfixed_const(10); 613 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 614 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 615 bandwidth.full = dfixed_mul(dram_channels, yclk); 616 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 617 618 return dfixed_trunc(bandwidth); 619 } 620 621 /** 622 * dce_v6_0_data_return_bandwidth - get the data return bandwidth 623 * 624 * @wm: watermark calculation data 625 * 626 * Calculate the data return bandwidth used for display (CIK). 627 * Used for display watermark bandwidth calculations 628 * Returns the data return bandwidth in MBytes/s 629 */ 630 static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm) 631 { 632 /* Calculate the display Data return Bandwidth */ 633 fixed20_12 return_efficiency; /* 0.8 */ 634 fixed20_12 sclk, bandwidth; 635 fixed20_12 a; 636 637 a.full = dfixed_const(1000); 638 sclk.full = dfixed_const(wm->sclk); 639 sclk.full = dfixed_div(sclk, a); 640 a.full = dfixed_const(10); 641 return_efficiency.full = dfixed_const(8); 642 return_efficiency.full = dfixed_div(return_efficiency, a); 643 a.full = dfixed_const(32); 644 bandwidth.full = dfixed_mul(a, sclk); 645 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 646 647 return dfixed_trunc(bandwidth); 648 } 649 650 /** 651 * dce_v6_0_dmif_request_bandwidth - get the dmif bandwidth 652 * 653 * @wm: watermark calculation data 654 * 655 * Calculate the dmif bandwidth used for display (CIK). 656 * Used for display watermark bandwidth calculations 657 * Returns the dmif bandwidth in MBytes/s 658 */ 659 static u32 dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params *wm) 660 { 661 /* Calculate the DMIF Request Bandwidth */ 662 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 663 fixed20_12 disp_clk, bandwidth; 664 fixed20_12 a, b; 665 666 a.full = dfixed_const(1000); 667 disp_clk.full = dfixed_const(wm->disp_clk); 668 disp_clk.full = dfixed_div(disp_clk, a); 669 a.full = dfixed_const(32); 670 b.full = dfixed_mul(a, disp_clk); 671 672 a.full = dfixed_const(10); 673 disp_clk_request_efficiency.full = dfixed_const(8); 674 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 675 676 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 677 678 return dfixed_trunc(bandwidth); 679 } 680 681 /** 682 * dce_v6_0_available_bandwidth - get the min available bandwidth 683 * 684 * @wm: watermark calculation data 685 * 686 * Calculate the min available bandwidth used for display (CIK). 687 * Used for display watermark bandwidth calculations 688 * Returns the min available bandwidth in MBytes/s 689 */ 690 static u32 dce_v6_0_available_bandwidth(struct dce6_wm_params *wm) 691 { 692 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 693 u32 dram_bandwidth = dce_v6_0_dram_bandwidth(wm); 694 u32 data_return_bandwidth = dce_v6_0_data_return_bandwidth(wm); 695 u32 dmif_req_bandwidth = dce_v6_0_dmif_request_bandwidth(wm); 696 697 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 698 } 699 700 /** 701 * dce_v6_0_average_bandwidth - get the average available bandwidth 702 * 703 * @wm: watermark calculation data 704 * 705 * Calculate the average available bandwidth used for display (CIK). 706 * Used for display watermark bandwidth calculations 707 * Returns the average available bandwidth in MBytes/s 708 */ 709 static u32 dce_v6_0_average_bandwidth(struct dce6_wm_params *wm) 710 { 711 /* Calculate the display mode Average Bandwidth 712 * DisplayMode should contain the source and destination dimensions, 713 * timing, etc. 714 */ 715 fixed20_12 bpp; 716 fixed20_12 line_time; 717 fixed20_12 src_width; 718 fixed20_12 bandwidth; 719 fixed20_12 a; 720 721 a.full = dfixed_const(1000); 722 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 723 line_time.full = dfixed_div(line_time, a); 724 bpp.full = dfixed_const(wm->bytes_per_pixel); 725 src_width.full = dfixed_const(wm->src_width); 726 bandwidth.full = dfixed_mul(src_width, bpp); 727 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 728 bandwidth.full = dfixed_div(bandwidth, line_time); 729 730 return dfixed_trunc(bandwidth); 731 } 732 733 /** 734 * dce_v6_0_latency_watermark - get the latency watermark 735 * 736 * @wm: watermark calculation data 737 * 738 * Calculate the latency watermark (CIK). 739 * Used for display watermark bandwidth calculations 740 * Returns the latency watermark in ns 741 */ 742 static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm) 743 { 744 /* First calculate the latency in ns */ 745 u32 mc_latency = 2000; /* 2000 ns. */ 746 u32 available_bandwidth = dce_v6_0_available_bandwidth(wm); 747 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 748 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 749 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 750 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 751 (wm->num_heads * cursor_line_pair_return_time); 752 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 753 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 754 u32 tmp, dmif_size = 12288; 755 fixed20_12 a, b, c; 756 757 if (wm->num_heads == 0) 758 return 0; 759 760 a.full = dfixed_const(2); 761 b.full = dfixed_const(1); 762 if ((wm->vsc.full > a.full) || 763 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 764 (wm->vtaps >= 5) || 765 ((wm->vsc.full >= a.full) && wm->interlaced)) 766 max_src_lines_per_dst_line = 4; 767 else 768 max_src_lines_per_dst_line = 2; 769 770 a.full = dfixed_const(available_bandwidth); 771 b.full = dfixed_const(wm->num_heads); 772 a.full = dfixed_div(a, b); 773 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); 774 tmp = min(dfixed_trunc(a), tmp); 775 776 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); 777 778 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 779 b.full = dfixed_const(1000); 780 c.full = dfixed_const(lb_fill_bw); 781 b.full = dfixed_div(c, b); 782 a.full = dfixed_div(a, b); 783 line_fill_time = dfixed_trunc(a); 784 785 if (line_fill_time < wm->active_time) 786 return latency; 787 else 788 return latency + (line_fill_time - wm->active_time); 789 790 } 791 792 /** 793 * dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display - check 794 * average and available dram bandwidth 795 * 796 * @wm: watermark calculation data 797 * 798 * Check if the display average bandwidth fits in the display 799 * dram bandwidth (CIK). 800 * Used for display watermark bandwidth calculations 801 * Returns true if the display fits, false if not. 802 */ 803 static bool dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm) 804 { 805 if (dce_v6_0_average_bandwidth(wm) <= 806 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 807 return true; 808 else 809 return false; 810 } 811 812 /** 813 * dce_v6_0_average_bandwidth_vs_available_bandwidth - check 814 * average and available bandwidth 815 * 816 * @wm: watermark calculation data 817 * 818 * Check if the display average bandwidth fits in the display 819 * available bandwidth (CIK). 820 * Used for display watermark bandwidth calculations 821 * Returns true if the display fits, false if not. 822 */ 823 static bool dce_v6_0_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm) 824 { 825 if (dce_v6_0_average_bandwidth(wm) <= 826 (dce_v6_0_available_bandwidth(wm) / wm->num_heads)) 827 return true; 828 else 829 return false; 830 } 831 832 /** 833 * dce_v6_0_check_latency_hiding - check latency hiding 834 * 835 * @wm: watermark calculation data 836 * 837 * Check latency hiding (CIK). 838 * Used for display watermark bandwidth calculations 839 * Returns true if the display fits, false if not. 840 */ 841 static bool dce_v6_0_check_latency_hiding(struct dce6_wm_params *wm) 842 { 843 u32 lb_partitions = wm->lb_size / wm->src_width; 844 u32 line_time = wm->active_time + wm->blank_time; 845 u32 latency_tolerant_lines; 846 u32 latency_hiding; 847 fixed20_12 a; 848 849 a.full = dfixed_const(1); 850 if (wm->vsc.full > a.full) 851 latency_tolerant_lines = 1; 852 else { 853 if (lb_partitions <= (wm->vtaps + 1)) 854 latency_tolerant_lines = 1; 855 else 856 latency_tolerant_lines = 2; 857 } 858 859 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 860 861 if (dce_v6_0_latency_watermark(wm) <= latency_hiding) 862 return true; 863 else 864 return false; 865 } 866 867 /** 868 * dce_v6_0_program_watermarks - program display watermarks 869 * 870 * @adev: amdgpu_device pointer 871 * @amdgpu_crtc: the selected display controller 872 * @lb_size: line buffer size 873 * @num_heads: number of display controllers in use 874 * 875 * Calculate and program the display watermarks for the 876 * selected display controller (CIK). 877 */ 878 static void dce_v6_0_program_watermarks(struct amdgpu_device *adev, 879 struct amdgpu_crtc *amdgpu_crtc, 880 u32 lb_size, u32 num_heads) 881 { 882 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 883 struct dce6_wm_params wm_low, wm_high; 884 u32 dram_channels; 885 u32 active_time; 886 u32 line_time = 0; 887 u32 latency_watermark_a = 0, latency_watermark_b = 0; 888 u32 priority_a_mark = 0, priority_b_mark = 0; 889 u32 priority_a_cnt = PRIORITY_OFF; 890 u32 priority_b_cnt = PRIORITY_OFF; 891 u32 tmp, arb_control3, lb_vblank_lead_lines = 0; 892 fixed20_12 a, b, c; 893 894 if (amdgpu_crtc->base.enabled && num_heads && mode) { 895 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, 896 (u32)mode->clock); 897 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, 898 (u32)mode->clock); 899 line_time = min_t(u32, line_time, 65535); 900 priority_a_cnt = 0; 901 priority_b_cnt = 0; 902 903 dram_channels = si_get_number_of_dram_channels(adev); 904 905 /* watermark for high clocks */ 906 if (adev->pm.dpm_enabled) { 907 wm_high.yclk = 908 amdgpu_dpm_get_mclk(adev, false) * 10; 909 wm_high.sclk = 910 amdgpu_dpm_get_sclk(adev, false) * 10; 911 } else { 912 wm_high.yclk = adev->pm.current_mclk * 10; 913 wm_high.sclk = adev->pm.current_sclk * 10; 914 } 915 916 wm_high.disp_clk = mode->clock; 917 wm_high.src_width = mode->crtc_hdisplay; 918 wm_high.active_time = active_time; 919 wm_high.blank_time = line_time - wm_high.active_time; 920 wm_high.interlaced = false; 921 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 922 wm_high.interlaced = true; 923 wm_high.vsc = amdgpu_crtc->vsc; 924 wm_high.vtaps = 1; 925 if (amdgpu_crtc->rmx_type != RMX_OFF) 926 wm_high.vtaps = 2; 927 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 928 wm_high.lb_size = lb_size; 929 wm_high.dram_channels = dram_channels; 930 wm_high.num_heads = num_heads; 931 932 /* watermark for low clocks */ 933 if (adev->pm.dpm_enabled) { 934 wm_low.yclk = 935 amdgpu_dpm_get_mclk(adev, true) * 10; 936 wm_low.sclk = 937 amdgpu_dpm_get_sclk(adev, true) * 10; 938 } else { 939 wm_low.yclk = adev->pm.current_mclk * 10; 940 wm_low.sclk = adev->pm.current_sclk * 10; 941 } 942 943 wm_low.disp_clk = mode->clock; 944 wm_low.src_width = mode->crtc_hdisplay; 945 wm_low.active_time = active_time; 946 wm_low.blank_time = line_time - wm_low.active_time; 947 wm_low.interlaced = false; 948 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 949 wm_low.interlaced = true; 950 wm_low.vsc = amdgpu_crtc->vsc; 951 wm_low.vtaps = 1; 952 if (amdgpu_crtc->rmx_type != RMX_OFF) 953 wm_low.vtaps = 2; 954 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 955 wm_low.lb_size = lb_size; 956 wm_low.dram_channels = dram_channels; 957 wm_low.num_heads = num_heads; 958 959 /* set for high clocks */ 960 latency_watermark_a = min_t(u32, dce_v6_0_latency_watermark(&wm_high), 65535); 961 /* set for low clocks */ 962 latency_watermark_b = min_t(u32, dce_v6_0_latency_watermark(&wm_low), 65535); 963 964 /* possibly force display priority to high */ 965 /* should really do this at mode validation time... */ 966 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 967 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 968 !dce_v6_0_check_latency_hiding(&wm_high) || 969 (adev->mode_info.disp_priority == 2)) { 970 DRM_DEBUG_KMS("force priority to high\n"); 971 priority_a_cnt |= PRIORITY_ALWAYS_ON; 972 priority_b_cnt |= PRIORITY_ALWAYS_ON; 973 } 974 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 975 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 976 !dce_v6_0_check_latency_hiding(&wm_low) || 977 (adev->mode_info.disp_priority == 2)) { 978 DRM_DEBUG_KMS("force priority to high\n"); 979 priority_a_cnt |= PRIORITY_ALWAYS_ON; 980 priority_b_cnt |= PRIORITY_ALWAYS_ON; 981 } 982 983 a.full = dfixed_const(1000); 984 b.full = dfixed_const(mode->clock); 985 b.full = dfixed_div(b, a); 986 c.full = dfixed_const(latency_watermark_a); 987 c.full = dfixed_mul(c, b); 988 c.full = dfixed_mul(c, amdgpu_crtc->hsc); 989 c.full = dfixed_div(c, a); 990 a.full = dfixed_const(16); 991 c.full = dfixed_div(c, a); 992 priority_a_mark = dfixed_trunc(c); 993 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK; 994 995 a.full = dfixed_const(1000); 996 b.full = dfixed_const(mode->clock); 997 b.full = dfixed_div(b, a); 998 c.full = dfixed_const(latency_watermark_b); 999 c.full = dfixed_mul(c, b); 1000 c.full = dfixed_mul(c, amdgpu_crtc->hsc); 1001 c.full = dfixed_div(c, a); 1002 a.full = dfixed_const(16); 1003 c.full = dfixed_div(c, a); 1004 priority_b_mark = dfixed_trunc(c); 1005 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; 1006 1007 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1008 } 1009 1010 /* select wm A */ 1011 arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); 1012 tmp = arb_control3; 1013 tmp &= ~LATENCY_WATERMARK_MASK(3); 1014 tmp |= LATENCY_WATERMARK_MASK(1); 1015 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); 1016 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 1017 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 1018 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 1019 /* select wm B */ 1020 tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); 1021 tmp &= ~LATENCY_WATERMARK_MASK(3); 1022 tmp |= LATENCY_WATERMARK_MASK(2); 1023 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); 1024 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 1025 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 1026 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 1027 /* restore original selection */ 1028 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3); 1029 1030 /* write the priority marks */ 1031 WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt); 1032 WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt); 1033 1034 /* save values for DPM */ 1035 amdgpu_crtc->line_time = line_time; 1036 amdgpu_crtc->wm_high = latency_watermark_a; 1037 1038 /* Save number of lines the linebuffer leads before the scanout */ 1039 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1040 } 1041 1042 /* watermark setup */ 1043 /** 1044 * dce_v6_0_line_buffer_adjust - Set up the line buffer 1045 * 1046 * @adev: amdgpu_device pointer 1047 * @amdgpu_crtc: the selected display controller 1048 * @mode: the current display mode on the selected display 1049 * controller 1050 * @other_mode: the display mode of another display controller 1051 * that may be sharing the line buffer 1052 * 1053 * Setup up the line buffer allocation for 1054 * the selected display controller (CIK). 1055 * Returns the line buffer size in pixels. 1056 */ 1057 static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev, 1058 struct amdgpu_crtc *amdgpu_crtc, 1059 struct drm_display_mode *mode, 1060 struct drm_display_mode *other_mode) 1061 { 1062 u32 tmp, buffer_alloc, i; 1063 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; 1064 /* 1065 * Line Buffer Setup 1066 * There are 3 line buffers, each one shared by 2 display controllers. 1067 * mmDC_LB_MEMORY_SPLIT controls how that line buffer is shared between 1068 * the display controllers. The paritioning is done via one of four 1069 * preset allocations specified in bits 21:20: 1070 * 0 - half lb 1071 * 2 - whole lb, other crtc must be disabled 1072 */ 1073 /* this can get tricky if we have two large displays on a paired group 1074 * of crtcs. Ideally for multiple large displays we'd assign them to 1075 * non-linked crtcs for maximum line buffer allocation. 1076 */ 1077 if (amdgpu_crtc->base.enabled && mode) { 1078 if (other_mode) { 1079 tmp = 0; /* 1/2 */ 1080 buffer_alloc = 1; 1081 } else { 1082 tmp = 2; /* whole */ 1083 buffer_alloc = 2; 1084 } 1085 } else { 1086 tmp = 0; 1087 buffer_alloc = 0; 1088 } 1089 1090 WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset, 1091 DC_LB_MEMORY_CONFIG(tmp)); 1092 1093 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, 1094 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT)); 1095 for (i = 0; i < adev->usec_timeout; i++) { 1096 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & 1097 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK) 1098 break; 1099 udelay(1); 1100 } 1101 1102 if (amdgpu_crtc->base.enabled && mode) { 1103 switch (tmp) { 1104 case 0: 1105 default: 1106 return 4096 * 2; 1107 case 2: 1108 return 8192 * 2; 1109 } 1110 } 1111 1112 /* controller not enabled, so no lb used */ 1113 return 0; 1114 } 1115 1116 1117 /** 1118 * dce_v6_0_bandwidth_update - program display watermarks 1119 * 1120 * @adev: amdgpu_device pointer 1121 * 1122 * Calculate and program the display watermarks and line 1123 * buffer allocation (CIK). 1124 */ 1125 static void dce_v6_0_bandwidth_update(struct amdgpu_device *adev) 1126 { 1127 struct drm_display_mode *mode0 = NULL; 1128 struct drm_display_mode *mode1 = NULL; 1129 u32 num_heads = 0, lb_size; 1130 int i; 1131 1132 if (!adev->mode_info.mode_config_initialized) 1133 return; 1134 1135 amdgpu_display_update_priority(adev); 1136 1137 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1138 if (adev->mode_info.crtcs[i]->base.enabled) 1139 num_heads++; 1140 } 1141 for (i = 0; i < adev->mode_info.num_crtc; i += 2) { 1142 mode0 = &adev->mode_info.crtcs[i]->base.mode; 1143 mode1 = &adev->mode_info.crtcs[i+1]->base.mode; 1144 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1); 1145 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads); 1146 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0); 1147 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads); 1148 } 1149 } 1150 1151 static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device *adev) 1152 { 1153 int i; 1154 u32 tmp; 1155 1156 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1157 tmp = RREG32_AUDIO_ENDPT(adev->mode_info.audio.pin[i].offset, 1158 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1159 if (REG_GET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT, 1160 PORT_CONNECTIVITY)) 1161 adev->mode_info.audio.pin[i].connected = false; 1162 else 1163 adev->mode_info.audio.pin[i].connected = true; 1164 } 1165 1166 } 1167 1168 static struct amdgpu_audio_pin *dce_v6_0_audio_get_pin(struct amdgpu_device *adev) 1169 { 1170 int i; 1171 1172 dce_v6_0_audio_get_connected_pins(adev); 1173 1174 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1175 if (adev->mode_info.audio.pin[i].connected) 1176 return &adev->mode_info.audio.pin[i]; 1177 } 1178 DRM_ERROR("No connected audio pins found!\n"); 1179 return NULL; 1180 } 1181 1182 static void dce_v6_0_audio_select_pin(struct drm_encoder *encoder) 1183 { 1184 struct amdgpu_device *adev = drm_to_adev(encoder->dev); 1185 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1186 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1187 1188 if (!dig || !dig->afmt || !dig->afmt->pin) 1189 return; 1190 1191 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, 1192 REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, 1193 dig->afmt->pin->id)); 1194 } 1195 1196 static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder, 1197 struct drm_display_mode *mode) 1198 { 1199 struct drm_device *dev = encoder->dev; 1200 struct amdgpu_device *adev = drm_to_adev(dev); 1201 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1202 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1203 struct drm_connector *connector; 1204 struct drm_connector_list_iter iter; 1205 struct amdgpu_connector *amdgpu_connector = NULL; 1206 int interlace = 0; 1207 u32 tmp; 1208 1209 drm_connector_list_iter_begin(dev, &iter); 1210 drm_for_each_connector_iter(connector, &iter) { 1211 if (connector->encoder == encoder) { 1212 amdgpu_connector = to_amdgpu_connector(connector); 1213 break; 1214 } 1215 } 1216 drm_connector_list_iter_end(&iter); 1217 1218 if (!amdgpu_connector) { 1219 DRM_ERROR("Couldn't find encoder's connector\n"); 1220 return; 1221 } 1222 1223 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1224 interlace = 1; 1225 1226 if (connector->latency_present[interlace]) { 1227 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1228 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1229 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1230 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1231 } else { 1232 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1233 VIDEO_LIPSYNC, 0); 1234 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1235 AUDIO_LIPSYNC, 0); 1236 } 1237 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1238 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1239 } 1240 1241 static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1242 { 1243 struct drm_device *dev = encoder->dev; 1244 struct amdgpu_device *adev = drm_to_adev(dev); 1245 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1246 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1247 struct drm_connector *connector; 1248 struct drm_connector_list_iter iter; 1249 struct amdgpu_connector *amdgpu_connector = NULL; 1250 u8 *sadb = NULL; 1251 int sad_count; 1252 u32 tmp; 1253 1254 drm_connector_list_iter_begin(dev, &iter); 1255 drm_for_each_connector_iter(connector, &iter) { 1256 if (connector->encoder == encoder) { 1257 amdgpu_connector = to_amdgpu_connector(connector); 1258 break; 1259 } 1260 } 1261 drm_connector_list_iter_end(&iter); 1262 1263 if (!amdgpu_connector) { 1264 DRM_ERROR("Couldn't find encoder's connector\n"); 1265 return; 1266 } 1267 1268 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb); 1269 if (sad_count < 0) { 1270 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1271 sad_count = 0; 1272 } 1273 1274 /* program the speaker allocation */ 1275 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1276 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1277 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1278 HDMI_CONNECTION, 0); 1279 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1280 DP_CONNECTION, 0); 1281 1282 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) 1283 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1284 DP_CONNECTION, 1); 1285 else 1286 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1287 HDMI_CONNECTION, 1); 1288 1289 if (sad_count) 1290 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1291 SPEAKER_ALLOCATION, sadb[0]); 1292 else 1293 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1294 SPEAKER_ALLOCATION, 5); /* stereo */ 1295 1296 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1297 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1298 1299 kfree(sadb); 1300 } 1301 1302 static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder) 1303 { 1304 struct drm_device *dev = encoder->dev; 1305 struct amdgpu_device *adev = drm_to_adev(dev); 1306 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1307 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1308 struct drm_connector *connector; 1309 struct drm_connector_list_iter iter; 1310 struct amdgpu_connector *amdgpu_connector = NULL; 1311 struct cea_sad *sads; 1312 int i, sad_count; 1313 1314 static const u16 eld_reg_to_type[][2] = { 1315 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1316 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1317 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1318 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1319 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1320 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1321 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1322 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1323 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1324 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1325 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1326 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1327 }; 1328 1329 drm_connector_list_iter_begin(dev, &iter); 1330 drm_for_each_connector_iter(connector, &iter) { 1331 if (connector->encoder == encoder) { 1332 amdgpu_connector = to_amdgpu_connector(connector); 1333 break; 1334 } 1335 } 1336 drm_connector_list_iter_end(&iter); 1337 1338 if (!amdgpu_connector) { 1339 DRM_ERROR("Couldn't find encoder's connector\n"); 1340 return; 1341 } 1342 1343 sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads); 1344 if (sad_count < 0) 1345 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1346 if (sad_count <= 0) 1347 return; 1348 1349 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1350 u32 tmp = 0; 1351 u8 stereo_freqs = 0; 1352 int max_channels = -1; 1353 int j; 1354 1355 for (j = 0; j < sad_count; j++) { 1356 struct cea_sad *sad = &sads[j]; 1357 1358 if (sad->format == eld_reg_to_type[i][1]) { 1359 if (sad->channels > max_channels) { 1360 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1361 MAX_CHANNELS, sad->channels); 1362 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1363 DESCRIPTOR_BYTE_2, sad->byte2); 1364 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1365 SUPPORTED_FREQUENCIES, sad->freq); 1366 max_channels = sad->channels; 1367 } 1368 1369 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1370 stereo_freqs |= sad->freq; 1371 else 1372 break; 1373 } 1374 } 1375 1376 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1377 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); 1378 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); 1379 } 1380 1381 kfree(sads); 1382 1383 } 1384 1385 static void dce_v6_0_audio_enable(struct amdgpu_device *adev, 1386 struct amdgpu_audio_pin *pin, 1387 bool enable) 1388 { 1389 if (!pin) 1390 return; 1391 1392 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1393 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1394 } 1395 1396 static const u32 pin_offsets[7] = 1397 { 1398 (0x1780 - 0x1780), 1399 (0x1786 - 0x1780), 1400 (0x178c - 0x1780), 1401 (0x1792 - 0x1780), 1402 (0x1798 - 0x1780), 1403 (0x179d - 0x1780), 1404 (0x17a4 - 0x1780), 1405 }; 1406 1407 static int dce_v6_0_audio_init(struct amdgpu_device *adev) 1408 { 1409 int i; 1410 1411 if (!amdgpu_audio) 1412 return 0; 1413 1414 adev->mode_info.audio.enabled = true; 1415 1416 switch (adev->asic_type) { 1417 case CHIP_TAHITI: 1418 case CHIP_PITCAIRN: 1419 case CHIP_VERDE: 1420 default: 1421 adev->mode_info.audio.num_pins = 6; 1422 break; 1423 case CHIP_OLAND: 1424 adev->mode_info.audio.num_pins = 2; 1425 break; 1426 } 1427 1428 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1429 adev->mode_info.audio.pin[i].channels = -1; 1430 adev->mode_info.audio.pin[i].rate = -1; 1431 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1432 adev->mode_info.audio.pin[i].status_bits = 0; 1433 adev->mode_info.audio.pin[i].category_code = 0; 1434 adev->mode_info.audio.pin[i].connected = false; 1435 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1436 adev->mode_info.audio.pin[i].id = i; 1437 /* disable audio. it will be set up later */ 1438 /* XXX remove once we switch to ip funcs */ 1439 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1440 } 1441 1442 return 0; 1443 } 1444 1445 static void dce_v6_0_audio_fini(struct amdgpu_device *adev) 1446 { 1447 int i; 1448 1449 if (!amdgpu_audio) 1450 return; 1451 1452 if (!adev->mode_info.audio.enabled) 1453 return; 1454 1455 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1456 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1457 1458 adev->mode_info.audio.enabled = false; 1459 } 1460 1461 static void dce_v6_0_audio_set_vbi_packet(struct drm_encoder *encoder) 1462 { 1463 struct drm_device *dev = encoder->dev; 1464 struct amdgpu_device *adev = drm_to_adev(dev); 1465 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1466 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1467 u32 tmp; 1468 1469 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1470 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1471 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); 1472 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); 1473 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1474 } 1475 1476 static void dce_v6_0_audio_set_acr(struct drm_encoder *encoder, 1477 uint32_t clock, int bpc) 1478 { 1479 struct drm_device *dev = encoder->dev; 1480 struct amdgpu_device *adev = drm_to_adev(dev); 1481 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1482 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1483 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1484 u32 tmp; 1485 1486 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1487 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1488 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1489 bpc > 8 ? 0 : 1); 1490 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1491 1492 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1493 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1494 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1495 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1496 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1497 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1498 1499 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1500 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1501 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1502 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1503 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1504 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1505 1506 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1507 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1508 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1509 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1510 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1511 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1512 } 1513 1514 static void dce_v6_0_audio_set_avi_infoframe(struct drm_encoder *encoder, 1515 struct drm_display_mode *mode) 1516 { 1517 struct drm_device *dev = encoder->dev; 1518 struct amdgpu_device *adev = drm_to_adev(dev); 1519 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1520 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1521 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1522 struct hdmi_avi_infoframe frame; 1523 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1524 uint8_t *payload = buffer + 3; 1525 uint8_t *header = buffer; 1526 ssize_t err; 1527 u32 tmp; 1528 1529 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); 1530 if (err < 0) { 1531 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1532 return; 1533 } 1534 1535 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1536 if (err < 0) { 1537 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1538 return; 1539 } 1540 1541 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1542 payload[0x0] | (payload[0x1] << 8) | (payload[0x2] << 16) | (payload[0x3] << 24)); 1543 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1544 payload[0x4] | (payload[0x5] << 8) | (payload[0x6] << 16) | (payload[0x7] << 24)); 1545 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1546 payload[0x8] | (payload[0x9] << 8) | (payload[0xA] << 16) | (payload[0xB] << 24)); 1547 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1548 payload[0xC] | (payload[0xD] << 8) | (header[1] << 24)); 1549 1550 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1551 /* anything other than 0 */ 1552 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, 1553 HDMI_AUDIO_INFO_LINE, 2); 1554 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1555 } 1556 1557 static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1558 { 1559 struct drm_device *dev = encoder->dev; 1560 struct amdgpu_device *adev = drm_to_adev(dev); 1561 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1562 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 1563 u32 tmp; 1564 1565 /* 1566 * Two dtos: generally use dto0 for hdmi, dto1 for dp. 1567 * Express [24MHz / target pixel clock] as an exact rational 1568 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1569 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1570 */ 1571 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1572 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, 1573 DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id); 1574 if (em == ATOM_ENCODER_MODE_HDMI) { 1575 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, 1576 DCCG_AUDIO_DTO_SEL, 0); 1577 } else if (ENCODER_MODE_IS_DP(em)) { 1578 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, 1579 DCCG_AUDIO_DTO_SEL, 1); 1580 } 1581 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1582 if (em == ATOM_ENCODER_MODE_HDMI) { 1583 WREG32(mmDCCG_AUDIO_DTO0_PHASE, 24000); 1584 WREG32(mmDCCG_AUDIO_DTO0_MODULE, clock); 1585 } else if (ENCODER_MODE_IS_DP(em)) { 1586 WREG32(mmDCCG_AUDIO_DTO1_PHASE, 24000); 1587 WREG32(mmDCCG_AUDIO_DTO1_MODULE, clock); 1588 } 1589 } 1590 1591 static void dce_v6_0_audio_set_packet(struct drm_encoder *encoder) 1592 { 1593 struct drm_device *dev = encoder->dev; 1594 struct amdgpu_device *adev = drm_to_adev(dev); 1595 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1596 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1597 u32 tmp; 1598 1599 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1600 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1601 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1602 1603 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1604 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1605 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1606 1607 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1608 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1609 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1610 1611 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1612 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1613 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1614 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1615 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1616 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1617 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1618 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1619 1620 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset); 1621 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, 0xff); 1622 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, tmp); 1623 1624 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1625 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1626 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1627 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1628 1629 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1630 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_RESET_FIFO_WHEN_AUDIO_DIS, 1); 1631 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1632 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1633 } 1634 1635 static void dce_v6_0_audio_set_mute(struct drm_encoder *encoder, bool mute) 1636 { 1637 struct drm_device *dev = encoder->dev; 1638 struct amdgpu_device *adev = drm_to_adev(dev); 1639 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1640 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1641 u32 tmp; 1642 1643 tmp = RREG32(mmHDMI_GC + dig->afmt->offset); 1644 tmp = REG_SET_FIELD(tmp, HDMI_GC, HDMI_GC_AVMUTE, mute ? 1 : 0); 1645 WREG32(mmHDMI_GC + dig->afmt->offset, tmp); 1646 } 1647 1648 static void dce_v6_0_audio_hdmi_enable(struct drm_encoder *encoder, bool enable) 1649 { 1650 struct drm_device *dev = encoder->dev; 1651 struct amdgpu_device *adev = drm_to_adev(dev); 1652 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1653 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1654 u32 tmp; 1655 1656 if (enable) { 1657 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1658 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1659 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1660 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1661 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1662 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1663 1664 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1665 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1666 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1667 1668 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1669 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1670 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1671 } else { 1672 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1673 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 0); 1674 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 0); 1675 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 0); 1676 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 0); 1677 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1678 1679 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1680 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 0); 1681 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1682 } 1683 } 1684 1685 static void dce_v6_0_audio_dp_enable(struct drm_encoder *encoder, bool enable) 1686 { 1687 struct drm_device *dev = encoder->dev; 1688 struct amdgpu_device *adev = drm_to_adev(dev); 1689 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1690 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1691 u32 tmp; 1692 1693 if (enable) { 1694 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1695 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1696 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1697 1698 tmp = RREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset); 1699 tmp = REG_SET_FIELD(tmp, DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, 1); 1700 WREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset, tmp); 1701 1702 tmp = RREG32(mmDP_SEC_CNTL + dig->afmt->offset); 1703 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); 1704 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ATP_ENABLE, 1); 1705 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_AIP_ENABLE, 1); 1706 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1707 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, tmp); 1708 } else { 1709 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, 0); 1710 } 1711 } 1712 1713 static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder, 1714 struct drm_display_mode *mode) 1715 { 1716 struct drm_device *dev = encoder->dev; 1717 struct amdgpu_device *adev = drm_to_adev(dev); 1718 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1719 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1720 struct drm_connector *connector; 1721 struct drm_connector_list_iter iter; 1722 struct amdgpu_connector *amdgpu_connector = NULL; 1723 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 1724 int bpc = 8; 1725 1726 if (!dig || !dig->afmt) 1727 return; 1728 1729 drm_connector_list_iter_begin(dev, &iter); 1730 drm_for_each_connector_iter(connector, &iter) { 1731 if (connector->encoder == encoder) { 1732 amdgpu_connector = to_amdgpu_connector(connector); 1733 break; 1734 } 1735 } 1736 drm_connector_list_iter_end(&iter); 1737 1738 if (!amdgpu_connector) { 1739 DRM_ERROR("Couldn't find encoder's connector\n"); 1740 return; 1741 } 1742 1743 if (!dig->afmt->enabled) 1744 return; 1745 1746 dig->afmt->pin = dce_v6_0_audio_get_pin(adev); 1747 if (!dig->afmt->pin) 1748 return; 1749 1750 if (encoder->crtc) { 1751 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1752 bpc = amdgpu_crtc->bpc; 1753 } 1754 1755 /* disable audio before setting up hw */ 1756 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); 1757 1758 dce_v6_0_audio_set_mute(encoder, true); 1759 dce_v6_0_audio_write_speaker_allocation(encoder); 1760 dce_v6_0_audio_write_sad_regs(encoder); 1761 dce_v6_0_audio_write_latency_fields(encoder, mode); 1762 if (em == ATOM_ENCODER_MODE_HDMI) { 1763 dce_v6_0_audio_set_dto(encoder, mode->clock); 1764 dce_v6_0_audio_set_vbi_packet(encoder); 1765 dce_v6_0_audio_set_acr(encoder, mode->clock, bpc); 1766 } else if (ENCODER_MODE_IS_DP(em)) { 1767 dce_v6_0_audio_set_dto(encoder, adev->clock.default_dispclk * 10); 1768 } 1769 dce_v6_0_audio_set_packet(encoder); 1770 dce_v6_0_audio_select_pin(encoder); 1771 dce_v6_0_audio_set_avi_infoframe(encoder, mode); 1772 dce_v6_0_audio_set_mute(encoder, false); 1773 if (em == ATOM_ENCODER_MODE_HDMI) { 1774 dce_v6_0_audio_hdmi_enable(encoder, 1); 1775 } else if (ENCODER_MODE_IS_DP(em)) { 1776 dce_v6_0_audio_dp_enable(encoder, 1); 1777 } 1778 1779 /* enable audio after setting up hw */ 1780 dce_v6_0_audio_enable(adev, dig->afmt->pin, true); 1781 } 1782 1783 static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1784 { 1785 struct drm_device *dev = encoder->dev; 1786 struct amdgpu_device *adev = drm_to_adev(dev); 1787 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1788 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1789 1790 if (!dig || !dig->afmt) 1791 return; 1792 1793 /* Silent, r600_hdmi_enable will raise WARN for us */ 1794 if (enable && dig->afmt->enabled) 1795 return; 1796 1797 if (!enable && !dig->afmt->enabled) 1798 return; 1799 1800 if (!enable && dig->afmt->pin) { 1801 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); 1802 dig->afmt->pin = NULL; 1803 } 1804 1805 dig->afmt->enabled = enable; 1806 1807 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1808 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1809 } 1810 1811 static int dce_v6_0_afmt_init(struct amdgpu_device *adev) 1812 { 1813 int i, j; 1814 1815 for (i = 0; i < adev->mode_info.num_dig; i++) 1816 adev->mode_info.afmt[i] = NULL; 1817 1818 /* DCE6 has audio blocks tied to DIG encoders */ 1819 for (i = 0; i < adev->mode_info.num_dig; i++) { 1820 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1821 if (adev->mode_info.afmt[i]) { 1822 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1823 adev->mode_info.afmt[i]->id = i; 1824 } else { 1825 for (j = 0; j < i; j++) { 1826 kfree(adev->mode_info.afmt[j]); 1827 adev->mode_info.afmt[j] = NULL; 1828 } 1829 DRM_ERROR("Out of memory allocating afmt table\n"); 1830 return -ENOMEM; 1831 } 1832 } 1833 return 0; 1834 } 1835 1836 static void dce_v6_0_afmt_fini(struct amdgpu_device *adev) 1837 { 1838 int i; 1839 1840 for (i = 0; i < adev->mode_info.num_dig; i++) { 1841 kfree(adev->mode_info.afmt[i]); 1842 adev->mode_info.afmt[i] = NULL; 1843 } 1844 } 1845 1846 static const u32 vga_control_regs[6] = 1847 { 1848 mmD1VGA_CONTROL, 1849 mmD2VGA_CONTROL, 1850 mmD3VGA_CONTROL, 1851 mmD4VGA_CONTROL, 1852 mmD5VGA_CONTROL, 1853 mmD6VGA_CONTROL, 1854 }; 1855 1856 static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable) 1857 { 1858 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1859 struct drm_device *dev = crtc->dev; 1860 struct amdgpu_device *adev = drm_to_adev(dev); 1861 u32 vga_control; 1862 1863 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 1864 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0)); 1865 } 1866 1867 static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable) 1868 { 1869 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1870 struct drm_device *dev = crtc->dev; 1871 struct amdgpu_device *adev = drm_to_adev(dev); 1872 1873 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); 1874 } 1875 1876 static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, 1877 struct drm_framebuffer *fb, 1878 int x, int y, int atomic) 1879 { 1880 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1881 struct drm_device *dev = crtc->dev; 1882 struct amdgpu_device *adev = drm_to_adev(dev); 1883 struct drm_framebuffer *target_fb; 1884 struct drm_gem_object *obj; 1885 struct amdgpu_bo *abo; 1886 uint64_t fb_location, tiling_flags; 1887 uint32_t fb_format, fb_pitch_pixels, pipe_config; 1888 u32 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_NONE); 1889 u32 viewport_w, viewport_h; 1890 int r; 1891 bool bypass_lut = false; 1892 1893 /* no fb bound */ 1894 if (!atomic && !crtc->primary->fb) { 1895 DRM_DEBUG_KMS("No FB bound\n"); 1896 return 0; 1897 } 1898 1899 if (atomic) 1900 target_fb = fb; 1901 else 1902 target_fb = crtc->primary->fb; 1903 1904 /* If atomic, assume fb object is pinned & idle & fenced and 1905 * just update base pointers 1906 */ 1907 obj = target_fb->obj[0]; 1908 abo = gem_to_amdgpu_bo(obj); 1909 r = amdgpu_bo_reserve(abo, false); 1910 if (unlikely(r != 0)) 1911 return r; 1912 1913 if (!atomic) { 1914 abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 1915 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); 1916 if (unlikely(r != 0)) { 1917 amdgpu_bo_unreserve(abo); 1918 return -EINVAL; 1919 } 1920 } 1921 fb_location = amdgpu_bo_gpu_offset(abo); 1922 1923 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1924 amdgpu_bo_unreserve(abo); 1925 1926 switch (target_fb->format->format) { 1927 case DRM_FORMAT_C8: 1928 fb_format = (GRPH_DEPTH(GRPH_DEPTH_8BPP) | 1929 GRPH_FORMAT(GRPH_FORMAT_INDEXED)); 1930 break; 1931 case DRM_FORMAT_XRGB4444: 1932 case DRM_FORMAT_ARGB4444: 1933 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 1934 GRPH_FORMAT(GRPH_FORMAT_ARGB4444)); 1935 #ifdef __BIG_ENDIAN 1936 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 1937 #endif 1938 break; 1939 case DRM_FORMAT_XRGB1555: 1940 case DRM_FORMAT_ARGB1555: 1941 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 1942 GRPH_FORMAT(GRPH_FORMAT_ARGB1555)); 1943 #ifdef __BIG_ENDIAN 1944 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 1945 #endif 1946 break; 1947 case DRM_FORMAT_BGRX5551: 1948 case DRM_FORMAT_BGRA5551: 1949 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 1950 GRPH_FORMAT(GRPH_FORMAT_BGRA5551)); 1951 #ifdef __BIG_ENDIAN 1952 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 1953 #endif 1954 break; 1955 case DRM_FORMAT_RGB565: 1956 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 1957 GRPH_FORMAT(GRPH_FORMAT_ARGB565)); 1958 #ifdef __BIG_ENDIAN 1959 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 1960 #endif 1961 break; 1962 case DRM_FORMAT_XRGB8888: 1963 case DRM_FORMAT_ARGB8888: 1964 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 1965 GRPH_FORMAT(GRPH_FORMAT_ARGB8888)); 1966 #ifdef __BIG_ENDIAN 1967 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 1968 #endif 1969 break; 1970 case DRM_FORMAT_XRGB2101010: 1971 case DRM_FORMAT_ARGB2101010: 1972 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 1973 GRPH_FORMAT(GRPH_FORMAT_ARGB2101010)); 1974 #ifdef __BIG_ENDIAN 1975 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 1976 #endif 1977 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1978 bypass_lut = true; 1979 break; 1980 case DRM_FORMAT_BGRX1010102: 1981 case DRM_FORMAT_BGRA1010102: 1982 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 1983 GRPH_FORMAT(GRPH_FORMAT_BGRA1010102)); 1984 #ifdef __BIG_ENDIAN 1985 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 1986 #endif 1987 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1988 bypass_lut = true; 1989 break; 1990 case DRM_FORMAT_XBGR8888: 1991 case DRM_FORMAT_ABGR8888: 1992 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 1993 GRPH_FORMAT(GRPH_FORMAT_ARGB8888)); 1994 fb_swap = (GRPH_RED_CROSSBAR(GRPH_RED_SEL_B) | 1995 GRPH_BLUE_CROSSBAR(GRPH_BLUE_SEL_R)); 1996 #ifdef __BIG_ENDIAN 1997 fb_swap |= GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 1998 #endif 1999 break; 2000 default: 2001 DRM_ERROR("Unsupported screen format %p4cc\n", 2002 &target_fb->format->format); 2003 return -EINVAL; 2004 } 2005 2006 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 2007 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 2008 2009 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2010 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2011 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2012 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2013 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2014 2015 fb_format |= GRPH_NUM_BANKS(num_banks); 2016 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_2D_TILED_THIN1); 2017 fb_format |= GRPH_TILE_SPLIT(tile_split); 2018 fb_format |= GRPH_BANK_WIDTH(bankw); 2019 fb_format |= GRPH_BANK_HEIGHT(bankh); 2020 fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect); 2021 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 2022 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_1D_TILED_THIN1); 2023 } 2024 2025 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2026 fb_format |= GRPH_PIPE_CONFIG(pipe_config); 2027 2028 dce_v6_0_vga_enable(crtc, false); 2029 2030 /* Make sure surface address is updated at vertical blank rather than 2031 * horizontal blank 2032 */ 2033 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); 2034 2035 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2036 upper_32_bits(fb_location)); 2037 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2038 upper_32_bits(fb_location)); 2039 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2040 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2041 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2042 (u32) fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2043 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2044 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2045 2046 /* 2047 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2048 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2049 * retain the full precision throughout the pipeline. 2050 */ 2051 WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, 2052 (bypass_lut ? GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK : 0), 2053 ~GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK); 2054 2055 if (bypass_lut) 2056 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2057 2058 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2059 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2060 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2061 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2062 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2063 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2064 2065 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 2066 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2067 2068 dce_v6_0_grph_enable(crtc, true); 2069 2070 WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2071 target_fb->height); 2072 x &= ~3; 2073 y &= ~1; 2074 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2075 (x << 16) | y); 2076 viewport_w = crtc->mode.hdisplay; 2077 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2078 2079 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2080 (viewport_w << 16) | viewport_h); 2081 2082 /* set pageflip to happen anywhere in vblank interval */ 2083 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); 2084 2085 if (!atomic && fb && fb != crtc->primary->fb) { 2086 abo = gem_to_amdgpu_bo(fb->obj[0]); 2087 r = amdgpu_bo_reserve(abo, true); 2088 if (unlikely(r != 0)) 2089 return r; 2090 amdgpu_bo_unpin(abo); 2091 amdgpu_bo_unreserve(abo); 2092 } 2093 2094 /* Bytes per pixel may have changed */ 2095 dce_v6_0_bandwidth_update(adev); 2096 2097 return 0; 2098 2099 } 2100 2101 static void dce_v6_0_set_interleave(struct drm_crtc *crtc, 2102 struct drm_display_mode *mode) 2103 { 2104 struct drm_device *dev = crtc->dev; 2105 struct amdgpu_device *adev = drm_to_adev(dev); 2106 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2107 2108 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2109 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 2110 INTERLEAVE_EN); 2111 else 2112 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0); 2113 } 2114 2115 static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc) 2116 { 2117 2118 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2119 struct drm_device *dev = crtc->dev; 2120 struct amdgpu_device *adev = drm_to_adev(dev); 2121 u16 *r, *g, *b; 2122 int i; 2123 2124 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2125 2126 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 2127 ((0 << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) | 2128 (0 << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT))); 2129 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, 2130 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK); 2131 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, 2132 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK); 2133 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2134 ((0 << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) | 2135 (0 << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT))); 2136 2137 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2138 2139 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2140 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2141 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2142 2143 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2144 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2145 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2146 2147 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2148 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2149 2150 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2151 r = crtc->gamma_store; 2152 g = r + crtc->gamma_size; 2153 b = g + crtc->gamma_size; 2154 for (i = 0; i < 256; i++) { 2155 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2156 ((*r++ & 0xffc0) << 14) | 2157 ((*g++ & 0xffc0) << 4) | 2158 (*b++ >> 6)); 2159 } 2160 2161 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2162 ((0 << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) | 2163 (0 << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) | 2164 ICON_DEGAMMA_MODE(0) | 2165 (0 << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT))); 2166 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, 2167 ((0 << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) | 2168 (0 << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT))); 2169 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2170 ((0 << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) | 2171 (0 << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT))); 2172 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 2173 ((0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) | 2174 (0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT))); 2175 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2176 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); 2177 2178 2179 } 2180 2181 static int dce_v6_0_pick_dig_encoder(struct drm_encoder *encoder) 2182 { 2183 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2184 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2185 2186 switch (amdgpu_encoder->encoder_id) { 2187 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2188 return dig->linkb ? 1 : 0; 2189 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2190 return dig->linkb ? 3 : 2; 2191 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2192 return dig->linkb ? 5 : 4; 2193 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2194 return 6; 2195 default: 2196 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2197 return 0; 2198 } 2199 } 2200 2201 /** 2202 * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc. 2203 * 2204 * @crtc: drm crtc 2205 * 2206 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2207 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2208 * monitors a dedicated PPLL must be used. If a particular board has 2209 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2210 * as there is no need to program the PLL itself. If we are not able to 2211 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2212 * avoid messing up an existing monitor. 2213 * 2214 * 2215 */ 2216 static u32 dce_v6_0_pick_pll(struct drm_crtc *crtc) 2217 { 2218 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2219 struct drm_device *dev = crtc->dev; 2220 struct amdgpu_device *adev = drm_to_adev(dev); 2221 u32 pll_in_use; 2222 int pll; 2223 2224 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2225 if (adev->clock.dp_extclk) 2226 /* skip PPLL programming if using ext clock */ 2227 return ATOM_PPLL_INVALID; 2228 else 2229 return ATOM_PPLL0; 2230 } else { 2231 /* use the same PPLL for all monitors with the same clock */ 2232 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2233 if (pll != ATOM_PPLL_INVALID) 2234 return pll; 2235 } 2236 2237 /* PPLL1, and PPLL2 */ 2238 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2239 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2240 return ATOM_PPLL2; 2241 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2242 return ATOM_PPLL1; 2243 DRM_ERROR("unable to allocate a PPLL\n"); 2244 return ATOM_PPLL_INVALID; 2245 } 2246 2247 static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2248 { 2249 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2250 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2251 uint32_t cur_lock; 2252 2253 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2254 if (lock) 2255 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 2256 else 2257 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 2258 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2259 } 2260 2261 static void dce_v6_0_hide_cursor(struct drm_crtc *crtc) 2262 { 2263 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2264 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2265 2266 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 2267 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 2268 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 2269 2270 2271 } 2272 2273 static void dce_v6_0_show_cursor(struct drm_crtc *crtc) 2274 { 2275 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2276 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2277 2278 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2279 upper_32_bits(amdgpu_crtc->cursor_addr)); 2280 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2281 lower_32_bits(amdgpu_crtc->cursor_addr)); 2282 2283 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 2284 CUR_CONTROL__CURSOR_EN_MASK | 2285 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 2286 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 2287 2288 } 2289 2290 static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc, 2291 int x, int y) 2292 { 2293 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2294 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2295 int xorigin = 0, yorigin = 0; 2296 2297 int w = amdgpu_crtc->cursor_width; 2298 2299 amdgpu_crtc->cursor_x = x; 2300 amdgpu_crtc->cursor_y = y; 2301 2302 /* avivo cursor are offset into the total surface */ 2303 x += crtc->x; 2304 y += crtc->y; 2305 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2306 2307 if (x < 0) { 2308 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2309 x = 0; 2310 } 2311 if (y < 0) { 2312 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2313 y = 0; 2314 } 2315 2316 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2317 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2318 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2319 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2320 2321 return 0; 2322 } 2323 2324 static int dce_v6_0_crtc_cursor_move(struct drm_crtc *crtc, 2325 int x, int y) 2326 { 2327 int ret; 2328 2329 dce_v6_0_lock_cursor(crtc, true); 2330 ret = dce_v6_0_cursor_move_locked(crtc, x, y); 2331 dce_v6_0_lock_cursor(crtc, false); 2332 2333 return ret; 2334 } 2335 2336 static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, 2337 struct drm_file *file_priv, 2338 uint32_t handle, 2339 uint32_t width, 2340 uint32_t height, 2341 int32_t hot_x, 2342 int32_t hot_y) 2343 { 2344 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2345 struct drm_gem_object *obj; 2346 struct amdgpu_bo *aobj; 2347 int ret; 2348 2349 if (!handle) { 2350 /* turn off cursor */ 2351 dce_v6_0_hide_cursor(crtc); 2352 obj = NULL; 2353 goto unpin; 2354 } 2355 2356 if ((width > amdgpu_crtc->max_cursor_width) || 2357 (height > amdgpu_crtc->max_cursor_height)) { 2358 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2359 return -EINVAL; 2360 } 2361 2362 obj = drm_gem_object_lookup(file_priv, handle); 2363 if (!obj) { 2364 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2365 return -ENOENT; 2366 } 2367 2368 aobj = gem_to_amdgpu_bo(obj); 2369 ret = amdgpu_bo_reserve(aobj, false); 2370 if (ret != 0) { 2371 drm_gem_object_put(obj); 2372 return ret; 2373 } 2374 2375 aobj->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 2376 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); 2377 amdgpu_bo_unreserve(aobj); 2378 if (ret) { 2379 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2380 drm_gem_object_put(obj); 2381 return ret; 2382 } 2383 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); 2384 2385 dce_v6_0_lock_cursor(crtc, true); 2386 2387 if (width != amdgpu_crtc->cursor_width || 2388 height != amdgpu_crtc->cursor_height || 2389 hot_x != amdgpu_crtc->cursor_hot_x || 2390 hot_y != amdgpu_crtc->cursor_hot_y) { 2391 int x, y; 2392 2393 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2394 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2395 2396 dce_v6_0_cursor_move_locked(crtc, x, y); 2397 2398 amdgpu_crtc->cursor_width = width; 2399 amdgpu_crtc->cursor_height = height; 2400 amdgpu_crtc->cursor_hot_x = hot_x; 2401 amdgpu_crtc->cursor_hot_y = hot_y; 2402 } 2403 2404 dce_v6_0_show_cursor(crtc); 2405 dce_v6_0_lock_cursor(crtc, false); 2406 2407 unpin: 2408 if (amdgpu_crtc->cursor_bo) { 2409 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2410 ret = amdgpu_bo_reserve(aobj, true); 2411 if (likely(ret == 0)) { 2412 amdgpu_bo_unpin(aobj); 2413 amdgpu_bo_unreserve(aobj); 2414 } 2415 drm_gem_object_put(amdgpu_crtc->cursor_bo); 2416 } 2417 2418 amdgpu_crtc->cursor_bo = obj; 2419 return 0; 2420 } 2421 2422 static void dce_v6_0_cursor_reset(struct drm_crtc *crtc) 2423 { 2424 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2425 2426 if (amdgpu_crtc->cursor_bo) { 2427 dce_v6_0_lock_cursor(crtc, true); 2428 2429 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2430 amdgpu_crtc->cursor_y); 2431 2432 dce_v6_0_show_cursor(crtc); 2433 dce_v6_0_lock_cursor(crtc, false); 2434 } 2435 } 2436 2437 static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2438 u16 *blue, uint32_t size, 2439 struct drm_modeset_acquire_ctx *ctx) 2440 { 2441 dce_v6_0_crtc_load_lut(crtc); 2442 2443 return 0; 2444 } 2445 2446 static void dce_v6_0_crtc_destroy(struct drm_crtc *crtc) 2447 { 2448 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2449 2450 drm_crtc_cleanup(crtc); 2451 kfree(amdgpu_crtc); 2452 } 2453 2454 static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = { 2455 .cursor_set2 = dce_v6_0_crtc_cursor_set2, 2456 .cursor_move = dce_v6_0_crtc_cursor_move, 2457 .gamma_set = dce_v6_0_crtc_gamma_set, 2458 .set_config = amdgpu_display_crtc_set_config, 2459 .destroy = dce_v6_0_crtc_destroy, 2460 .page_flip_target = amdgpu_display_crtc_page_flip_target, 2461 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 2462 .enable_vblank = amdgpu_enable_vblank_kms, 2463 .disable_vblank = amdgpu_disable_vblank_kms, 2464 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 2465 }; 2466 2467 static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2468 { 2469 struct drm_device *dev = crtc->dev; 2470 struct amdgpu_device *adev = drm_to_adev(dev); 2471 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2472 unsigned type; 2473 2474 switch (mode) { 2475 case DRM_MODE_DPMS_ON: 2476 amdgpu_crtc->enabled = true; 2477 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2478 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2479 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2480 type = amdgpu_display_crtc_idx_to_irq_type(adev, 2481 amdgpu_crtc->crtc_id); 2482 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2483 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2484 drm_crtc_vblank_on(crtc); 2485 dce_v6_0_crtc_load_lut(crtc); 2486 break; 2487 case DRM_MODE_DPMS_STANDBY: 2488 case DRM_MODE_DPMS_SUSPEND: 2489 case DRM_MODE_DPMS_OFF: 2490 drm_crtc_vblank_off(crtc); 2491 if (amdgpu_crtc->enabled) 2492 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2493 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2494 amdgpu_crtc->enabled = false; 2495 break; 2496 } 2497 /* adjust pm to dpms */ 2498 amdgpu_dpm_compute_clocks(adev); 2499 } 2500 2501 static void dce_v6_0_crtc_prepare(struct drm_crtc *crtc) 2502 { 2503 /* disable crtc pair power gating before programming */ 2504 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2505 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2506 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2507 } 2508 2509 static void dce_v6_0_crtc_commit(struct drm_crtc *crtc) 2510 { 2511 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2512 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2513 } 2514 2515 static void dce_v6_0_crtc_disable(struct drm_crtc *crtc) 2516 { 2517 2518 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2519 struct drm_device *dev = crtc->dev; 2520 struct amdgpu_device *adev = drm_to_adev(dev); 2521 struct amdgpu_atom_ss ss; 2522 int i; 2523 2524 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2525 if (crtc->primary->fb) { 2526 int r; 2527 struct amdgpu_bo *abo; 2528 2529 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); 2530 r = amdgpu_bo_reserve(abo, true); 2531 if (unlikely(r)) 2532 DRM_ERROR("failed to reserve abo before unpin\n"); 2533 else { 2534 amdgpu_bo_unpin(abo); 2535 amdgpu_bo_unreserve(abo); 2536 } 2537 } 2538 /* disable the GRPH */ 2539 dce_v6_0_grph_enable(crtc, false); 2540 2541 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2542 2543 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2544 if (adev->mode_info.crtcs[i] && 2545 adev->mode_info.crtcs[i]->enabled && 2546 i != amdgpu_crtc->crtc_id && 2547 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2548 /* one other crtc is using this pll don't turn 2549 * off the pll 2550 */ 2551 goto done; 2552 } 2553 } 2554 2555 switch (amdgpu_crtc->pll_id) { 2556 case ATOM_PPLL1: 2557 case ATOM_PPLL2: 2558 /* disable the ppll */ 2559 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2560 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2561 break; 2562 default: 2563 break; 2564 } 2565 done: 2566 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2567 amdgpu_crtc->adjusted_clock = 0; 2568 amdgpu_crtc->encoder = NULL; 2569 amdgpu_crtc->connector = NULL; 2570 } 2571 2572 static int dce_v6_0_crtc_mode_set(struct drm_crtc *crtc, 2573 struct drm_display_mode *mode, 2574 struct drm_display_mode *adjusted_mode, 2575 int x, int y, struct drm_framebuffer *old_fb) 2576 { 2577 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2578 2579 if (!amdgpu_crtc->adjusted_clock) 2580 return -EINVAL; 2581 2582 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2583 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2584 dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2585 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2586 amdgpu_atombios_crtc_scaler_setup(crtc); 2587 dce_v6_0_cursor_reset(crtc); 2588 /* update the hw version fpr dpm */ 2589 amdgpu_crtc->hw_mode = *adjusted_mode; 2590 2591 return 0; 2592 } 2593 2594 static bool dce_v6_0_crtc_mode_fixup(struct drm_crtc *crtc, 2595 const struct drm_display_mode *mode, 2596 struct drm_display_mode *adjusted_mode) 2597 { 2598 2599 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2600 struct drm_device *dev = crtc->dev; 2601 struct drm_encoder *encoder; 2602 2603 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2604 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2605 if (encoder->crtc == crtc) { 2606 amdgpu_crtc->encoder = encoder; 2607 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2608 break; 2609 } 2610 } 2611 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2612 amdgpu_crtc->encoder = NULL; 2613 amdgpu_crtc->connector = NULL; 2614 return false; 2615 } 2616 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2617 return false; 2618 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2619 return false; 2620 /* pick pll */ 2621 amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc); 2622 /* if we can't get a PPLL for a non-DP encoder, fail */ 2623 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2624 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2625 return false; 2626 2627 return true; 2628 } 2629 2630 static int dce_v6_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2631 struct drm_framebuffer *old_fb) 2632 { 2633 return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2634 } 2635 2636 static int dce_v6_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2637 struct drm_framebuffer *fb, 2638 int x, int y, enum mode_set_atomic state) 2639 { 2640 return dce_v6_0_crtc_do_set_base(crtc, fb, x, y, 1); 2641 } 2642 2643 static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = { 2644 .dpms = dce_v6_0_crtc_dpms, 2645 .mode_fixup = dce_v6_0_crtc_mode_fixup, 2646 .mode_set = dce_v6_0_crtc_mode_set, 2647 .mode_set_base = dce_v6_0_crtc_set_base, 2648 .mode_set_base_atomic = dce_v6_0_crtc_set_base_atomic, 2649 .prepare = dce_v6_0_crtc_prepare, 2650 .commit = dce_v6_0_crtc_commit, 2651 .disable = dce_v6_0_crtc_disable, 2652 .get_scanout_position = amdgpu_crtc_get_scanout_position, 2653 }; 2654 2655 static void dce_v6_0_panic_flush(struct drm_plane *plane) 2656 { 2657 struct drm_framebuffer *fb; 2658 struct amdgpu_crtc *amdgpu_crtc; 2659 struct amdgpu_device *adev; 2660 uint32_t fb_format; 2661 2662 if (!plane->fb) 2663 return; 2664 2665 fb = plane->fb; 2666 amdgpu_crtc = to_amdgpu_crtc(plane->crtc); 2667 adev = drm_to_adev(fb->dev); 2668 2669 /* Disable DC tiling */ 2670 fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset); 2671 fb_format &= ~GRPH_ARRAY_MODE(0x7); 2672 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2673 2674 } 2675 2676 static const struct drm_plane_helper_funcs dce_v6_0_drm_primary_plane_helper_funcs = { 2677 .get_scanout_buffer = amdgpu_display_get_scanout_buffer, 2678 .panic_flush = dce_v6_0_panic_flush, 2679 }; 2680 2681 static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index) 2682 { 2683 struct amdgpu_crtc *amdgpu_crtc; 2684 2685 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2686 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2687 if (amdgpu_crtc == NULL) 2688 return -ENOMEM; 2689 2690 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v6_0_crtc_funcs); 2691 2692 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2693 amdgpu_crtc->crtc_id = index; 2694 adev->mode_info.crtcs[index] = amdgpu_crtc; 2695 2696 amdgpu_crtc->max_cursor_width = CURSOR_WIDTH; 2697 amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT; 2698 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2699 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2700 2701 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; 2702 2703 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2704 amdgpu_crtc->adjusted_clock = 0; 2705 amdgpu_crtc->encoder = NULL; 2706 amdgpu_crtc->connector = NULL; 2707 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs); 2708 drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v6_0_drm_primary_plane_helper_funcs); 2709 2710 return 0; 2711 } 2712 2713 static int dce_v6_0_early_init(struct amdgpu_ip_block *ip_block) 2714 { 2715 struct amdgpu_device *adev = ip_block->adev; 2716 2717 adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg; 2718 adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg; 2719 2720 dce_v6_0_set_display_funcs(adev); 2721 2722 adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev); 2723 2724 switch (adev->asic_type) { 2725 case CHIP_TAHITI: 2726 case CHIP_PITCAIRN: 2727 case CHIP_VERDE: 2728 adev->mode_info.num_hpd = 6; 2729 adev->mode_info.num_dig = 6; 2730 break; 2731 case CHIP_OLAND: 2732 adev->mode_info.num_hpd = 2; 2733 adev->mode_info.num_dig = 2; 2734 break; 2735 default: 2736 return -EINVAL; 2737 } 2738 2739 dce_v6_0_set_irq_funcs(adev); 2740 2741 return 0; 2742 } 2743 2744 static int dce_v6_0_sw_init(struct amdgpu_ip_block *ip_block) 2745 { 2746 int r, i; 2747 bool ret; 2748 struct amdgpu_device *adev = ip_block->adev; 2749 2750 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2751 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); 2752 if (r) 2753 return r; 2754 } 2755 2756 for (i = 8; i < 20; i += 2) { 2757 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq); 2758 if (r) 2759 return r; 2760 } 2761 2762 /* HPD hotplug */ 2763 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq); 2764 if (r) 2765 return r; 2766 2767 adev->mode_info.mode_config_initialized = true; 2768 2769 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs; 2770 adev_to_drm(adev)->mode_config.async_page_flip = true; 2771 adev_to_drm(adev)->mode_config.max_width = 16384; 2772 adev_to_drm(adev)->mode_config.max_height = 16384; 2773 adev_to_drm(adev)->mode_config.preferred_depth = 24; 2774 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 2775 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; 2776 2777 r = amdgpu_display_modeset_create_props(adev); 2778 if (r) 2779 return r; 2780 2781 adev_to_drm(adev)->mode_config.max_width = 16384; 2782 adev_to_drm(adev)->mode_config.max_height = 16384; 2783 2784 /* allocate crtcs */ 2785 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2786 r = dce_v6_0_crtc_init(adev, i); 2787 if (r) 2788 return r; 2789 } 2790 2791 ret = amdgpu_atombios_get_connector_info_from_object_table(adev); 2792 if (ret) 2793 amdgpu_display_print_display_setup(adev_to_drm(adev)); 2794 else 2795 return -EINVAL; 2796 2797 /* setup afmt */ 2798 r = dce_v6_0_afmt_init(adev); 2799 if (r) 2800 return r; 2801 2802 r = dce_v6_0_audio_init(adev); 2803 if (r) 2804 return r; 2805 2806 /* Disable vblank IRQs aggressively for power-saving */ 2807 /* XXX: can this be enabled for DC? */ 2808 adev_to_drm(adev)->vblank_disable_immediate = true; 2809 2810 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc); 2811 if (r) 2812 return r; 2813 2814 /* Pre-DCE11 */ 2815 INIT_DELAYED_WORK(&adev->hotplug_work, 2816 amdgpu_display_hotplug_work_func); 2817 2818 drm_kms_helper_poll_init(adev_to_drm(adev)); 2819 2820 return r; 2821 } 2822 2823 static int dce_v6_0_sw_fini(struct amdgpu_ip_block *ip_block) 2824 { 2825 struct amdgpu_device *adev = ip_block->adev; 2826 2827 drm_edid_free(adev->mode_info.bios_hardcoded_edid); 2828 2829 drm_kms_helper_poll_fini(adev_to_drm(adev)); 2830 2831 dce_v6_0_audio_fini(adev); 2832 dce_v6_0_afmt_fini(adev); 2833 2834 drm_mode_config_cleanup(adev_to_drm(adev)); 2835 adev->mode_info.mode_config_initialized = false; 2836 2837 return 0; 2838 } 2839 2840 static int dce_v6_0_hw_init(struct amdgpu_ip_block *ip_block) 2841 { 2842 int i; 2843 struct amdgpu_device *adev = ip_block->adev; 2844 2845 /* disable vga render */ 2846 dce_v6_0_set_vga_render_state(adev, false); 2847 /* init dig PHYs, disp eng pll */ 2848 amdgpu_atombios_encoder_init_dig(adev); 2849 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 2850 2851 /* initialize hpd */ 2852 dce_v6_0_hpd_init(adev); 2853 2854 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2855 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2856 } 2857 2858 dce_v6_0_pageflip_interrupt_init(adev); 2859 2860 return 0; 2861 } 2862 2863 static int dce_v6_0_hw_fini(struct amdgpu_ip_block *ip_block) 2864 { 2865 int i; 2866 struct amdgpu_device *adev = ip_block->adev; 2867 2868 dce_v6_0_hpd_fini(adev); 2869 2870 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2871 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2872 } 2873 2874 dce_v6_0_pageflip_interrupt_fini(adev); 2875 2876 flush_delayed_work(&adev->hotplug_work); 2877 2878 return 0; 2879 } 2880 2881 static int dce_v6_0_suspend(struct amdgpu_ip_block *ip_block) 2882 { 2883 struct amdgpu_device *adev = ip_block->adev; 2884 int r; 2885 2886 r = amdgpu_display_suspend_helper(adev); 2887 if (r) 2888 return r; 2889 adev->mode_info.bl_level = 2890 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); 2891 2892 return dce_v6_0_hw_fini(ip_block); 2893 } 2894 2895 static int dce_v6_0_resume(struct amdgpu_ip_block *ip_block) 2896 { 2897 struct amdgpu_device *adev = ip_block->adev; 2898 int ret; 2899 2900 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, 2901 adev->mode_info.bl_level); 2902 2903 ret = dce_v6_0_hw_init(ip_block); 2904 2905 /* turn on the BL */ 2906 if (adev->mode_info.bl_encoder) { 2907 u8 bl_level = amdgpu_display_backlight_get_level(adev, 2908 adev->mode_info.bl_encoder); 2909 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 2910 bl_level); 2911 } 2912 if (ret) 2913 return ret; 2914 2915 return amdgpu_display_resume_helper(adev); 2916 } 2917 2918 static bool dce_v6_0_is_idle(struct amdgpu_ip_block *ip_block) 2919 { 2920 return true; 2921 } 2922 2923 static int dce_v6_0_soft_reset(struct amdgpu_ip_block *ip_block) 2924 { 2925 u32 srbm_soft_reset = 0, tmp; 2926 struct amdgpu_device *adev = ip_block->adev; 2927 2928 if (dce_v6_0_is_display_hung(adev)) 2929 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 2930 2931 if (srbm_soft_reset) { 2932 tmp = RREG32(mmSRBM_SOFT_RESET); 2933 tmp |= srbm_soft_reset; 2934 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 2935 WREG32(mmSRBM_SOFT_RESET, tmp); 2936 tmp = RREG32(mmSRBM_SOFT_RESET); 2937 2938 udelay(50); 2939 2940 tmp &= ~srbm_soft_reset; 2941 WREG32(mmSRBM_SOFT_RESET, tmp); 2942 tmp = RREG32(mmSRBM_SOFT_RESET); 2943 2944 /* Wait a little for things to settle down */ 2945 udelay(50); 2946 } 2947 return 0; 2948 } 2949 2950 static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 2951 int crtc, 2952 enum amdgpu_interrupt_state state) 2953 { 2954 u32 reg_block, interrupt_mask; 2955 2956 if (crtc >= adev->mode_info.num_crtc) { 2957 DRM_DEBUG("invalid crtc %d\n", crtc); 2958 return; 2959 } 2960 2961 switch (crtc) { 2962 case 0: 2963 reg_block = SI_CRTC0_REGISTER_OFFSET; 2964 break; 2965 case 1: 2966 reg_block = SI_CRTC1_REGISTER_OFFSET; 2967 break; 2968 case 2: 2969 reg_block = SI_CRTC2_REGISTER_OFFSET; 2970 break; 2971 case 3: 2972 reg_block = SI_CRTC3_REGISTER_OFFSET; 2973 break; 2974 case 4: 2975 reg_block = SI_CRTC4_REGISTER_OFFSET; 2976 break; 2977 case 5: 2978 reg_block = SI_CRTC5_REGISTER_OFFSET; 2979 break; 2980 default: 2981 DRM_DEBUG("invalid crtc %d\n", crtc); 2982 return; 2983 } 2984 2985 switch (state) { 2986 case AMDGPU_IRQ_STATE_DISABLE: 2987 interrupt_mask = RREG32(mmINT_MASK + reg_block); 2988 interrupt_mask &= ~VBLANK_INT_MASK; 2989 WREG32(mmINT_MASK + reg_block, interrupt_mask); 2990 break; 2991 case AMDGPU_IRQ_STATE_ENABLE: 2992 interrupt_mask = RREG32(mmINT_MASK + reg_block); 2993 interrupt_mask |= VBLANK_INT_MASK; 2994 WREG32(mmINT_MASK + reg_block, interrupt_mask); 2995 break; 2996 default: 2997 break; 2998 } 2999 } 3000 3001 static void dce_v6_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 3002 int crtc, 3003 enum amdgpu_interrupt_state state) 3004 { 3005 3006 } 3007 3008 static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev, 3009 struct amdgpu_irq_src *src, 3010 unsigned type, 3011 enum amdgpu_interrupt_state state) 3012 { 3013 u32 dc_hpd_int_cntl; 3014 3015 if (type >= adev->mode_info.num_hpd) { 3016 DRM_DEBUG("invalid hdp %d\n", type); 3017 return 0; 3018 } 3019 3020 switch (state) { 3021 case AMDGPU_IRQ_STATE_DISABLE: 3022 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); 3023 dc_hpd_int_cntl &= ~DC_HPDx_INT_EN; 3024 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 3025 break; 3026 case AMDGPU_IRQ_STATE_ENABLE: 3027 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); 3028 dc_hpd_int_cntl |= DC_HPDx_INT_EN; 3029 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 3030 break; 3031 default: 3032 break; 3033 } 3034 3035 return 0; 3036 } 3037 3038 static int dce_v6_0_set_crtc_interrupt_state(struct amdgpu_device *adev, 3039 struct amdgpu_irq_src *src, 3040 unsigned type, 3041 enum amdgpu_interrupt_state state) 3042 { 3043 switch (type) { 3044 case AMDGPU_CRTC_IRQ_VBLANK1: 3045 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3046 break; 3047 case AMDGPU_CRTC_IRQ_VBLANK2: 3048 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3049 break; 3050 case AMDGPU_CRTC_IRQ_VBLANK3: 3051 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3052 break; 3053 case AMDGPU_CRTC_IRQ_VBLANK4: 3054 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3055 break; 3056 case AMDGPU_CRTC_IRQ_VBLANK5: 3057 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3058 break; 3059 case AMDGPU_CRTC_IRQ_VBLANK6: 3060 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3061 break; 3062 case AMDGPU_CRTC_IRQ_VLINE1: 3063 dce_v6_0_set_crtc_vline_interrupt_state(adev, 0, state); 3064 break; 3065 case AMDGPU_CRTC_IRQ_VLINE2: 3066 dce_v6_0_set_crtc_vline_interrupt_state(adev, 1, state); 3067 break; 3068 case AMDGPU_CRTC_IRQ_VLINE3: 3069 dce_v6_0_set_crtc_vline_interrupt_state(adev, 2, state); 3070 break; 3071 case AMDGPU_CRTC_IRQ_VLINE4: 3072 dce_v6_0_set_crtc_vline_interrupt_state(adev, 3, state); 3073 break; 3074 case AMDGPU_CRTC_IRQ_VLINE5: 3075 dce_v6_0_set_crtc_vline_interrupt_state(adev, 4, state); 3076 break; 3077 case AMDGPU_CRTC_IRQ_VLINE6: 3078 dce_v6_0_set_crtc_vline_interrupt_state(adev, 5, state); 3079 break; 3080 default: 3081 break; 3082 } 3083 return 0; 3084 } 3085 3086 static int dce_v6_0_crtc_irq(struct amdgpu_device *adev, 3087 struct amdgpu_irq_src *source, 3088 struct amdgpu_iv_entry *entry) 3089 { 3090 unsigned crtc = entry->src_id - 1; 3091 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3092 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, 3093 crtc); 3094 3095 switch (entry->src_data[0]) { 3096 case 0: /* vblank */ 3097 if (disp_int & interrupt_status_offsets[crtc].vblank) 3098 WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK); 3099 else 3100 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3101 3102 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3103 drm_handle_vblank(adev_to_drm(adev), crtc); 3104 } 3105 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3106 break; 3107 case 1: /* vline */ 3108 if (disp_int & interrupt_status_offsets[crtc].vline) 3109 WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK); 3110 else 3111 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3112 3113 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3114 break; 3115 default: 3116 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3117 break; 3118 } 3119 3120 return 0; 3121 } 3122 3123 static int dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device *adev, 3124 struct amdgpu_irq_src *src, 3125 unsigned type, 3126 enum amdgpu_interrupt_state state) 3127 { 3128 u32 reg; 3129 3130 if (type >= adev->mode_info.num_crtc) { 3131 DRM_ERROR("invalid pageflip crtc %d\n", type); 3132 return -EINVAL; 3133 } 3134 3135 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3136 if (state == AMDGPU_IRQ_STATE_DISABLE) 3137 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3138 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3139 else 3140 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3141 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3142 3143 return 0; 3144 } 3145 3146 static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev, 3147 struct amdgpu_irq_src *source, 3148 struct amdgpu_iv_entry *entry) 3149 { 3150 unsigned long flags; 3151 unsigned crtc_id; 3152 struct amdgpu_crtc *amdgpu_crtc; 3153 struct amdgpu_flip_work *works; 3154 3155 crtc_id = (entry->src_id - 8) >> 1; 3156 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3157 3158 if (crtc_id >= adev->mode_info.num_crtc) { 3159 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3160 return -EINVAL; 3161 } 3162 3163 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3164 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3165 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3166 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3167 3168 /* IRQ could occur when in initial stage */ 3169 if (amdgpu_crtc == NULL) 3170 return 0; 3171 3172 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 3173 works = amdgpu_crtc->pflip_works; 3174 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 3175 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3176 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3177 amdgpu_crtc->pflip_status, 3178 AMDGPU_FLIP_SUBMITTED); 3179 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3180 return 0; 3181 } 3182 3183 /* page flip completed. clean up */ 3184 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3185 amdgpu_crtc->pflip_works = NULL; 3186 3187 /* wakeup usersapce */ 3188 if (works->event) 3189 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); 3190 3191 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3192 3193 drm_crtc_vblank_put(&amdgpu_crtc->base); 3194 schedule_work(&works->unpin_work); 3195 3196 return 0; 3197 } 3198 3199 static int dce_v6_0_hpd_irq(struct amdgpu_device *adev, 3200 struct amdgpu_irq_src *source, 3201 struct amdgpu_iv_entry *entry) 3202 { 3203 uint32_t disp_int, mask; 3204 unsigned hpd; 3205 3206 if (entry->src_data[0] >= adev->mode_info.num_hpd) { 3207 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3208 return 0; 3209 } 3210 3211 hpd = entry->src_data[0]; 3212 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3213 mask = interrupt_status_offsets[hpd].hpd; 3214 3215 if (disp_int & mask) { 3216 dce_v6_0_hpd_int_ack(adev, hpd); 3217 schedule_delayed_work(&adev->hotplug_work, 0); 3218 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3219 } 3220 3221 return 0; 3222 } 3223 3224 static int dce_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 3225 enum amd_clockgating_state state) 3226 { 3227 return 0; 3228 } 3229 3230 static int dce_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 3231 enum amd_powergating_state state) 3232 { 3233 return 0; 3234 } 3235 3236 static const struct amd_ip_funcs dce_v6_0_ip_funcs = { 3237 .name = "dce_v6_0", 3238 .early_init = dce_v6_0_early_init, 3239 .sw_init = dce_v6_0_sw_init, 3240 .sw_fini = dce_v6_0_sw_fini, 3241 .hw_init = dce_v6_0_hw_init, 3242 .hw_fini = dce_v6_0_hw_fini, 3243 .suspend = dce_v6_0_suspend, 3244 .resume = dce_v6_0_resume, 3245 .is_idle = dce_v6_0_is_idle, 3246 .soft_reset = dce_v6_0_soft_reset, 3247 .set_clockgating_state = dce_v6_0_set_clockgating_state, 3248 .set_powergating_state = dce_v6_0_set_powergating_state, 3249 }; 3250 3251 static void 3252 dce_v6_0_encoder_mode_set(struct drm_encoder *encoder, 3253 struct drm_display_mode *mode, 3254 struct drm_display_mode *adjusted_mode) 3255 { 3256 3257 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3258 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 3259 3260 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3261 3262 /* need to call this here rather than in prepare() since we need some crtc info */ 3263 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3264 3265 /* set scaler clears this on some chips */ 3266 dce_v6_0_set_interleave(encoder->crtc, mode); 3267 3268 if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em)) { 3269 dce_v6_0_afmt_enable(encoder, true); 3270 dce_v6_0_afmt_setmode(encoder, adjusted_mode); 3271 } 3272 } 3273 3274 static void dce_v6_0_encoder_prepare(struct drm_encoder *encoder) 3275 { 3276 3277 struct amdgpu_device *adev = drm_to_adev(encoder->dev); 3278 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3279 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3280 3281 if ((amdgpu_encoder->active_device & 3282 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3283 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3284 ENCODER_OBJECT_ID_NONE)) { 3285 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3286 if (dig) { 3287 dig->dig_encoder = dce_v6_0_pick_dig_encoder(encoder); 3288 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3289 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3290 } 3291 } 3292 3293 amdgpu_atombios_scratch_regs_lock(adev, true); 3294 3295 if (connector) { 3296 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3297 3298 /* select the clock/data port if it uses a router */ 3299 if (amdgpu_connector->router.cd_valid) 3300 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3301 3302 /* turn eDP panel on for mode set */ 3303 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3304 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3305 ATOM_TRANSMITTER_ACTION_POWER_ON); 3306 } 3307 3308 /* this is needed for the pll/ss setup to work correctly in some cases */ 3309 amdgpu_atombios_encoder_set_crtc_source(encoder); 3310 /* set up the FMT blocks */ 3311 dce_v6_0_program_fmt(encoder); 3312 } 3313 3314 static void dce_v6_0_encoder_commit(struct drm_encoder *encoder) 3315 { 3316 3317 struct drm_device *dev = encoder->dev; 3318 struct amdgpu_device *adev = drm_to_adev(dev); 3319 3320 /* need to call this here as we need the crtc set up */ 3321 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3322 amdgpu_atombios_scratch_regs_lock(adev, false); 3323 } 3324 3325 static void dce_v6_0_encoder_disable(struct drm_encoder *encoder) 3326 { 3327 3328 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3329 struct amdgpu_encoder_atom_dig *dig; 3330 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 3331 3332 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3333 3334 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3335 if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em)) 3336 dce_v6_0_afmt_enable(encoder, false); 3337 dig = amdgpu_encoder->enc_priv; 3338 dig->dig_encoder = -1; 3339 } 3340 amdgpu_encoder->active_device = 0; 3341 } 3342 3343 /* these are handled by the primary encoders */ 3344 static void dce_v6_0_ext_prepare(struct drm_encoder *encoder) 3345 { 3346 3347 } 3348 3349 static void dce_v6_0_ext_commit(struct drm_encoder *encoder) 3350 { 3351 3352 } 3353 3354 static void dce_v6_0_ext_mode_set(struct drm_encoder *encoder, 3355 struct drm_display_mode *mode, 3356 struct drm_display_mode *adjusted_mode) 3357 { 3358 3359 } 3360 3361 static void dce_v6_0_ext_disable(struct drm_encoder *encoder) 3362 { 3363 3364 } 3365 3366 static void dce_v6_0_ext_dpms(struct drm_encoder *encoder, int mode) 3367 { 3368 3369 } 3370 3371 static bool dce_v6_0_ext_mode_fixup(struct drm_encoder *encoder, 3372 const struct drm_display_mode *mode, 3373 struct drm_display_mode *adjusted_mode) 3374 { 3375 return true; 3376 } 3377 3378 static const struct drm_encoder_helper_funcs dce_v6_0_ext_helper_funcs = { 3379 .dpms = dce_v6_0_ext_dpms, 3380 .mode_fixup = dce_v6_0_ext_mode_fixup, 3381 .prepare = dce_v6_0_ext_prepare, 3382 .mode_set = dce_v6_0_ext_mode_set, 3383 .commit = dce_v6_0_ext_commit, 3384 .disable = dce_v6_0_ext_disable, 3385 /* no detect for TMDS/LVDS yet */ 3386 }; 3387 3388 static const struct drm_encoder_helper_funcs dce_v6_0_dig_helper_funcs = { 3389 .dpms = amdgpu_atombios_encoder_dpms, 3390 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3391 .prepare = dce_v6_0_encoder_prepare, 3392 .mode_set = dce_v6_0_encoder_mode_set, 3393 .commit = dce_v6_0_encoder_commit, 3394 .disable = dce_v6_0_encoder_disable, 3395 .detect = amdgpu_atombios_encoder_dig_detect, 3396 }; 3397 3398 static const struct drm_encoder_helper_funcs dce_v6_0_dac_helper_funcs = { 3399 .dpms = amdgpu_atombios_encoder_dpms, 3400 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3401 .prepare = dce_v6_0_encoder_prepare, 3402 .mode_set = dce_v6_0_encoder_mode_set, 3403 .commit = dce_v6_0_encoder_commit, 3404 .detect = amdgpu_atombios_encoder_dac_detect, 3405 }; 3406 3407 static void dce_v6_0_encoder_destroy(struct drm_encoder *encoder) 3408 { 3409 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3410 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3411 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3412 kfree(amdgpu_encoder->enc_priv); 3413 drm_encoder_cleanup(encoder); 3414 kfree(amdgpu_encoder); 3415 } 3416 3417 static const struct drm_encoder_funcs dce_v6_0_encoder_funcs = { 3418 .destroy = dce_v6_0_encoder_destroy, 3419 }; 3420 3421 static void dce_v6_0_encoder_add(struct amdgpu_device *adev, 3422 uint32_t encoder_enum, 3423 uint32_t supported_device, 3424 u16 caps) 3425 { 3426 struct drm_device *dev = adev_to_drm(adev); 3427 struct drm_encoder *encoder; 3428 struct amdgpu_encoder *amdgpu_encoder; 3429 3430 /* see if we already added it */ 3431 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3432 amdgpu_encoder = to_amdgpu_encoder(encoder); 3433 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3434 amdgpu_encoder->devices |= supported_device; 3435 return; 3436 } 3437 } 3438 3439 /* add a new one */ 3440 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3441 if (!amdgpu_encoder) 3442 return; 3443 3444 encoder = &amdgpu_encoder->base; 3445 switch (adev->mode_info.num_crtc) { 3446 case 1: 3447 encoder->possible_crtcs = 0x1; 3448 break; 3449 case 2: 3450 default: 3451 encoder->possible_crtcs = 0x3; 3452 break; 3453 case 4: 3454 encoder->possible_crtcs = 0xf; 3455 break; 3456 case 6: 3457 encoder->possible_crtcs = 0x3f; 3458 break; 3459 } 3460 3461 amdgpu_encoder->enc_priv = NULL; 3462 amdgpu_encoder->encoder_enum = encoder_enum; 3463 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3464 amdgpu_encoder->devices = supported_device; 3465 amdgpu_encoder->rmx_type = RMX_OFF; 3466 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3467 amdgpu_encoder->is_ext_encoder = false; 3468 amdgpu_encoder->caps = caps; 3469 3470 switch (amdgpu_encoder->encoder_id) { 3471 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3472 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3473 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3474 DRM_MODE_ENCODER_DAC, NULL); 3475 drm_encoder_helper_add(encoder, &dce_v6_0_dac_helper_funcs); 3476 break; 3477 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3478 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3479 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3480 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3481 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3482 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3483 amdgpu_encoder->rmx_type = RMX_FULL; 3484 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3485 DRM_MODE_ENCODER_LVDS, NULL); 3486 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3487 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3488 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3489 DRM_MODE_ENCODER_DAC, NULL); 3490 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3491 } else { 3492 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3493 DRM_MODE_ENCODER_TMDS, NULL); 3494 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3495 } 3496 drm_encoder_helper_add(encoder, &dce_v6_0_dig_helper_funcs); 3497 break; 3498 case ENCODER_OBJECT_ID_SI170B: 3499 case ENCODER_OBJECT_ID_CH7303: 3500 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3501 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3502 case ENCODER_OBJECT_ID_TITFP513: 3503 case ENCODER_OBJECT_ID_VT1623: 3504 case ENCODER_OBJECT_ID_HDMI_SI1930: 3505 case ENCODER_OBJECT_ID_TRAVIS: 3506 case ENCODER_OBJECT_ID_NUTMEG: 3507 /* these are handled by the primary encoders */ 3508 amdgpu_encoder->is_ext_encoder = true; 3509 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3510 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3511 DRM_MODE_ENCODER_LVDS, NULL); 3512 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3513 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3514 DRM_MODE_ENCODER_DAC, NULL); 3515 else 3516 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3517 DRM_MODE_ENCODER_TMDS, NULL); 3518 drm_encoder_helper_add(encoder, &dce_v6_0_ext_helper_funcs); 3519 break; 3520 } 3521 } 3522 3523 static const struct amdgpu_display_funcs dce_v6_0_display_funcs = { 3524 .bandwidth_update = &dce_v6_0_bandwidth_update, 3525 .vblank_get_counter = &dce_v6_0_vblank_get_counter, 3526 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3527 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3528 .hpd_sense = &dce_v6_0_hpd_sense, 3529 .hpd_set_polarity = &dce_v6_0_hpd_set_polarity, 3530 .hpd_get_gpio_reg = &dce_v6_0_hpd_get_gpio_reg, 3531 .page_flip = &dce_v6_0_page_flip, 3532 .page_flip_get_scanoutpos = &dce_v6_0_crtc_get_scanoutpos, 3533 .add_encoder = &dce_v6_0_encoder_add, 3534 .add_connector = &amdgpu_connector_add, 3535 }; 3536 3537 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev) 3538 { 3539 adev->mode_info.funcs = &dce_v6_0_display_funcs; 3540 } 3541 3542 static const struct amdgpu_irq_src_funcs dce_v6_0_crtc_irq_funcs = { 3543 .set = dce_v6_0_set_crtc_interrupt_state, 3544 .process = dce_v6_0_crtc_irq, 3545 }; 3546 3547 static const struct amdgpu_irq_src_funcs dce_v6_0_pageflip_irq_funcs = { 3548 .set = dce_v6_0_set_pageflip_interrupt_state, 3549 .process = dce_v6_0_pageflip_irq, 3550 }; 3551 3552 static const struct amdgpu_irq_src_funcs dce_v6_0_hpd_irq_funcs = { 3553 .set = dce_v6_0_set_hpd_interrupt_state, 3554 .process = dce_v6_0_hpd_irq, 3555 }; 3556 3557 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev) 3558 { 3559 if (adev->mode_info.num_crtc > 0) 3560 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; 3561 else 3562 adev->crtc_irq.num_types = 0; 3563 adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs; 3564 3565 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; 3566 adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs; 3567 3568 adev->hpd_irq.num_types = adev->mode_info.num_hpd; 3569 adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs; 3570 } 3571 3572 const struct amdgpu_ip_block_version dce_v6_0_ip_block = 3573 { 3574 .type = AMD_IP_BLOCK_TYPE_DCE, 3575 .major = 6, 3576 .minor = 0, 3577 .rev = 0, 3578 .funcs = &dce_v6_0_ip_funcs, 3579 }; 3580 3581 const struct amdgpu_ip_block_version dce_v6_4_ip_block = 3582 { 3583 .type = AMD_IP_BLOCK_TYPE_DCE, 3584 .major = 6, 3585 .minor = 4, 3586 .rev = 0, 3587 .funcs = &dce_v6_0_ip_funcs, 3588 }; 3589