1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include <drm/drm_edid.h> 27 #include <drm/drm_fourcc.h> 28 #include <drm/drm_modeset_helper.h> 29 #include <drm/drm_modeset_helper_vtables.h> 30 #include <drm/drm_vblank.h> 31 32 #include "amdgpu.h" 33 #include "amdgpu_pm.h" 34 #include "amdgpu_i2c.h" 35 #include "atom.h" 36 #include "amdgpu_atombios.h" 37 #include "atombios_crtc.h" 38 #include "atombios_encoders.h" 39 #include "amdgpu_pll.h" 40 #include "amdgpu_connectors.h" 41 #include "amdgpu_display.h" 42 43 #include "bif/bif_3_0_d.h" 44 #include "bif/bif_3_0_sh_mask.h" 45 #include "oss/oss_1_0_d.h" 46 #include "oss/oss_1_0_sh_mask.h" 47 #include "gca/gfx_6_0_d.h" 48 #include "gca/gfx_6_0_sh_mask.h" 49 #include "gmc/gmc_6_0_d.h" 50 #include "gmc/gmc_6_0_sh_mask.h" 51 #include "dce/dce_6_0_d.h" 52 #include "dce/dce_6_0_sh_mask.h" 53 #include "gca/gfx_7_2_enum.h" 54 #include "dce_v6_0.h" 55 #include "si_enums.h" 56 57 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev); 58 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev); 59 60 static const u32 crtc_offsets[6] = 61 { 62 SI_CRTC0_REGISTER_OFFSET, 63 SI_CRTC1_REGISTER_OFFSET, 64 SI_CRTC2_REGISTER_OFFSET, 65 SI_CRTC3_REGISTER_OFFSET, 66 SI_CRTC4_REGISTER_OFFSET, 67 SI_CRTC5_REGISTER_OFFSET 68 }; 69 70 static const u32 hpd_offsets[] = 71 { 72 mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS, 73 mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS, 74 mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS, 75 mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS, 76 mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS, 77 mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS, 78 }; 79 80 static const uint32_t dig_offsets[] = { 81 SI_CRTC0_REGISTER_OFFSET, 82 SI_CRTC1_REGISTER_OFFSET, 83 SI_CRTC2_REGISTER_OFFSET, 84 SI_CRTC3_REGISTER_OFFSET, 85 SI_CRTC4_REGISTER_OFFSET, 86 SI_CRTC5_REGISTER_OFFSET, 87 (0x13830 - 0x7030) >> 2, 88 }; 89 90 static const struct { 91 uint32_t reg; 92 uint32_t vblank; 93 uint32_t vline; 94 uint32_t hpd; 95 96 } interrupt_status_offsets[6] = { { 97 .reg = mmDISP_INTERRUPT_STATUS, 98 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 99 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 100 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 101 }, { 102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 104 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 106 }, { 107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 109 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 111 }, { 112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 114 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 116 }, { 117 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 118 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 119 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 120 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 121 }, { 122 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 123 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 124 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 125 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 126 } }; 127 128 static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev, 129 u32 block_offset, u32 reg) 130 { 131 unsigned long flags; 132 u32 r; 133 134 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 135 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 136 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 137 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 138 139 return r; 140 } 141 142 static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev, 143 u32 block_offset, u32 reg, u32 v) 144 { 145 unsigned long flags; 146 147 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 148 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, 149 reg | AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK); 150 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 151 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 152 } 153 154 static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 155 { 156 if (crtc >= adev->mode_info.num_crtc) 157 return 0; 158 else 159 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 160 } 161 162 static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev) 163 { 164 unsigned i; 165 166 /* Enable pflip interrupts */ 167 for (i = 0; i < adev->mode_info.num_crtc; i++) 168 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 169 } 170 171 static void dce_v6_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 172 { 173 unsigned i; 174 175 /* Disable pflip interrupts */ 176 for (i = 0; i < adev->mode_info.num_crtc; i++) 177 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 178 } 179 180 /** 181 * dce_v6_0_page_flip - pageflip callback. 182 * 183 * @adev: amdgpu_device pointer 184 * @crtc_id: crtc to cleanup pageflip on 185 * @crtc_base: new address of the crtc (GPU MC address) 186 * @async: asynchronous flip 187 * 188 * Does the actual pageflip (evergreen+). 189 * During vblank we take the crtc lock and wait for the update_pending 190 * bit to go high, when it does, we release the lock, and allow the 191 * double buffered update to take place. 192 * Returns the current update pending status. 193 */ 194 static void dce_v6_0_page_flip(struct amdgpu_device *adev, 195 int crtc_id, u64 crtc_base, bool async) 196 { 197 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 198 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; 199 200 /* flip at hsync for async, default is vsync */ 201 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? 202 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); 203 /* update pitch */ 204 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, 205 fb->pitches[0] / fb->format->cpp[0]); 206 /* update the scanout addresses */ 207 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 208 upper_32_bits(crtc_base)); 209 /* writing to the low address triggers the update */ 210 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 211 (u32)crtc_base); 212 /* post the write */ 213 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 214 } 215 216 static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 217 u32 *vbl, u32 *position) 218 { 219 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 220 return -EINVAL; 221 222 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 223 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 224 225 return 0; 226 } 227 228 /** 229 * dce_v6_0_hpd_sense - hpd sense callback. 230 * 231 * @adev: amdgpu_device pointer 232 * @hpd: hpd (hotplug detect) pin 233 * 234 * Checks if a digital monitor is connected (evergreen+). 235 * Returns true if connected, false if not connected. 236 */ 237 static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev, 238 enum amdgpu_hpd_id hpd) 239 { 240 bool connected = false; 241 242 if (hpd >= adev->mode_info.num_hpd) 243 return connected; 244 245 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) 246 connected = true; 247 248 return connected; 249 } 250 251 /** 252 * dce_v6_0_hpd_set_polarity - hpd set polarity callback. 253 * 254 * @adev: amdgpu_device pointer 255 * @hpd: hpd (hotplug detect) pin 256 * 257 * Set the polarity of the hpd pin (evergreen+). 258 */ 259 static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev, 260 enum amdgpu_hpd_id hpd) 261 { 262 u32 tmp; 263 bool connected = dce_v6_0_hpd_sense(adev, hpd); 264 265 if (hpd >= adev->mode_info.num_hpd) 266 return; 267 268 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 269 if (connected) 270 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 271 else 272 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 273 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 274 } 275 276 static void dce_v6_0_hpd_int_ack(struct amdgpu_device *adev, 277 int hpd) 278 { 279 u32 tmp; 280 281 if (hpd >= adev->mode_info.num_hpd) { 282 DRM_DEBUG("invalid hdp %d\n", hpd); 283 return; 284 } 285 286 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 287 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; 288 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 289 } 290 291 /** 292 * dce_v6_0_hpd_init - hpd setup callback. 293 * 294 * @adev: amdgpu_device pointer 295 * 296 * Setup the hpd pins used by the card (evergreen+). 297 * Enable the pin, set the polarity, and enable the hpd interrupts. 298 */ 299 static void dce_v6_0_hpd_init(struct amdgpu_device *adev) 300 { 301 struct drm_device *dev = adev_to_drm(adev); 302 struct drm_connector *connector; 303 struct drm_connector_list_iter iter; 304 u32 tmp; 305 306 drm_connector_list_iter_begin(dev, &iter); 307 drm_for_each_connector_iter(connector, &iter) { 308 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 309 310 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 311 continue; 312 313 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 314 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK; 315 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 316 317 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 318 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 319 /* don't try to enable hpd on eDP or LVDS avoid breaking the 320 * aux dp channel on imac and help (but not completely fix) 321 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 322 * also avoid interrupt storms during dpms. 323 */ 324 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 325 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 326 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 327 continue; 328 } 329 330 dce_v6_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd); 331 dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 332 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 333 } 334 drm_connector_list_iter_end(&iter); 335 } 336 337 /** 338 * dce_v6_0_hpd_fini - hpd tear down callback. 339 * 340 * @adev: amdgpu_device pointer 341 * 342 * Tear down the hpd pins used by the card (evergreen+). 343 * Disable the hpd interrupts. 344 */ 345 static void dce_v6_0_hpd_fini(struct amdgpu_device *adev) 346 { 347 struct drm_device *dev = adev_to_drm(adev); 348 struct drm_connector *connector; 349 struct drm_connector_list_iter iter; 350 u32 tmp; 351 352 drm_connector_list_iter_begin(dev, &iter); 353 drm_for_each_connector_iter(connector, &iter) { 354 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 355 356 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 357 continue; 358 359 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 360 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK; 361 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 362 363 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 364 } 365 drm_connector_list_iter_end(&iter); 366 } 367 368 static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 369 { 370 return mmDC_GPIO_HPD_A; 371 } 372 373 static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev, 374 bool render) 375 { 376 if (!render) 377 WREG32(mmVGA_RENDER_CONTROL, 378 RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL); 379 380 } 381 382 static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev) 383 { 384 switch (adev->asic_type) { 385 case CHIP_TAHITI: 386 case CHIP_PITCAIRN: 387 case CHIP_VERDE: 388 return 6; 389 case CHIP_OLAND: 390 return 2; 391 default: 392 return 0; 393 } 394 } 395 396 void dce_v6_0_disable_dce(struct amdgpu_device *adev) 397 { 398 /*Disable VGA render and enabled crtc, if has DCE engine*/ 399 if (amdgpu_atombios_has_dce_engine_info(adev)) { 400 u32 tmp; 401 int crtc_enabled, i; 402 403 dce_v6_0_set_vga_render_state(adev, false); 404 405 /*Disable crtc*/ 406 for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) { 407 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & 408 CRTC_CONTROL__CRTC_MASTER_EN_MASK; 409 if (crtc_enabled) { 410 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 411 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 412 tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK; 413 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 414 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 415 } 416 } 417 } 418 } 419 420 static void dce_v6_0_program_fmt(struct drm_encoder *encoder) 421 { 422 423 struct drm_device *dev = encoder->dev; 424 struct amdgpu_device *adev = drm_to_adev(dev); 425 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 426 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 427 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 428 int bpc = 0; 429 u32 tmp = 0; 430 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 431 432 if (connector) { 433 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 434 bpc = amdgpu_connector_get_monitor_bpc(connector); 435 dither = amdgpu_connector->dither; 436 } 437 438 /* LVDS FMT is set up by atom */ 439 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 440 return; 441 442 if (bpc == 0) 443 return; 444 445 446 switch (bpc) { 447 case 6: 448 if (dither == AMDGPU_FMT_DITHER_ENABLE) 449 /* XXX sort out optimal dither settings */ 450 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 451 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 452 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK); 453 else 454 tmp |= FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK; 455 break; 456 case 8: 457 if (dither == AMDGPU_FMT_DITHER_ENABLE) 458 /* XXX sort out optimal dither settings */ 459 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 460 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 461 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK | 462 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | 463 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK); 464 else 465 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | 466 FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK); 467 break; 468 case 10: 469 default: 470 /* not needed */ 471 break; 472 } 473 474 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 475 } 476 477 /** 478 * si_get_number_of_dram_channels - get the number of dram channels 479 * 480 * @adev: amdgpu_device pointer 481 * 482 * Look up the number of video ram channels (CIK). 483 * Used for display watermark bandwidth calculations 484 * Returns the number of dram channels 485 */ 486 static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev) 487 { 488 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 489 490 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { 491 case 0: 492 default: 493 return 1; 494 case 1: 495 return 2; 496 case 2: 497 return 4; 498 case 3: 499 return 8; 500 case 4: 501 return 3; 502 case 5: 503 return 6; 504 case 6: 505 return 10; 506 case 7: 507 return 12; 508 case 8: 509 return 16; 510 } 511 } 512 513 struct dce6_wm_params { 514 u32 dram_channels; /* number of dram channels */ 515 u32 yclk; /* bandwidth per dram data pin in kHz */ 516 u32 sclk; /* engine clock in kHz */ 517 u32 disp_clk; /* display clock in kHz */ 518 u32 src_width; /* viewport width */ 519 u32 active_time; /* active display time in ns */ 520 u32 blank_time; /* blank time in ns */ 521 bool interlaced; /* mode is interlaced */ 522 fixed20_12 vsc; /* vertical scale ratio */ 523 u32 num_heads; /* number of active crtcs */ 524 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 525 u32 lb_size; /* line buffer allocated to pipe */ 526 u32 vtaps; /* vertical scaler taps */ 527 }; 528 529 /** 530 * dce_v6_0_dram_bandwidth - get the dram bandwidth 531 * 532 * @wm: watermark calculation data 533 * 534 * Calculate the raw dram bandwidth (CIK). 535 * Used for display watermark bandwidth calculations 536 * Returns the dram bandwidth in MBytes/s 537 */ 538 static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm) 539 { 540 /* Calculate raw DRAM Bandwidth */ 541 fixed20_12 dram_efficiency; /* 0.7 */ 542 fixed20_12 yclk, dram_channels, bandwidth; 543 fixed20_12 a; 544 545 a.full = dfixed_const(1000); 546 yclk.full = dfixed_const(wm->yclk); 547 yclk.full = dfixed_div(yclk, a); 548 dram_channels.full = dfixed_const(wm->dram_channels * 4); 549 a.full = dfixed_const(10); 550 dram_efficiency.full = dfixed_const(7); 551 dram_efficiency.full = dfixed_div(dram_efficiency, a); 552 bandwidth.full = dfixed_mul(dram_channels, yclk); 553 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 554 555 return dfixed_trunc(bandwidth); 556 } 557 558 /** 559 * dce_v6_0_dram_bandwidth_for_display - get the dram bandwidth for display 560 * 561 * @wm: watermark calculation data 562 * 563 * Calculate the dram bandwidth used for display (CIK). 564 * Used for display watermark bandwidth calculations 565 * Returns the dram bandwidth for display in MBytes/s 566 */ 567 static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm) 568 { 569 /* Calculate DRAM Bandwidth and the part allocated to display. */ 570 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 571 fixed20_12 yclk, dram_channels, bandwidth; 572 fixed20_12 a; 573 574 a.full = dfixed_const(1000); 575 yclk.full = dfixed_const(wm->yclk); 576 yclk.full = dfixed_div(yclk, a); 577 dram_channels.full = dfixed_const(wm->dram_channels * 4); 578 a.full = dfixed_const(10); 579 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 580 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 581 bandwidth.full = dfixed_mul(dram_channels, yclk); 582 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 583 584 return dfixed_trunc(bandwidth); 585 } 586 587 /** 588 * dce_v6_0_data_return_bandwidth - get the data return bandwidth 589 * 590 * @wm: watermark calculation data 591 * 592 * Calculate the data return bandwidth used for display (CIK). 593 * Used for display watermark bandwidth calculations 594 * Returns the data return bandwidth in MBytes/s 595 */ 596 static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm) 597 { 598 /* Calculate the display Data return Bandwidth */ 599 fixed20_12 return_efficiency; /* 0.8 */ 600 fixed20_12 sclk, bandwidth; 601 fixed20_12 a; 602 603 a.full = dfixed_const(1000); 604 sclk.full = dfixed_const(wm->sclk); 605 sclk.full = dfixed_div(sclk, a); 606 a.full = dfixed_const(10); 607 return_efficiency.full = dfixed_const(8); 608 return_efficiency.full = dfixed_div(return_efficiency, a); 609 a.full = dfixed_const(32); 610 bandwidth.full = dfixed_mul(a, sclk); 611 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 612 613 return dfixed_trunc(bandwidth); 614 } 615 616 /** 617 * dce_v6_0_dmif_request_bandwidth - get the dmif bandwidth 618 * 619 * @wm: watermark calculation data 620 * 621 * Calculate the dmif bandwidth used for display (CIK). 622 * Used for display watermark bandwidth calculations 623 * Returns the dmif bandwidth in MBytes/s 624 */ 625 static u32 dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params *wm) 626 { 627 /* Calculate the DMIF Request Bandwidth */ 628 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 629 fixed20_12 disp_clk, bandwidth; 630 fixed20_12 a, b; 631 632 a.full = dfixed_const(1000); 633 disp_clk.full = dfixed_const(wm->disp_clk); 634 disp_clk.full = dfixed_div(disp_clk, a); 635 a.full = dfixed_const(32); 636 b.full = dfixed_mul(a, disp_clk); 637 638 a.full = dfixed_const(10); 639 disp_clk_request_efficiency.full = dfixed_const(8); 640 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 641 642 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 643 644 return dfixed_trunc(bandwidth); 645 } 646 647 /** 648 * dce_v6_0_available_bandwidth - get the min available bandwidth 649 * 650 * @wm: watermark calculation data 651 * 652 * Calculate the min available bandwidth used for display (CIK). 653 * Used for display watermark bandwidth calculations 654 * Returns the min available bandwidth in MBytes/s 655 */ 656 static u32 dce_v6_0_available_bandwidth(struct dce6_wm_params *wm) 657 { 658 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 659 u32 dram_bandwidth = dce_v6_0_dram_bandwidth(wm); 660 u32 data_return_bandwidth = dce_v6_0_data_return_bandwidth(wm); 661 u32 dmif_req_bandwidth = dce_v6_0_dmif_request_bandwidth(wm); 662 663 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 664 } 665 666 /** 667 * dce_v6_0_average_bandwidth - get the average available bandwidth 668 * 669 * @wm: watermark calculation data 670 * 671 * Calculate the average available bandwidth used for display (CIK). 672 * Used for display watermark bandwidth calculations 673 * Returns the average available bandwidth in MBytes/s 674 */ 675 static u32 dce_v6_0_average_bandwidth(struct dce6_wm_params *wm) 676 { 677 /* Calculate the display mode Average Bandwidth 678 * DisplayMode should contain the source and destination dimensions, 679 * timing, etc. 680 */ 681 fixed20_12 bpp; 682 fixed20_12 line_time; 683 fixed20_12 src_width; 684 fixed20_12 bandwidth; 685 fixed20_12 a; 686 687 a.full = dfixed_const(1000); 688 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 689 line_time.full = dfixed_div(line_time, a); 690 bpp.full = dfixed_const(wm->bytes_per_pixel); 691 src_width.full = dfixed_const(wm->src_width); 692 bandwidth.full = dfixed_mul(src_width, bpp); 693 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 694 bandwidth.full = dfixed_div(bandwidth, line_time); 695 696 return dfixed_trunc(bandwidth); 697 } 698 699 /** 700 * dce_v6_0_latency_watermark - get the latency watermark 701 * 702 * @wm: watermark calculation data 703 * 704 * Calculate the latency watermark (CIK). 705 * Used for display watermark bandwidth calculations 706 * Returns the latency watermark in ns 707 */ 708 static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm) 709 { 710 /* First calculate the latency in ns */ 711 u32 mc_latency = 2000; /* 2000 ns. */ 712 u32 available_bandwidth = dce_v6_0_available_bandwidth(wm); 713 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 714 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 715 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 716 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 717 (wm->num_heads * cursor_line_pair_return_time); 718 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 719 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 720 u32 tmp, dmif_size = 12288; 721 fixed20_12 a, b, c; 722 723 if (wm->num_heads == 0) 724 return 0; 725 726 a.full = dfixed_const(2); 727 b.full = dfixed_const(1); 728 if ((wm->vsc.full > a.full) || 729 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 730 (wm->vtaps >= 5) || 731 ((wm->vsc.full >= a.full) && wm->interlaced)) 732 max_src_lines_per_dst_line = 4; 733 else 734 max_src_lines_per_dst_line = 2; 735 736 a.full = dfixed_const(available_bandwidth); 737 b.full = dfixed_const(wm->num_heads); 738 a.full = dfixed_div(a, b); 739 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); 740 tmp = min(dfixed_trunc(a), tmp); 741 742 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); 743 744 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 745 b.full = dfixed_const(1000); 746 c.full = dfixed_const(lb_fill_bw); 747 b.full = dfixed_div(c, b); 748 a.full = dfixed_div(a, b); 749 line_fill_time = dfixed_trunc(a); 750 751 if (line_fill_time < wm->active_time) 752 return latency; 753 else 754 return latency + (line_fill_time - wm->active_time); 755 756 } 757 758 /** 759 * dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display - check 760 * average and available dram bandwidth 761 * 762 * @wm: watermark calculation data 763 * 764 * Check if the display average bandwidth fits in the display 765 * dram bandwidth (CIK). 766 * Used for display watermark bandwidth calculations 767 * Returns true if the display fits, false if not. 768 */ 769 static bool dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm) 770 { 771 if (dce_v6_0_average_bandwidth(wm) <= 772 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 773 return true; 774 else 775 return false; 776 } 777 778 /** 779 * dce_v6_0_average_bandwidth_vs_available_bandwidth - check 780 * average and available bandwidth 781 * 782 * @wm: watermark calculation data 783 * 784 * Check if the display average bandwidth fits in the display 785 * available bandwidth (CIK). 786 * Used for display watermark bandwidth calculations 787 * Returns true if the display fits, false if not. 788 */ 789 static bool dce_v6_0_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm) 790 { 791 if (dce_v6_0_average_bandwidth(wm) <= 792 (dce_v6_0_available_bandwidth(wm) / wm->num_heads)) 793 return true; 794 else 795 return false; 796 } 797 798 /** 799 * dce_v6_0_check_latency_hiding - check latency hiding 800 * 801 * @wm: watermark calculation data 802 * 803 * Check latency hiding (CIK). 804 * Used for display watermark bandwidth calculations 805 * Returns true if the display fits, false if not. 806 */ 807 static bool dce_v6_0_check_latency_hiding(struct dce6_wm_params *wm) 808 { 809 u32 lb_partitions = wm->lb_size / wm->src_width; 810 u32 line_time = wm->active_time + wm->blank_time; 811 u32 latency_tolerant_lines; 812 u32 latency_hiding; 813 fixed20_12 a; 814 815 a.full = dfixed_const(1); 816 if (wm->vsc.full > a.full) 817 latency_tolerant_lines = 1; 818 else { 819 if (lb_partitions <= (wm->vtaps + 1)) 820 latency_tolerant_lines = 1; 821 else 822 latency_tolerant_lines = 2; 823 } 824 825 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 826 827 if (dce_v6_0_latency_watermark(wm) <= latency_hiding) 828 return true; 829 else 830 return false; 831 } 832 833 /** 834 * dce_v6_0_program_watermarks - program display watermarks 835 * 836 * @adev: amdgpu_device pointer 837 * @amdgpu_crtc: the selected display controller 838 * @lb_size: line buffer size 839 * @num_heads: number of display controllers in use 840 * 841 * Calculate and program the display watermarks for the 842 * selected display controller (CIK). 843 */ 844 static void dce_v6_0_program_watermarks(struct amdgpu_device *adev, 845 struct amdgpu_crtc *amdgpu_crtc, 846 u32 lb_size, u32 num_heads) 847 { 848 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 849 struct dce6_wm_params wm_low, wm_high; 850 u32 dram_channels; 851 u32 active_time; 852 u32 line_time = 0; 853 u32 latency_watermark_a = 0, latency_watermark_b = 0; 854 u32 priority_a_mark = 0, priority_b_mark = 0; 855 u32 priority_a_cnt = PRIORITY_OFF; 856 u32 priority_b_cnt = PRIORITY_OFF; 857 u32 tmp, arb_control3, lb_vblank_lead_lines = 0; 858 fixed20_12 a, b, c; 859 860 if (amdgpu_crtc->base.enabled && num_heads && mode) { 861 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, 862 (u32)mode->clock); 863 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, 864 (u32)mode->clock); 865 line_time = min_t(u32, line_time, 65535); 866 priority_a_cnt = 0; 867 priority_b_cnt = 0; 868 869 dram_channels = si_get_number_of_dram_channels(adev); 870 871 /* watermark for high clocks */ 872 if (adev->pm.dpm_enabled) { 873 wm_high.yclk = 874 amdgpu_dpm_get_mclk(adev, false) * 10; 875 wm_high.sclk = 876 amdgpu_dpm_get_sclk(adev, false) * 10; 877 } else { 878 wm_high.yclk = adev->pm.current_mclk * 10; 879 wm_high.sclk = adev->pm.current_sclk * 10; 880 } 881 882 wm_high.disp_clk = mode->clock; 883 wm_high.src_width = mode->crtc_hdisplay; 884 wm_high.active_time = active_time; 885 wm_high.blank_time = line_time - wm_high.active_time; 886 wm_high.interlaced = false; 887 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 888 wm_high.interlaced = true; 889 wm_high.vsc = amdgpu_crtc->vsc; 890 wm_high.vtaps = 1; 891 if (amdgpu_crtc->rmx_type != RMX_OFF) 892 wm_high.vtaps = 2; 893 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 894 wm_high.lb_size = lb_size; 895 wm_high.dram_channels = dram_channels; 896 wm_high.num_heads = num_heads; 897 898 if (adev->pm.dpm_enabled) { 899 /* watermark for low clocks */ 900 wm_low.yclk = 901 amdgpu_dpm_get_mclk(adev, true) * 10; 902 wm_low.sclk = 903 amdgpu_dpm_get_sclk(adev, true) * 10; 904 } else { 905 wm_low.yclk = adev->pm.current_mclk * 10; 906 wm_low.sclk = adev->pm.current_sclk * 10; 907 } 908 909 wm_low.disp_clk = mode->clock; 910 wm_low.src_width = mode->crtc_hdisplay; 911 wm_low.active_time = active_time; 912 wm_low.blank_time = line_time - wm_low.active_time; 913 wm_low.interlaced = false; 914 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 915 wm_low.interlaced = true; 916 wm_low.vsc = amdgpu_crtc->vsc; 917 wm_low.vtaps = 1; 918 if (amdgpu_crtc->rmx_type != RMX_OFF) 919 wm_low.vtaps = 2; 920 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 921 wm_low.lb_size = lb_size; 922 wm_low.dram_channels = dram_channels; 923 wm_low.num_heads = num_heads; 924 925 /* set for high clocks */ 926 latency_watermark_a = min_t(u32, dce_v6_0_latency_watermark(&wm_high), 65535); 927 /* set for low clocks */ 928 latency_watermark_b = min_t(u32, dce_v6_0_latency_watermark(&wm_low), 65535); 929 930 /* possibly force display priority to high */ 931 /* should really do this at mode validation time... */ 932 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 933 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 934 !dce_v6_0_check_latency_hiding(&wm_high) || 935 (adev->mode_info.disp_priority == 2)) { 936 DRM_DEBUG_KMS("force priority to high\n"); 937 priority_a_cnt |= PRIORITY_ALWAYS_ON; 938 priority_b_cnt |= PRIORITY_ALWAYS_ON; 939 } 940 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 941 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 942 !dce_v6_0_check_latency_hiding(&wm_low) || 943 (adev->mode_info.disp_priority == 2)) { 944 DRM_DEBUG_KMS("force priority to high\n"); 945 priority_a_cnt |= PRIORITY_ALWAYS_ON; 946 priority_b_cnt |= PRIORITY_ALWAYS_ON; 947 } 948 949 a.full = dfixed_const(1000); 950 b.full = dfixed_const(mode->clock); 951 b.full = dfixed_div(b, a); 952 c.full = dfixed_const(latency_watermark_a); 953 c.full = dfixed_mul(c, b); 954 c.full = dfixed_mul(c, amdgpu_crtc->hsc); 955 c.full = dfixed_div(c, a); 956 a.full = dfixed_const(16); 957 c.full = dfixed_div(c, a); 958 priority_a_mark = dfixed_trunc(c); 959 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK; 960 961 a.full = dfixed_const(1000); 962 b.full = dfixed_const(mode->clock); 963 b.full = dfixed_div(b, a); 964 c.full = dfixed_const(latency_watermark_b); 965 c.full = dfixed_mul(c, b); 966 c.full = dfixed_mul(c, amdgpu_crtc->hsc); 967 c.full = dfixed_div(c, a); 968 a.full = dfixed_const(16); 969 c.full = dfixed_div(c, a); 970 priority_b_mark = dfixed_trunc(c); 971 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; 972 973 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 974 } 975 976 /* select wm A */ 977 arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); 978 tmp = arb_control3; 979 tmp &= ~LATENCY_WATERMARK_MASK(3); 980 tmp |= LATENCY_WATERMARK_MASK(1); 981 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); 982 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 983 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 984 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 985 /* select wm B */ 986 tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); 987 tmp &= ~LATENCY_WATERMARK_MASK(3); 988 tmp |= LATENCY_WATERMARK_MASK(2); 989 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); 990 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 991 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 992 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 993 /* restore original selection */ 994 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3); 995 996 /* write the priority marks */ 997 WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt); 998 WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt); 999 1000 /* save values for DPM */ 1001 amdgpu_crtc->line_time = line_time; 1002 amdgpu_crtc->wm_high = latency_watermark_a; 1003 1004 /* Save number of lines the linebuffer leads before the scanout */ 1005 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1006 } 1007 1008 /* watermark setup */ 1009 /** 1010 * dce_v6_0_line_buffer_adjust - Set up the line buffer 1011 * 1012 * @adev: amdgpu_device pointer 1013 * @amdgpu_crtc: the selected display controller 1014 * @mode: the current display mode on the selected display 1015 * controller 1016 * 1017 * Setup up the line buffer allocation for 1018 * the selected display controller (CIK). 1019 * Returns the line buffer size in pixels. 1020 */ 1021 static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev, 1022 struct amdgpu_crtc *amdgpu_crtc, 1023 struct drm_display_mode *mode, 1024 struct drm_display_mode *other_mode) 1025 { 1026 u32 tmp, buffer_alloc, i; 1027 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; 1028 /* 1029 * Line Buffer Setup 1030 * There are 3 line buffers, each one shared by 2 display controllers. 1031 * mmDC_LB_MEMORY_SPLIT controls how that line buffer is shared between 1032 * the display controllers. The paritioning is done via one of four 1033 * preset allocations specified in bits 21:20: 1034 * 0 - half lb 1035 * 2 - whole lb, other crtc must be disabled 1036 */ 1037 /* this can get tricky if we have two large displays on a paired group 1038 * of crtcs. Ideally for multiple large displays we'd assign them to 1039 * non-linked crtcs for maximum line buffer allocation. 1040 */ 1041 if (amdgpu_crtc->base.enabled && mode) { 1042 if (other_mode) { 1043 tmp = 0; /* 1/2 */ 1044 buffer_alloc = 1; 1045 } else { 1046 tmp = 2; /* whole */ 1047 buffer_alloc = 2; 1048 } 1049 } else { 1050 tmp = 0; 1051 buffer_alloc = 0; 1052 } 1053 1054 WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset, 1055 DC_LB_MEMORY_CONFIG(tmp)); 1056 1057 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, 1058 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT)); 1059 for (i = 0; i < adev->usec_timeout; i++) { 1060 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & 1061 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK) 1062 break; 1063 udelay(1); 1064 } 1065 1066 if (amdgpu_crtc->base.enabled && mode) { 1067 switch (tmp) { 1068 case 0: 1069 default: 1070 return 4096 * 2; 1071 case 2: 1072 return 8192 * 2; 1073 } 1074 } 1075 1076 /* controller not enabled, so no lb used */ 1077 return 0; 1078 } 1079 1080 1081 /** 1082 * dce_v6_0_bandwidth_update - program display watermarks 1083 * 1084 * @adev: amdgpu_device pointer 1085 * 1086 * Calculate and program the display watermarks and line 1087 * buffer allocation (CIK). 1088 */ 1089 static void dce_v6_0_bandwidth_update(struct amdgpu_device *adev) 1090 { 1091 struct drm_display_mode *mode0 = NULL; 1092 struct drm_display_mode *mode1 = NULL; 1093 u32 num_heads = 0, lb_size; 1094 int i; 1095 1096 if (!adev->mode_info.mode_config_initialized) 1097 return; 1098 1099 amdgpu_display_update_priority(adev); 1100 1101 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1102 if (adev->mode_info.crtcs[i]->base.enabled) 1103 num_heads++; 1104 } 1105 for (i = 0; i < adev->mode_info.num_crtc; i += 2) { 1106 mode0 = &adev->mode_info.crtcs[i]->base.mode; 1107 mode1 = &adev->mode_info.crtcs[i+1]->base.mode; 1108 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1); 1109 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads); 1110 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0); 1111 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads); 1112 } 1113 } 1114 1115 static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device *adev) 1116 { 1117 int i; 1118 u32 tmp; 1119 1120 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1121 tmp = RREG32_AUDIO_ENDPT(adev->mode_info.audio.pin[i].offset, 1122 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1123 if (REG_GET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT, 1124 PORT_CONNECTIVITY)) 1125 adev->mode_info.audio.pin[i].connected = false; 1126 else 1127 adev->mode_info.audio.pin[i].connected = true; 1128 } 1129 1130 } 1131 1132 static struct amdgpu_audio_pin *dce_v6_0_audio_get_pin(struct amdgpu_device *adev) 1133 { 1134 int i; 1135 1136 dce_v6_0_audio_get_connected_pins(adev); 1137 1138 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1139 if (adev->mode_info.audio.pin[i].connected) 1140 return &adev->mode_info.audio.pin[i]; 1141 } 1142 DRM_ERROR("No connected audio pins found!\n"); 1143 return NULL; 1144 } 1145 1146 static void dce_v6_0_audio_select_pin(struct drm_encoder *encoder) 1147 { 1148 struct amdgpu_device *adev = drm_to_adev(encoder->dev); 1149 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1150 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1151 1152 if (!dig || !dig->afmt || !dig->afmt->pin) 1153 return; 1154 1155 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, 1156 REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, 1157 dig->afmt->pin->id)); 1158 } 1159 1160 static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder, 1161 struct drm_display_mode *mode) 1162 { 1163 struct drm_device *dev = encoder->dev; 1164 struct amdgpu_device *adev = drm_to_adev(dev); 1165 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1166 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1167 struct drm_connector *connector; 1168 struct drm_connector_list_iter iter; 1169 struct amdgpu_connector *amdgpu_connector = NULL; 1170 int interlace = 0; 1171 u32 tmp; 1172 1173 drm_connector_list_iter_begin(dev, &iter); 1174 drm_for_each_connector_iter(connector, &iter) { 1175 if (connector->encoder == encoder) { 1176 amdgpu_connector = to_amdgpu_connector(connector); 1177 break; 1178 } 1179 } 1180 drm_connector_list_iter_end(&iter); 1181 1182 if (!amdgpu_connector) { 1183 DRM_ERROR("Couldn't find encoder's connector\n"); 1184 return; 1185 } 1186 1187 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1188 interlace = 1; 1189 1190 if (connector->latency_present[interlace]) { 1191 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1192 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1193 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1194 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1195 } else { 1196 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1197 VIDEO_LIPSYNC, 0); 1198 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1199 AUDIO_LIPSYNC, 0); 1200 } 1201 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1202 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1203 } 1204 1205 static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1206 { 1207 struct drm_device *dev = encoder->dev; 1208 struct amdgpu_device *adev = drm_to_adev(dev); 1209 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1210 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1211 struct drm_connector *connector; 1212 struct drm_connector_list_iter iter; 1213 struct amdgpu_connector *amdgpu_connector = NULL; 1214 u8 *sadb = NULL; 1215 int sad_count; 1216 u32 tmp; 1217 1218 drm_connector_list_iter_begin(dev, &iter); 1219 drm_for_each_connector_iter(connector, &iter) { 1220 if (connector->encoder == encoder) { 1221 amdgpu_connector = to_amdgpu_connector(connector); 1222 break; 1223 } 1224 } 1225 drm_connector_list_iter_end(&iter); 1226 1227 if (!amdgpu_connector) { 1228 DRM_ERROR("Couldn't find encoder's connector\n"); 1229 return; 1230 } 1231 1232 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb); 1233 if (sad_count < 0) { 1234 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1235 sad_count = 0; 1236 } 1237 1238 /* program the speaker allocation */ 1239 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1240 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1241 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1242 HDMI_CONNECTION, 0); 1243 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1244 DP_CONNECTION, 0); 1245 1246 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) 1247 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1248 DP_CONNECTION, 1); 1249 else 1250 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1251 HDMI_CONNECTION, 1); 1252 1253 if (sad_count) 1254 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1255 SPEAKER_ALLOCATION, sadb[0]); 1256 else 1257 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1258 SPEAKER_ALLOCATION, 5); /* stereo */ 1259 1260 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1261 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1262 1263 kfree(sadb); 1264 } 1265 1266 static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder) 1267 { 1268 struct drm_device *dev = encoder->dev; 1269 struct amdgpu_device *adev = drm_to_adev(dev); 1270 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1271 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1272 struct drm_connector *connector; 1273 struct drm_connector_list_iter iter; 1274 struct amdgpu_connector *amdgpu_connector = NULL; 1275 struct cea_sad *sads; 1276 int i, sad_count; 1277 1278 static const u16 eld_reg_to_type[][2] = { 1279 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1280 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1281 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1282 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1283 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1284 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1285 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1286 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1287 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1288 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1289 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1290 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1291 }; 1292 1293 drm_connector_list_iter_begin(dev, &iter); 1294 drm_for_each_connector_iter(connector, &iter) { 1295 if (connector->encoder == encoder) { 1296 amdgpu_connector = to_amdgpu_connector(connector); 1297 break; 1298 } 1299 } 1300 drm_connector_list_iter_end(&iter); 1301 1302 if (!amdgpu_connector) { 1303 DRM_ERROR("Couldn't find encoder's connector\n"); 1304 return; 1305 } 1306 1307 sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads); 1308 if (sad_count < 0) 1309 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1310 if (sad_count <= 0) 1311 return; 1312 1313 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1314 u32 tmp = 0; 1315 u8 stereo_freqs = 0; 1316 int max_channels = -1; 1317 int j; 1318 1319 for (j = 0; j < sad_count; j++) { 1320 struct cea_sad *sad = &sads[j]; 1321 1322 if (sad->format == eld_reg_to_type[i][1]) { 1323 if (sad->channels > max_channels) { 1324 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1325 MAX_CHANNELS, sad->channels); 1326 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1327 DESCRIPTOR_BYTE_2, sad->byte2); 1328 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1329 SUPPORTED_FREQUENCIES, sad->freq); 1330 max_channels = sad->channels; 1331 } 1332 1333 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1334 stereo_freqs |= sad->freq; 1335 else 1336 break; 1337 } 1338 } 1339 1340 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1341 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); 1342 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); 1343 } 1344 1345 kfree(sads); 1346 1347 } 1348 1349 static void dce_v6_0_audio_enable(struct amdgpu_device *adev, 1350 struct amdgpu_audio_pin *pin, 1351 bool enable) 1352 { 1353 if (!pin) 1354 return; 1355 1356 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1357 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1358 } 1359 1360 static const u32 pin_offsets[7] = 1361 { 1362 (0x1780 - 0x1780), 1363 (0x1786 - 0x1780), 1364 (0x178c - 0x1780), 1365 (0x1792 - 0x1780), 1366 (0x1798 - 0x1780), 1367 (0x179d - 0x1780), 1368 (0x17a4 - 0x1780), 1369 }; 1370 1371 static int dce_v6_0_audio_init(struct amdgpu_device *adev) 1372 { 1373 int i; 1374 1375 if (!amdgpu_audio) 1376 return 0; 1377 1378 adev->mode_info.audio.enabled = true; 1379 1380 switch (adev->asic_type) { 1381 case CHIP_TAHITI: 1382 case CHIP_PITCAIRN: 1383 case CHIP_VERDE: 1384 default: 1385 adev->mode_info.audio.num_pins = 6; 1386 break; 1387 case CHIP_OLAND: 1388 adev->mode_info.audio.num_pins = 2; 1389 break; 1390 } 1391 1392 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1393 adev->mode_info.audio.pin[i].channels = -1; 1394 adev->mode_info.audio.pin[i].rate = -1; 1395 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1396 adev->mode_info.audio.pin[i].status_bits = 0; 1397 adev->mode_info.audio.pin[i].category_code = 0; 1398 adev->mode_info.audio.pin[i].connected = false; 1399 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1400 adev->mode_info.audio.pin[i].id = i; 1401 /* disable audio. it will be set up later */ 1402 /* XXX remove once we switch to ip funcs */ 1403 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1404 } 1405 1406 return 0; 1407 } 1408 1409 static void dce_v6_0_audio_fini(struct amdgpu_device *adev) 1410 { 1411 int i; 1412 1413 if (!amdgpu_audio) 1414 return; 1415 1416 if (!adev->mode_info.audio.enabled) 1417 return; 1418 1419 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1420 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1421 1422 adev->mode_info.audio.enabled = false; 1423 } 1424 1425 static void dce_v6_0_audio_set_vbi_packet(struct drm_encoder *encoder) 1426 { 1427 struct drm_device *dev = encoder->dev; 1428 struct amdgpu_device *adev = drm_to_adev(dev); 1429 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1430 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1431 u32 tmp; 1432 1433 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1434 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1435 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); 1436 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); 1437 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1438 } 1439 1440 static void dce_v6_0_audio_set_acr(struct drm_encoder *encoder, 1441 uint32_t clock, int bpc) 1442 { 1443 struct drm_device *dev = encoder->dev; 1444 struct amdgpu_device *adev = drm_to_adev(dev); 1445 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1446 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1447 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1448 u32 tmp; 1449 1450 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1451 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1452 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1453 bpc > 8 ? 0 : 1); 1454 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1455 1456 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1457 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1458 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1459 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1460 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1461 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1462 1463 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1464 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1465 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1466 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1467 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1468 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1469 1470 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1471 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1472 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1473 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1474 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1475 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1476 } 1477 1478 static void dce_v6_0_audio_set_avi_infoframe(struct drm_encoder *encoder, 1479 struct drm_display_mode *mode) 1480 { 1481 struct drm_device *dev = encoder->dev; 1482 struct amdgpu_device *adev = drm_to_adev(dev); 1483 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1484 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1485 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1486 struct hdmi_avi_infoframe frame; 1487 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1488 uint8_t *payload = buffer + 3; 1489 uint8_t *header = buffer; 1490 ssize_t err; 1491 u32 tmp; 1492 1493 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); 1494 if (err < 0) { 1495 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1496 return; 1497 } 1498 1499 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1500 if (err < 0) { 1501 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1502 return; 1503 } 1504 1505 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1506 payload[0x0] | (payload[0x1] << 8) | (payload[0x2] << 16) | (payload[0x3] << 24)); 1507 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1508 payload[0x4] | (payload[0x5] << 8) | (payload[0x6] << 16) | (payload[0x7] << 24)); 1509 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1510 payload[0x8] | (payload[0x9] << 8) | (payload[0xA] << 16) | (payload[0xB] << 24)); 1511 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1512 payload[0xC] | (payload[0xD] << 8) | (header[1] << 24)); 1513 1514 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1515 /* anything other than 0 */ 1516 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, 1517 HDMI_AUDIO_INFO_LINE, 2); 1518 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1519 } 1520 1521 static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1522 { 1523 struct drm_device *dev = encoder->dev; 1524 struct amdgpu_device *adev = drm_to_adev(dev); 1525 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1526 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 1527 u32 tmp; 1528 1529 /* 1530 * Two dtos: generally use dto0 for hdmi, dto1 for dp. 1531 * Express [24MHz / target pixel clock] as an exact rational 1532 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1533 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1534 */ 1535 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1536 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, 1537 DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id); 1538 if (em == ATOM_ENCODER_MODE_HDMI) { 1539 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, 1540 DCCG_AUDIO_DTO_SEL, 0); 1541 } else if (ENCODER_MODE_IS_DP(em)) { 1542 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, 1543 DCCG_AUDIO_DTO_SEL, 1); 1544 } 1545 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1546 if (em == ATOM_ENCODER_MODE_HDMI) { 1547 WREG32(mmDCCG_AUDIO_DTO0_PHASE, 24000); 1548 WREG32(mmDCCG_AUDIO_DTO0_MODULE, clock); 1549 } else if (ENCODER_MODE_IS_DP(em)) { 1550 WREG32(mmDCCG_AUDIO_DTO1_PHASE, 24000); 1551 WREG32(mmDCCG_AUDIO_DTO1_MODULE, clock); 1552 } 1553 } 1554 1555 static void dce_v6_0_audio_set_packet(struct drm_encoder *encoder) 1556 { 1557 struct drm_device *dev = encoder->dev; 1558 struct amdgpu_device *adev = drm_to_adev(dev); 1559 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1560 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1561 u32 tmp; 1562 1563 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1564 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1565 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1566 1567 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1568 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1569 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1570 1571 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1572 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1573 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1574 1575 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1576 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1577 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1578 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1579 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1580 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1581 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1582 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1583 1584 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset); 1585 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, 0xff); 1586 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, tmp); 1587 1588 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1589 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1590 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1591 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1592 1593 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1594 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_RESET_FIFO_WHEN_AUDIO_DIS, 1); 1595 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1596 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1597 } 1598 1599 static void dce_v6_0_audio_set_mute(struct drm_encoder *encoder, bool mute) 1600 { 1601 struct drm_device *dev = encoder->dev; 1602 struct amdgpu_device *adev = drm_to_adev(dev); 1603 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1604 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1605 u32 tmp; 1606 1607 tmp = RREG32(mmHDMI_GC + dig->afmt->offset); 1608 tmp = REG_SET_FIELD(tmp, HDMI_GC, HDMI_GC_AVMUTE, mute ? 1 : 0); 1609 WREG32(mmHDMI_GC + dig->afmt->offset, tmp); 1610 } 1611 1612 static void dce_v6_0_audio_hdmi_enable(struct drm_encoder *encoder, bool enable) 1613 { 1614 struct drm_device *dev = encoder->dev; 1615 struct amdgpu_device *adev = drm_to_adev(dev); 1616 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1617 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1618 u32 tmp; 1619 1620 if (enable) { 1621 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1622 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1623 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1624 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1625 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1626 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1627 1628 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1629 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1630 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1631 1632 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1633 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1634 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1635 } else { 1636 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1637 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 0); 1638 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 0); 1639 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 0); 1640 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 0); 1641 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1642 1643 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1644 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 0); 1645 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1646 } 1647 } 1648 1649 static void dce_v6_0_audio_dp_enable(struct drm_encoder *encoder, bool enable) 1650 { 1651 struct drm_device *dev = encoder->dev; 1652 struct amdgpu_device *adev = drm_to_adev(dev); 1653 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1654 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1655 u32 tmp; 1656 1657 if (enable) { 1658 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1659 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1660 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1661 1662 tmp = RREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset); 1663 tmp = REG_SET_FIELD(tmp, DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, 1); 1664 WREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset, tmp); 1665 1666 tmp = RREG32(mmDP_SEC_CNTL + dig->afmt->offset); 1667 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); 1668 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ATP_ENABLE, 1); 1669 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_AIP_ENABLE, 1); 1670 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1671 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, tmp); 1672 } else { 1673 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, 0); 1674 } 1675 } 1676 1677 static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder, 1678 struct drm_display_mode *mode) 1679 { 1680 struct drm_device *dev = encoder->dev; 1681 struct amdgpu_device *adev = drm_to_adev(dev); 1682 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1683 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1684 struct drm_connector *connector; 1685 struct drm_connector_list_iter iter; 1686 struct amdgpu_connector *amdgpu_connector = NULL; 1687 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 1688 int bpc = 8; 1689 1690 if (!dig || !dig->afmt) 1691 return; 1692 1693 drm_connector_list_iter_begin(dev, &iter); 1694 drm_for_each_connector_iter(connector, &iter) { 1695 if (connector->encoder == encoder) { 1696 amdgpu_connector = to_amdgpu_connector(connector); 1697 break; 1698 } 1699 } 1700 drm_connector_list_iter_end(&iter); 1701 1702 if (!amdgpu_connector) { 1703 DRM_ERROR("Couldn't find encoder's connector\n"); 1704 return; 1705 } 1706 1707 if (!dig->afmt->enabled) 1708 return; 1709 1710 dig->afmt->pin = dce_v6_0_audio_get_pin(adev); 1711 if (!dig->afmt->pin) 1712 return; 1713 1714 if (encoder->crtc) { 1715 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1716 bpc = amdgpu_crtc->bpc; 1717 } 1718 1719 /* disable audio before setting up hw */ 1720 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); 1721 1722 dce_v6_0_audio_set_mute(encoder, true); 1723 dce_v6_0_audio_write_speaker_allocation(encoder); 1724 dce_v6_0_audio_write_sad_regs(encoder); 1725 dce_v6_0_audio_write_latency_fields(encoder, mode); 1726 if (em == ATOM_ENCODER_MODE_HDMI) { 1727 dce_v6_0_audio_set_dto(encoder, mode->clock); 1728 dce_v6_0_audio_set_vbi_packet(encoder); 1729 dce_v6_0_audio_set_acr(encoder, mode->clock, bpc); 1730 } else if (ENCODER_MODE_IS_DP(em)) { 1731 dce_v6_0_audio_set_dto(encoder, adev->clock.default_dispclk * 10); 1732 } 1733 dce_v6_0_audio_set_packet(encoder); 1734 dce_v6_0_audio_select_pin(encoder); 1735 dce_v6_0_audio_set_avi_infoframe(encoder, mode); 1736 dce_v6_0_audio_set_mute(encoder, false); 1737 if (em == ATOM_ENCODER_MODE_HDMI) { 1738 dce_v6_0_audio_hdmi_enable(encoder, 1); 1739 } else if (ENCODER_MODE_IS_DP(em)) { 1740 dce_v6_0_audio_dp_enable(encoder, 1); 1741 } 1742 1743 /* enable audio after setting up hw */ 1744 dce_v6_0_audio_enable(adev, dig->afmt->pin, true); 1745 } 1746 1747 static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1748 { 1749 struct drm_device *dev = encoder->dev; 1750 struct amdgpu_device *adev = drm_to_adev(dev); 1751 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1752 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1753 1754 if (!dig || !dig->afmt) 1755 return; 1756 1757 /* Silent, r600_hdmi_enable will raise WARN for us */ 1758 if (enable && dig->afmt->enabled) 1759 return; 1760 1761 if (!enable && !dig->afmt->enabled) 1762 return; 1763 1764 if (!enable && dig->afmt->pin) { 1765 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); 1766 dig->afmt->pin = NULL; 1767 } 1768 1769 dig->afmt->enabled = enable; 1770 1771 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1772 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1773 } 1774 1775 static int dce_v6_0_afmt_init(struct amdgpu_device *adev) 1776 { 1777 int i, j; 1778 1779 for (i = 0; i < adev->mode_info.num_dig; i++) 1780 adev->mode_info.afmt[i] = NULL; 1781 1782 /* DCE6 has audio blocks tied to DIG encoders */ 1783 for (i = 0; i < adev->mode_info.num_dig; i++) { 1784 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1785 if (adev->mode_info.afmt[i]) { 1786 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1787 adev->mode_info.afmt[i]->id = i; 1788 } else { 1789 for (j = 0; j < i; j++) { 1790 kfree(adev->mode_info.afmt[j]); 1791 adev->mode_info.afmt[j] = NULL; 1792 } 1793 DRM_ERROR("Out of memory allocating afmt table\n"); 1794 return -ENOMEM; 1795 } 1796 } 1797 return 0; 1798 } 1799 1800 static void dce_v6_0_afmt_fini(struct amdgpu_device *adev) 1801 { 1802 int i; 1803 1804 for (i = 0; i < adev->mode_info.num_dig; i++) { 1805 kfree(adev->mode_info.afmt[i]); 1806 adev->mode_info.afmt[i] = NULL; 1807 } 1808 } 1809 1810 static const u32 vga_control_regs[6] = 1811 { 1812 mmD1VGA_CONTROL, 1813 mmD2VGA_CONTROL, 1814 mmD3VGA_CONTROL, 1815 mmD4VGA_CONTROL, 1816 mmD5VGA_CONTROL, 1817 mmD6VGA_CONTROL, 1818 }; 1819 1820 static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable) 1821 { 1822 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1823 struct drm_device *dev = crtc->dev; 1824 struct amdgpu_device *adev = drm_to_adev(dev); 1825 u32 vga_control; 1826 1827 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 1828 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0)); 1829 } 1830 1831 static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable) 1832 { 1833 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1834 struct drm_device *dev = crtc->dev; 1835 struct amdgpu_device *adev = drm_to_adev(dev); 1836 1837 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); 1838 } 1839 1840 static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, 1841 struct drm_framebuffer *fb, 1842 int x, int y, int atomic) 1843 { 1844 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1845 struct drm_device *dev = crtc->dev; 1846 struct amdgpu_device *adev = drm_to_adev(dev); 1847 struct drm_framebuffer *target_fb; 1848 struct drm_gem_object *obj; 1849 struct amdgpu_bo *abo; 1850 uint64_t fb_location, tiling_flags; 1851 uint32_t fb_format, fb_pitch_pixels, pipe_config; 1852 u32 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_NONE); 1853 u32 viewport_w, viewport_h; 1854 int r; 1855 bool bypass_lut = false; 1856 1857 /* no fb bound */ 1858 if (!atomic && !crtc->primary->fb) { 1859 DRM_DEBUG_KMS("No FB bound\n"); 1860 return 0; 1861 } 1862 1863 if (atomic) 1864 target_fb = fb; 1865 else 1866 target_fb = crtc->primary->fb; 1867 1868 /* If atomic, assume fb object is pinned & idle & fenced and 1869 * just update base pointers 1870 */ 1871 obj = target_fb->obj[0]; 1872 abo = gem_to_amdgpu_bo(obj); 1873 r = amdgpu_bo_reserve(abo, false); 1874 if (unlikely(r != 0)) 1875 return r; 1876 1877 if (!atomic) { 1878 abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 1879 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); 1880 if (unlikely(r != 0)) { 1881 amdgpu_bo_unreserve(abo); 1882 return -EINVAL; 1883 } 1884 } 1885 fb_location = amdgpu_bo_gpu_offset(abo); 1886 1887 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1888 amdgpu_bo_unreserve(abo); 1889 1890 switch (target_fb->format->format) { 1891 case DRM_FORMAT_C8: 1892 fb_format = (GRPH_DEPTH(GRPH_DEPTH_8BPP) | 1893 GRPH_FORMAT(GRPH_FORMAT_INDEXED)); 1894 break; 1895 case DRM_FORMAT_XRGB4444: 1896 case DRM_FORMAT_ARGB4444: 1897 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 1898 GRPH_FORMAT(GRPH_FORMAT_ARGB4444)); 1899 #ifdef __BIG_ENDIAN 1900 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 1901 #endif 1902 break; 1903 case DRM_FORMAT_XRGB1555: 1904 case DRM_FORMAT_ARGB1555: 1905 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 1906 GRPH_FORMAT(GRPH_FORMAT_ARGB1555)); 1907 #ifdef __BIG_ENDIAN 1908 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 1909 #endif 1910 break; 1911 case DRM_FORMAT_BGRX5551: 1912 case DRM_FORMAT_BGRA5551: 1913 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 1914 GRPH_FORMAT(GRPH_FORMAT_BGRA5551)); 1915 #ifdef __BIG_ENDIAN 1916 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 1917 #endif 1918 break; 1919 case DRM_FORMAT_RGB565: 1920 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 1921 GRPH_FORMAT(GRPH_FORMAT_ARGB565)); 1922 #ifdef __BIG_ENDIAN 1923 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 1924 #endif 1925 break; 1926 case DRM_FORMAT_XRGB8888: 1927 case DRM_FORMAT_ARGB8888: 1928 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 1929 GRPH_FORMAT(GRPH_FORMAT_ARGB8888)); 1930 #ifdef __BIG_ENDIAN 1931 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 1932 #endif 1933 break; 1934 case DRM_FORMAT_XRGB2101010: 1935 case DRM_FORMAT_ARGB2101010: 1936 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 1937 GRPH_FORMAT(GRPH_FORMAT_ARGB2101010)); 1938 #ifdef __BIG_ENDIAN 1939 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 1940 #endif 1941 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1942 bypass_lut = true; 1943 break; 1944 case DRM_FORMAT_BGRX1010102: 1945 case DRM_FORMAT_BGRA1010102: 1946 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 1947 GRPH_FORMAT(GRPH_FORMAT_BGRA1010102)); 1948 #ifdef __BIG_ENDIAN 1949 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 1950 #endif 1951 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1952 bypass_lut = true; 1953 break; 1954 case DRM_FORMAT_XBGR8888: 1955 case DRM_FORMAT_ABGR8888: 1956 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 1957 GRPH_FORMAT(GRPH_FORMAT_ARGB8888)); 1958 fb_swap = (GRPH_RED_CROSSBAR(GRPH_RED_SEL_B) | 1959 GRPH_BLUE_CROSSBAR(GRPH_BLUE_SEL_R)); 1960 #ifdef __BIG_ENDIAN 1961 fb_swap |= GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 1962 #endif 1963 break; 1964 default: 1965 DRM_ERROR("Unsupported screen format %p4cc\n", 1966 &target_fb->format->format); 1967 return -EINVAL; 1968 } 1969 1970 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 1971 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 1972 1973 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 1974 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 1975 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 1976 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 1977 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 1978 1979 fb_format |= GRPH_NUM_BANKS(num_banks); 1980 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_2D_TILED_THIN1); 1981 fb_format |= GRPH_TILE_SPLIT(tile_split); 1982 fb_format |= GRPH_BANK_WIDTH(bankw); 1983 fb_format |= GRPH_BANK_HEIGHT(bankh); 1984 fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect); 1985 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 1986 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_1D_TILED_THIN1); 1987 } 1988 1989 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 1990 fb_format |= GRPH_PIPE_CONFIG(pipe_config); 1991 1992 dce_v6_0_vga_enable(crtc, false); 1993 1994 /* Make sure surface address is updated at vertical blank rather than 1995 * horizontal blank 1996 */ 1997 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); 1998 1999 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2000 upper_32_bits(fb_location)); 2001 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2002 upper_32_bits(fb_location)); 2003 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2004 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2005 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2006 (u32) fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2007 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2008 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2009 2010 /* 2011 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2012 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2013 * retain the full precision throughout the pipeline. 2014 */ 2015 WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, 2016 (bypass_lut ? GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK : 0), 2017 ~GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK); 2018 2019 if (bypass_lut) 2020 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2021 2022 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2023 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2024 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2025 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2026 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2027 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2028 2029 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 2030 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2031 2032 dce_v6_0_grph_enable(crtc, true); 2033 2034 WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2035 target_fb->height); 2036 x &= ~3; 2037 y &= ~1; 2038 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2039 (x << 16) | y); 2040 viewport_w = crtc->mode.hdisplay; 2041 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2042 2043 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2044 (viewport_w << 16) | viewport_h); 2045 2046 /* set pageflip to happen anywhere in vblank interval */ 2047 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); 2048 2049 if (!atomic && fb && fb != crtc->primary->fb) { 2050 abo = gem_to_amdgpu_bo(fb->obj[0]); 2051 r = amdgpu_bo_reserve(abo, true); 2052 if (unlikely(r != 0)) 2053 return r; 2054 amdgpu_bo_unpin(abo); 2055 amdgpu_bo_unreserve(abo); 2056 } 2057 2058 /* Bytes per pixel may have changed */ 2059 dce_v6_0_bandwidth_update(adev); 2060 2061 return 0; 2062 2063 } 2064 2065 static void dce_v6_0_set_interleave(struct drm_crtc *crtc, 2066 struct drm_display_mode *mode) 2067 { 2068 struct drm_device *dev = crtc->dev; 2069 struct amdgpu_device *adev = drm_to_adev(dev); 2070 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2071 2072 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2073 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 2074 INTERLEAVE_EN); 2075 else 2076 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0); 2077 } 2078 2079 static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc) 2080 { 2081 2082 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2083 struct drm_device *dev = crtc->dev; 2084 struct amdgpu_device *adev = drm_to_adev(dev); 2085 u16 *r, *g, *b; 2086 int i; 2087 2088 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2089 2090 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 2091 ((0 << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) | 2092 (0 << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT))); 2093 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, 2094 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK); 2095 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, 2096 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK); 2097 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2098 ((0 << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) | 2099 (0 << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT))); 2100 2101 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2102 2103 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2104 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2105 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2106 2107 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2108 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2109 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2110 2111 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2112 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2113 2114 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2115 r = crtc->gamma_store; 2116 g = r + crtc->gamma_size; 2117 b = g + crtc->gamma_size; 2118 for (i = 0; i < 256; i++) { 2119 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2120 ((*r++ & 0xffc0) << 14) | 2121 ((*g++ & 0xffc0) << 4) | 2122 (*b++ >> 6)); 2123 } 2124 2125 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2126 ((0 << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) | 2127 (0 << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) | 2128 ICON_DEGAMMA_MODE(0) | 2129 (0 << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT))); 2130 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, 2131 ((0 << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) | 2132 (0 << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT))); 2133 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2134 ((0 << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) | 2135 (0 << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT))); 2136 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 2137 ((0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) | 2138 (0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT))); 2139 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2140 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); 2141 2142 2143 } 2144 2145 static int dce_v6_0_pick_dig_encoder(struct drm_encoder *encoder) 2146 { 2147 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2148 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2149 2150 switch (amdgpu_encoder->encoder_id) { 2151 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2152 return dig->linkb ? 1 : 0; 2153 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2154 return dig->linkb ? 3 : 2; 2155 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2156 return dig->linkb ? 5 : 4; 2157 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2158 return 6; 2159 default: 2160 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2161 return 0; 2162 } 2163 } 2164 2165 /** 2166 * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc. 2167 * 2168 * @crtc: drm crtc 2169 * 2170 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2171 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2172 * monitors a dedicated PPLL must be used. If a particular board has 2173 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2174 * as there is no need to program the PLL itself. If we are not able to 2175 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2176 * avoid messing up an existing monitor. 2177 * 2178 * 2179 */ 2180 static u32 dce_v6_0_pick_pll(struct drm_crtc *crtc) 2181 { 2182 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2183 struct drm_device *dev = crtc->dev; 2184 struct amdgpu_device *adev = drm_to_adev(dev); 2185 u32 pll_in_use; 2186 int pll; 2187 2188 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2189 if (adev->clock.dp_extclk) 2190 /* skip PPLL programming if using ext clock */ 2191 return ATOM_PPLL_INVALID; 2192 else 2193 return ATOM_PPLL0; 2194 } else { 2195 /* use the same PPLL for all monitors with the same clock */ 2196 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2197 if (pll != ATOM_PPLL_INVALID) 2198 return pll; 2199 } 2200 2201 /* PPLL1, and PPLL2 */ 2202 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2203 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2204 return ATOM_PPLL2; 2205 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2206 return ATOM_PPLL1; 2207 DRM_ERROR("unable to allocate a PPLL\n"); 2208 return ATOM_PPLL_INVALID; 2209 } 2210 2211 static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2212 { 2213 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2214 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2215 uint32_t cur_lock; 2216 2217 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2218 if (lock) 2219 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 2220 else 2221 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 2222 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2223 } 2224 2225 static void dce_v6_0_hide_cursor(struct drm_crtc *crtc) 2226 { 2227 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2228 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2229 2230 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 2231 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 2232 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 2233 2234 2235 } 2236 2237 static void dce_v6_0_show_cursor(struct drm_crtc *crtc) 2238 { 2239 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2240 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2241 2242 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2243 upper_32_bits(amdgpu_crtc->cursor_addr)); 2244 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2245 lower_32_bits(amdgpu_crtc->cursor_addr)); 2246 2247 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 2248 CUR_CONTROL__CURSOR_EN_MASK | 2249 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 2250 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 2251 2252 } 2253 2254 static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc, 2255 int x, int y) 2256 { 2257 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2258 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2259 int xorigin = 0, yorigin = 0; 2260 2261 int w = amdgpu_crtc->cursor_width; 2262 2263 amdgpu_crtc->cursor_x = x; 2264 amdgpu_crtc->cursor_y = y; 2265 2266 /* avivo cursor are offset into the total surface */ 2267 x += crtc->x; 2268 y += crtc->y; 2269 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2270 2271 if (x < 0) { 2272 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2273 x = 0; 2274 } 2275 if (y < 0) { 2276 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2277 y = 0; 2278 } 2279 2280 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2281 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2282 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2283 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2284 2285 return 0; 2286 } 2287 2288 static int dce_v6_0_crtc_cursor_move(struct drm_crtc *crtc, 2289 int x, int y) 2290 { 2291 int ret; 2292 2293 dce_v6_0_lock_cursor(crtc, true); 2294 ret = dce_v6_0_cursor_move_locked(crtc, x, y); 2295 dce_v6_0_lock_cursor(crtc, false); 2296 2297 return ret; 2298 } 2299 2300 static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, 2301 struct drm_file *file_priv, 2302 uint32_t handle, 2303 uint32_t width, 2304 uint32_t height, 2305 int32_t hot_x, 2306 int32_t hot_y) 2307 { 2308 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2309 struct drm_gem_object *obj; 2310 struct amdgpu_bo *aobj; 2311 int ret; 2312 2313 if (!handle) { 2314 /* turn off cursor */ 2315 dce_v6_0_hide_cursor(crtc); 2316 obj = NULL; 2317 goto unpin; 2318 } 2319 2320 if ((width > amdgpu_crtc->max_cursor_width) || 2321 (height > amdgpu_crtc->max_cursor_height)) { 2322 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2323 return -EINVAL; 2324 } 2325 2326 obj = drm_gem_object_lookup(file_priv, handle); 2327 if (!obj) { 2328 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2329 return -ENOENT; 2330 } 2331 2332 aobj = gem_to_amdgpu_bo(obj); 2333 ret = amdgpu_bo_reserve(aobj, false); 2334 if (ret != 0) { 2335 drm_gem_object_put(obj); 2336 return ret; 2337 } 2338 2339 aobj->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 2340 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); 2341 amdgpu_bo_unreserve(aobj); 2342 if (ret) { 2343 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2344 drm_gem_object_put(obj); 2345 return ret; 2346 } 2347 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); 2348 2349 dce_v6_0_lock_cursor(crtc, true); 2350 2351 if (width != amdgpu_crtc->cursor_width || 2352 height != amdgpu_crtc->cursor_height || 2353 hot_x != amdgpu_crtc->cursor_hot_x || 2354 hot_y != amdgpu_crtc->cursor_hot_y) { 2355 int x, y; 2356 2357 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2358 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2359 2360 dce_v6_0_cursor_move_locked(crtc, x, y); 2361 2362 amdgpu_crtc->cursor_width = width; 2363 amdgpu_crtc->cursor_height = height; 2364 amdgpu_crtc->cursor_hot_x = hot_x; 2365 amdgpu_crtc->cursor_hot_y = hot_y; 2366 } 2367 2368 dce_v6_0_show_cursor(crtc); 2369 dce_v6_0_lock_cursor(crtc, false); 2370 2371 unpin: 2372 if (amdgpu_crtc->cursor_bo) { 2373 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2374 ret = amdgpu_bo_reserve(aobj, true); 2375 if (likely(ret == 0)) { 2376 amdgpu_bo_unpin(aobj); 2377 amdgpu_bo_unreserve(aobj); 2378 } 2379 drm_gem_object_put(amdgpu_crtc->cursor_bo); 2380 } 2381 2382 amdgpu_crtc->cursor_bo = obj; 2383 return 0; 2384 } 2385 2386 static void dce_v6_0_cursor_reset(struct drm_crtc *crtc) 2387 { 2388 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2389 2390 if (amdgpu_crtc->cursor_bo) { 2391 dce_v6_0_lock_cursor(crtc, true); 2392 2393 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2394 amdgpu_crtc->cursor_y); 2395 2396 dce_v6_0_show_cursor(crtc); 2397 dce_v6_0_lock_cursor(crtc, false); 2398 } 2399 } 2400 2401 static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2402 u16 *blue, uint32_t size, 2403 struct drm_modeset_acquire_ctx *ctx) 2404 { 2405 dce_v6_0_crtc_load_lut(crtc); 2406 2407 return 0; 2408 } 2409 2410 static void dce_v6_0_crtc_destroy(struct drm_crtc *crtc) 2411 { 2412 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2413 2414 drm_crtc_cleanup(crtc); 2415 kfree(amdgpu_crtc); 2416 } 2417 2418 static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = { 2419 .cursor_set2 = dce_v6_0_crtc_cursor_set2, 2420 .cursor_move = dce_v6_0_crtc_cursor_move, 2421 .gamma_set = dce_v6_0_crtc_gamma_set, 2422 .set_config = amdgpu_display_crtc_set_config, 2423 .destroy = dce_v6_0_crtc_destroy, 2424 .page_flip_target = amdgpu_display_crtc_page_flip_target, 2425 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 2426 .enable_vblank = amdgpu_enable_vblank_kms, 2427 .disable_vblank = amdgpu_disable_vblank_kms, 2428 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 2429 }; 2430 2431 static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2432 { 2433 struct drm_device *dev = crtc->dev; 2434 struct amdgpu_device *adev = drm_to_adev(dev); 2435 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2436 unsigned type; 2437 2438 switch (mode) { 2439 case DRM_MODE_DPMS_ON: 2440 amdgpu_crtc->enabled = true; 2441 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2442 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2443 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2444 type = amdgpu_display_crtc_idx_to_irq_type(adev, 2445 amdgpu_crtc->crtc_id); 2446 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2447 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2448 drm_crtc_vblank_on(crtc); 2449 dce_v6_0_crtc_load_lut(crtc); 2450 break; 2451 case DRM_MODE_DPMS_STANDBY: 2452 case DRM_MODE_DPMS_SUSPEND: 2453 case DRM_MODE_DPMS_OFF: 2454 drm_crtc_vblank_off(crtc); 2455 if (amdgpu_crtc->enabled) 2456 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2457 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2458 amdgpu_crtc->enabled = false; 2459 break; 2460 } 2461 /* adjust pm to dpms */ 2462 amdgpu_dpm_compute_clocks(adev); 2463 } 2464 2465 static void dce_v6_0_crtc_prepare(struct drm_crtc *crtc) 2466 { 2467 /* disable crtc pair power gating before programming */ 2468 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2469 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2470 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2471 } 2472 2473 static void dce_v6_0_crtc_commit(struct drm_crtc *crtc) 2474 { 2475 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2476 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2477 } 2478 2479 static void dce_v6_0_crtc_disable(struct drm_crtc *crtc) 2480 { 2481 2482 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2483 struct drm_device *dev = crtc->dev; 2484 struct amdgpu_device *adev = drm_to_adev(dev); 2485 struct amdgpu_atom_ss ss; 2486 int i; 2487 2488 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2489 if (crtc->primary->fb) { 2490 int r; 2491 struct amdgpu_bo *abo; 2492 2493 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); 2494 r = amdgpu_bo_reserve(abo, true); 2495 if (unlikely(r)) 2496 DRM_ERROR("failed to reserve abo before unpin\n"); 2497 else { 2498 amdgpu_bo_unpin(abo); 2499 amdgpu_bo_unreserve(abo); 2500 } 2501 } 2502 /* disable the GRPH */ 2503 dce_v6_0_grph_enable(crtc, false); 2504 2505 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2506 2507 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2508 if (adev->mode_info.crtcs[i] && 2509 adev->mode_info.crtcs[i]->enabled && 2510 i != amdgpu_crtc->crtc_id && 2511 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2512 /* one other crtc is using this pll don't turn 2513 * off the pll 2514 */ 2515 goto done; 2516 } 2517 } 2518 2519 switch (amdgpu_crtc->pll_id) { 2520 case ATOM_PPLL1: 2521 case ATOM_PPLL2: 2522 /* disable the ppll */ 2523 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2524 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2525 break; 2526 default: 2527 break; 2528 } 2529 done: 2530 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2531 amdgpu_crtc->adjusted_clock = 0; 2532 amdgpu_crtc->encoder = NULL; 2533 amdgpu_crtc->connector = NULL; 2534 } 2535 2536 static int dce_v6_0_crtc_mode_set(struct drm_crtc *crtc, 2537 struct drm_display_mode *mode, 2538 struct drm_display_mode *adjusted_mode, 2539 int x, int y, struct drm_framebuffer *old_fb) 2540 { 2541 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2542 2543 if (!amdgpu_crtc->adjusted_clock) 2544 return -EINVAL; 2545 2546 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2547 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2548 dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2549 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2550 amdgpu_atombios_crtc_scaler_setup(crtc); 2551 dce_v6_0_cursor_reset(crtc); 2552 /* update the hw version fpr dpm */ 2553 amdgpu_crtc->hw_mode = *adjusted_mode; 2554 2555 return 0; 2556 } 2557 2558 static bool dce_v6_0_crtc_mode_fixup(struct drm_crtc *crtc, 2559 const struct drm_display_mode *mode, 2560 struct drm_display_mode *adjusted_mode) 2561 { 2562 2563 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2564 struct drm_device *dev = crtc->dev; 2565 struct drm_encoder *encoder; 2566 2567 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2568 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2569 if (encoder->crtc == crtc) { 2570 amdgpu_crtc->encoder = encoder; 2571 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2572 break; 2573 } 2574 } 2575 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2576 amdgpu_crtc->encoder = NULL; 2577 amdgpu_crtc->connector = NULL; 2578 return false; 2579 } 2580 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2581 return false; 2582 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2583 return false; 2584 /* pick pll */ 2585 amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc); 2586 /* if we can't get a PPLL for a non-DP encoder, fail */ 2587 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2588 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2589 return false; 2590 2591 return true; 2592 } 2593 2594 static int dce_v6_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2595 struct drm_framebuffer *old_fb) 2596 { 2597 return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2598 } 2599 2600 static int dce_v6_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2601 struct drm_framebuffer *fb, 2602 int x, int y, enum mode_set_atomic state) 2603 { 2604 return dce_v6_0_crtc_do_set_base(crtc, fb, x, y, 1); 2605 } 2606 2607 static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = { 2608 .dpms = dce_v6_0_crtc_dpms, 2609 .mode_fixup = dce_v6_0_crtc_mode_fixup, 2610 .mode_set = dce_v6_0_crtc_mode_set, 2611 .mode_set_base = dce_v6_0_crtc_set_base, 2612 .mode_set_base_atomic = dce_v6_0_crtc_set_base_atomic, 2613 .prepare = dce_v6_0_crtc_prepare, 2614 .commit = dce_v6_0_crtc_commit, 2615 .disable = dce_v6_0_crtc_disable, 2616 .get_scanout_position = amdgpu_crtc_get_scanout_position, 2617 }; 2618 2619 static void dce_v6_0_panic_flush(struct drm_plane *plane) 2620 { 2621 struct drm_framebuffer *fb; 2622 struct amdgpu_crtc *amdgpu_crtc; 2623 struct amdgpu_device *adev; 2624 uint32_t fb_format; 2625 2626 if (!plane->fb) 2627 return; 2628 2629 fb = plane->fb; 2630 amdgpu_crtc = to_amdgpu_crtc(plane->crtc); 2631 adev = drm_to_adev(fb->dev); 2632 2633 /* Disable DC tiling */ 2634 fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset); 2635 fb_format &= ~GRPH_ARRAY_MODE(0x7); 2636 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2637 2638 } 2639 2640 static const struct drm_plane_helper_funcs dce_v6_0_drm_primary_plane_helper_funcs = { 2641 .get_scanout_buffer = amdgpu_display_get_scanout_buffer, 2642 .panic_flush = dce_v6_0_panic_flush, 2643 }; 2644 2645 static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index) 2646 { 2647 struct amdgpu_crtc *amdgpu_crtc; 2648 2649 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2650 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2651 if (amdgpu_crtc == NULL) 2652 return -ENOMEM; 2653 2654 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v6_0_crtc_funcs); 2655 2656 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2657 amdgpu_crtc->crtc_id = index; 2658 adev->mode_info.crtcs[index] = amdgpu_crtc; 2659 2660 amdgpu_crtc->max_cursor_width = CURSOR_WIDTH; 2661 amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT; 2662 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2663 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2664 2665 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; 2666 2667 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2668 amdgpu_crtc->adjusted_clock = 0; 2669 amdgpu_crtc->encoder = NULL; 2670 amdgpu_crtc->connector = NULL; 2671 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs); 2672 drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v6_0_drm_primary_plane_helper_funcs); 2673 2674 return 0; 2675 } 2676 2677 static int dce_v6_0_early_init(struct amdgpu_ip_block *ip_block) 2678 { 2679 struct amdgpu_device *adev = ip_block->adev; 2680 2681 adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg; 2682 adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg; 2683 2684 dce_v6_0_set_display_funcs(adev); 2685 2686 adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev); 2687 2688 switch (adev->asic_type) { 2689 case CHIP_TAHITI: 2690 case CHIP_PITCAIRN: 2691 case CHIP_VERDE: 2692 adev->mode_info.num_hpd = 6; 2693 adev->mode_info.num_dig = 6; 2694 break; 2695 case CHIP_OLAND: 2696 adev->mode_info.num_hpd = 2; 2697 adev->mode_info.num_dig = 2; 2698 break; 2699 default: 2700 return -EINVAL; 2701 } 2702 2703 dce_v6_0_set_irq_funcs(adev); 2704 2705 return 0; 2706 } 2707 2708 static int dce_v6_0_sw_init(struct amdgpu_ip_block *ip_block) 2709 { 2710 int r, i; 2711 bool ret; 2712 struct amdgpu_device *adev = ip_block->adev; 2713 2714 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2715 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); 2716 if (r) 2717 return r; 2718 } 2719 2720 for (i = 8; i < 20; i += 2) { 2721 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq); 2722 if (r) 2723 return r; 2724 } 2725 2726 /* HPD hotplug */ 2727 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq); 2728 if (r) 2729 return r; 2730 2731 adev->mode_info.mode_config_initialized = true; 2732 2733 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs; 2734 adev_to_drm(adev)->mode_config.async_page_flip = true; 2735 adev_to_drm(adev)->mode_config.max_width = 16384; 2736 adev_to_drm(adev)->mode_config.max_height = 16384; 2737 adev_to_drm(adev)->mode_config.preferred_depth = 24; 2738 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 2739 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; 2740 2741 r = amdgpu_display_modeset_create_props(adev); 2742 if (r) 2743 return r; 2744 2745 adev_to_drm(adev)->mode_config.max_width = 16384; 2746 adev_to_drm(adev)->mode_config.max_height = 16384; 2747 2748 /* allocate crtcs */ 2749 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2750 r = dce_v6_0_crtc_init(adev, i); 2751 if (r) 2752 return r; 2753 } 2754 2755 ret = amdgpu_atombios_get_connector_info_from_object_table(adev); 2756 if (ret) 2757 amdgpu_display_print_display_setup(adev_to_drm(adev)); 2758 else 2759 return -EINVAL; 2760 2761 /* setup afmt */ 2762 r = dce_v6_0_afmt_init(adev); 2763 if (r) 2764 return r; 2765 2766 r = dce_v6_0_audio_init(adev); 2767 if (r) 2768 return r; 2769 2770 /* Disable vblank IRQs aggressively for power-saving */ 2771 /* XXX: can this be enabled for DC? */ 2772 adev_to_drm(adev)->vblank_disable_immediate = true; 2773 2774 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc); 2775 if (r) 2776 return r; 2777 2778 /* Pre-DCE11 */ 2779 INIT_DELAYED_WORK(&adev->hotplug_work, 2780 amdgpu_display_hotplug_work_func); 2781 2782 drm_kms_helper_poll_init(adev_to_drm(adev)); 2783 2784 return r; 2785 } 2786 2787 static int dce_v6_0_sw_fini(struct amdgpu_ip_block *ip_block) 2788 { 2789 struct amdgpu_device *adev = ip_block->adev; 2790 2791 drm_edid_free(adev->mode_info.bios_hardcoded_edid); 2792 2793 drm_kms_helper_poll_fini(adev_to_drm(adev)); 2794 2795 dce_v6_0_audio_fini(adev); 2796 dce_v6_0_afmt_fini(adev); 2797 2798 drm_mode_config_cleanup(adev_to_drm(adev)); 2799 adev->mode_info.mode_config_initialized = false; 2800 2801 return 0; 2802 } 2803 2804 static int dce_v6_0_hw_init(struct amdgpu_ip_block *ip_block) 2805 { 2806 int i; 2807 struct amdgpu_device *adev = ip_block->adev; 2808 2809 /* disable vga render */ 2810 dce_v6_0_set_vga_render_state(adev, false); 2811 /* init dig PHYs, disp eng pll */ 2812 amdgpu_atombios_encoder_init_dig(adev); 2813 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 2814 2815 /* initialize hpd */ 2816 dce_v6_0_hpd_init(adev); 2817 2818 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2819 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2820 } 2821 2822 dce_v6_0_pageflip_interrupt_init(adev); 2823 2824 return 0; 2825 } 2826 2827 static int dce_v6_0_hw_fini(struct amdgpu_ip_block *ip_block) 2828 { 2829 int i; 2830 struct amdgpu_device *adev = ip_block->adev; 2831 2832 dce_v6_0_hpd_fini(adev); 2833 2834 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2835 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2836 } 2837 2838 dce_v6_0_pageflip_interrupt_fini(adev); 2839 2840 flush_delayed_work(&adev->hotplug_work); 2841 2842 return 0; 2843 } 2844 2845 static int dce_v6_0_suspend(struct amdgpu_ip_block *ip_block) 2846 { 2847 struct amdgpu_device *adev = ip_block->adev; 2848 int r; 2849 2850 r = amdgpu_display_suspend_helper(adev); 2851 if (r) 2852 return r; 2853 adev->mode_info.bl_level = 2854 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); 2855 2856 return dce_v6_0_hw_fini(ip_block); 2857 } 2858 2859 static int dce_v6_0_resume(struct amdgpu_ip_block *ip_block) 2860 { 2861 struct amdgpu_device *adev = ip_block->adev; 2862 int ret; 2863 2864 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, 2865 adev->mode_info.bl_level); 2866 2867 ret = dce_v6_0_hw_init(ip_block); 2868 2869 /* turn on the BL */ 2870 if (adev->mode_info.bl_encoder) { 2871 u8 bl_level = amdgpu_display_backlight_get_level(adev, 2872 adev->mode_info.bl_encoder); 2873 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 2874 bl_level); 2875 } 2876 if (ret) 2877 return ret; 2878 2879 return amdgpu_display_resume_helper(adev); 2880 } 2881 2882 static bool dce_v6_0_is_idle(struct amdgpu_ip_block *ip_block) 2883 { 2884 return true; 2885 } 2886 2887 static int dce_v6_0_soft_reset(struct amdgpu_ip_block *ip_block) 2888 { 2889 DRM_INFO("xxxx: dce_v6_0_soft_reset --- no impl!!\n"); 2890 return 0; 2891 } 2892 2893 static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 2894 int crtc, 2895 enum amdgpu_interrupt_state state) 2896 { 2897 u32 reg_block, interrupt_mask; 2898 2899 if (crtc >= adev->mode_info.num_crtc) { 2900 DRM_DEBUG("invalid crtc %d\n", crtc); 2901 return; 2902 } 2903 2904 switch (crtc) { 2905 case 0: 2906 reg_block = SI_CRTC0_REGISTER_OFFSET; 2907 break; 2908 case 1: 2909 reg_block = SI_CRTC1_REGISTER_OFFSET; 2910 break; 2911 case 2: 2912 reg_block = SI_CRTC2_REGISTER_OFFSET; 2913 break; 2914 case 3: 2915 reg_block = SI_CRTC3_REGISTER_OFFSET; 2916 break; 2917 case 4: 2918 reg_block = SI_CRTC4_REGISTER_OFFSET; 2919 break; 2920 case 5: 2921 reg_block = SI_CRTC5_REGISTER_OFFSET; 2922 break; 2923 default: 2924 DRM_DEBUG("invalid crtc %d\n", crtc); 2925 return; 2926 } 2927 2928 switch (state) { 2929 case AMDGPU_IRQ_STATE_DISABLE: 2930 interrupt_mask = RREG32(mmINT_MASK + reg_block); 2931 interrupt_mask &= ~VBLANK_INT_MASK; 2932 WREG32(mmINT_MASK + reg_block, interrupt_mask); 2933 break; 2934 case AMDGPU_IRQ_STATE_ENABLE: 2935 interrupt_mask = RREG32(mmINT_MASK + reg_block); 2936 interrupt_mask |= VBLANK_INT_MASK; 2937 WREG32(mmINT_MASK + reg_block, interrupt_mask); 2938 break; 2939 default: 2940 break; 2941 } 2942 } 2943 2944 static void dce_v6_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 2945 int crtc, 2946 enum amdgpu_interrupt_state state) 2947 { 2948 2949 } 2950 2951 static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev, 2952 struct amdgpu_irq_src *src, 2953 unsigned type, 2954 enum amdgpu_interrupt_state state) 2955 { 2956 u32 dc_hpd_int_cntl; 2957 2958 if (type >= adev->mode_info.num_hpd) { 2959 DRM_DEBUG("invalid hdp %d\n", type); 2960 return 0; 2961 } 2962 2963 switch (state) { 2964 case AMDGPU_IRQ_STATE_DISABLE: 2965 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); 2966 dc_hpd_int_cntl &= ~DC_HPDx_INT_EN; 2967 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 2968 break; 2969 case AMDGPU_IRQ_STATE_ENABLE: 2970 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); 2971 dc_hpd_int_cntl |= DC_HPDx_INT_EN; 2972 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 2973 break; 2974 default: 2975 break; 2976 } 2977 2978 return 0; 2979 } 2980 2981 static int dce_v6_0_set_crtc_interrupt_state(struct amdgpu_device *adev, 2982 struct amdgpu_irq_src *src, 2983 unsigned type, 2984 enum amdgpu_interrupt_state state) 2985 { 2986 switch (type) { 2987 case AMDGPU_CRTC_IRQ_VBLANK1: 2988 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 0, state); 2989 break; 2990 case AMDGPU_CRTC_IRQ_VBLANK2: 2991 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 1, state); 2992 break; 2993 case AMDGPU_CRTC_IRQ_VBLANK3: 2994 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 2, state); 2995 break; 2996 case AMDGPU_CRTC_IRQ_VBLANK4: 2997 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 3, state); 2998 break; 2999 case AMDGPU_CRTC_IRQ_VBLANK5: 3000 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3001 break; 3002 case AMDGPU_CRTC_IRQ_VBLANK6: 3003 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3004 break; 3005 case AMDGPU_CRTC_IRQ_VLINE1: 3006 dce_v6_0_set_crtc_vline_interrupt_state(adev, 0, state); 3007 break; 3008 case AMDGPU_CRTC_IRQ_VLINE2: 3009 dce_v6_0_set_crtc_vline_interrupt_state(adev, 1, state); 3010 break; 3011 case AMDGPU_CRTC_IRQ_VLINE3: 3012 dce_v6_0_set_crtc_vline_interrupt_state(adev, 2, state); 3013 break; 3014 case AMDGPU_CRTC_IRQ_VLINE4: 3015 dce_v6_0_set_crtc_vline_interrupt_state(adev, 3, state); 3016 break; 3017 case AMDGPU_CRTC_IRQ_VLINE5: 3018 dce_v6_0_set_crtc_vline_interrupt_state(adev, 4, state); 3019 break; 3020 case AMDGPU_CRTC_IRQ_VLINE6: 3021 dce_v6_0_set_crtc_vline_interrupt_state(adev, 5, state); 3022 break; 3023 default: 3024 break; 3025 } 3026 return 0; 3027 } 3028 3029 static int dce_v6_0_crtc_irq(struct amdgpu_device *adev, 3030 struct amdgpu_irq_src *source, 3031 struct amdgpu_iv_entry *entry) 3032 { 3033 unsigned crtc = entry->src_id - 1; 3034 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3035 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, 3036 crtc); 3037 3038 switch (entry->src_data[0]) { 3039 case 0: /* vblank */ 3040 if (disp_int & interrupt_status_offsets[crtc].vblank) 3041 WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK); 3042 else 3043 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3044 3045 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3046 drm_handle_vblank(adev_to_drm(adev), crtc); 3047 } 3048 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3049 break; 3050 case 1: /* vline */ 3051 if (disp_int & interrupt_status_offsets[crtc].vline) 3052 WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK); 3053 else 3054 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3055 3056 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3057 break; 3058 default: 3059 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3060 break; 3061 } 3062 3063 return 0; 3064 } 3065 3066 static int dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device *adev, 3067 struct amdgpu_irq_src *src, 3068 unsigned type, 3069 enum amdgpu_interrupt_state state) 3070 { 3071 u32 reg; 3072 3073 if (type >= adev->mode_info.num_crtc) { 3074 DRM_ERROR("invalid pageflip crtc %d\n", type); 3075 return -EINVAL; 3076 } 3077 3078 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3079 if (state == AMDGPU_IRQ_STATE_DISABLE) 3080 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3081 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3082 else 3083 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3084 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3085 3086 return 0; 3087 } 3088 3089 static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev, 3090 struct amdgpu_irq_src *source, 3091 struct amdgpu_iv_entry *entry) 3092 { 3093 unsigned long flags; 3094 unsigned crtc_id; 3095 struct amdgpu_crtc *amdgpu_crtc; 3096 struct amdgpu_flip_work *works; 3097 3098 crtc_id = (entry->src_id - 8) >> 1; 3099 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3100 3101 if (crtc_id >= adev->mode_info.num_crtc) { 3102 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3103 return -EINVAL; 3104 } 3105 3106 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3107 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3108 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3109 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3110 3111 /* IRQ could occur when in initial stage */ 3112 if (amdgpu_crtc == NULL) 3113 return 0; 3114 3115 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 3116 works = amdgpu_crtc->pflip_works; 3117 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 3118 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3119 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3120 amdgpu_crtc->pflip_status, 3121 AMDGPU_FLIP_SUBMITTED); 3122 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3123 return 0; 3124 } 3125 3126 /* page flip completed. clean up */ 3127 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3128 amdgpu_crtc->pflip_works = NULL; 3129 3130 /* wakeup usersapce */ 3131 if (works->event) 3132 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); 3133 3134 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3135 3136 drm_crtc_vblank_put(&amdgpu_crtc->base); 3137 schedule_work(&works->unpin_work); 3138 3139 return 0; 3140 } 3141 3142 static int dce_v6_0_hpd_irq(struct amdgpu_device *adev, 3143 struct amdgpu_irq_src *source, 3144 struct amdgpu_iv_entry *entry) 3145 { 3146 uint32_t disp_int, mask; 3147 unsigned hpd; 3148 3149 if (entry->src_data[0] >= adev->mode_info.num_hpd) { 3150 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3151 return 0; 3152 } 3153 3154 hpd = entry->src_data[0]; 3155 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3156 mask = interrupt_status_offsets[hpd].hpd; 3157 3158 if (disp_int & mask) { 3159 dce_v6_0_hpd_int_ack(adev, hpd); 3160 schedule_delayed_work(&adev->hotplug_work, 0); 3161 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3162 } 3163 3164 return 0; 3165 3166 } 3167 3168 static int dce_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 3169 enum amd_clockgating_state state) 3170 { 3171 return 0; 3172 } 3173 3174 static int dce_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 3175 enum amd_powergating_state state) 3176 { 3177 return 0; 3178 } 3179 3180 static const struct amd_ip_funcs dce_v6_0_ip_funcs = { 3181 .name = "dce_v6_0", 3182 .early_init = dce_v6_0_early_init, 3183 .sw_init = dce_v6_0_sw_init, 3184 .sw_fini = dce_v6_0_sw_fini, 3185 .hw_init = dce_v6_0_hw_init, 3186 .hw_fini = dce_v6_0_hw_fini, 3187 .suspend = dce_v6_0_suspend, 3188 .resume = dce_v6_0_resume, 3189 .is_idle = dce_v6_0_is_idle, 3190 .soft_reset = dce_v6_0_soft_reset, 3191 .set_clockgating_state = dce_v6_0_set_clockgating_state, 3192 .set_powergating_state = dce_v6_0_set_powergating_state, 3193 }; 3194 3195 static void 3196 dce_v6_0_encoder_mode_set(struct drm_encoder *encoder, 3197 struct drm_display_mode *mode, 3198 struct drm_display_mode *adjusted_mode) 3199 { 3200 3201 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3202 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 3203 3204 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3205 3206 /* need to call this here rather than in prepare() since we need some crtc info */ 3207 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3208 3209 /* set scaler clears this on some chips */ 3210 dce_v6_0_set_interleave(encoder->crtc, mode); 3211 3212 if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em)) { 3213 dce_v6_0_afmt_enable(encoder, true); 3214 dce_v6_0_afmt_setmode(encoder, adjusted_mode); 3215 } 3216 } 3217 3218 static void dce_v6_0_encoder_prepare(struct drm_encoder *encoder) 3219 { 3220 3221 struct amdgpu_device *adev = drm_to_adev(encoder->dev); 3222 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3223 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3224 3225 if ((amdgpu_encoder->active_device & 3226 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3227 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3228 ENCODER_OBJECT_ID_NONE)) { 3229 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3230 if (dig) { 3231 dig->dig_encoder = dce_v6_0_pick_dig_encoder(encoder); 3232 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3233 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3234 } 3235 } 3236 3237 amdgpu_atombios_scratch_regs_lock(adev, true); 3238 3239 if (connector) { 3240 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3241 3242 /* select the clock/data port if it uses a router */ 3243 if (amdgpu_connector->router.cd_valid) 3244 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3245 3246 /* turn eDP panel on for mode set */ 3247 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3248 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3249 ATOM_TRANSMITTER_ACTION_POWER_ON); 3250 } 3251 3252 /* this is needed for the pll/ss setup to work correctly in some cases */ 3253 amdgpu_atombios_encoder_set_crtc_source(encoder); 3254 /* set up the FMT blocks */ 3255 dce_v6_0_program_fmt(encoder); 3256 } 3257 3258 static void dce_v6_0_encoder_commit(struct drm_encoder *encoder) 3259 { 3260 3261 struct drm_device *dev = encoder->dev; 3262 struct amdgpu_device *adev = drm_to_adev(dev); 3263 3264 /* need to call this here as we need the crtc set up */ 3265 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3266 amdgpu_atombios_scratch_regs_lock(adev, false); 3267 } 3268 3269 static void dce_v6_0_encoder_disable(struct drm_encoder *encoder) 3270 { 3271 3272 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3273 struct amdgpu_encoder_atom_dig *dig; 3274 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 3275 3276 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3277 3278 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3279 if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em)) 3280 dce_v6_0_afmt_enable(encoder, false); 3281 dig = amdgpu_encoder->enc_priv; 3282 dig->dig_encoder = -1; 3283 } 3284 amdgpu_encoder->active_device = 0; 3285 } 3286 3287 /* these are handled by the primary encoders */ 3288 static void dce_v6_0_ext_prepare(struct drm_encoder *encoder) 3289 { 3290 3291 } 3292 3293 static void dce_v6_0_ext_commit(struct drm_encoder *encoder) 3294 { 3295 3296 } 3297 3298 static void 3299 dce_v6_0_ext_mode_set(struct drm_encoder *encoder, 3300 struct drm_display_mode *mode, 3301 struct drm_display_mode *adjusted_mode) 3302 { 3303 3304 } 3305 3306 static void dce_v6_0_ext_disable(struct drm_encoder *encoder) 3307 { 3308 3309 } 3310 3311 static void 3312 dce_v6_0_ext_dpms(struct drm_encoder *encoder, int mode) 3313 { 3314 3315 } 3316 3317 static bool dce_v6_0_ext_mode_fixup(struct drm_encoder *encoder, 3318 const struct drm_display_mode *mode, 3319 struct drm_display_mode *adjusted_mode) 3320 { 3321 return true; 3322 } 3323 3324 static const struct drm_encoder_helper_funcs dce_v6_0_ext_helper_funcs = { 3325 .dpms = dce_v6_0_ext_dpms, 3326 .mode_fixup = dce_v6_0_ext_mode_fixup, 3327 .prepare = dce_v6_0_ext_prepare, 3328 .mode_set = dce_v6_0_ext_mode_set, 3329 .commit = dce_v6_0_ext_commit, 3330 .disable = dce_v6_0_ext_disable, 3331 /* no detect for TMDS/LVDS yet */ 3332 }; 3333 3334 static const struct drm_encoder_helper_funcs dce_v6_0_dig_helper_funcs = { 3335 .dpms = amdgpu_atombios_encoder_dpms, 3336 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3337 .prepare = dce_v6_0_encoder_prepare, 3338 .mode_set = dce_v6_0_encoder_mode_set, 3339 .commit = dce_v6_0_encoder_commit, 3340 .disable = dce_v6_0_encoder_disable, 3341 .detect = amdgpu_atombios_encoder_dig_detect, 3342 }; 3343 3344 static const struct drm_encoder_helper_funcs dce_v6_0_dac_helper_funcs = { 3345 .dpms = amdgpu_atombios_encoder_dpms, 3346 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3347 .prepare = dce_v6_0_encoder_prepare, 3348 .mode_set = dce_v6_0_encoder_mode_set, 3349 .commit = dce_v6_0_encoder_commit, 3350 .detect = amdgpu_atombios_encoder_dac_detect, 3351 }; 3352 3353 static void dce_v6_0_encoder_destroy(struct drm_encoder *encoder) 3354 { 3355 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3356 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3357 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3358 kfree(amdgpu_encoder->enc_priv); 3359 drm_encoder_cleanup(encoder); 3360 kfree(amdgpu_encoder); 3361 } 3362 3363 static const struct drm_encoder_funcs dce_v6_0_encoder_funcs = { 3364 .destroy = dce_v6_0_encoder_destroy, 3365 }; 3366 3367 static void dce_v6_0_encoder_add(struct amdgpu_device *adev, 3368 uint32_t encoder_enum, 3369 uint32_t supported_device, 3370 u16 caps) 3371 { 3372 struct drm_device *dev = adev_to_drm(adev); 3373 struct drm_encoder *encoder; 3374 struct amdgpu_encoder *amdgpu_encoder; 3375 3376 /* see if we already added it */ 3377 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3378 amdgpu_encoder = to_amdgpu_encoder(encoder); 3379 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3380 amdgpu_encoder->devices |= supported_device; 3381 return; 3382 } 3383 3384 } 3385 3386 /* add a new one */ 3387 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3388 if (!amdgpu_encoder) 3389 return; 3390 3391 encoder = &amdgpu_encoder->base; 3392 switch (adev->mode_info.num_crtc) { 3393 case 1: 3394 encoder->possible_crtcs = 0x1; 3395 break; 3396 case 2: 3397 default: 3398 encoder->possible_crtcs = 0x3; 3399 break; 3400 case 4: 3401 encoder->possible_crtcs = 0xf; 3402 break; 3403 case 6: 3404 encoder->possible_crtcs = 0x3f; 3405 break; 3406 } 3407 3408 amdgpu_encoder->enc_priv = NULL; 3409 amdgpu_encoder->encoder_enum = encoder_enum; 3410 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3411 amdgpu_encoder->devices = supported_device; 3412 amdgpu_encoder->rmx_type = RMX_OFF; 3413 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3414 amdgpu_encoder->is_ext_encoder = false; 3415 amdgpu_encoder->caps = caps; 3416 3417 switch (amdgpu_encoder->encoder_id) { 3418 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3419 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3420 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3421 DRM_MODE_ENCODER_DAC, NULL); 3422 drm_encoder_helper_add(encoder, &dce_v6_0_dac_helper_funcs); 3423 break; 3424 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3425 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3426 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3427 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3428 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3429 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3430 amdgpu_encoder->rmx_type = RMX_FULL; 3431 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3432 DRM_MODE_ENCODER_LVDS, NULL); 3433 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3434 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3435 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3436 DRM_MODE_ENCODER_DAC, NULL); 3437 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3438 } else { 3439 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3440 DRM_MODE_ENCODER_TMDS, NULL); 3441 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3442 } 3443 drm_encoder_helper_add(encoder, &dce_v6_0_dig_helper_funcs); 3444 break; 3445 case ENCODER_OBJECT_ID_SI170B: 3446 case ENCODER_OBJECT_ID_CH7303: 3447 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3448 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3449 case ENCODER_OBJECT_ID_TITFP513: 3450 case ENCODER_OBJECT_ID_VT1623: 3451 case ENCODER_OBJECT_ID_HDMI_SI1930: 3452 case ENCODER_OBJECT_ID_TRAVIS: 3453 case ENCODER_OBJECT_ID_NUTMEG: 3454 /* these are handled by the primary encoders */ 3455 amdgpu_encoder->is_ext_encoder = true; 3456 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3457 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3458 DRM_MODE_ENCODER_LVDS, NULL); 3459 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3460 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3461 DRM_MODE_ENCODER_DAC, NULL); 3462 else 3463 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3464 DRM_MODE_ENCODER_TMDS, NULL); 3465 drm_encoder_helper_add(encoder, &dce_v6_0_ext_helper_funcs); 3466 break; 3467 } 3468 } 3469 3470 static const struct amdgpu_display_funcs dce_v6_0_display_funcs = { 3471 .bandwidth_update = &dce_v6_0_bandwidth_update, 3472 .vblank_get_counter = &dce_v6_0_vblank_get_counter, 3473 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3474 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3475 .hpd_sense = &dce_v6_0_hpd_sense, 3476 .hpd_set_polarity = &dce_v6_0_hpd_set_polarity, 3477 .hpd_get_gpio_reg = &dce_v6_0_hpd_get_gpio_reg, 3478 .page_flip = &dce_v6_0_page_flip, 3479 .page_flip_get_scanoutpos = &dce_v6_0_crtc_get_scanoutpos, 3480 .add_encoder = &dce_v6_0_encoder_add, 3481 .add_connector = &amdgpu_connector_add, 3482 }; 3483 3484 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev) 3485 { 3486 adev->mode_info.funcs = &dce_v6_0_display_funcs; 3487 } 3488 3489 static const struct amdgpu_irq_src_funcs dce_v6_0_crtc_irq_funcs = { 3490 .set = dce_v6_0_set_crtc_interrupt_state, 3491 .process = dce_v6_0_crtc_irq, 3492 }; 3493 3494 static const struct amdgpu_irq_src_funcs dce_v6_0_pageflip_irq_funcs = { 3495 .set = dce_v6_0_set_pageflip_interrupt_state, 3496 .process = dce_v6_0_pageflip_irq, 3497 }; 3498 3499 static const struct amdgpu_irq_src_funcs dce_v6_0_hpd_irq_funcs = { 3500 .set = dce_v6_0_set_hpd_interrupt_state, 3501 .process = dce_v6_0_hpd_irq, 3502 }; 3503 3504 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev) 3505 { 3506 if (adev->mode_info.num_crtc > 0) 3507 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; 3508 else 3509 adev->crtc_irq.num_types = 0; 3510 adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs; 3511 3512 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; 3513 adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs; 3514 3515 adev->hpd_irq.num_types = adev->mode_info.num_hpd; 3516 adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs; 3517 } 3518 3519 const struct amdgpu_ip_block_version dce_v6_0_ip_block = 3520 { 3521 .type = AMD_IP_BLOCK_TYPE_DCE, 3522 .major = 6, 3523 .minor = 0, 3524 .rev = 0, 3525 .funcs = &dce_v6_0_ip_funcs, 3526 }; 3527 3528 const struct amdgpu_ip_block_version dce_v6_4_ip_block = 3529 { 3530 .type = AMD_IP_BLOCK_TYPE_DCE, 3531 .major = 6, 3532 .minor = 4, 3533 .rev = 0, 3534 .funcs = &dce_v6_0_ip_funcs, 3535 }; 3536