1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <linux/slab.h> 26 #include <linux/module.h> 27 #include "drmP.h" 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "cikd.h" 34 #include "atom.h" 35 36 #include "cik.h" 37 #include "gmc_v7_0.h" 38 #include "cik_ih.h" 39 #include "dce_v8_0.h" 40 #include "gfx_v7_0.h" 41 #include "cik_sdma.h" 42 #include "uvd_v4_2.h" 43 #include "vce_v2_0.h" 44 #include "cik_dpm.h" 45 46 #include "uvd/uvd_4_2_d.h" 47 48 #include "smu/smu_7_0_1_d.h" 49 #include "smu/smu_7_0_1_sh_mask.h" 50 51 #include "dce/dce_8_0_d.h" 52 #include "dce/dce_8_0_sh_mask.h" 53 54 #include "bif/bif_4_1_d.h" 55 #include "bif/bif_4_1_sh_mask.h" 56 57 #include "gca/gfx_7_2_d.h" 58 #include "gca/gfx_7_2_enum.h" 59 #include "gca/gfx_7_2_sh_mask.h" 60 61 #include "gmc/gmc_7_1_d.h" 62 #include "gmc/gmc_7_1_sh_mask.h" 63 64 #include "oss/oss_2_0_d.h" 65 #include "oss/oss_2_0_sh_mask.h" 66 67 #include "amdgpu_amdkfd.h" 68 69 /* 70 * Indirect registers accessor 71 */ 72 static u32 cik_pcie_rreg(struct amdgpu_device *adev, u32 reg) 73 { 74 unsigned long flags; 75 u32 r; 76 77 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 78 WREG32(mmPCIE_INDEX, reg); 79 (void)RREG32(mmPCIE_INDEX); 80 r = RREG32(mmPCIE_DATA); 81 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 82 return r; 83 } 84 85 static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 86 { 87 unsigned long flags; 88 89 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 90 WREG32(mmPCIE_INDEX, reg); 91 (void)RREG32(mmPCIE_INDEX); 92 WREG32(mmPCIE_DATA, v); 93 (void)RREG32(mmPCIE_DATA); 94 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 95 } 96 97 static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg) 98 { 99 unsigned long flags; 100 u32 r; 101 102 spin_lock_irqsave(&adev->smc_idx_lock, flags); 103 WREG32(mmSMC_IND_INDEX_0, (reg)); 104 r = RREG32(mmSMC_IND_DATA_0); 105 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 106 return r; 107 } 108 109 static void cik_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 110 { 111 unsigned long flags; 112 113 spin_lock_irqsave(&adev->smc_idx_lock, flags); 114 WREG32(mmSMC_IND_INDEX_0, (reg)); 115 WREG32(mmSMC_IND_DATA_0, (v)); 116 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 117 } 118 119 static u32 cik_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 120 { 121 unsigned long flags; 122 u32 r; 123 124 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 125 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 126 r = RREG32(mmUVD_CTX_DATA); 127 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 128 return r; 129 } 130 131 static void cik_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 132 { 133 unsigned long flags; 134 135 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 136 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 137 WREG32(mmUVD_CTX_DATA, (v)); 138 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 139 } 140 141 static u32 cik_didt_rreg(struct amdgpu_device *adev, u32 reg) 142 { 143 unsigned long flags; 144 u32 r; 145 146 spin_lock_irqsave(&adev->didt_idx_lock, flags); 147 WREG32(mmDIDT_IND_INDEX, (reg)); 148 r = RREG32(mmDIDT_IND_DATA); 149 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 150 return r; 151 } 152 153 static void cik_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 154 { 155 unsigned long flags; 156 157 spin_lock_irqsave(&adev->didt_idx_lock, flags); 158 WREG32(mmDIDT_IND_INDEX, (reg)); 159 WREG32(mmDIDT_IND_DATA, (v)); 160 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 161 } 162 163 static const u32 bonaire_golden_spm_registers[] = 164 { 165 0xc200, 0xe0ffffff, 0xe0000000 166 }; 167 168 static const u32 bonaire_golden_common_registers[] = 169 { 170 0x31dc, 0xffffffff, 0x00000800, 171 0x31dd, 0xffffffff, 0x00000800, 172 0x31e6, 0xffffffff, 0x00007fbf, 173 0x31e7, 0xffffffff, 0x00007faf 174 }; 175 176 static const u32 bonaire_golden_registers[] = 177 { 178 0xcd5, 0x00000333, 0x00000333, 179 0xcd4, 0x000c0fc0, 0x00040200, 180 0x2684, 0x00010000, 0x00058208, 181 0xf000, 0xffff1fff, 0x00140000, 182 0xf080, 0xfdfc0fff, 0x00000100, 183 0xf08d, 0x40000000, 0x40000200, 184 0x260c, 0xffffffff, 0x00000000, 185 0x260d, 0xf00fffff, 0x00000400, 186 0x260e, 0x0002021c, 0x00020200, 187 0x31e, 0x00000080, 0x00000000, 188 0x16ec, 0x000000f0, 0x00000070, 189 0x16f0, 0xf0311fff, 0x80300000, 190 0x263e, 0x73773777, 0x12010001, 191 0xd43, 0x00810000, 0x408af000, 192 0x1c0c, 0x31000111, 0x00000011, 193 0xbd2, 0x73773777, 0x12010001, 194 0x883, 0x00007fb6, 0x0021a1b1, 195 0x884, 0x00007fb6, 0x002021b1, 196 0x860, 0x00007fb6, 0x00002191, 197 0x886, 0x00007fb6, 0x002121b1, 198 0x887, 0x00007fb6, 0x002021b1, 199 0x877, 0x00007fb6, 0x00002191, 200 0x878, 0x00007fb6, 0x00002191, 201 0xd8a, 0x0000003f, 0x0000000a, 202 0xd8b, 0x0000003f, 0x0000000a, 203 0xab9, 0x00073ffe, 0x000022a2, 204 0x903, 0x000007ff, 0x00000000, 205 0x2285, 0xf000003f, 0x00000007, 206 0x22fc, 0x00002001, 0x00000001, 207 0x22c9, 0xffffffff, 0x00ffffff, 208 0xc281, 0x0000ff0f, 0x00000000, 209 0xa293, 0x07ffffff, 0x06000000, 210 0x136, 0x00000fff, 0x00000100, 211 0xf9e, 0x00000001, 0x00000002, 212 0x2440, 0x03000000, 0x0362c688, 213 0x2300, 0x000000ff, 0x00000001, 214 0x390, 0x00001fff, 0x00001fff, 215 0x2418, 0x0000007f, 0x00000020, 216 0x2542, 0x00010000, 0x00010000, 217 0x2b05, 0x000003ff, 0x000000f3, 218 0x2b03, 0xffffffff, 0x00001032 219 }; 220 221 static const u32 bonaire_mgcg_cgcg_init[] = 222 { 223 0x3108, 0xffffffff, 0xfffffffc, 224 0xc200, 0xffffffff, 0xe0000000, 225 0xf0a8, 0xffffffff, 0x00000100, 226 0xf082, 0xffffffff, 0x00000100, 227 0xf0b0, 0xffffffff, 0xc0000100, 228 0xf0b2, 0xffffffff, 0xc0000100, 229 0xf0b1, 0xffffffff, 0xc0000100, 230 0x1579, 0xffffffff, 0x00600100, 231 0xf0a0, 0xffffffff, 0x00000100, 232 0xf085, 0xffffffff, 0x06000100, 233 0xf088, 0xffffffff, 0x00000100, 234 0xf086, 0xffffffff, 0x06000100, 235 0xf081, 0xffffffff, 0x00000100, 236 0xf0b8, 0xffffffff, 0x00000100, 237 0xf089, 0xffffffff, 0x00000100, 238 0xf080, 0xffffffff, 0x00000100, 239 0xf08c, 0xffffffff, 0x00000100, 240 0xf08d, 0xffffffff, 0x00000100, 241 0xf094, 0xffffffff, 0x00000100, 242 0xf095, 0xffffffff, 0x00000100, 243 0xf096, 0xffffffff, 0x00000100, 244 0xf097, 0xffffffff, 0x00000100, 245 0xf098, 0xffffffff, 0x00000100, 246 0xf09f, 0xffffffff, 0x00000100, 247 0xf09e, 0xffffffff, 0x00000100, 248 0xf084, 0xffffffff, 0x06000100, 249 0xf0a4, 0xffffffff, 0x00000100, 250 0xf09d, 0xffffffff, 0x00000100, 251 0xf0ad, 0xffffffff, 0x00000100, 252 0xf0ac, 0xffffffff, 0x00000100, 253 0xf09c, 0xffffffff, 0x00000100, 254 0xc200, 0xffffffff, 0xe0000000, 255 0xf008, 0xffffffff, 0x00010000, 256 0xf009, 0xffffffff, 0x00030002, 257 0xf00a, 0xffffffff, 0x00040007, 258 0xf00b, 0xffffffff, 0x00060005, 259 0xf00c, 0xffffffff, 0x00090008, 260 0xf00d, 0xffffffff, 0x00010000, 261 0xf00e, 0xffffffff, 0x00030002, 262 0xf00f, 0xffffffff, 0x00040007, 263 0xf010, 0xffffffff, 0x00060005, 264 0xf011, 0xffffffff, 0x00090008, 265 0xf012, 0xffffffff, 0x00010000, 266 0xf013, 0xffffffff, 0x00030002, 267 0xf014, 0xffffffff, 0x00040007, 268 0xf015, 0xffffffff, 0x00060005, 269 0xf016, 0xffffffff, 0x00090008, 270 0xf017, 0xffffffff, 0x00010000, 271 0xf018, 0xffffffff, 0x00030002, 272 0xf019, 0xffffffff, 0x00040007, 273 0xf01a, 0xffffffff, 0x00060005, 274 0xf01b, 0xffffffff, 0x00090008, 275 0xf01c, 0xffffffff, 0x00010000, 276 0xf01d, 0xffffffff, 0x00030002, 277 0xf01e, 0xffffffff, 0x00040007, 278 0xf01f, 0xffffffff, 0x00060005, 279 0xf020, 0xffffffff, 0x00090008, 280 0xf021, 0xffffffff, 0x00010000, 281 0xf022, 0xffffffff, 0x00030002, 282 0xf023, 0xffffffff, 0x00040007, 283 0xf024, 0xffffffff, 0x00060005, 284 0xf025, 0xffffffff, 0x00090008, 285 0xf026, 0xffffffff, 0x00010000, 286 0xf027, 0xffffffff, 0x00030002, 287 0xf028, 0xffffffff, 0x00040007, 288 0xf029, 0xffffffff, 0x00060005, 289 0xf02a, 0xffffffff, 0x00090008, 290 0xf000, 0xffffffff, 0x96e00200, 291 0x21c2, 0xffffffff, 0x00900100, 292 0x3109, 0xffffffff, 0x0020003f, 293 0xe, 0xffffffff, 0x0140001c, 294 0xf, 0x000f0000, 0x000f0000, 295 0x88, 0xffffffff, 0xc060000c, 296 0x89, 0xc0000fff, 0x00000100, 297 0x3e4, 0xffffffff, 0x00000100, 298 0x3e6, 0x00000101, 0x00000000, 299 0x82a, 0xffffffff, 0x00000104, 300 0x1579, 0xff000fff, 0x00000100, 301 0xc33, 0xc0000fff, 0x00000104, 302 0x3079, 0x00000001, 0x00000001, 303 0x3403, 0xff000ff0, 0x00000100, 304 0x3603, 0xff000ff0, 0x00000100 305 }; 306 307 static const u32 spectre_golden_spm_registers[] = 308 { 309 0xc200, 0xe0ffffff, 0xe0000000 310 }; 311 312 static const u32 spectre_golden_common_registers[] = 313 { 314 0x31dc, 0xffffffff, 0x00000800, 315 0x31dd, 0xffffffff, 0x00000800, 316 0x31e6, 0xffffffff, 0x00007fbf, 317 0x31e7, 0xffffffff, 0x00007faf 318 }; 319 320 static const u32 spectre_golden_registers[] = 321 { 322 0xf000, 0xffff1fff, 0x96940200, 323 0xf003, 0xffff0001, 0xff000000, 324 0xf080, 0xfffc0fff, 0x00000100, 325 0x1bb6, 0x00010101, 0x00010000, 326 0x260d, 0xf00fffff, 0x00000400, 327 0x260e, 0xfffffffc, 0x00020200, 328 0x16ec, 0x000000f0, 0x00000070, 329 0x16f0, 0xf0311fff, 0x80300000, 330 0x263e, 0x73773777, 0x12010001, 331 0x26df, 0x00ff0000, 0x00fc0000, 332 0xbd2, 0x73773777, 0x12010001, 333 0x2285, 0xf000003f, 0x00000007, 334 0x22c9, 0xffffffff, 0x00ffffff, 335 0xa0d4, 0x3f3f3fff, 0x00000082, 336 0xa0d5, 0x0000003f, 0x00000000, 337 0xf9e, 0x00000001, 0x00000002, 338 0x244f, 0xffff03df, 0x00000004, 339 0x31da, 0x00000008, 0x00000008, 340 0x2300, 0x000008ff, 0x00000800, 341 0x2542, 0x00010000, 0x00010000, 342 0x2b03, 0xffffffff, 0x54763210, 343 0x853e, 0x01ff01ff, 0x00000002, 344 0x8526, 0x007ff800, 0x00200000, 345 0x8057, 0xffffffff, 0x00000f40, 346 0xc24d, 0xffffffff, 0x00000001 347 }; 348 349 static const u32 spectre_mgcg_cgcg_init[] = 350 { 351 0x3108, 0xffffffff, 0xfffffffc, 352 0xc200, 0xffffffff, 0xe0000000, 353 0xf0a8, 0xffffffff, 0x00000100, 354 0xf082, 0xffffffff, 0x00000100, 355 0xf0b0, 0xffffffff, 0x00000100, 356 0xf0b2, 0xffffffff, 0x00000100, 357 0xf0b1, 0xffffffff, 0x00000100, 358 0x1579, 0xffffffff, 0x00600100, 359 0xf0a0, 0xffffffff, 0x00000100, 360 0xf085, 0xffffffff, 0x06000100, 361 0xf088, 0xffffffff, 0x00000100, 362 0xf086, 0xffffffff, 0x06000100, 363 0xf081, 0xffffffff, 0x00000100, 364 0xf0b8, 0xffffffff, 0x00000100, 365 0xf089, 0xffffffff, 0x00000100, 366 0xf080, 0xffffffff, 0x00000100, 367 0xf08c, 0xffffffff, 0x00000100, 368 0xf08d, 0xffffffff, 0x00000100, 369 0xf094, 0xffffffff, 0x00000100, 370 0xf095, 0xffffffff, 0x00000100, 371 0xf096, 0xffffffff, 0x00000100, 372 0xf097, 0xffffffff, 0x00000100, 373 0xf098, 0xffffffff, 0x00000100, 374 0xf09f, 0xffffffff, 0x00000100, 375 0xf09e, 0xffffffff, 0x00000100, 376 0xf084, 0xffffffff, 0x06000100, 377 0xf0a4, 0xffffffff, 0x00000100, 378 0xf09d, 0xffffffff, 0x00000100, 379 0xf0ad, 0xffffffff, 0x00000100, 380 0xf0ac, 0xffffffff, 0x00000100, 381 0xf09c, 0xffffffff, 0x00000100, 382 0xc200, 0xffffffff, 0xe0000000, 383 0xf008, 0xffffffff, 0x00010000, 384 0xf009, 0xffffffff, 0x00030002, 385 0xf00a, 0xffffffff, 0x00040007, 386 0xf00b, 0xffffffff, 0x00060005, 387 0xf00c, 0xffffffff, 0x00090008, 388 0xf00d, 0xffffffff, 0x00010000, 389 0xf00e, 0xffffffff, 0x00030002, 390 0xf00f, 0xffffffff, 0x00040007, 391 0xf010, 0xffffffff, 0x00060005, 392 0xf011, 0xffffffff, 0x00090008, 393 0xf012, 0xffffffff, 0x00010000, 394 0xf013, 0xffffffff, 0x00030002, 395 0xf014, 0xffffffff, 0x00040007, 396 0xf015, 0xffffffff, 0x00060005, 397 0xf016, 0xffffffff, 0x00090008, 398 0xf017, 0xffffffff, 0x00010000, 399 0xf018, 0xffffffff, 0x00030002, 400 0xf019, 0xffffffff, 0x00040007, 401 0xf01a, 0xffffffff, 0x00060005, 402 0xf01b, 0xffffffff, 0x00090008, 403 0xf01c, 0xffffffff, 0x00010000, 404 0xf01d, 0xffffffff, 0x00030002, 405 0xf01e, 0xffffffff, 0x00040007, 406 0xf01f, 0xffffffff, 0x00060005, 407 0xf020, 0xffffffff, 0x00090008, 408 0xf021, 0xffffffff, 0x00010000, 409 0xf022, 0xffffffff, 0x00030002, 410 0xf023, 0xffffffff, 0x00040007, 411 0xf024, 0xffffffff, 0x00060005, 412 0xf025, 0xffffffff, 0x00090008, 413 0xf026, 0xffffffff, 0x00010000, 414 0xf027, 0xffffffff, 0x00030002, 415 0xf028, 0xffffffff, 0x00040007, 416 0xf029, 0xffffffff, 0x00060005, 417 0xf02a, 0xffffffff, 0x00090008, 418 0xf02b, 0xffffffff, 0x00010000, 419 0xf02c, 0xffffffff, 0x00030002, 420 0xf02d, 0xffffffff, 0x00040007, 421 0xf02e, 0xffffffff, 0x00060005, 422 0xf02f, 0xffffffff, 0x00090008, 423 0xf000, 0xffffffff, 0x96e00200, 424 0x21c2, 0xffffffff, 0x00900100, 425 0x3109, 0xffffffff, 0x0020003f, 426 0xe, 0xffffffff, 0x0140001c, 427 0xf, 0x000f0000, 0x000f0000, 428 0x88, 0xffffffff, 0xc060000c, 429 0x89, 0xc0000fff, 0x00000100, 430 0x3e4, 0xffffffff, 0x00000100, 431 0x3e6, 0x00000101, 0x00000000, 432 0x82a, 0xffffffff, 0x00000104, 433 0x1579, 0xff000fff, 0x00000100, 434 0xc33, 0xc0000fff, 0x00000104, 435 0x3079, 0x00000001, 0x00000001, 436 0x3403, 0xff000ff0, 0x00000100, 437 0x3603, 0xff000ff0, 0x00000100 438 }; 439 440 static const u32 kalindi_golden_spm_registers[] = 441 { 442 0xc200, 0xe0ffffff, 0xe0000000 443 }; 444 445 static const u32 kalindi_golden_common_registers[] = 446 { 447 0x31dc, 0xffffffff, 0x00000800, 448 0x31dd, 0xffffffff, 0x00000800, 449 0x31e6, 0xffffffff, 0x00007fbf, 450 0x31e7, 0xffffffff, 0x00007faf 451 }; 452 453 static const u32 kalindi_golden_registers[] = 454 { 455 0xf000, 0xffffdfff, 0x6e944040, 456 0x1579, 0xff607fff, 0xfc000100, 457 0xf088, 0xff000fff, 0x00000100, 458 0xf089, 0xff000fff, 0x00000100, 459 0xf080, 0xfffc0fff, 0x00000100, 460 0x1bb6, 0x00010101, 0x00010000, 461 0x260c, 0xffffffff, 0x00000000, 462 0x260d, 0xf00fffff, 0x00000400, 463 0x16ec, 0x000000f0, 0x00000070, 464 0x16f0, 0xf0311fff, 0x80300000, 465 0x263e, 0x73773777, 0x12010001, 466 0x263f, 0xffffffff, 0x00000010, 467 0x26df, 0x00ff0000, 0x00fc0000, 468 0x200c, 0x00001f0f, 0x0000100a, 469 0xbd2, 0x73773777, 0x12010001, 470 0x902, 0x000fffff, 0x000c007f, 471 0x2285, 0xf000003f, 0x00000007, 472 0x22c9, 0x3fff3fff, 0x00ffcfff, 473 0xc281, 0x0000ff0f, 0x00000000, 474 0xa293, 0x07ffffff, 0x06000000, 475 0x136, 0x00000fff, 0x00000100, 476 0xf9e, 0x00000001, 0x00000002, 477 0x31da, 0x00000008, 0x00000008, 478 0x2300, 0x000000ff, 0x00000003, 479 0x853e, 0x01ff01ff, 0x00000002, 480 0x8526, 0x007ff800, 0x00200000, 481 0x8057, 0xffffffff, 0x00000f40, 482 0x2231, 0x001f3ae3, 0x00000082, 483 0x2235, 0x0000001f, 0x00000010, 484 0xc24d, 0xffffffff, 0x00000000 485 }; 486 487 static const u32 kalindi_mgcg_cgcg_init[] = 488 { 489 0x3108, 0xffffffff, 0xfffffffc, 490 0xc200, 0xffffffff, 0xe0000000, 491 0xf0a8, 0xffffffff, 0x00000100, 492 0xf082, 0xffffffff, 0x00000100, 493 0xf0b0, 0xffffffff, 0x00000100, 494 0xf0b2, 0xffffffff, 0x00000100, 495 0xf0b1, 0xffffffff, 0x00000100, 496 0x1579, 0xffffffff, 0x00600100, 497 0xf0a0, 0xffffffff, 0x00000100, 498 0xf085, 0xffffffff, 0x06000100, 499 0xf088, 0xffffffff, 0x00000100, 500 0xf086, 0xffffffff, 0x06000100, 501 0xf081, 0xffffffff, 0x00000100, 502 0xf0b8, 0xffffffff, 0x00000100, 503 0xf089, 0xffffffff, 0x00000100, 504 0xf080, 0xffffffff, 0x00000100, 505 0xf08c, 0xffffffff, 0x00000100, 506 0xf08d, 0xffffffff, 0x00000100, 507 0xf094, 0xffffffff, 0x00000100, 508 0xf095, 0xffffffff, 0x00000100, 509 0xf096, 0xffffffff, 0x00000100, 510 0xf097, 0xffffffff, 0x00000100, 511 0xf098, 0xffffffff, 0x00000100, 512 0xf09f, 0xffffffff, 0x00000100, 513 0xf09e, 0xffffffff, 0x00000100, 514 0xf084, 0xffffffff, 0x06000100, 515 0xf0a4, 0xffffffff, 0x00000100, 516 0xf09d, 0xffffffff, 0x00000100, 517 0xf0ad, 0xffffffff, 0x00000100, 518 0xf0ac, 0xffffffff, 0x00000100, 519 0xf09c, 0xffffffff, 0x00000100, 520 0xc200, 0xffffffff, 0xe0000000, 521 0xf008, 0xffffffff, 0x00010000, 522 0xf009, 0xffffffff, 0x00030002, 523 0xf00a, 0xffffffff, 0x00040007, 524 0xf00b, 0xffffffff, 0x00060005, 525 0xf00c, 0xffffffff, 0x00090008, 526 0xf00d, 0xffffffff, 0x00010000, 527 0xf00e, 0xffffffff, 0x00030002, 528 0xf00f, 0xffffffff, 0x00040007, 529 0xf010, 0xffffffff, 0x00060005, 530 0xf011, 0xffffffff, 0x00090008, 531 0xf000, 0xffffffff, 0x96e00200, 532 0x21c2, 0xffffffff, 0x00900100, 533 0x3109, 0xffffffff, 0x0020003f, 534 0xe, 0xffffffff, 0x0140001c, 535 0xf, 0x000f0000, 0x000f0000, 536 0x88, 0xffffffff, 0xc060000c, 537 0x89, 0xc0000fff, 0x00000100, 538 0x82a, 0xffffffff, 0x00000104, 539 0x1579, 0xff000fff, 0x00000100, 540 0xc33, 0xc0000fff, 0x00000104, 541 0x3079, 0x00000001, 0x00000001, 542 0x3403, 0xff000ff0, 0x00000100, 543 0x3603, 0xff000ff0, 0x00000100 544 }; 545 546 static const u32 hawaii_golden_spm_registers[] = 547 { 548 0xc200, 0xe0ffffff, 0xe0000000 549 }; 550 551 static const u32 hawaii_golden_common_registers[] = 552 { 553 0xc200, 0xffffffff, 0xe0000000, 554 0xa0d4, 0xffffffff, 0x3a00161a, 555 0xa0d5, 0xffffffff, 0x0000002e, 556 0x2684, 0xffffffff, 0x00018208, 557 0x263e, 0xffffffff, 0x12011003 558 }; 559 560 static const u32 hawaii_golden_registers[] = 561 { 562 0xcd5, 0x00000333, 0x00000333, 563 0x2684, 0x00010000, 0x00058208, 564 0x260c, 0xffffffff, 0x00000000, 565 0x260d, 0xf00fffff, 0x00000400, 566 0x260e, 0x0002021c, 0x00020200, 567 0x31e, 0x00000080, 0x00000000, 568 0x16ec, 0x000000f0, 0x00000070, 569 0x16f0, 0xf0311fff, 0x80300000, 570 0xd43, 0x00810000, 0x408af000, 571 0x1c0c, 0x31000111, 0x00000011, 572 0xbd2, 0x73773777, 0x12010001, 573 0x848, 0x0000007f, 0x0000001b, 574 0x877, 0x00007fb6, 0x00002191, 575 0xd8a, 0x0000003f, 0x0000000a, 576 0xd8b, 0x0000003f, 0x0000000a, 577 0xab9, 0x00073ffe, 0x000022a2, 578 0x903, 0x000007ff, 0x00000000, 579 0x22fc, 0x00002001, 0x00000001, 580 0x22c9, 0xffffffff, 0x00ffffff, 581 0xc281, 0x0000ff0f, 0x00000000, 582 0xa293, 0x07ffffff, 0x06000000, 583 0xf9e, 0x00000001, 0x00000002, 584 0x31da, 0x00000008, 0x00000008, 585 0x31dc, 0x00000f00, 0x00000800, 586 0x31dd, 0x00000f00, 0x00000800, 587 0x31e6, 0x00ffffff, 0x00ff7fbf, 588 0x31e7, 0x00ffffff, 0x00ff7faf, 589 0x2300, 0x000000ff, 0x00000800, 590 0x390, 0x00001fff, 0x00001fff, 591 0x2418, 0x0000007f, 0x00000020, 592 0x2542, 0x00010000, 0x00010000, 593 0x2b80, 0x00100000, 0x000ff07c, 594 0x2b05, 0x000003ff, 0x0000000f, 595 0x2b04, 0xffffffff, 0x7564fdec, 596 0x2b03, 0xffffffff, 0x3120b9a8, 597 0x2b02, 0x20000000, 0x0f9c0000 598 }; 599 600 static const u32 hawaii_mgcg_cgcg_init[] = 601 { 602 0x3108, 0xffffffff, 0xfffffffd, 603 0xc200, 0xffffffff, 0xe0000000, 604 0xf0a8, 0xffffffff, 0x00000100, 605 0xf082, 0xffffffff, 0x00000100, 606 0xf0b0, 0xffffffff, 0x00000100, 607 0xf0b2, 0xffffffff, 0x00000100, 608 0xf0b1, 0xffffffff, 0x00000100, 609 0x1579, 0xffffffff, 0x00200100, 610 0xf0a0, 0xffffffff, 0x00000100, 611 0xf085, 0xffffffff, 0x06000100, 612 0xf088, 0xffffffff, 0x00000100, 613 0xf086, 0xffffffff, 0x06000100, 614 0xf081, 0xffffffff, 0x00000100, 615 0xf0b8, 0xffffffff, 0x00000100, 616 0xf089, 0xffffffff, 0x00000100, 617 0xf080, 0xffffffff, 0x00000100, 618 0xf08c, 0xffffffff, 0x00000100, 619 0xf08d, 0xffffffff, 0x00000100, 620 0xf094, 0xffffffff, 0x00000100, 621 0xf095, 0xffffffff, 0x00000100, 622 0xf096, 0xffffffff, 0x00000100, 623 0xf097, 0xffffffff, 0x00000100, 624 0xf098, 0xffffffff, 0x00000100, 625 0xf09f, 0xffffffff, 0x00000100, 626 0xf09e, 0xffffffff, 0x00000100, 627 0xf084, 0xffffffff, 0x06000100, 628 0xf0a4, 0xffffffff, 0x00000100, 629 0xf09d, 0xffffffff, 0x00000100, 630 0xf0ad, 0xffffffff, 0x00000100, 631 0xf0ac, 0xffffffff, 0x00000100, 632 0xf09c, 0xffffffff, 0x00000100, 633 0xc200, 0xffffffff, 0xe0000000, 634 0xf008, 0xffffffff, 0x00010000, 635 0xf009, 0xffffffff, 0x00030002, 636 0xf00a, 0xffffffff, 0x00040007, 637 0xf00b, 0xffffffff, 0x00060005, 638 0xf00c, 0xffffffff, 0x00090008, 639 0xf00d, 0xffffffff, 0x00010000, 640 0xf00e, 0xffffffff, 0x00030002, 641 0xf00f, 0xffffffff, 0x00040007, 642 0xf010, 0xffffffff, 0x00060005, 643 0xf011, 0xffffffff, 0x00090008, 644 0xf012, 0xffffffff, 0x00010000, 645 0xf013, 0xffffffff, 0x00030002, 646 0xf014, 0xffffffff, 0x00040007, 647 0xf015, 0xffffffff, 0x00060005, 648 0xf016, 0xffffffff, 0x00090008, 649 0xf017, 0xffffffff, 0x00010000, 650 0xf018, 0xffffffff, 0x00030002, 651 0xf019, 0xffffffff, 0x00040007, 652 0xf01a, 0xffffffff, 0x00060005, 653 0xf01b, 0xffffffff, 0x00090008, 654 0xf01c, 0xffffffff, 0x00010000, 655 0xf01d, 0xffffffff, 0x00030002, 656 0xf01e, 0xffffffff, 0x00040007, 657 0xf01f, 0xffffffff, 0x00060005, 658 0xf020, 0xffffffff, 0x00090008, 659 0xf021, 0xffffffff, 0x00010000, 660 0xf022, 0xffffffff, 0x00030002, 661 0xf023, 0xffffffff, 0x00040007, 662 0xf024, 0xffffffff, 0x00060005, 663 0xf025, 0xffffffff, 0x00090008, 664 0xf026, 0xffffffff, 0x00010000, 665 0xf027, 0xffffffff, 0x00030002, 666 0xf028, 0xffffffff, 0x00040007, 667 0xf029, 0xffffffff, 0x00060005, 668 0xf02a, 0xffffffff, 0x00090008, 669 0xf02b, 0xffffffff, 0x00010000, 670 0xf02c, 0xffffffff, 0x00030002, 671 0xf02d, 0xffffffff, 0x00040007, 672 0xf02e, 0xffffffff, 0x00060005, 673 0xf02f, 0xffffffff, 0x00090008, 674 0xf030, 0xffffffff, 0x00010000, 675 0xf031, 0xffffffff, 0x00030002, 676 0xf032, 0xffffffff, 0x00040007, 677 0xf033, 0xffffffff, 0x00060005, 678 0xf034, 0xffffffff, 0x00090008, 679 0xf035, 0xffffffff, 0x00010000, 680 0xf036, 0xffffffff, 0x00030002, 681 0xf037, 0xffffffff, 0x00040007, 682 0xf038, 0xffffffff, 0x00060005, 683 0xf039, 0xffffffff, 0x00090008, 684 0xf03a, 0xffffffff, 0x00010000, 685 0xf03b, 0xffffffff, 0x00030002, 686 0xf03c, 0xffffffff, 0x00040007, 687 0xf03d, 0xffffffff, 0x00060005, 688 0xf03e, 0xffffffff, 0x00090008, 689 0x30c6, 0xffffffff, 0x00020200, 690 0xcd4, 0xffffffff, 0x00000200, 691 0x570, 0xffffffff, 0x00000400, 692 0x157a, 0xffffffff, 0x00000000, 693 0xbd4, 0xffffffff, 0x00000902, 694 0xf000, 0xffffffff, 0x96940200, 695 0x21c2, 0xffffffff, 0x00900100, 696 0x3109, 0xffffffff, 0x0020003f, 697 0xe, 0xffffffff, 0x0140001c, 698 0xf, 0x000f0000, 0x000f0000, 699 0x88, 0xffffffff, 0xc060000c, 700 0x89, 0xc0000fff, 0x00000100, 701 0x3e4, 0xffffffff, 0x00000100, 702 0x3e6, 0x00000101, 0x00000000, 703 0x82a, 0xffffffff, 0x00000104, 704 0x1579, 0xff000fff, 0x00000100, 705 0xc33, 0xc0000fff, 0x00000104, 706 0x3079, 0x00000001, 0x00000001, 707 0x3403, 0xff000ff0, 0x00000100, 708 0x3603, 0xff000ff0, 0x00000100 709 }; 710 711 static const u32 godavari_golden_registers[] = 712 { 713 0x1579, 0xff607fff, 0xfc000100, 714 0x1bb6, 0x00010101, 0x00010000, 715 0x260c, 0xffffffff, 0x00000000, 716 0x260c0, 0xf00fffff, 0x00000400, 717 0x184c, 0xffffffff, 0x00010000, 718 0x16ec, 0x000000f0, 0x00000070, 719 0x16f0, 0xf0311fff, 0x80300000, 720 0x263e, 0x73773777, 0x12010001, 721 0x263f, 0xffffffff, 0x00000010, 722 0x200c, 0x00001f0f, 0x0000100a, 723 0xbd2, 0x73773777, 0x12010001, 724 0x902, 0x000fffff, 0x000c007f, 725 0x2285, 0xf000003f, 0x00000007, 726 0x22c9, 0xffffffff, 0x00ff0fff, 727 0xc281, 0x0000ff0f, 0x00000000, 728 0xa293, 0x07ffffff, 0x06000000, 729 0x136, 0x00000fff, 0x00000100, 730 0x3405, 0x00010000, 0x00810001, 731 0x3605, 0x00010000, 0x00810001, 732 0xf9e, 0x00000001, 0x00000002, 733 0x31da, 0x00000008, 0x00000008, 734 0x31dc, 0x00000f00, 0x00000800, 735 0x31dd, 0x00000f00, 0x00000800, 736 0x31e6, 0x00ffffff, 0x00ff7fbf, 737 0x31e7, 0x00ffffff, 0x00ff7faf, 738 0x2300, 0x000000ff, 0x00000001, 739 0x853e, 0x01ff01ff, 0x00000002, 740 0x8526, 0x007ff800, 0x00200000, 741 0x8057, 0xffffffff, 0x00000f40, 742 0x2231, 0x001f3ae3, 0x00000082, 743 0x2235, 0x0000001f, 0x00000010, 744 0xc24d, 0xffffffff, 0x00000000 745 }; 746 747 static void cik_init_golden_registers(struct amdgpu_device *adev) 748 { 749 /* Some of the registers might be dependent on GRBM_GFX_INDEX */ 750 mutex_lock(&adev->grbm_idx_mutex); 751 752 switch (adev->asic_type) { 753 case CHIP_BONAIRE: 754 amdgpu_program_register_sequence(adev, 755 bonaire_mgcg_cgcg_init, 756 (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init)); 757 amdgpu_program_register_sequence(adev, 758 bonaire_golden_registers, 759 (const u32)ARRAY_SIZE(bonaire_golden_registers)); 760 amdgpu_program_register_sequence(adev, 761 bonaire_golden_common_registers, 762 (const u32)ARRAY_SIZE(bonaire_golden_common_registers)); 763 amdgpu_program_register_sequence(adev, 764 bonaire_golden_spm_registers, 765 (const u32)ARRAY_SIZE(bonaire_golden_spm_registers)); 766 break; 767 case CHIP_KABINI: 768 amdgpu_program_register_sequence(adev, 769 kalindi_mgcg_cgcg_init, 770 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init)); 771 amdgpu_program_register_sequence(adev, 772 kalindi_golden_registers, 773 (const u32)ARRAY_SIZE(kalindi_golden_registers)); 774 amdgpu_program_register_sequence(adev, 775 kalindi_golden_common_registers, 776 (const u32)ARRAY_SIZE(kalindi_golden_common_registers)); 777 amdgpu_program_register_sequence(adev, 778 kalindi_golden_spm_registers, 779 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers)); 780 break; 781 case CHIP_MULLINS: 782 amdgpu_program_register_sequence(adev, 783 kalindi_mgcg_cgcg_init, 784 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init)); 785 amdgpu_program_register_sequence(adev, 786 godavari_golden_registers, 787 (const u32)ARRAY_SIZE(godavari_golden_registers)); 788 amdgpu_program_register_sequence(adev, 789 kalindi_golden_common_registers, 790 (const u32)ARRAY_SIZE(kalindi_golden_common_registers)); 791 amdgpu_program_register_sequence(adev, 792 kalindi_golden_spm_registers, 793 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers)); 794 break; 795 case CHIP_KAVERI: 796 amdgpu_program_register_sequence(adev, 797 spectre_mgcg_cgcg_init, 798 (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init)); 799 amdgpu_program_register_sequence(adev, 800 spectre_golden_registers, 801 (const u32)ARRAY_SIZE(spectre_golden_registers)); 802 amdgpu_program_register_sequence(adev, 803 spectre_golden_common_registers, 804 (const u32)ARRAY_SIZE(spectre_golden_common_registers)); 805 amdgpu_program_register_sequence(adev, 806 spectre_golden_spm_registers, 807 (const u32)ARRAY_SIZE(spectre_golden_spm_registers)); 808 break; 809 case CHIP_HAWAII: 810 amdgpu_program_register_sequence(adev, 811 hawaii_mgcg_cgcg_init, 812 (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init)); 813 amdgpu_program_register_sequence(adev, 814 hawaii_golden_registers, 815 (const u32)ARRAY_SIZE(hawaii_golden_registers)); 816 amdgpu_program_register_sequence(adev, 817 hawaii_golden_common_registers, 818 (const u32)ARRAY_SIZE(hawaii_golden_common_registers)); 819 amdgpu_program_register_sequence(adev, 820 hawaii_golden_spm_registers, 821 (const u32)ARRAY_SIZE(hawaii_golden_spm_registers)); 822 break; 823 default: 824 break; 825 } 826 mutex_unlock(&adev->grbm_idx_mutex); 827 } 828 829 /** 830 * cik_get_xclk - get the xclk 831 * 832 * @adev: amdgpu_device pointer 833 * 834 * Returns the reference clock used by the gfx engine 835 * (CIK). 836 */ 837 static u32 cik_get_xclk(struct amdgpu_device *adev) 838 { 839 u32 reference_clock = adev->clock.spll.reference_freq; 840 841 if (adev->flags & AMD_IS_APU) { 842 if (RREG32_SMC(ixGENERAL_PWRMGT) & GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK) 843 return reference_clock / 2; 844 } else { 845 if (RREG32_SMC(ixCG_CLKPIN_CNTL) & CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK) 846 return reference_clock / 4; 847 } 848 return reference_clock; 849 } 850 851 /** 852 * cik_srbm_select - select specific register instances 853 * 854 * @adev: amdgpu_device pointer 855 * @me: selected ME (micro engine) 856 * @pipe: pipe 857 * @queue: queue 858 * @vmid: VMID 859 * 860 * Switches the currently active registers instances. Some 861 * registers are instanced per VMID, others are instanced per 862 * me/pipe/queue combination. 863 */ 864 void cik_srbm_select(struct amdgpu_device *adev, 865 u32 me, u32 pipe, u32 queue, u32 vmid) 866 { 867 u32 srbm_gfx_cntl = 868 (((pipe << SRBM_GFX_CNTL__PIPEID__SHIFT) & SRBM_GFX_CNTL__PIPEID_MASK)| 869 ((me << SRBM_GFX_CNTL__MEID__SHIFT) & SRBM_GFX_CNTL__MEID_MASK)| 870 ((vmid << SRBM_GFX_CNTL__VMID__SHIFT) & SRBM_GFX_CNTL__VMID_MASK)| 871 ((queue << SRBM_GFX_CNTL__QUEUEID__SHIFT) & SRBM_GFX_CNTL__QUEUEID_MASK)); 872 WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl); 873 } 874 875 static void cik_vga_set_state(struct amdgpu_device *adev, bool state) 876 { 877 uint32_t tmp; 878 879 tmp = RREG32(mmCONFIG_CNTL); 880 if (state == false) 881 tmp |= CONFIG_CNTL__VGA_DIS_MASK; 882 else 883 tmp &= ~CONFIG_CNTL__VGA_DIS_MASK; 884 WREG32(mmCONFIG_CNTL, tmp); 885 } 886 887 static bool cik_read_disabled_bios(struct amdgpu_device *adev) 888 { 889 u32 bus_cntl; 890 u32 d1vga_control = 0; 891 u32 d2vga_control = 0; 892 u32 vga_render_control = 0; 893 u32 rom_cntl; 894 bool r; 895 896 bus_cntl = RREG32(mmBUS_CNTL); 897 if (adev->mode_info.num_crtc) { 898 d1vga_control = RREG32(mmD1VGA_CONTROL); 899 d2vga_control = RREG32(mmD2VGA_CONTROL); 900 vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 901 } 902 rom_cntl = RREG32_SMC(ixROM_CNTL); 903 904 /* enable the rom */ 905 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK)); 906 if (adev->mode_info.num_crtc) { 907 /* Disable VGA mode */ 908 WREG32(mmD1VGA_CONTROL, 909 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK | 910 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK))); 911 WREG32(mmD2VGA_CONTROL, 912 (d2vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK | 913 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK))); 914 WREG32(mmVGA_RENDER_CONTROL, 915 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK)); 916 } 917 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); 918 919 r = amdgpu_read_bios(adev); 920 921 /* restore regs */ 922 WREG32(mmBUS_CNTL, bus_cntl); 923 if (adev->mode_info.num_crtc) { 924 WREG32(mmD1VGA_CONTROL, d1vga_control); 925 WREG32(mmD2VGA_CONTROL, d2vga_control); 926 WREG32(mmVGA_RENDER_CONTROL, vga_render_control); 927 } 928 WREG32_SMC(ixROM_CNTL, rom_cntl); 929 return r; 930 } 931 932 static bool cik_read_bios_from_rom(struct amdgpu_device *adev, 933 u8 *bios, u32 length_bytes) 934 { 935 u32 *dw_ptr; 936 unsigned long flags; 937 u32 i, length_dw; 938 939 if (bios == NULL) 940 return false; 941 if (length_bytes == 0) 942 return false; 943 /* APU vbios image is part of sbios image */ 944 if (adev->flags & AMD_IS_APU) 945 return false; 946 947 dw_ptr = (u32 *)bios; 948 length_dw = ALIGN(length_bytes, 4) / 4; 949 /* take the smc lock since we are using the smc index */ 950 spin_lock_irqsave(&adev->smc_idx_lock, flags); 951 /* set rom index to 0 */ 952 WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX); 953 WREG32(mmSMC_IND_DATA_0, 0); 954 /* set index to data for continous read */ 955 WREG32(mmSMC_IND_INDEX_0, ixROM_DATA); 956 for (i = 0; i < length_dw; i++) 957 dw_ptr[i] = RREG32(mmSMC_IND_DATA_0); 958 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 959 960 return true; 961 } 962 963 static struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = { 964 {mmGRBM_STATUS, false}, 965 {mmGB_ADDR_CONFIG, false}, 966 {mmMC_ARB_RAMCFG, false}, 967 {mmGB_TILE_MODE0, false}, 968 {mmGB_TILE_MODE1, false}, 969 {mmGB_TILE_MODE2, false}, 970 {mmGB_TILE_MODE3, false}, 971 {mmGB_TILE_MODE4, false}, 972 {mmGB_TILE_MODE5, false}, 973 {mmGB_TILE_MODE6, false}, 974 {mmGB_TILE_MODE7, false}, 975 {mmGB_TILE_MODE8, false}, 976 {mmGB_TILE_MODE9, false}, 977 {mmGB_TILE_MODE10, false}, 978 {mmGB_TILE_MODE11, false}, 979 {mmGB_TILE_MODE12, false}, 980 {mmGB_TILE_MODE13, false}, 981 {mmGB_TILE_MODE14, false}, 982 {mmGB_TILE_MODE15, false}, 983 {mmGB_TILE_MODE16, false}, 984 {mmGB_TILE_MODE17, false}, 985 {mmGB_TILE_MODE18, false}, 986 {mmGB_TILE_MODE19, false}, 987 {mmGB_TILE_MODE20, false}, 988 {mmGB_TILE_MODE21, false}, 989 {mmGB_TILE_MODE22, false}, 990 {mmGB_TILE_MODE23, false}, 991 {mmGB_TILE_MODE24, false}, 992 {mmGB_TILE_MODE25, false}, 993 {mmGB_TILE_MODE26, false}, 994 {mmGB_TILE_MODE27, false}, 995 {mmGB_TILE_MODE28, false}, 996 {mmGB_TILE_MODE29, false}, 997 {mmGB_TILE_MODE30, false}, 998 {mmGB_TILE_MODE31, false}, 999 {mmGB_MACROTILE_MODE0, false}, 1000 {mmGB_MACROTILE_MODE1, false}, 1001 {mmGB_MACROTILE_MODE2, false}, 1002 {mmGB_MACROTILE_MODE3, false}, 1003 {mmGB_MACROTILE_MODE4, false}, 1004 {mmGB_MACROTILE_MODE5, false}, 1005 {mmGB_MACROTILE_MODE6, false}, 1006 {mmGB_MACROTILE_MODE7, false}, 1007 {mmGB_MACROTILE_MODE8, false}, 1008 {mmGB_MACROTILE_MODE9, false}, 1009 {mmGB_MACROTILE_MODE10, false}, 1010 {mmGB_MACROTILE_MODE11, false}, 1011 {mmGB_MACROTILE_MODE12, false}, 1012 {mmGB_MACROTILE_MODE13, false}, 1013 {mmGB_MACROTILE_MODE14, false}, 1014 {mmGB_MACROTILE_MODE15, false}, 1015 {mmCC_RB_BACKEND_DISABLE, false, true}, 1016 {mmGC_USER_RB_BACKEND_DISABLE, false, true}, 1017 {mmGB_BACKEND_MAP, false, false}, 1018 {mmPA_SC_RASTER_CONFIG, false, true}, 1019 {mmPA_SC_RASTER_CONFIG_1, false, true}, 1020 }; 1021 1022 static uint32_t cik_read_indexed_register(struct amdgpu_device *adev, 1023 u32 se_num, u32 sh_num, 1024 u32 reg_offset) 1025 { 1026 uint32_t val; 1027 1028 mutex_lock(&adev->grbm_idx_mutex); 1029 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1030 gfx_v7_0_select_se_sh(adev, se_num, sh_num); 1031 1032 val = RREG32(reg_offset); 1033 1034 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1035 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 1036 mutex_unlock(&adev->grbm_idx_mutex); 1037 return val; 1038 } 1039 1040 static int cik_read_register(struct amdgpu_device *adev, u32 se_num, 1041 u32 sh_num, u32 reg_offset, u32 *value) 1042 { 1043 uint32_t i; 1044 1045 *value = 0; 1046 for (i = 0; i < ARRAY_SIZE(cik_allowed_read_registers); i++) { 1047 if (reg_offset != cik_allowed_read_registers[i].reg_offset) 1048 continue; 1049 1050 if (!cik_allowed_read_registers[i].untouched) 1051 *value = cik_allowed_read_registers[i].grbm_indexed ? 1052 cik_read_indexed_register(adev, se_num, 1053 sh_num, reg_offset) : 1054 RREG32(reg_offset); 1055 return 0; 1056 } 1057 return -EINVAL; 1058 } 1059 1060 static void cik_print_gpu_status_regs(struct amdgpu_device *adev) 1061 { 1062 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", 1063 RREG32(mmGRBM_STATUS)); 1064 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n", 1065 RREG32(mmGRBM_STATUS2)); 1066 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n", 1067 RREG32(mmGRBM_STATUS_SE0)); 1068 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n", 1069 RREG32(mmGRBM_STATUS_SE1)); 1070 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n", 1071 RREG32(mmGRBM_STATUS_SE2)); 1072 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n", 1073 RREG32(mmGRBM_STATUS_SE3)); 1074 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", 1075 RREG32(mmSRBM_STATUS)); 1076 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", 1077 RREG32(mmSRBM_STATUS2)); 1078 dev_info(adev->dev, " SDMA0_STATUS_REG = 0x%08X\n", 1079 RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET)); 1080 dev_info(adev->dev, " SDMA1_STATUS_REG = 0x%08X\n", 1081 RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET)); 1082 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT)); 1083 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n", 1084 RREG32(mmCP_STALLED_STAT1)); 1085 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n", 1086 RREG32(mmCP_STALLED_STAT2)); 1087 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n", 1088 RREG32(mmCP_STALLED_STAT3)); 1089 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n", 1090 RREG32(mmCP_CPF_BUSY_STAT)); 1091 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n", 1092 RREG32(mmCP_CPF_STALLED_STAT1)); 1093 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS)); 1094 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT)); 1095 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n", 1096 RREG32(mmCP_CPC_STALLED_STAT1)); 1097 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS)); 1098 } 1099 1100 /** 1101 * cik_gpu_check_soft_reset - check which blocks are busy 1102 * 1103 * @adev: amdgpu_device pointer 1104 * 1105 * Check which blocks are busy and return the relevant reset 1106 * mask to be used by cik_gpu_soft_reset(). 1107 * Returns a mask of the blocks to be reset. 1108 */ 1109 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev) 1110 { 1111 u32 reset_mask = 0; 1112 u32 tmp; 1113 1114 /* GRBM_STATUS */ 1115 tmp = RREG32(mmGRBM_STATUS); 1116 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 1117 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 1118 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 1119 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 1120 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 1121 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) 1122 reset_mask |= AMDGPU_RESET_GFX; 1123 1124 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) 1125 reset_mask |= AMDGPU_RESET_CP; 1126 1127 /* GRBM_STATUS2 */ 1128 tmp = RREG32(mmGRBM_STATUS2); 1129 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK) 1130 reset_mask |= AMDGPU_RESET_RLC; 1131 1132 /* SDMA0_STATUS_REG */ 1133 tmp = RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET); 1134 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1135 reset_mask |= AMDGPU_RESET_DMA; 1136 1137 /* SDMA1_STATUS_REG */ 1138 tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET); 1139 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1140 reset_mask |= AMDGPU_RESET_DMA1; 1141 1142 /* SRBM_STATUS2 */ 1143 tmp = RREG32(mmSRBM_STATUS2); 1144 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) 1145 reset_mask |= AMDGPU_RESET_DMA; 1146 1147 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) 1148 reset_mask |= AMDGPU_RESET_DMA1; 1149 1150 /* SRBM_STATUS */ 1151 tmp = RREG32(mmSRBM_STATUS); 1152 1153 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 1154 reset_mask |= AMDGPU_RESET_IH; 1155 1156 if (tmp & SRBM_STATUS__SEM_BUSY_MASK) 1157 reset_mask |= AMDGPU_RESET_SEM; 1158 1159 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK) 1160 reset_mask |= AMDGPU_RESET_GRBM; 1161 1162 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1163 reset_mask |= AMDGPU_RESET_VMC; 1164 1165 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1166 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) 1167 reset_mask |= AMDGPU_RESET_MC; 1168 1169 if (amdgpu_display_is_display_hung(adev)) 1170 reset_mask |= AMDGPU_RESET_DISPLAY; 1171 1172 /* Skip MC reset as it's mostly likely not hung, just busy */ 1173 if (reset_mask & AMDGPU_RESET_MC) { 1174 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); 1175 reset_mask &= ~AMDGPU_RESET_MC; 1176 } 1177 1178 return reset_mask; 1179 } 1180 1181 /** 1182 * cik_gpu_soft_reset - soft reset GPU 1183 * 1184 * @adev: amdgpu_device pointer 1185 * @reset_mask: mask of which blocks to reset 1186 * 1187 * Soft reset the blocks specified in @reset_mask. 1188 */ 1189 static void cik_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask) 1190 { 1191 struct amdgpu_mode_mc_save save; 1192 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 1193 u32 tmp; 1194 1195 if (reset_mask == 0) 1196 return; 1197 1198 dev_info(adev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1199 1200 cik_print_gpu_status_regs(adev); 1201 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1202 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR)); 1203 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1204 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS)); 1205 1206 /* disable CG/PG */ 1207 1208 /* stop the rlc */ 1209 gfx_v7_0_rlc_stop(adev); 1210 1211 /* Disable GFX parsing/prefetching */ 1212 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK); 1213 1214 /* Disable MEC parsing/prefetching */ 1215 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); 1216 1217 if (reset_mask & AMDGPU_RESET_DMA) { 1218 /* sdma0 */ 1219 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); 1220 tmp |= SDMA0_F32_CNTL__HALT_MASK; 1221 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); 1222 } 1223 if (reset_mask & AMDGPU_RESET_DMA1) { 1224 /* sdma1 */ 1225 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); 1226 tmp |= SDMA0_F32_CNTL__HALT_MASK; 1227 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); 1228 } 1229 1230 gmc_v7_0_mc_stop(adev, &save); 1231 if (amdgpu_asic_wait_for_mc_idle(adev)) { 1232 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 1233 } 1234 1235 if (reset_mask & (AMDGPU_RESET_GFX | AMDGPU_RESET_COMPUTE | AMDGPU_RESET_CP)) 1236 grbm_soft_reset = GRBM_SOFT_RESET__SOFT_RESET_CP_MASK | 1237 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK; 1238 1239 if (reset_mask & AMDGPU_RESET_CP) { 1240 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK; 1241 1242 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; 1243 } 1244 1245 if (reset_mask & AMDGPU_RESET_DMA) 1246 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1247 1248 if (reset_mask & AMDGPU_RESET_DMA1) 1249 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1250 1251 if (reset_mask & AMDGPU_RESET_DISPLAY) 1252 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 1253 1254 if (reset_mask & AMDGPU_RESET_RLC) 1255 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 1256 1257 if (reset_mask & AMDGPU_RESET_SEM) 1258 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK; 1259 1260 if (reset_mask & AMDGPU_RESET_IH) 1261 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK; 1262 1263 if (reset_mask & AMDGPU_RESET_GRBM) 1264 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; 1265 1266 if (reset_mask & AMDGPU_RESET_VMC) 1267 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK; 1268 1269 if (!(adev->flags & AMD_IS_APU)) { 1270 if (reset_mask & AMDGPU_RESET_MC) 1271 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_MC_MASK; 1272 } 1273 1274 if (grbm_soft_reset) { 1275 tmp = RREG32(mmGRBM_SOFT_RESET); 1276 tmp |= grbm_soft_reset; 1277 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 1278 WREG32(mmGRBM_SOFT_RESET, tmp); 1279 tmp = RREG32(mmGRBM_SOFT_RESET); 1280 1281 udelay(50); 1282 1283 tmp &= ~grbm_soft_reset; 1284 WREG32(mmGRBM_SOFT_RESET, tmp); 1285 tmp = RREG32(mmGRBM_SOFT_RESET); 1286 } 1287 1288 if (srbm_soft_reset) { 1289 tmp = RREG32(mmSRBM_SOFT_RESET); 1290 tmp |= srbm_soft_reset; 1291 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1292 WREG32(mmSRBM_SOFT_RESET, tmp); 1293 tmp = RREG32(mmSRBM_SOFT_RESET); 1294 1295 udelay(50); 1296 1297 tmp &= ~srbm_soft_reset; 1298 WREG32(mmSRBM_SOFT_RESET, tmp); 1299 tmp = RREG32(mmSRBM_SOFT_RESET); 1300 } 1301 1302 /* Wait a little for things to settle down */ 1303 udelay(50); 1304 1305 gmc_v7_0_mc_resume(adev, &save); 1306 udelay(50); 1307 1308 cik_print_gpu_status_regs(adev); 1309 } 1310 1311 struct kv_reset_save_regs { 1312 u32 gmcon_reng_execute; 1313 u32 gmcon_misc; 1314 u32 gmcon_misc3; 1315 }; 1316 1317 static void kv_save_regs_for_reset(struct amdgpu_device *adev, 1318 struct kv_reset_save_regs *save) 1319 { 1320 save->gmcon_reng_execute = RREG32(mmGMCON_RENG_EXECUTE); 1321 save->gmcon_misc = RREG32(mmGMCON_MISC); 1322 save->gmcon_misc3 = RREG32(mmGMCON_MISC3); 1323 1324 WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute & 1325 ~GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK); 1326 WREG32(mmGMCON_MISC, save->gmcon_misc & 1327 ~(GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK | 1328 GMCON_MISC__STCTRL_STUTTER_EN_MASK)); 1329 } 1330 1331 static void kv_restore_regs_for_reset(struct amdgpu_device *adev, 1332 struct kv_reset_save_regs *save) 1333 { 1334 int i; 1335 1336 WREG32(mmGMCON_PGFSM_WRITE, 0); 1337 WREG32(mmGMCON_PGFSM_CONFIG, 0x200010ff); 1338 1339 for (i = 0; i < 5; i++) 1340 WREG32(mmGMCON_PGFSM_WRITE, 0); 1341 1342 WREG32(mmGMCON_PGFSM_WRITE, 0); 1343 WREG32(mmGMCON_PGFSM_CONFIG, 0x300010ff); 1344 1345 for (i = 0; i < 5; i++) 1346 WREG32(mmGMCON_PGFSM_WRITE, 0); 1347 1348 WREG32(mmGMCON_PGFSM_WRITE, 0x210000); 1349 WREG32(mmGMCON_PGFSM_CONFIG, 0xa00010ff); 1350 1351 for (i = 0; i < 5; i++) 1352 WREG32(mmGMCON_PGFSM_WRITE, 0); 1353 1354 WREG32(mmGMCON_PGFSM_WRITE, 0x21003); 1355 WREG32(mmGMCON_PGFSM_CONFIG, 0xb00010ff); 1356 1357 for (i = 0; i < 5; i++) 1358 WREG32(mmGMCON_PGFSM_WRITE, 0); 1359 1360 WREG32(mmGMCON_PGFSM_WRITE, 0x2b00); 1361 WREG32(mmGMCON_PGFSM_CONFIG, 0xc00010ff); 1362 1363 for (i = 0; i < 5; i++) 1364 WREG32(mmGMCON_PGFSM_WRITE, 0); 1365 1366 WREG32(mmGMCON_PGFSM_WRITE, 0); 1367 WREG32(mmGMCON_PGFSM_CONFIG, 0xd00010ff); 1368 1369 for (i = 0; i < 5; i++) 1370 WREG32(mmGMCON_PGFSM_WRITE, 0); 1371 1372 WREG32(mmGMCON_PGFSM_WRITE, 0x420000); 1373 WREG32(mmGMCON_PGFSM_CONFIG, 0x100010ff); 1374 1375 for (i = 0; i < 5; i++) 1376 WREG32(mmGMCON_PGFSM_WRITE, 0); 1377 1378 WREG32(mmGMCON_PGFSM_WRITE, 0x120202); 1379 WREG32(mmGMCON_PGFSM_CONFIG, 0x500010ff); 1380 1381 for (i = 0; i < 5; i++) 1382 WREG32(mmGMCON_PGFSM_WRITE, 0); 1383 1384 WREG32(mmGMCON_PGFSM_WRITE, 0x3e3e36); 1385 WREG32(mmGMCON_PGFSM_CONFIG, 0x600010ff); 1386 1387 for (i = 0; i < 5; i++) 1388 WREG32(mmGMCON_PGFSM_WRITE, 0); 1389 1390 WREG32(mmGMCON_PGFSM_WRITE, 0x373f3e); 1391 WREG32(mmGMCON_PGFSM_CONFIG, 0x700010ff); 1392 1393 for (i = 0; i < 5; i++) 1394 WREG32(mmGMCON_PGFSM_WRITE, 0); 1395 1396 WREG32(mmGMCON_PGFSM_WRITE, 0x3e1332); 1397 WREG32(mmGMCON_PGFSM_CONFIG, 0xe00010ff); 1398 1399 WREG32(mmGMCON_MISC3, save->gmcon_misc3); 1400 WREG32(mmGMCON_MISC, save->gmcon_misc); 1401 WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute); 1402 } 1403 1404 static void cik_gpu_pci_config_reset(struct amdgpu_device *adev) 1405 { 1406 struct amdgpu_mode_mc_save save; 1407 struct kv_reset_save_regs kv_save = { 0 }; 1408 u32 tmp, i; 1409 1410 dev_info(adev->dev, "GPU pci config reset\n"); 1411 1412 /* disable dpm? */ 1413 1414 /* disable cg/pg */ 1415 1416 /* Disable GFX parsing/prefetching */ 1417 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | 1418 CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK); 1419 1420 /* Disable MEC parsing/prefetching */ 1421 WREG32(mmCP_MEC_CNTL, 1422 CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); 1423 1424 /* sdma0 */ 1425 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); 1426 tmp |= SDMA0_F32_CNTL__HALT_MASK; 1427 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); 1428 /* sdma1 */ 1429 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); 1430 tmp |= SDMA0_F32_CNTL__HALT_MASK; 1431 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); 1432 /* XXX other engines? */ 1433 1434 /* halt the rlc, disable cp internal ints */ 1435 gfx_v7_0_rlc_stop(adev); 1436 1437 udelay(50); 1438 1439 /* disable mem access */ 1440 gmc_v7_0_mc_stop(adev, &save); 1441 if (amdgpu_asic_wait_for_mc_idle(adev)) { 1442 dev_warn(adev->dev, "Wait for MC idle timed out !\n"); 1443 } 1444 1445 if (adev->flags & AMD_IS_APU) 1446 kv_save_regs_for_reset(adev, &kv_save); 1447 1448 /* disable BM */ 1449 pci_clear_master(adev->pdev); 1450 /* reset */ 1451 amdgpu_pci_config_reset(adev); 1452 1453 udelay(100); 1454 1455 /* wait for asic to come out of reset */ 1456 for (i = 0; i < adev->usec_timeout; i++) { 1457 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) 1458 break; 1459 udelay(1); 1460 } 1461 1462 /* does asic init need to be run first??? */ 1463 if (adev->flags & AMD_IS_APU) 1464 kv_restore_regs_for_reset(adev, &kv_save); 1465 } 1466 1467 static void cik_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung) 1468 { 1469 u32 tmp = RREG32(mmBIOS_SCRATCH_3); 1470 1471 if (hung) 1472 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1473 else 1474 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1475 1476 WREG32(mmBIOS_SCRATCH_3, tmp); 1477 } 1478 1479 /** 1480 * cik_asic_reset - soft reset GPU 1481 * 1482 * @adev: amdgpu_device pointer 1483 * 1484 * Look up which blocks are hung and attempt 1485 * to reset them. 1486 * Returns 0 for success. 1487 */ 1488 static int cik_asic_reset(struct amdgpu_device *adev) 1489 { 1490 u32 reset_mask; 1491 1492 reset_mask = amdgpu_cik_gpu_check_soft_reset(adev); 1493 1494 if (reset_mask) 1495 cik_set_bios_scratch_engine_hung(adev, true); 1496 1497 /* try soft reset */ 1498 cik_gpu_soft_reset(adev, reset_mask); 1499 1500 reset_mask = amdgpu_cik_gpu_check_soft_reset(adev); 1501 1502 /* try pci config reset */ 1503 if (reset_mask && amdgpu_hard_reset) 1504 cik_gpu_pci_config_reset(adev); 1505 1506 reset_mask = amdgpu_cik_gpu_check_soft_reset(adev); 1507 1508 if (!reset_mask) 1509 cik_set_bios_scratch_engine_hung(adev, false); 1510 1511 return 0; 1512 } 1513 1514 static int cik_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 1515 u32 cntl_reg, u32 status_reg) 1516 { 1517 int r, i; 1518 struct atom_clock_dividers dividers; 1519 uint32_t tmp; 1520 1521 r = amdgpu_atombios_get_clock_dividers(adev, 1522 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 1523 clock, false, ÷rs); 1524 if (r) 1525 return r; 1526 1527 tmp = RREG32_SMC(cntl_reg); 1528 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK | 1529 CG_DCLK_CNTL__DCLK_DIVIDER_MASK); 1530 tmp |= dividers.post_divider; 1531 WREG32_SMC(cntl_reg, tmp); 1532 1533 for (i = 0; i < 100; i++) { 1534 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK) 1535 break; 1536 mdelay(10); 1537 } 1538 if (i == 100) 1539 return -ETIMEDOUT; 1540 1541 return 0; 1542 } 1543 1544 static int cik_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 1545 { 1546 int r = 0; 1547 1548 r = cik_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 1549 if (r) 1550 return r; 1551 1552 r = cik_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 1553 return r; 1554 } 1555 1556 static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 1557 { 1558 int r, i; 1559 struct atom_clock_dividers dividers; 1560 u32 tmp; 1561 1562 r = amdgpu_atombios_get_clock_dividers(adev, 1563 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 1564 ecclk, false, ÷rs); 1565 if (r) 1566 return r; 1567 1568 for (i = 0; i < 100; i++) { 1569 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK) 1570 break; 1571 mdelay(10); 1572 } 1573 if (i == 100) 1574 return -ETIMEDOUT; 1575 1576 tmp = RREG32_SMC(ixCG_ECLK_CNTL); 1577 tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | 1578 CG_ECLK_CNTL__ECLK_DIVIDER_MASK); 1579 tmp |= dividers.post_divider; 1580 WREG32_SMC(ixCG_ECLK_CNTL, tmp); 1581 1582 for (i = 0; i < 100; i++) { 1583 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK) 1584 break; 1585 mdelay(10); 1586 } 1587 if (i == 100) 1588 return -ETIMEDOUT; 1589 1590 return 0; 1591 } 1592 1593 static void cik_pcie_gen3_enable(struct amdgpu_device *adev) 1594 { 1595 struct pci_dev *root = adev->pdev->bus->self; 1596 int bridge_pos, gpu_pos; 1597 u32 speed_cntl, mask, current_data_rate; 1598 int ret, i; 1599 u16 tmp16; 1600 1601 if (pci_is_root_bus(adev->pdev->bus)) 1602 return; 1603 1604 if (amdgpu_pcie_gen2 == 0) 1605 return; 1606 1607 if (adev->flags & AMD_IS_APU) 1608 return; 1609 1610 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); 1611 if (ret != 0) 1612 return; 1613 1614 if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80))) 1615 return; 1616 1617 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); 1618 current_data_rate = (speed_cntl & PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) >> 1619 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 1620 if (mask & DRM_PCIE_SPEED_80) { 1621 if (current_data_rate == 2) { 1622 DRM_INFO("PCIE gen 3 link speeds already enabled\n"); 1623 return; 1624 } 1625 DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n"); 1626 } else if (mask & DRM_PCIE_SPEED_50) { 1627 if (current_data_rate == 1) { 1628 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 1629 return; 1630 } 1631 DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"); 1632 } 1633 1634 bridge_pos = pci_pcie_cap(root); 1635 if (!bridge_pos) 1636 return; 1637 1638 gpu_pos = pci_pcie_cap(adev->pdev); 1639 if (!gpu_pos) 1640 return; 1641 1642 if (mask & DRM_PCIE_SPEED_80) { 1643 /* re-try equalization if gen3 is not already enabled */ 1644 if (current_data_rate != 2) { 1645 u16 bridge_cfg, gpu_cfg; 1646 u16 bridge_cfg2, gpu_cfg2; 1647 u32 max_lw, current_lw, tmp; 1648 1649 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); 1650 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); 1651 1652 tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; 1653 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); 1654 1655 tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; 1656 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); 1657 1658 tmp = RREG32_PCIE(ixPCIE_LC_STATUS1); 1659 max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >> 1660 PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT; 1661 current_lw = (tmp & PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK) 1662 >> PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT; 1663 1664 if (current_lw < max_lw) { 1665 tmp = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL); 1666 if (tmp & PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK) { 1667 tmp &= ~(PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK | 1668 PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK); 1669 tmp |= (max_lw << 1670 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT); 1671 tmp |= PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK | 1672 PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK | 1673 PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK; 1674 WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, tmp); 1675 } 1676 } 1677 1678 for (i = 0; i < 10; i++) { 1679 /* check status */ 1680 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16); 1681 if (tmp16 & PCI_EXP_DEVSTA_TRPND) 1682 break; 1683 1684 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); 1685 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); 1686 1687 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2); 1688 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2); 1689 1690 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); 1691 tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK; 1692 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); 1693 1694 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); 1695 tmp |= PCIE_LC_CNTL4__LC_REDO_EQ_MASK; 1696 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); 1697 1698 mdelay(100); 1699 1700 /* linkctl */ 1701 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); 1702 tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 1703 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); 1704 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); 1705 1706 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16); 1707 tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 1708 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); 1709 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); 1710 1711 /* linkctl2 */ 1712 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); 1713 tmp16 &= ~((1 << 4) | (7 << 9)); 1714 tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9))); 1715 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); 1716 1717 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); 1718 tmp16 &= ~((1 << 4) | (7 << 9)); 1719 tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9))); 1720 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); 1721 1722 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); 1723 tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK; 1724 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); 1725 } 1726 } 1727 } 1728 1729 /* set the link speed */ 1730 speed_cntl |= PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK | 1731 PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK; 1732 speed_cntl &= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK; 1733 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); 1734 1735 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); 1736 tmp16 &= ~0xf; 1737 if (mask & DRM_PCIE_SPEED_80) 1738 tmp16 |= 3; /* gen3 */ 1739 else if (mask & DRM_PCIE_SPEED_50) 1740 tmp16 |= 2; /* gen2 */ 1741 else 1742 tmp16 |= 1; /* gen1 */ 1743 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); 1744 1745 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); 1746 speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK; 1747 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); 1748 1749 for (i = 0; i < adev->usec_timeout; i++) { 1750 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); 1751 if ((speed_cntl & PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK) == 0) 1752 break; 1753 udelay(1); 1754 } 1755 } 1756 1757 static void cik_program_aspm(struct amdgpu_device *adev) 1758 { 1759 u32 data, orig; 1760 bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false; 1761 bool disable_clkreq = false; 1762 1763 if (amdgpu_aspm == 0) 1764 return; 1765 1766 /* XXX double check APUs */ 1767 if (adev->flags & AMD_IS_APU) 1768 return; 1769 1770 orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); 1771 data &= ~PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK; 1772 data |= (0x24 << PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT) | 1773 PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK; 1774 if (orig != data) 1775 WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data); 1776 1777 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3); 1778 data |= PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK; 1779 if (orig != data) 1780 WREG32_PCIE(ixPCIE_LC_CNTL3, data); 1781 1782 orig = data = RREG32_PCIE(ixPCIE_P_CNTL); 1783 data |= PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK; 1784 if (orig != data) 1785 WREG32_PCIE(ixPCIE_P_CNTL, data); 1786 1787 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); 1788 data &= ~(PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK | 1789 PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK); 1790 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 1791 if (!disable_l0s) 1792 data |= (7 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT); 1793 1794 if (!disable_l1) { 1795 data |= (7 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT); 1796 data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 1797 if (orig != data) 1798 WREG32_PCIE(ixPCIE_LC_CNTL, data); 1799 1800 if (!disable_plloff_in_l1) { 1801 bool clk_req_support; 1802 1803 orig = data = RREG32_PCIE(ixPB0_PIF_PWRDOWN_0); 1804 data &= ~(PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK | 1805 PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK); 1806 data |= (7 << PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) | 1807 (7 << PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT); 1808 if (orig != data) 1809 WREG32_PCIE(ixPB0_PIF_PWRDOWN_0, data); 1810 1811 orig = data = RREG32_PCIE(ixPB0_PIF_PWRDOWN_1); 1812 data &= ~(PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK | 1813 PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK); 1814 data |= (7 << PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) | 1815 (7 << PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT); 1816 if (orig != data) 1817 WREG32_PCIE(ixPB0_PIF_PWRDOWN_1, data); 1818 1819 orig = data = RREG32_PCIE(ixPB1_PIF_PWRDOWN_0); 1820 data &= ~(PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK | 1821 PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK); 1822 data |= (7 << PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) | 1823 (7 << PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT); 1824 if (orig != data) 1825 WREG32_PCIE(ixPB1_PIF_PWRDOWN_0, data); 1826 1827 orig = data = RREG32_PCIE(ixPB1_PIF_PWRDOWN_1); 1828 data &= ~(PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK | 1829 PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK); 1830 data |= (7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) | 1831 (7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT); 1832 if (orig != data) 1833 WREG32_PCIE(ixPB1_PIF_PWRDOWN_1, data); 1834 1835 orig = data = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL); 1836 data &= ~PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK; 1837 data |= ~(3 << PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT); 1838 if (orig != data) 1839 WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, data); 1840 1841 if (!disable_clkreq) { 1842 struct pci_dev *root = adev->pdev->bus->self; 1843 u32 lnkcap; 1844 1845 clk_req_support = false; 1846 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap); 1847 if (lnkcap & PCI_EXP_LNKCAP_CLKPM) 1848 clk_req_support = true; 1849 } else { 1850 clk_req_support = false; 1851 } 1852 1853 if (clk_req_support) { 1854 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL2); 1855 data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK | 1856 PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK; 1857 if (orig != data) 1858 WREG32_PCIE(ixPCIE_LC_CNTL2, data); 1859 1860 orig = data = RREG32_SMC(ixTHM_CLK_CNTL); 1861 data &= ~(THM_CLK_CNTL__CMON_CLK_SEL_MASK | 1862 THM_CLK_CNTL__TMON_CLK_SEL_MASK); 1863 data |= (1 << THM_CLK_CNTL__CMON_CLK_SEL__SHIFT) | 1864 (1 << THM_CLK_CNTL__TMON_CLK_SEL__SHIFT); 1865 if (orig != data) 1866 WREG32_SMC(ixTHM_CLK_CNTL, data); 1867 1868 orig = data = RREG32_SMC(ixMISC_CLK_CTRL); 1869 data &= ~(MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK | 1870 MISC_CLK_CTRL__ZCLK_SEL_MASK); 1871 data |= (1 << MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT) | 1872 (1 << MISC_CLK_CTRL__ZCLK_SEL__SHIFT); 1873 if (orig != data) 1874 WREG32_SMC(ixMISC_CLK_CTRL, data); 1875 1876 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL); 1877 data &= ~CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK; 1878 if (orig != data) 1879 WREG32_SMC(ixCG_CLKPIN_CNTL, data); 1880 1881 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL_2); 1882 data &= ~CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK; 1883 if (orig != data) 1884 WREG32_SMC(ixCG_CLKPIN_CNTL_2, data); 1885 1886 orig = data = RREG32_SMC(ixMPLL_BYPASSCLK_SEL); 1887 data &= ~MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK; 1888 data |= (4 << MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT); 1889 if (orig != data) 1890 WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data); 1891 } 1892 } 1893 } else { 1894 if (orig != data) 1895 WREG32_PCIE(ixPCIE_LC_CNTL, data); 1896 } 1897 1898 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 1899 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 1900 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 1901 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK; 1902 if (orig != data) 1903 WREG32_PCIE(ixPCIE_CNTL2, data); 1904 1905 if (!disable_l0s) { 1906 data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); 1907 if ((data & PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) == 1908 PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) { 1909 data = RREG32_PCIE(ixPCIE_LC_STATUS1); 1910 if ((data & PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK) && 1911 (data & PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK)) { 1912 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); 1913 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 1914 if (orig != data) 1915 WREG32_PCIE(ixPCIE_LC_CNTL, data); 1916 } 1917 } 1918 } 1919 } 1920 1921 static uint32_t cik_get_rev_id(struct amdgpu_device *adev) 1922 { 1923 return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK) 1924 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT; 1925 } 1926 1927 static const struct amdgpu_ip_block_version bonaire_ip_blocks[] = 1928 { 1929 /* ORDER MATTERS! */ 1930 { 1931 .type = AMD_IP_BLOCK_TYPE_COMMON, 1932 .major = 1, 1933 .minor = 0, 1934 .rev = 0, 1935 .funcs = &cik_common_ip_funcs, 1936 }, 1937 { 1938 .type = AMD_IP_BLOCK_TYPE_GMC, 1939 .major = 7, 1940 .minor = 0, 1941 .rev = 0, 1942 .funcs = &gmc_v7_0_ip_funcs, 1943 }, 1944 { 1945 .type = AMD_IP_BLOCK_TYPE_IH, 1946 .major = 2, 1947 .minor = 0, 1948 .rev = 0, 1949 .funcs = &cik_ih_ip_funcs, 1950 }, 1951 { 1952 .type = AMD_IP_BLOCK_TYPE_SMC, 1953 .major = 7, 1954 .minor = 0, 1955 .rev = 0, 1956 .funcs = &ci_dpm_ip_funcs, 1957 }, 1958 { 1959 .type = AMD_IP_BLOCK_TYPE_DCE, 1960 .major = 8, 1961 .minor = 2, 1962 .rev = 0, 1963 .funcs = &dce_v8_0_ip_funcs, 1964 }, 1965 { 1966 .type = AMD_IP_BLOCK_TYPE_GFX, 1967 .major = 7, 1968 .minor = 2, 1969 .rev = 0, 1970 .funcs = &gfx_v7_0_ip_funcs, 1971 }, 1972 { 1973 .type = AMD_IP_BLOCK_TYPE_SDMA, 1974 .major = 2, 1975 .minor = 0, 1976 .rev = 0, 1977 .funcs = &cik_sdma_ip_funcs, 1978 }, 1979 { 1980 .type = AMD_IP_BLOCK_TYPE_UVD, 1981 .major = 4, 1982 .minor = 2, 1983 .rev = 0, 1984 .funcs = &uvd_v4_2_ip_funcs, 1985 }, 1986 { 1987 .type = AMD_IP_BLOCK_TYPE_VCE, 1988 .major = 2, 1989 .minor = 0, 1990 .rev = 0, 1991 .funcs = &vce_v2_0_ip_funcs, 1992 }, 1993 }; 1994 1995 static const struct amdgpu_ip_block_version hawaii_ip_blocks[] = 1996 { 1997 /* ORDER MATTERS! */ 1998 { 1999 .type = AMD_IP_BLOCK_TYPE_COMMON, 2000 .major = 1, 2001 .minor = 0, 2002 .rev = 0, 2003 .funcs = &cik_common_ip_funcs, 2004 }, 2005 { 2006 .type = AMD_IP_BLOCK_TYPE_GMC, 2007 .major = 7, 2008 .minor = 0, 2009 .rev = 0, 2010 .funcs = &gmc_v7_0_ip_funcs, 2011 }, 2012 { 2013 .type = AMD_IP_BLOCK_TYPE_IH, 2014 .major = 2, 2015 .minor = 0, 2016 .rev = 0, 2017 .funcs = &cik_ih_ip_funcs, 2018 }, 2019 { 2020 .type = AMD_IP_BLOCK_TYPE_SMC, 2021 .major = 7, 2022 .minor = 0, 2023 .rev = 0, 2024 .funcs = &ci_dpm_ip_funcs, 2025 }, 2026 { 2027 .type = AMD_IP_BLOCK_TYPE_DCE, 2028 .major = 8, 2029 .minor = 5, 2030 .rev = 0, 2031 .funcs = &dce_v8_0_ip_funcs, 2032 }, 2033 { 2034 .type = AMD_IP_BLOCK_TYPE_GFX, 2035 .major = 7, 2036 .minor = 3, 2037 .rev = 0, 2038 .funcs = &gfx_v7_0_ip_funcs, 2039 }, 2040 { 2041 .type = AMD_IP_BLOCK_TYPE_SDMA, 2042 .major = 2, 2043 .minor = 0, 2044 .rev = 0, 2045 .funcs = &cik_sdma_ip_funcs, 2046 }, 2047 { 2048 .type = AMD_IP_BLOCK_TYPE_UVD, 2049 .major = 4, 2050 .minor = 2, 2051 .rev = 0, 2052 .funcs = &uvd_v4_2_ip_funcs, 2053 }, 2054 { 2055 .type = AMD_IP_BLOCK_TYPE_VCE, 2056 .major = 2, 2057 .minor = 0, 2058 .rev = 0, 2059 .funcs = &vce_v2_0_ip_funcs, 2060 }, 2061 }; 2062 2063 static const struct amdgpu_ip_block_version kabini_ip_blocks[] = 2064 { 2065 /* ORDER MATTERS! */ 2066 { 2067 .type = AMD_IP_BLOCK_TYPE_COMMON, 2068 .major = 1, 2069 .minor = 0, 2070 .rev = 0, 2071 .funcs = &cik_common_ip_funcs, 2072 }, 2073 { 2074 .type = AMD_IP_BLOCK_TYPE_GMC, 2075 .major = 7, 2076 .minor = 0, 2077 .rev = 0, 2078 .funcs = &gmc_v7_0_ip_funcs, 2079 }, 2080 { 2081 .type = AMD_IP_BLOCK_TYPE_IH, 2082 .major = 2, 2083 .minor = 0, 2084 .rev = 0, 2085 .funcs = &cik_ih_ip_funcs, 2086 }, 2087 { 2088 .type = AMD_IP_BLOCK_TYPE_SMC, 2089 .major = 7, 2090 .minor = 0, 2091 .rev = 0, 2092 .funcs = &kv_dpm_ip_funcs, 2093 }, 2094 { 2095 .type = AMD_IP_BLOCK_TYPE_DCE, 2096 .major = 8, 2097 .minor = 3, 2098 .rev = 0, 2099 .funcs = &dce_v8_0_ip_funcs, 2100 }, 2101 { 2102 .type = AMD_IP_BLOCK_TYPE_GFX, 2103 .major = 7, 2104 .minor = 2, 2105 .rev = 0, 2106 .funcs = &gfx_v7_0_ip_funcs, 2107 }, 2108 { 2109 .type = AMD_IP_BLOCK_TYPE_SDMA, 2110 .major = 2, 2111 .minor = 0, 2112 .rev = 0, 2113 .funcs = &cik_sdma_ip_funcs, 2114 }, 2115 { 2116 .type = AMD_IP_BLOCK_TYPE_UVD, 2117 .major = 4, 2118 .minor = 2, 2119 .rev = 0, 2120 .funcs = &uvd_v4_2_ip_funcs, 2121 }, 2122 { 2123 .type = AMD_IP_BLOCK_TYPE_VCE, 2124 .major = 2, 2125 .minor = 0, 2126 .rev = 0, 2127 .funcs = &vce_v2_0_ip_funcs, 2128 }, 2129 }; 2130 2131 static const struct amdgpu_ip_block_version mullins_ip_blocks[] = 2132 { 2133 /* ORDER MATTERS! */ 2134 { 2135 .type = AMD_IP_BLOCK_TYPE_COMMON, 2136 .major = 1, 2137 .minor = 0, 2138 .rev = 0, 2139 .funcs = &cik_common_ip_funcs, 2140 }, 2141 { 2142 .type = AMD_IP_BLOCK_TYPE_GMC, 2143 .major = 7, 2144 .minor = 0, 2145 .rev = 0, 2146 .funcs = &gmc_v7_0_ip_funcs, 2147 }, 2148 { 2149 .type = AMD_IP_BLOCK_TYPE_IH, 2150 .major = 2, 2151 .minor = 0, 2152 .rev = 0, 2153 .funcs = &cik_ih_ip_funcs, 2154 }, 2155 { 2156 .type = AMD_IP_BLOCK_TYPE_SMC, 2157 .major = 7, 2158 .minor = 0, 2159 .rev = 0, 2160 .funcs = &kv_dpm_ip_funcs, 2161 }, 2162 { 2163 .type = AMD_IP_BLOCK_TYPE_DCE, 2164 .major = 8, 2165 .minor = 3, 2166 .rev = 0, 2167 .funcs = &dce_v8_0_ip_funcs, 2168 }, 2169 { 2170 .type = AMD_IP_BLOCK_TYPE_GFX, 2171 .major = 7, 2172 .minor = 2, 2173 .rev = 0, 2174 .funcs = &gfx_v7_0_ip_funcs, 2175 }, 2176 { 2177 .type = AMD_IP_BLOCK_TYPE_SDMA, 2178 .major = 2, 2179 .minor = 0, 2180 .rev = 0, 2181 .funcs = &cik_sdma_ip_funcs, 2182 }, 2183 { 2184 .type = AMD_IP_BLOCK_TYPE_UVD, 2185 .major = 4, 2186 .minor = 2, 2187 .rev = 0, 2188 .funcs = &uvd_v4_2_ip_funcs, 2189 }, 2190 { 2191 .type = AMD_IP_BLOCK_TYPE_VCE, 2192 .major = 2, 2193 .minor = 0, 2194 .rev = 0, 2195 .funcs = &vce_v2_0_ip_funcs, 2196 }, 2197 }; 2198 2199 static const struct amdgpu_ip_block_version kaveri_ip_blocks[] = 2200 { 2201 /* ORDER MATTERS! */ 2202 { 2203 .type = AMD_IP_BLOCK_TYPE_COMMON, 2204 .major = 1, 2205 .minor = 0, 2206 .rev = 0, 2207 .funcs = &cik_common_ip_funcs, 2208 }, 2209 { 2210 .type = AMD_IP_BLOCK_TYPE_GMC, 2211 .major = 7, 2212 .minor = 0, 2213 .rev = 0, 2214 .funcs = &gmc_v7_0_ip_funcs, 2215 }, 2216 { 2217 .type = AMD_IP_BLOCK_TYPE_IH, 2218 .major = 2, 2219 .minor = 0, 2220 .rev = 0, 2221 .funcs = &cik_ih_ip_funcs, 2222 }, 2223 { 2224 .type = AMD_IP_BLOCK_TYPE_SMC, 2225 .major = 7, 2226 .minor = 0, 2227 .rev = 0, 2228 .funcs = &kv_dpm_ip_funcs, 2229 }, 2230 { 2231 .type = AMD_IP_BLOCK_TYPE_DCE, 2232 .major = 8, 2233 .minor = 1, 2234 .rev = 0, 2235 .funcs = &dce_v8_0_ip_funcs, 2236 }, 2237 { 2238 .type = AMD_IP_BLOCK_TYPE_GFX, 2239 .major = 7, 2240 .minor = 1, 2241 .rev = 0, 2242 .funcs = &gfx_v7_0_ip_funcs, 2243 }, 2244 { 2245 .type = AMD_IP_BLOCK_TYPE_SDMA, 2246 .major = 2, 2247 .minor = 0, 2248 .rev = 0, 2249 .funcs = &cik_sdma_ip_funcs, 2250 }, 2251 { 2252 .type = AMD_IP_BLOCK_TYPE_UVD, 2253 .major = 4, 2254 .minor = 2, 2255 .rev = 0, 2256 .funcs = &uvd_v4_2_ip_funcs, 2257 }, 2258 { 2259 .type = AMD_IP_BLOCK_TYPE_VCE, 2260 .major = 2, 2261 .minor = 0, 2262 .rev = 0, 2263 .funcs = &vce_v2_0_ip_funcs, 2264 }, 2265 }; 2266 2267 int cik_set_ip_blocks(struct amdgpu_device *adev) 2268 { 2269 switch (adev->asic_type) { 2270 case CHIP_BONAIRE: 2271 adev->ip_blocks = bonaire_ip_blocks; 2272 adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks); 2273 break; 2274 case CHIP_HAWAII: 2275 adev->ip_blocks = hawaii_ip_blocks; 2276 adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks); 2277 break; 2278 case CHIP_KAVERI: 2279 adev->ip_blocks = kaveri_ip_blocks; 2280 adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks); 2281 break; 2282 case CHIP_KABINI: 2283 adev->ip_blocks = kabini_ip_blocks; 2284 adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks); 2285 break; 2286 case CHIP_MULLINS: 2287 adev->ip_blocks = mullins_ip_blocks; 2288 adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks); 2289 break; 2290 default: 2291 /* FIXME: not supported yet */ 2292 return -EINVAL; 2293 } 2294 2295 return 0; 2296 } 2297 2298 static const struct amdgpu_asic_funcs cik_asic_funcs = 2299 { 2300 .read_disabled_bios = &cik_read_disabled_bios, 2301 .read_bios_from_rom = &cik_read_bios_from_rom, 2302 .read_register = &cik_read_register, 2303 .reset = &cik_asic_reset, 2304 .set_vga_state = &cik_vga_set_state, 2305 .get_xclk = &cik_get_xclk, 2306 .set_uvd_clocks = &cik_set_uvd_clocks, 2307 .set_vce_clocks = &cik_set_vce_clocks, 2308 .get_cu_info = &gfx_v7_0_get_cu_info, 2309 /* these should be moved to their own ip modules */ 2310 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter, 2311 .wait_for_mc_idle = &gmc_v7_0_mc_wait_for_idle, 2312 }; 2313 2314 static int cik_common_early_init(void *handle) 2315 { 2316 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2317 2318 adev->smc_rreg = &cik_smc_rreg; 2319 adev->smc_wreg = &cik_smc_wreg; 2320 adev->pcie_rreg = &cik_pcie_rreg; 2321 adev->pcie_wreg = &cik_pcie_wreg; 2322 adev->uvd_ctx_rreg = &cik_uvd_ctx_rreg; 2323 adev->uvd_ctx_wreg = &cik_uvd_ctx_wreg; 2324 adev->didt_rreg = &cik_didt_rreg; 2325 adev->didt_wreg = &cik_didt_wreg; 2326 2327 adev->asic_funcs = &cik_asic_funcs; 2328 2329 adev->has_uvd = true; 2330 2331 adev->rev_id = cik_get_rev_id(adev); 2332 adev->external_rev_id = 0xFF; 2333 switch (adev->asic_type) { 2334 case CHIP_BONAIRE: 2335 adev->cg_flags = 2336 AMDGPU_CG_SUPPORT_GFX_MGCG | 2337 AMDGPU_CG_SUPPORT_GFX_MGLS | 2338 /*AMDGPU_CG_SUPPORT_GFX_CGCG |*/ 2339 AMDGPU_CG_SUPPORT_GFX_CGLS | 2340 AMDGPU_CG_SUPPORT_GFX_CGTS | 2341 AMDGPU_CG_SUPPORT_GFX_CGTS_LS | 2342 AMDGPU_CG_SUPPORT_GFX_CP_LS | 2343 AMDGPU_CG_SUPPORT_MC_LS | 2344 AMDGPU_CG_SUPPORT_MC_MGCG | 2345 AMDGPU_CG_SUPPORT_SDMA_MGCG | 2346 AMDGPU_CG_SUPPORT_SDMA_LS | 2347 AMDGPU_CG_SUPPORT_BIF_LS | 2348 AMDGPU_CG_SUPPORT_VCE_MGCG | 2349 AMDGPU_CG_SUPPORT_UVD_MGCG | 2350 AMDGPU_CG_SUPPORT_HDP_LS | 2351 AMDGPU_CG_SUPPORT_HDP_MGCG; 2352 adev->pg_flags = 0; 2353 adev->external_rev_id = adev->rev_id + 0x14; 2354 break; 2355 case CHIP_HAWAII: 2356 adev->cg_flags = 2357 AMDGPU_CG_SUPPORT_GFX_MGCG | 2358 AMDGPU_CG_SUPPORT_GFX_MGLS | 2359 /*AMDGPU_CG_SUPPORT_GFX_CGCG |*/ 2360 AMDGPU_CG_SUPPORT_GFX_CGLS | 2361 AMDGPU_CG_SUPPORT_GFX_CGTS | 2362 AMDGPU_CG_SUPPORT_GFX_CP_LS | 2363 AMDGPU_CG_SUPPORT_MC_LS | 2364 AMDGPU_CG_SUPPORT_MC_MGCG | 2365 AMDGPU_CG_SUPPORT_SDMA_MGCG | 2366 AMDGPU_CG_SUPPORT_SDMA_LS | 2367 AMDGPU_CG_SUPPORT_BIF_LS | 2368 AMDGPU_CG_SUPPORT_VCE_MGCG | 2369 AMDGPU_CG_SUPPORT_UVD_MGCG | 2370 AMDGPU_CG_SUPPORT_HDP_LS | 2371 AMDGPU_CG_SUPPORT_HDP_MGCG; 2372 adev->pg_flags = 0; 2373 adev->external_rev_id = 0x28; 2374 break; 2375 case CHIP_KAVERI: 2376 adev->cg_flags = 2377 AMDGPU_CG_SUPPORT_GFX_MGCG | 2378 AMDGPU_CG_SUPPORT_GFX_MGLS | 2379 /*AMDGPU_CG_SUPPORT_GFX_CGCG |*/ 2380 AMDGPU_CG_SUPPORT_GFX_CGLS | 2381 AMDGPU_CG_SUPPORT_GFX_CGTS | 2382 AMDGPU_CG_SUPPORT_GFX_CGTS_LS | 2383 AMDGPU_CG_SUPPORT_GFX_CP_LS | 2384 AMDGPU_CG_SUPPORT_SDMA_MGCG | 2385 AMDGPU_CG_SUPPORT_SDMA_LS | 2386 AMDGPU_CG_SUPPORT_BIF_LS | 2387 AMDGPU_CG_SUPPORT_VCE_MGCG | 2388 AMDGPU_CG_SUPPORT_UVD_MGCG | 2389 AMDGPU_CG_SUPPORT_HDP_LS | 2390 AMDGPU_CG_SUPPORT_HDP_MGCG; 2391 adev->pg_flags = 2392 /*AMDGPU_PG_SUPPORT_GFX_PG | 2393 AMDGPU_PG_SUPPORT_GFX_SMG | 2394 AMDGPU_PG_SUPPORT_GFX_DMG |*/ 2395 AMDGPU_PG_SUPPORT_UVD | 2396 /*AMDGPU_PG_SUPPORT_VCE | 2397 AMDGPU_PG_SUPPORT_CP | 2398 AMDGPU_PG_SUPPORT_GDS | 2399 AMDGPU_PG_SUPPORT_RLC_SMU_HS | 2400 AMDGPU_PG_SUPPORT_ACP | 2401 AMDGPU_PG_SUPPORT_SAMU |*/ 2402 0; 2403 if (adev->pdev->device == 0x1312 || 2404 adev->pdev->device == 0x1316 || 2405 adev->pdev->device == 0x1317) 2406 adev->external_rev_id = 0x41; 2407 else 2408 adev->external_rev_id = 0x1; 2409 break; 2410 case CHIP_KABINI: 2411 case CHIP_MULLINS: 2412 adev->cg_flags = 2413 AMDGPU_CG_SUPPORT_GFX_MGCG | 2414 AMDGPU_CG_SUPPORT_GFX_MGLS | 2415 /*AMDGPU_CG_SUPPORT_GFX_CGCG |*/ 2416 AMDGPU_CG_SUPPORT_GFX_CGLS | 2417 AMDGPU_CG_SUPPORT_GFX_CGTS | 2418 AMDGPU_CG_SUPPORT_GFX_CGTS_LS | 2419 AMDGPU_CG_SUPPORT_GFX_CP_LS | 2420 AMDGPU_CG_SUPPORT_SDMA_MGCG | 2421 AMDGPU_CG_SUPPORT_SDMA_LS | 2422 AMDGPU_CG_SUPPORT_BIF_LS | 2423 AMDGPU_CG_SUPPORT_VCE_MGCG | 2424 AMDGPU_CG_SUPPORT_UVD_MGCG | 2425 AMDGPU_CG_SUPPORT_HDP_LS | 2426 AMDGPU_CG_SUPPORT_HDP_MGCG; 2427 adev->pg_flags = 2428 /*AMDGPU_PG_SUPPORT_GFX_PG | 2429 AMDGPU_PG_SUPPORT_GFX_SMG | */ 2430 AMDGPU_PG_SUPPORT_UVD | 2431 /*AMDGPU_PG_SUPPORT_VCE | 2432 AMDGPU_PG_SUPPORT_CP | 2433 AMDGPU_PG_SUPPORT_GDS | 2434 AMDGPU_PG_SUPPORT_RLC_SMU_HS | 2435 AMDGPU_PG_SUPPORT_SAMU |*/ 2436 0; 2437 if (adev->asic_type == CHIP_KABINI) { 2438 if (adev->rev_id == 0) 2439 adev->external_rev_id = 0x81; 2440 else if (adev->rev_id == 1) 2441 adev->external_rev_id = 0x82; 2442 else if (adev->rev_id == 2) 2443 adev->external_rev_id = 0x85; 2444 } else 2445 adev->external_rev_id = adev->rev_id + 0xa1; 2446 break; 2447 default: 2448 /* FIXME: not supported yet */ 2449 return -EINVAL; 2450 } 2451 2452 return 0; 2453 } 2454 2455 static int cik_common_sw_init(void *handle) 2456 { 2457 return 0; 2458 } 2459 2460 static int cik_common_sw_fini(void *handle) 2461 { 2462 return 0; 2463 } 2464 2465 static int cik_common_hw_init(void *handle) 2466 { 2467 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2468 2469 /* move the golden regs per IP block */ 2470 cik_init_golden_registers(adev); 2471 /* enable pcie gen2/3 link */ 2472 cik_pcie_gen3_enable(adev); 2473 /* enable aspm */ 2474 cik_program_aspm(adev); 2475 2476 return 0; 2477 } 2478 2479 static int cik_common_hw_fini(void *handle) 2480 { 2481 return 0; 2482 } 2483 2484 static int cik_common_suspend(void *handle) 2485 { 2486 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2487 2488 amdgpu_amdkfd_suspend(adev); 2489 2490 return cik_common_hw_fini(adev); 2491 } 2492 2493 static int cik_common_resume(void *handle) 2494 { 2495 int r; 2496 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2497 2498 r = cik_common_hw_init(adev); 2499 if (r) 2500 return r; 2501 2502 return amdgpu_amdkfd_resume(adev); 2503 } 2504 2505 static bool cik_common_is_idle(void *handle) 2506 { 2507 return true; 2508 } 2509 2510 static int cik_common_wait_for_idle(void *handle) 2511 { 2512 return 0; 2513 } 2514 2515 static void cik_common_print_status(void *handle) 2516 { 2517 2518 } 2519 2520 static int cik_common_soft_reset(void *handle) 2521 { 2522 /* XXX hard reset?? */ 2523 return 0; 2524 } 2525 2526 static int cik_common_set_clockgating_state(void *handle, 2527 enum amd_clockgating_state state) 2528 { 2529 return 0; 2530 } 2531 2532 static int cik_common_set_powergating_state(void *handle, 2533 enum amd_powergating_state state) 2534 { 2535 return 0; 2536 } 2537 2538 const struct amd_ip_funcs cik_common_ip_funcs = { 2539 .early_init = cik_common_early_init, 2540 .late_init = NULL, 2541 .sw_init = cik_common_sw_init, 2542 .sw_fini = cik_common_sw_fini, 2543 .hw_init = cik_common_hw_init, 2544 .hw_fini = cik_common_hw_fini, 2545 .suspend = cik_common_suspend, 2546 .resume = cik_common_resume, 2547 .is_idle = cik_common_is_idle, 2548 .wait_for_idle = cik_common_wait_for_idle, 2549 .soft_reset = cik_common_soft_reset, 2550 .print_status = cik_common_print_status, 2551 .set_clockgating_state = cik_common_set_clockgating_state, 2552 .set_powergating_state = cik_common_set_powergating_state, 2553 }; 2554