1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_VM_H__ 25 #define __AMDGPU_VM_H__ 26 27 #include <linux/idr.h> 28 #include <linux/kfifo.h> 29 #include <linux/rbtree.h> 30 #include <drm/gpu_scheduler.h> 31 #include <drm/drm_file.h> 32 #include <drm/ttm/ttm_bo.h> 33 #include <linux/sched/mm.h> 34 35 #include "amdgpu_sync.h" 36 #include "amdgpu_ring.h" 37 #include "amdgpu_ids.h" 38 39 struct drm_exec; 40 41 struct amdgpu_bo_va; 42 struct amdgpu_job; 43 struct amdgpu_bo_list_entry; 44 struct amdgpu_bo_vm; 45 struct amdgpu_mem_stats; 46 47 /* 48 * GPUVM handling 49 */ 50 51 /* Maximum number of PTEs the hardware can write with one command */ 52 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF 53 54 /* number of entries in page table */ 55 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) 56 57 #define AMDGPU_PTE_VALID (1ULL << 0) 58 #define AMDGPU_PTE_SYSTEM (1ULL << 1) 59 #define AMDGPU_PTE_SNOOPED (1ULL << 2) 60 61 /* RV+ */ 62 #define AMDGPU_PTE_TMZ (1ULL << 3) 63 64 /* VI only */ 65 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) 66 67 #define AMDGPU_PTE_READABLE (1ULL << 5) 68 #define AMDGPU_PTE_WRITEABLE (1ULL << 6) 69 70 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) 71 72 /* TILED for VEGA10, reserved for older ASICs */ 73 #define AMDGPU_PTE_PRT (1ULL << 51) 74 75 /* PDE is handled as PTE for VEGA10 */ 76 #define AMDGPU_PDE_PTE (1ULL << 54) 77 78 #define AMDGPU_PTE_LOG (1ULL << 55) 79 80 /* PTE is handled as PDE for VEGA10 (Translate Further) */ 81 #define AMDGPU_PTE_TF (1ULL << 56) 82 83 /* MALL noalloc for sienna_cichlid, reserved for older ASICs */ 84 #define AMDGPU_PTE_NOALLOC (1ULL << 58) 85 86 /* PDE Block Fragment Size for VEGA10 */ 87 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59) 88 89 /* Flag combination to set no-retry with TF disabled */ 90 #define AMDGPU_VM_NORETRY_FLAGS (AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE | \ 91 AMDGPU_PTE_TF) 92 93 /* Flag combination to set no-retry with TF enabled */ 94 #define AMDGPU_VM_NORETRY_FLAGS_TF (AMDGPU_PTE_VALID | AMDGPU_PTE_SYSTEM | \ 95 AMDGPU_PTE_PRT) 96 /* For GFX9 */ 97 #define AMDGPU_PTE_MTYPE_VG10(a) ((uint64_t)(a) << 57) 98 #define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10(3ULL) 99 100 #define AMDGPU_MTYPE_NC 0 101 #define AMDGPU_MTYPE_CC 2 102 103 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ 104 | AMDGPU_PTE_SNOOPED \ 105 | AMDGPU_PTE_EXECUTABLE \ 106 | AMDGPU_PTE_READABLE \ 107 | AMDGPU_PTE_WRITEABLE \ 108 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC)) 109 110 /* gfx10 */ 111 #define AMDGPU_PTE_MTYPE_NV10(a) ((uint64_t)(a) << 48) 112 #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10(7ULL) 113 114 /* gfx12 */ 115 #define AMDGPU_PTE_PRT_GFX12 (1ULL << 56) 116 #define AMDGPU_PTE_PRT_FLAG(adev) \ 117 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PTE_PRT_GFX12 : AMDGPU_PTE_PRT) 118 119 #define AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype) ((uint64_t)(mtype) << 54) 120 #define AMDGPU_PTE_MTYPE_GFX12_MASK AMDGPU_PTE_MTYPE_GFX12_SHIFT(3ULL) 121 #define AMDGPU_PTE_MTYPE_GFX12(flags, mtype) \ 122 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_GFX12_MASK)) | \ 123 AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype)) 124 125 #define AMDGPU_PTE_IS_PTE (1ULL << 63) 126 127 /* PDE Block Fragment Size for gfx v12 */ 128 #define AMDGPU_PDE_BFS_GFX12(a) ((uint64_t)((a) & 0x1fULL) << 58) 129 #define AMDGPU_PDE_BFS_FLAG(adev, a) \ 130 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_BFS_GFX12(a) : AMDGPU_PDE_BFS(a)) 131 /* PDE is handled as PTE for gfx v12 */ 132 #define AMDGPU_PDE_PTE_GFX12 (1ULL << 63) 133 #define AMDGPU_PDE_PTE_FLAG(adev) \ 134 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_PTE_GFX12 : AMDGPU_PDE_PTE) 135 136 /* How to program VM fault handling */ 137 #define AMDGPU_VM_FAULT_STOP_NEVER 0 138 #define AMDGPU_VM_FAULT_STOP_FIRST 1 139 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 140 141 /* How much VRAM be reserved for page tables */ 142 #define AMDGPU_VM_RESERVED_VRAM (8ULL << 20) 143 144 /* 145 * max number of VMHUB 146 * layout: max 8 GFXHUB + 4 MMHUB0 + 1 MMHUB1 147 */ 148 #define AMDGPU_MAX_VMHUBS 13 149 #define AMDGPU_GFXHUB_START 0 150 #define AMDGPU_MMHUB0_START 8 151 #define AMDGPU_MMHUB1_START 12 152 #define AMDGPU_GFXHUB(x) (AMDGPU_GFXHUB_START + (x)) 153 #define AMDGPU_MMHUB0(x) (AMDGPU_MMHUB0_START + (x)) 154 #define AMDGPU_MMHUB1(x) (AMDGPU_MMHUB1_START + (x)) 155 156 #define AMDGPU_IS_GFXHUB(x) ((x) >= AMDGPU_GFXHUB_START && (x) < AMDGPU_MMHUB0_START) 157 #define AMDGPU_IS_MMHUB0(x) ((x) >= AMDGPU_MMHUB0_START && (x) < AMDGPU_MMHUB1_START) 158 #define AMDGPU_IS_MMHUB1(x) ((x) >= AMDGPU_MMHUB1_START && (x) < AMDGPU_MAX_VMHUBS) 159 160 /* Reserve space at top/bottom of address space for kernel use */ 161 #define AMDGPU_VA_RESERVED_CSA_SIZE (2ULL << 20) 162 #define AMDGPU_VA_RESERVED_CSA_START(adev) (((adev)->vm_manager.max_pfn \ 163 << AMDGPU_GPU_PAGE_SHIFT) \ 164 - AMDGPU_VA_RESERVED_CSA_SIZE) 165 #define AMDGPU_VA_RESERVED_SEQ64_SIZE (2ULL << 20) 166 #define AMDGPU_VA_RESERVED_SEQ64_START(adev) (AMDGPU_VA_RESERVED_CSA_START(adev) \ 167 - AMDGPU_VA_RESERVED_SEQ64_SIZE) 168 #define AMDGPU_VA_RESERVED_TRAP_SIZE (2ULL << 12) 169 #define AMDGPU_VA_RESERVED_TRAP_START(adev) (AMDGPU_VA_RESERVED_SEQ64_START(adev) \ 170 - AMDGPU_VA_RESERVED_TRAP_SIZE) 171 #define AMDGPU_VA_RESERVED_BOTTOM (1ULL << 16) 172 #define AMDGPU_VA_RESERVED_TOP (AMDGPU_VA_RESERVED_TRAP_SIZE + \ 173 AMDGPU_VA_RESERVED_SEQ64_SIZE + \ 174 AMDGPU_VA_RESERVED_CSA_SIZE) 175 176 /* See vm_update_mode */ 177 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) 178 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) 179 180 /* VMPT level enumerate, and the hiberachy is: 181 * PDB2->PDB1->PDB0->PTB 182 */ 183 enum amdgpu_vm_level { 184 AMDGPU_VM_PDB2, 185 AMDGPU_VM_PDB1, 186 AMDGPU_VM_PDB0, 187 AMDGPU_VM_PTB 188 }; 189 190 /* base structure for tracking BO usage in a VM */ 191 struct amdgpu_vm_bo_base { 192 /* constant after initialization */ 193 struct amdgpu_vm *vm; 194 struct amdgpu_bo *bo; 195 196 /* protected by bo being reserved */ 197 struct amdgpu_vm_bo_base *next; 198 199 /* protected by spinlock */ 200 struct list_head vm_status; 201 202 /* protected by the BO being reserved */ 203 bool moved; 204 }; 205 206 /* provided by hw blocks that can write ptes, e.g., sdma */ 207 struct amdgpu_vm_pte_funcs { 208 /* number of dw to reserve per operation */ 209 unsigned copy_pte_num_dw; 210 211 /* copy pte entries from GART */ 212 void (*copy_pte)(struct amdgpu_ib *ib, 213 uint64_t pe, uint64_t src, 214 unsigned count); 215 216 /* write pte one entry at a time with addr mapping */ 217 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 218 uint64_t value, unsigned count, 219 uint32_t incr); 220 /* for linear pte/pde updates without addr mapping */ 221 void (*set_pte_pde)(struct amdgpu_ib *ib, 222 uint64_t pe, 223 uint64_t addr, unsigned count, 224 uint32_t incr, uint64_t flags); 225 }; 226 227 struct amdgpu_task_info { 228 char process_name[TASK_COMM_LEN]; 229 char task_name[TASK_COMM_LEN]; 230 pid_t pid; 231 pid_t tgid; 232 struct kref refcount; 233 }; 234 235 /** 236 * struct amdgpu_vm_update_params 237 * 238 * Encapsulate some VM table update parameters to reduce 239 * the number of function parameters 240 * 241 */ 242 struct amdgpu_vm_update_params { 243 244 /** 245 * @adev: amdgpu device we do this update for 246 */ 247 struct amdgpu_device *adev; 248 249 /** 250 * @vm: optional amdgpu_vm we do this update for 251 */ 252 struct amdgpu_vm *vm; 253 254 /** 255 * @immediate: if changes should be made immediately 256 */ 257 bool immediate; 258 259 /** 260 * @unlocked: true if the root BO is not locked 261 */ 262 bool unlocked; 263 264 /** 265 * @pages_addr: 266 * 267 * DMA addresses to use for mapping 268 */ 269 dma_addr_t *pages_addr; 270 271 /** 272 * @job: job to used for hw submission 273 */ 274 struct amdgpu_job *job; 275 276 /** 277 * @num_dw_left: number of dw left for the IB 278 */ 279 unsigned int num_dw_left; 280 281 /** 282 * @needs_flush: true whenever we need to invalidate the TLB 283 */ 284 bool needs_flush; 285 286 /** 287 * @allow_override: true for memory that is not uncached: allows MTYPE 288 * to be overridden for NUMA local memory. 289 */ 290 bool allow_override; 291 292 /** 293 * @tlb_flush_waitlist: temporary storage for BOs until tlb_flush 294 */ 295 struct list_head tlb_flush_waitlist; 296 }; 297 298 struct amdgpu_vm_update_funcs { 299 int (*map_table)(struct amdgpu_bo_vm *bo); 300 int (*prepare)(struct amdgpu_vm_update_params *p, struct dma_resv *resv, 301 enum amdgpu_sync_mode sync_mode); 302 int (*update)(struct amdgpu_vm_update_params *p, 303 struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr, 304 unsigned count, uint32_t incr, uint64_t flags); 305 int (*commit)(struct amdgpu_vm_update_params *p, 306 struct dma_fence **fence); 307 }; 308 309 struct amdgpu_vm_fault_info { 310 /* fault address */ 311 uint64_t addr; 312 /* fault status register */ 313 uint32_t status; 314 /* which vmhub? gfxhub, mmhub, etc. */ 315 unsigned int vmhub; 316 }; 317 318 struct amdgpu_vm { 319 /* tree of virtual addresses mapped */ 320 struct rb_root_cached va; 321 322 /* Lock to prevent eviction while we are updating page tables 323 * use vm_eviction_lock/unlock(vm) 324 */ 325 struct mutex eviction_lock; 326 bool evicting; 327 unsigned int saved_flags; 328 329 /* Lock to protect vm_bo add/del/move on all lists of vm */ 330 spinlock_t status_lock; 331 332 /* Per-VM and PT BOs who needs a validation */ 333 struct list_head evicted; 334 335 /* BOs for user mode queues that need a validation */ 336 struct list_head evicted_user; 337 338 /* PT BOs which relocated and their parent need an update */ 339 struct list_head relocated; 340 341 /* per VM BOs moved, but not yet updated in the PT */ 342 struct list_head moved; 343 344 /* All BOs of this VM not currently in the state machine */ 345 struct list_head idle; 346 347 /* regular invalidated BOs, but not yet updated in the PT */ 348 struct list_head invalidated; 349 350 /* BO mappings freed, but not yet updated in the PT */ 351 struct list_head freed; 352 353 /* BOs which are invalidated, has been updated in the PTs */ 354 struct list_head done; 355 356 /* PT BOs scheduled to free and fill with zero if vm_resv is not hold */ 357 struct list_head pt_freed; 358 struct work_struct pt_free_work; 359 360 /* contains the page directory */ 361 struct amdgpu_vm_bo_base root; 362 struct dma_fence *last_update; 363 364 /* Scheduler entities for page table updates */ 365 struct drm_sched_entity immediate; 366 struct drm_sched_entity delayed; 367 368 /* Last finished delayed update */ 369 atomic64_t tlb_seq; 370 struct dma_fence *last_tlb_flush; 371 atomic64_t kfd_last_flushed_seq; 372 uint64_t tlb_fence_context; 373 374 /* How many times we had to re-generate the page tables */ 375 uint64_t generation; 376 377 /* Last unlocked submission to the scheduler entities */ 378 struct dma_fence *last_unlocked; 379 380 unsigned int pasid; 381 bool reserved_vmid[AMDGPU_MAX_VMHUBS]; 382 383 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ 384 bool use_cpu_for_update; 385 386 /* Functions to use for VM table updates */ 387 const struct amdgpu_vm_update_funcs *update_funcs; 388 389 /* Up to 128 pending retry page faults */ 390 DECLARE_KFIFO(faults, u64, 128); 391 392 /* Points to the KFD process VM info */ 393 struct amdkfd_process_info *process_info; 394 395 /* List node in amdkfd_process_info.vm_list_head */ 396 struct list_head vm_list_node; 397 398 /* Valid while the PD is reserved or fenced */ 399 uint64_t pd_phys_addr; 400 401 /* Some basic info about the task */ 402 struct amdgpu_task_info *task_info; 403 404 /* Store positions of group of BOs */ 405 struct ttm_lru_bulk_move lru_bulk_move; 406 /* Flag to indicate if VM is used for compute */ 407 bool is_compute_context; 408 409 /* Memory partition number, -1 means any partition */ 410 int8_t mem_id; 411 412 /* cached fault info */ 413 struct amdgpu_vm_fault_info fault_info; 414 }; 415 416 struct amdgpu_vm_manager { 417 /* Handling of VMIDs */ 418 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS]; 419 unsigned int first_kfd_vmid; 420 bool concurrent_flush; 421 422 /* Handling of VM fences */ 423 u64 fence_context; 424 unsigned seqno[AMDGPU_MAX_RINGS]; 425 426 uint64_t max_pfn; 427 uint32_t num_level; 428 uint32_t block_size; 429 uint32_t fragment_size; 430 enum amdgpu_vm_level root_level; 431 /* vram base address for page table entry */ 432 u64 vram_base_offset; 433 /* vm pte handling */ 434 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 435 struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS]; 436 unsigned vm_pte_num_scheds; 437 struct amdgpu_ring *page_fault; 438 439 /* partial resident texture handling */ 440 spinlock_t prt_lock; 441 atomic_t num_prt_users; 442 443 /* controls how VM page tables are updated for Graphics and Compute. 444 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU 445 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU 446 */ 447 int vm_update_mode; 448 449 /* PASID to VM mapping, will be used in interrupt context to 450 * look up VM of a page fault 451 */ 452 struct xarray pasids; 453 /* Global registration of recent page fault information */ 454 struct amdgpu_vm_fault_info fault_info; 455 }; 456 457 struct amdgpu_bo_va_mapping; 458 459 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 460 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 461 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 462 463 extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs; 464 extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs; 465 466 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 467 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 468 469 int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm, 470 u32 pasid); 471 472 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout); 473 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id); 474 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 475 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 476 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 477 int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec, 478 unsigned int num_fences); 479 bool amdgpu_vm_ready(struct amdgpu_vm *vm); 480 uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm); 481 int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, 482 struct ww_acquire_ctx *ticket, 483 int (*callback)(void *p, struct amdgpu_bo *bo), 484 void *param); 485 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); 486 int amdgpu_vm_update_pdes(struct amdgpu_device *adev, 487 struct amdgpu_vm *vm, bool immediate); 488 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 489 struct amdgpu_vm *vm, 490 struct dma_fence **fence); 491 int amdgpu_vm_handle_moved(struct amdgpu_device *adev, 492 struct amdgpu_vm *vm, 493 struct ww_acquire_ctx *ticket); 494 int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev, 495 struct amdgpu_vm *vm, 496 uint32_t flush_type, 497 uint32_t xcc_mask); 498 void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, 499 struct amdgpu_vm *vm, struct amdgpu_bo *bo); 500 int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, 501 bool immediate, bool unlocked, bool flush_tlb, bool allow_override, 502 struct dma_resv *resv, uint64_t start, uint64_t last, 503 uint64_t flags, uint64_t offset, uint64_t vram_base, 504 struct ttm_resource *res, dma_addr_t *pages_addr, 505 struct dma_fence **fence); 506 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 507 struct amdgpu_bo_va *bo_va, 508 bool clear); 509 bool amdgpu_vm_evictable(struct amdgpu_bo *bo); 510 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 511 struct amdgpu_bo *bo, bool evicted); 512 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 513 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 514 struct amdgpu_bo *bo); 515 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 516 struct amdgpu_vm *vm, 517 struct amdgpu_bo *bo); 518 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 519 struct amdgpu_bo_va *bo_va, 520 uint64_t addr, uint64_t offset, 521 uint64_t size, uint64_t flags); 522 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, 523 struct amdgpu_bo_va *bo_va, 524 uint64_t addr, uint64_t offset, 525 uint64_t size, uint64_t flags); 526 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 527 struct amdgpu_bo_va *bo_va, 528 uint64_t addr); 529 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, 530 struct amdgpu_vm *vm, 531 uint64_t saddr, uint64_t size); 532 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, 533 uint64_t addr); 534 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket); 535 void amdgpu_vm_bo_del(struct amdgpu_device *adev, 536 struct amdgpu_bo_va *bo_va); 537 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, 538 uint32_t fragment_size_default, unsigned max_level, 539 unsigned max_bits); 540 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 541 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, 542 struct amdgpu_job *job); 543 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); 544 545 struct amdgpu_task_info * 546 amdgpu_vm_get_task_info_pasid(struct amdgpu_device *adev, u32 pasid); 547 548 struct amdgpu_task_info * 549 amdgpu_vm_get_task_info_vm(struct amdgpu_vm *vm); 550 551 void amdgpu_vm_put_task_info(struct amdgpu_task_info *task_info); 552 553 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, 554 u32 vmid, u32 node_id, uint64_t addr, 555 bool write_fault); 556 557 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm); 558 559 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, 560 struct amdgpu_vm *vm); 561 void amdgpu_vm_get_memory(struct amdgpu_vm *vm, 562 struct amdgpu_mem_stats *stats); 563 564 int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, 565 struct amdgpu_bo_vm *vmbo, bool immediate); 566 int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, 567 int level, bool immediate, struct amdgpu_bo_vm **vmbo, 568 int32_t xcp_id); 569 void amdgpu_vm_pt_free_root(struct amdgpu_device *adev, struct amdgpu_vm *vm); 570 571 int amdgpu_vm_pde_update(struct amdgpu_vm_update_params *params, 572 struct amdgpu_vm_bo_base *entry); 573 int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params, 574 uint64_t start, uint64_t end, 575 uint64_t dst, uint64_t flags); 576 void amdgpu_vm_pt_free_work(struct work_struct *work); 577 void amdgpu_vm_pt_free_list(struct amdgpu_device *adev, 578 struct amdgpu_vm_update_params *params); 579 580 #if defined(CONFIG_DEBUG_FS) 581 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m); 582 #endif 583 584 int amdgpu_vm_pt_map_tables(struct amdgpu_device *adev, struct amdgpu_vm *vm); 585 586 bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo); 587 588 /** 589 * amdgpu_vm_tlb_seq - return tlb flush sequence number 590 * @vm: the amdgpu_vm structure to query 591 * 592 * Returns the tlb flush sequence number which indicates that the VM TLBs needs 593 * to be invalidated whenever the sequence number change. 594 */ 595 static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm *vm) 596 { 597 unsigned long flags; 598 spinlock_t *lock; 599 600 /* 601 * Workaround to stop racing between the fence signaling and handling 602 * the cb. The lock is static after initially setting it up, just make 603 * sure that the dma_fence structure isn't freed up. 604 */ 605 rcu_read_lock(); 606 lock = vm->last_tlb_flush->lock; 607 rcu_read_unlock(); 608 609 spin_lock_irqsave(lock, flags); 610 spin_unlock_irqrestore(lock, flags); 611 612 return atomic64_read(&vm->tlb_seq); 613 } 614 615 /* 616 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS 617 * happens while holding this lock anywhere to prevent deadlocks when 618 * an MMU notifier runs in reclaim-FS context. 619 */ 620 static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm) 621 { 622 mutex_lock(&vm->eviction_lock); 623 vm->saved_flags = memalloc_noreclaim_save(); 624 } 625 626 static inline bool amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm) 627 { 628 if (mutex_trylock(&vm->eviction_lock)) { 629 vm->saved_flags = memalloc_noreclaim_save(); 630 return true; 631 } 632 return false; 633 } 634 635 static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm) 636 { 637 memalloc_noreclaim_restore(vm->saved_flags); 638 mutex_unlock(&vm->eviction_lock); 639 } 640 641 void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, 642 unsigned int pasid, 643 uint64_t addr, 644 uint32_t status, 645 unsigned int vmhub); 646 void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, 647 struct amdgpu_vm *vm, 648 struct dma_fence **fence); 649 650 #endif 651