1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: [email protected] 23 */ 24 #ifndef AMDGPU_VIRT_H 25 #define AMDGPU_VIRT_H 26 27 #include "amdgv_sriovmsg.h" 28 29 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */ 30 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */ 31 #define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */ 32 #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */ 33 #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */ 34 #define AMDGPU_VF_MMIO_ACCESS_PROTECT (1 << 5) /* MMIO write access is not allowed in sriov runtime */ 35 36 /* flags for indirect register access path supported by rlcg for sriov */ 37 #define AMDGPU_RLCG_GC_WRITE_LEGACY (0x8 << 28) 38 #define AMDGPU_RLCG_GC_WRITE (0x0 << 28) 39 #define AMDGPU_RLCG_GC_READ (0x1 << 28) 40 #define AMDGPU_RLCG_MMHUB_WRITE (0x2 << 28) 41 42 /* error code for indirect register access path supported by rlcg for sriov */ 43 #define AMDGPU_RLCG_VFGATE_DISABLED 0x4000000 44 #define AMDGPU_RLCG_WRONG_OPERATION_TYPE 0x2000000 45 #define AMDGPU_RLCG_REG_NOT_IN_RANGE 0x1000000 46 47 #define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK 0xFFFFF 48 #define AMDGPU_RLCG_SCRATCH1_ERROR_MASK 0xF000000 49 50 /* all asic after AI use this offset */ 51 #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5 52 /* tonga/fiji use this offset */ 53 #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503 54 55 #define AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT 2 56 57 enum amdgpu_sriov_vf_mode { 58 SRIOV_VF_MODE_BARE_METAL = 0, 59 SRIOV_VF_MODE_ONE_VF, 60 SRIOV_VF_MODE_MULTI_VF, 61 }; 62 63 struct amdgpu_mm_table { 64 struct amdgpu_bo *bo; 65 uint32_t *cpu_addr; 66 uint64_t gpu_addr; 67 }; 68 69 #define AMDGPU_VF_ERROR_ENTRY_SIZE 16 70 71 /* struct error_entry - amdgpu VF error information. */ 72 struct amdgpu_vf_error_buffer { 73 struct mutex lock; 74 int read_count; 75 int write_count; 76 uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE]; 77 uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE]; 78 uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE]; 79 }; 80 81 enum idh_request; 82 83 /** 84 * struct amdgpu_virt_ops - amdgpu device virt operations 85 */ 86 struct amdgpu_virt_ops { 87 int (*req_full_gpu)(struct amdgpu_device *adev, bool init); 88 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init); 89 int (*req_init_data)(struct amdgpu_device *adev); 90 int (*reset_gpu)(struct amdgpu_device *adev); 91 void (*ready_to_reset)(struct amdgpu_device *adev); 92 int (*wait_reset)(struct amdgpu_device *adev); 93 void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req, 94 u32 data1, u32 data2, u32 data3); 95 void (*ras_poison_handler)(struct amdgpu_device *adev, 96 enum amdgpu_ras_block block); 97 bool (*rcvd_ras_intr)(struct amdgpu_device *adev); 98 int (*req_ras_err_count)(struct amdgpu_device *adev); 99 }; 100 101 /* 102 * Firmware Reserve Frame buffer 103 */ 104 struct amdgpu_virt_fw_reserve { 105 struct amd_sriov_msg_pf2vf_info_header *p_pf2vf; 106 struct amd_sriov_msg_vf2pf_info_header *p_vf2pf; 107 unsigned int checksum_key; 108 }; 109 110 /* 111 * Legacy GIM header 112 * 113 * Defination between PF and VF 114 * Structures forcibly aligned to 4 to keep the same style as PF. 115 */ 116 #define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024) 117 118 #define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \ 119 (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2)) 120 121 enum AMDGIM_FEATURE_FLAG { 122 /* GIM supports feature of Error log collecting */ 123 AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1, 124 /* GIM supports feature of loading uCodes */ 125 AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2, 126 /* VRAM LOST by GIM */ 127 AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4, 128 /* MM bandwidth */ 129 AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8, 130 /* PP ONE VF MODE in GIM */ 131 AMDGIM_FEATURE_PP_ONE_VF = (1 << 4), 132 /* Indirect Reg Access enabled */ 133 AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5), 134 /* AV1 Support MODE*/ 135 AMDGIM_FEATURE_AV1_SUPPORT = (1 << 6), 136 /* VCN RB decouple */ 137 AMDGIM_FEATURE_VCN_RB_DECOUPLE = (1 << 7), 138 /* MES info */ 139 AMDGIM_FEATURE_MES_INFO_ENABLE = (1 << 8), 140 AMDGIM_FEATURE_RAS_CAPS = (1 << 9), 141 }; 142 143 enum AMDGIM_REG_ACCESS_FLAG { 144 /* Use PSP to program IH_RB_CNTL */ 145 AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0), 146 /* Use RLC to program MMHUB regs */ 147 AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1), 148 /* Use RLC to program GC regs */ 149 AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2), 150 }; 151 152 struct amdgim_pf2vf_info_v1 { 153 /* header contains size and version */ 154 struct amd_sriov_msg_pf2vf_info_header header; 155 /* max_width * max_height */ 156 unsigned int uvd_enc_max_pixels_count; 157 /* 16x16 pixels/sec, codec independent */ 158 unsigned int uvd_enc_max_bandwidth; 159 /* max_width * max_height */ 160 unsigned int vce_enc_max_pixels_count; 161 /* 16x16 pixels/sec, codec independent */ 162 unsigned int vce_enc_max_bandwidth; 163 /* MEC FW position in kb from the start of visible frame buffer */ 164 unsigned int mecfw_kboffset; 165 /* The features flags of the GIM driver supports. */ 166 unsigned int feature_flags; 167 /* use private key from mailbox 2 to create chueksum */ 168 unsigned int checksum; 169 } __aligned(4); 170 171 struct amdgim_vf2pf_info_v1 { 172 /* header contains size and version */ 173 struct amd_sriov_msg_vf2pf_info_header header; 174 /* driver version */ 175 char driver_version[64]; 176 /* driver certification, 1=WHQL, 0=None */ 177 unsigned int driver_cert; 178 /* guest OS type and version: need a define */ 179 unsigned int os_info; 180 /* in the unit of 1M */ 181 unsigned int fb_usage; 182 /* guest gfx engine usage percentage */ 183 unsigned int gfx_usage; 184 /* guest gfx engine health percentage */ 185 unsigned int gfx_health; 186 /* guest compute engine usage percentage */ 187 unsigned int compute_usage; 188 /* guest compute engine health percentage */ 189 unsigned int compute_health; 190 /* guest vce engine usage percentage. 0xffff means N/A. */ 191 unsigned int vce_enc_usage; 192 /* guest vce engine health percentage. 0xffff means N/A. */ 193 unsigned int vce_enc_health; 194 /* guest uvd engine usage percentage. 0xffff means N/A. */ 195 unsigned int uvd_enc_usage; 196 /* guest uvd engine usage percentage. 0xffff means N/A. */ 197 unsigned int uvd_enc_health; 198 unsigned int checksum; 199 } __aligned(4); 200 201 struct amdgim_vf2pf_info_v2 { 202 /* header contains size and version */ 203 struct amd_sriov_msg_vf2pf_info_header header; 204 uint32_t checksum; 205 /* driver version */ 206 uint8_t driver_version[64]; 207 /* driver certification, 1=WHQL, 0=None */ 208 uint32_t driver_cert; 209 /* guest OS type and version: need a define */ 210 uint32_t os_info; 211 /* in the unit of 1M */ 212 uint32_t fb_usage; 213 /* guest gfx engine usage percentage */ 214 uint32_t gfx_usage; 215 /* guest gfx engine health percentage */ 216 uint32_t gfx_health; 217 /* guest compute engine usage percentage */ 218 uint32_t compute_usage; 219 /* guest compute engine health percentage */ 220 uint32_t compute_health; 221 /* guest vce engine usage percentage. 0xffff means N/A. */ 222 uint32_t vce_enc_usage; 223 /* guest vce engine health percentage. 0xffff means N/A. */ 224 uint32_t vce_enc_health; 225 /* guest uvd engine usage percentage. 0xffff means N/A. */ 226 uint32_t uvd_enc_usage; 227 /* guest uvd engine usage percentage. 0xffff means N/A. */ 228 uint32_t uvd_enc_health; 229 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)]; 230 } __aligned(4); 231 232 struct amdgpu_virt_ras_err_handler_data { 233 /* point to bad page records array */ 234 struct eeprom_table_record *bps; 235 /* point to reserved bo array */ 236 struct amdgpu_bo **bps_bo; 237 /* the count of entries */ 238 int count; 239 /* last reserved entry's index + 1 */ 240 int last_reserved; 241 }; 242 243 /* GPU virtualization */ 244 struct amdgpu_virt { 245 uint32_t caps; 246 struct amdgpu_bo *csa_obj; 247 void *csa_cpu_addr; 248 bool chained_ib_support; 249 uint32_t reg_val_offs; 250 struct amdgpu_irq_src ack_irq; 251 struct amdgpu_irq_src rcv_irq; 252 struct work_struct flr_work; 253 struct amdgpu_mm_table mm_table; 254 const struct amdgpu_virt_ops *ops; 255 struct amdgpu_vf_error_buffer vf_errors; 256 struct amdgpu_virt_fw_reserve fw_reserve; 257 uint32_t gim_feature; 258 uint32_t reg_access_mode; 259 int req_init_data_ver; 260 bool tdr_debug; 261 struct amdgpu_virt_ras_err_handler_data *virt_eh_data; 262 bool ras_init_done; 263 uint32_t reg_access; 264 265 /* vf2pf message */ 266 struct delayed_work vf2pf_work; 267 uint32_t vf2pf_update_interval_ms; 268 int vf2pf_update_retry_cnt; 269 270 /* multimedia bandwidth config */ 271 bool is_mm_bw_enabled; 272 uint32_t decode_max_dimension_pixels; 273 uint32_t decode_max_frame_pixels; 274 uint32_t encode_max_dimension_pixels; 275 uint32_t encode_max_frame_pixels; 276 277 /* the ucode id to signal the autoload */ 278 uint32_t autoload_ucode_id; 279 280 struct mutex rlcg_reg_lock; 281 282 union amd_sriov_ras_caps ras_en_caps; 283 }; 284 285 struct amdgpu_video_codec_info; 286 287 #define amdgpu_sriov_enabled(adev) \ 288 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV) 289 290 #define amdgpu_sriov_vf(adev) \ 291 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF) 292 293 #define amdgpu_sriov_bios(adev) \ 294 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS) 295 296 #define amdgpu_sriov_runtime(adev) \ 297 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME) 298 299 #define amdgpu_sriov_fullaccess(adev) \ 300 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev))) 301 302 #define amdgpu_sriov_reg_indirect_en(adev) \ 303 (amdgpu_sriov_vf((adev)) && \ 304 ((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS))) 305 306 #define amdgpu_sriov_reg_indirect_ih(adev) \ 307 (amdgpu_sriov_vf((adev)) && \ 308 ((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN))) 309 310 #define amdgpu_sriov_reg_indirect_mmhub(adev) \ 311 (amdgpu_sriov_vf((adev)) && \ 312 ((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN))) 313 314 #define amdgpu_sriov_reg_indirect_gc(adev) \ 315 (amdgpu_sriov_vf((adev)) && \ 316 ((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN))) 317 318 #define amdgpu_sriov_rlcg_error_report_enabled(adev) \ 319 (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev)) 320 321 #define amdgpu_passthrough(adev) \ 322 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE) 323 324 #define amdgpu_sriov_vf_mmio_access_protection(adev) \ 325 ((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT) 326 327 #define amdgpu_sriov_ras_caps_en(adev) \ 328 ((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_CAPS) 329 330 static inline bool is_virtual_machine(void) 331 { 332 #if defined(CONFIG_X86) 333 return boot_cpu_has(X86_FEATURE_HYPERVISOR); 334 #elif defined(CONFIG_ARM64) 335 return !is_kernel_in_hyp_mode(); 336 #else 337 return false; 338 #endif 339 } 340 341 #define amdgpu_sriov_is_pp_one_vf(adev) \ 342 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF) 343 #define amdgpu_sriov_is_debug(adev) \ 344 ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug) 345 #define amdgpu_sriov_is_normal(adev) \ 346 ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug)) 347 #define amdgpu_sriov_is_av1_support(adev) \ 348 ((adev)->virt.gim_feature & AMDGIM_FEATURE_AV1_SUPPORT) 349 #define amdgpu_sriov_is_vcn_rb_decouple(adev) \ 350 ((adev)->virt.gim_feature & AMDGIM_FEATURE_VCN_RB_DECOUPLE) 351 #define amdgpu_sriov_is_mes_info_enable(adev) \ 352 ((adev)->virt.gim_feature & AMDGIM_FEATURE_MES_INFO_ENABLE) 353 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev); 354 void amdgpu_virt_init_setting(struct amdgpu_device *adev); 355 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); 356 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); 357 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); 358 void amdgpu_virt_request_init_data(struct amdgpu_device *adev); 359 void amdgpu_virt_ready_to_reset(struct amdgpu_device *adev); 360 int amdgpu_virt_wait_reset(struct amdgpu_device *adev); 361 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev); 362 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev); 363 bool amdgpu_virt_rcvd_ras_interrupt(struct amdgpu_device *adev); 364 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev); 365 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev); 366 void amdgpu_virt_exchange_data(struct amdgpu_device *adev); 367 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev); 368 void amdgpu_detect_virtualization(struct amdgpu_device *adev); 369 370 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev); 371 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev); 372 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev); 373 374 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev); 375 376 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, 377 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, 378 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size); 379 void amdgpu_sriov_wreg(struct amdgpu_device *adev, 380 u32 offset, u32 value, 381 u32 acc_flags, u32 hwip, u32 xcc_id); 382 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, 383 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id); 384 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, 385 uint32_t ucode_id); 386 void amdgpu_virt_pre_reset(struct amdgpu_device *adev); 387 void amdgpu_virt_post_reset(struct amdgpu_device *adev); 388 bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev); 389 bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, 390 u32 acc_flags, u32 hwip, 391 bool write, u32 *rlcg_flag); 392 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id); 393 bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev); 394 #endif 395