189041940SGavin Wan /*
289041940SGavin Wan  * Copyright 2017 Advanced Micro Devices, Inc.
389041940SGavin Wan  *
489041940SGavin Wan  * Permission is hereby granted, free of charge, to any person obtaining a
589041940SGavin Wan  * copy of this software and associated documentation files (the "Software"),
689041940SGavin Wan  * to deal in the Software without restriction, including without limitation
789041940SGavin Wan  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
889041940SGavin Wan  * and/or sell copies of the Software, and to permit persons to whom the
989041940SGavin Wan  * Software is furnished to do so, subject to the following conditions:
1089041940SGavin Wan  *
1189041940SGavin Wan  * The above copyright notice and this permission notice shall be included in
1289041940SGavin Wan  * all copies or substantial portions of the Software.
1389041940SGavin Wan  *
1489041940SGavin Wan  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1589041940SGavin Wan  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1689041940SGavin Wan  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
1789041940SGavin Wan  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
1889041940SGavin Wan  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
1989041940SGavin Wan  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2089041940SGavin Wan  * OTHER DEALINGS IN THE SOFTWARE.
2189041940SGavin Wan  *
2289041940SGavin Wan  */
2389041940SGavin Wan 
2489041940SGavin Wan #include "amdgpu.h"
2589041940SGavin Wan #include "amdgpu_vf_error.h"
2689041940SGavin Wan #include "mxgpu_ai.h"
2789041940SGavin Wan 
amdgpu_vf_error_put(struct amdgpu_device * adev,uint16_t sub_error_code,uint16_t error_flags,uint64_t error_data)28e23b74aaSAlex Deucher void amdgpu_vf_error_put(struct amdgpu_device *adev,
29e23b74aaSAlex Deucher 			 uint16_t sub_error_code,
30e23b74aaSAlex Deucher 			 uint16_t error_flags,
31e23b74aaSAlex Deucher 			 uint64_t error_data)
3289041940SGavin Wan {
3389041940SGavin Wan 	int index;
34*6867e1b5SMonk Liu 	uint16_t error_code;
35*6867e1b5SMonk Liu 
36*6867e1b5SMonk Liu 	if (!amdgpu_sriov_vf(adev))
37*6867e1b5SMonk Liu 		return;
38*6867e1b5SMonk Liu 
39*6867e1b5SMonk Liu 	error_code = AMDGIM_ERROR_CODE(AMDGIM_ERROR_CATEGORY_VF, sub_error_code);
4089041940SGavin Wan 
41e23b74aaSAlex Deucher 	mutex_lock(&adev->virt.vf_errors.lock);
42e23b74aaSAlex Deucher 	index = adev->virt.vf_errors.write_count % AMDGPU_VF_ERROR_ENTRY_SIZE;
43e23b74aaSAlex Deucher 	adev->virt.vf_errors.code [index] = error_code;
44e23b74aaSAlex Deucher 	adev->virt.vf_errors.flags [index] = error_flags;
45e23b74aaSAlex Deucher 	adev->virt.vf_errors.data [index] = error_data;
46e23b74aaSAlex Deucher 	adev->virt.vf_errors.write_count ++;
47e23b74aaSAlex Deucher 	mutex_unlock(&adev->virt.vf_errors.lock);
4889041940SGavin Wan }
4989041940SGavin Wan 
5089041940SGavin Wan 
amdgpu_vf_error_trans_all(struct amdgpu_device * adev)5189041940SGavin Wan void amdgpu_vf_error_trans_all(struct amdgpu_device *adev)
5289041940SGavin Wan {
5389041940SGavin Wan 	/* u32 pf2vf_flags = 0; */
5489041940SGavin Wan 	u32 data1, data2, data3;
5589041940SGavin Wan 	int index;
5689041940SGavin Wan 
57e23b74aaSAlex Deucher 	if ((NULL == adev) || (!amdgpu_sriov_vf(adev)) ||
58e23b74aaSAlex Deucher 	    (!adev->virt.ops) || (!adev->virt.ops->trans_msg)) {
5989041940SGavin Wan 		return;
6089041940SGavin Wan 	}
6189041940SGavin Wan /*
6289041940SGavin Wan 	TODO: Enable these code when pv2vf_info is merged
6389041940SGavin Wan 	AMDGPU_FW_VRAM_PF2VF_READ (adev, feature_flags, &pf2vf_flags);
6489041940SGavin Wan 	if (!(pf2vf_flags & AMDGIM_FEATURE_ERROR_LOG_COLLECT)) {
6589041940SGavin Wan 		return;
6689041940SGavin Wan 	}
6789041940SGavin Wan */
68e23b74aaSAlex Deucher 
69e23b74aaSAlex Deucher 	mutex_lock(&adev->virt.vf_errors.lock);
7089041940SGavin Wan 	/* The errors are overlay of array, correct read_count as full. */
71e23b74aaSAlex Deucher 	if (adev->virt.vf_errors.write_count - adev->virt.vf_errors.read_count > AMDGPU_VF_ERROR_ENTRY_SIZE) {
72e23b74aaSAlex Deucher 		adev->virt.vf_errors.read_count = adev->virt.vf_errors.write_count - AMDGPU_VF_ERROR_ENTRY_SIZE;
7389041940SGavin Wan 	}
7489041940SGavin Wan 
75e23b74aaSAlex Deucher 	while (adev->virt.vf_errors.read_count < adev->virt.vf_errors.write_count) {
76e23b74aaSAlex Deucher 		index =adev->virt.vf_errors.read_count % AMDGPU_VF_ERROR_ENTRY_SIZE;
77e23b74aaSAlex Deucher 		data1 = AMDGIM_ERROR_CODE_FLAGS_TO_MAILBOX(adev->virt.vf_errors.code[index],
78e23b74aaSAlex Deucher 							   adev->virt.vf_errors.flags[index]);
79e23b74aaSAlex Deucher 		data2 = adev->virt.vf_errors.data[index] & 0xFFFFFFFF;
80e23b74aaSAlex Deucher 		data3 = (adev->virt.vf_errors.data[index] >> 32) & 0xFFFFFFFF;
8189041940SGavin Wan 
8289041940SGavin Wan 		adev->virt.ops->trans_msg(adev, IDH_LOG_VF_ERROR, data1, data2, data3);
83e23b74aaSAlex Deucher 		adev->virt.vf_errors.read_count ++;
8489041940SGavin Wan 	}
85e23b74aaSAlex Deucher 	mutex_unlock(&adev->virt.vf_errors.lock);
8689041940SGavin Wan }
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