1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <[email protected]> 29 */ 30 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 34 #include <drm/drm.h> 35 36 #include "amdgpu.h" 37 #include "amdgpu_pm.h" 38 #include "amdgpu_uvd.h" 39 #include "cikd.h" 40 #include "uvd/uvd_4_2_d.h" 41 42 #include "amdgpu_ras.h" 43 44 /* 1 second timeout */ 45 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000) 46 47 /* Firmware versions for VI */ 48 #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8)) 49 #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8)) 50 #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8)) 51 #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8)) 52 53 /* Polaris10/11 firmware version */ 54 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) 55 56 /* Firmware Names */ 57 #ifdef CONFIG_DRM_AMDGPU_CIK 58 #define FIRMWARE_BONAIRE "amdgpu/bonaire_uvd.bin" 59 #define FIRMWARE_KABINI "amdgpu/kabini_uvd.bin" 60 #define FIRMWARE_KAVERI "amdgpu/kaveri_uvd.bin" 61 #define FIRMWARE_HAWAII "amdgpu/hawaii_uvd.bin" 62 #define FIRMWARE_MULLINS "amdgpu/mullins_uvd.bin" 63 #endif 64 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" 65 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" 66 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" 67 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" 68 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" 69 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" 70 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin" 71 #define FIRMWARE_VEGAM "amdgpu/vegam_uvd.bin" 72 73 #define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin" 74 #define FIRMWARE_VEGA12 "amdgpu/vega12_uvd.bin" 75 #define FIRMWARE_VEGA20 "amdgpu/vega20_uvd.bin" 76 77 /* These are common relative offsets for all asics, from uvd_7_0_offset.h, */ 78 #define UVD_GPCOM_VCPU_CMD 0x03c3 79 #define UVD_GPCOM_VCPU_DATA0 0x03c4 80 #define UVD_GPCOM_VCPU_DATA1 0x03c5 81 #define UVD_NO_OP 0x03ff 82 #define UVD_BASE_SI 0x3800 83 84 /** 85 * amdgpu_uvd_cs_ctx - Command submission parser context 86 * 87 * Used for emulating virtual memory support on UVD 4.2. 88 */ 89 struct amdgpu_uvd_cs_ctx { 90 struct amdgpu_cs_parser *parser; 91 unsigned reg, count; 92 unsigned data0, data1; 93 unsigned idx; 94 unsigned ib_idx; 95 96 /* does the IB has a msg command */ 97 bool has_msg_cmd; 98 99 /* minimum buffer sizes */ 100 unsigned *buf_sizes; 101 }; 102 103 #ifdef CONFIG_DRM_AMDGPU_CIK 104 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 105 MODULE_FIRMWARE(FIRMWARE_KABINI); 106 MODULE_FIRMWARE(FIRMWARE_KAVERI); 107 MODULE_FIRMWARE(FIRMWARE_HAWAII); 108 MODULE_FIRMWARE(FIRMWARE_MULLINS); 109 #endif 110 MODULE_FIRMWARE(FIRMWARE_TONGA); 111 MODULE_FIRMWARE(FIRMWARE_CARRIZO); 112 MODULE_FIRMWARE(FIRMWARE_FIJI); 113 MODULE_FIRMWARE(FIRMWARE_STONEY); 114 MODULE_FIRMWARE(FIRMWARE_POLARIS10); 115 MODULE_FIRMWARE(FIRMWARE_POLARIS11); 116 MODULE_FIRMWARE(FIRMWARE_POLARIS12); 117 MODULE_FIRMWARE(FIRMWARE_VEGAM); 118 119 MODULE_FIRMWARE(FIRMWARE_VEGA10); 120 MODULE_FIRMWARE(FIRMWARE_VEGA12); 121 MODULE_FIRMWARE(FIRMWARE_VEGA20); 122 123 static void amdgpu_uvd_idle_work_handler(struct work_struct *work); 124 125 int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 126 { 127 unsigned long bo_size; 128 const char *fw_name; 129 const struct common_firmware_header *hdr; 130 unsigned family_id; 131 int i, j, r; 132 133 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); 134 135 switch (adev->asic_type) { 136 #ifdef CONFIG_DRM_AMDGPU_CIK 137 case CHIP_BONAIRE: 138 fw_name = FIRMWARE_BONAIRE; 139 break; 140 case CHIP_KABINI: 141 fw_name = FIRMWARE_KABINI; 142 break; 143 case CHIP_KAVERI: 144 fw_name = FIRMWARE_KAVERI; 145 break; 146 case CHIP_HAWAII: 147 fw_name = FIRMWARE_HAWAII; 148 break; 149 case CHIP_MULLINS: 150 fw_name = FIRMWARE_MULLINS; 151 break; 152 #endif 153 case CHIP_TONGA: 154 fw_name = FIRMWARE_TONGA; 155 break; 156 case CHIP_FIJI: 157 fw_name = FIRMWARE_FIJI; 158 break; 159 case CHIP_CARRIZO: 160 fw_name = FIRMWARE_CARRIZO; 161 break; 162 case CHIP_STONEY: 163 fw_name = FIRMWARE_STONEY; 164 break; 165 case CHIP_POLARIS10: 166 fw_name = FIRMWARE_POLARIS10; 167 break; 168 case CHIP_POLARIS11: 169 fw_name = FIRMWARE_POLARIS11; 170 break; 171 case CHIP_POLARIS12: 172 fw_name = FIRMWARE_POLARIS12; 173 break; 174 case CHIP_VEGA10: 175 fw_name = FIRMWARE_VEGA10; 176 break; 177 case CHIP_VEGA12: 178 fw_name = FIRMWARE_VEGA12; 179 break; 180 case CHIP_VEGAM: 181 fw_name = FIRMWARE_VEGAM; 182 break; 183 case CHIP_VEGA20: 184 fw_name = FIRMWARE_VEGA20; 185 break; 186 default: 187 return -EINVAL; 188 } 189 190 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); 191 if (r) { 192 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n", 193 fw_name); 194 return r; 195 } 196 197 r = amdgpu_ucode_validate(adev->uvd.fw); 198 if (r) { 199 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", 200 fw_name); 201 release_firmware(adev->uvd.fw); 202 adev->uvd.fw = NULL; 203 return r; 204 } 205 206 /* Set the default UVD handles that the firmware can handle */ 207 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; 208 209 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 210 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 211 212 if (adev->asic_type < CHIP_VEGA20) { 213 unsigned version_major, version_minor; 214 215 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 216 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 217 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", 218 version_major, version_minor, family_id); 219 220 /* 221 * Limit the number of UVD handles depending on microcode major 222 * and minor versions. The firmware version which has 40 UVD 223 * instances support is 1.80. So all subsequent versions should 224 * also have the same support. 225 */ 226 if ((version_major > 0x01) || 227 ((version_major == 0x01) && (version_minor >= 0x50))) 228 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 229 230 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | 231 (family_id << 8)); 232 233 if ((adev->asic_type == CHIP_POLARIS10 || 234 adev->asic_type == CHIP_POLARIS11) && 235 (adev->uvd.fw_version < FW_1_66_16)) 236 DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n", 237 version_major, version_minor); 238 } else { 239 unsigned int enc_major, enc_minor, dec_minor; 240 241 dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 242 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f; 243 enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3; 244 DRM_INFO("Found UVD firmware ENC: %hu.%hu DEC: .%hu Family ID: %hu\n", 245 enc_major, enc_minor, dec_minor, family_id); 246 247 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 248 249 adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version); 250 } 251 252 bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE 253 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; 254 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 255 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 256 257 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 258 if (adev->uvd.harvest_config & (1 << j)) 259 continue; 260 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 261 AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.inst[j].vcpu_bo, 262 &adev->uvd.inst[j].gpu_addr, &adev->uvd.inst[j].cpu_addr); 263 if (r) { 264 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); 265 return r; 266 } 267 } 268 269 for (i = 0; i < adev->uvd.max_handles; ++i) { 270 atomic_set(&adev->uvd.handles[i], 0); 271 adev->uvd.filp[i] = NULL; 272 } 273 274 /* from uvd v5.0 HW addressing capacity increased to 64 bits */ 275 if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) 276 adev->uvd.address_64_bit = true; 277 278 switch (adev->asic_type) { 279 case CHIP_TONGA: 280 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; 281 break; 282 case CHIP_CARRIZO: 283 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; 284 break; 285 case CHIP_FIJI: 286 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; 287 break; 288 case CHIP_STONEY: 289 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; 290 break; 291 default: 292 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; 293 } 294 295 return 0; 296 } 297 298 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) 299 { 300 int i, j; 301 302 drm_sched_entity_destroy(&adev->uvd.entity); 303 304 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 305 if (adev->uvd.harvest_config & (1 << j)) 306 continue; 307 kvfree(adev->uvd.inst[j].saved_bo); 308 309 amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo, 310 &adev->uvd.inst[j].gpu_addr, 311 (void **)&adev->uvd.inst[j].cpu_addr); 312 313 amdgpu_ring_fini(&adev->uvd.inst[j].ring); 314 315 for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i) 316 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); 317 } 318 release_firmware(adev->uvd.fw); 319 320 return 0; 321 } 322 323 /** 324 * amdgpu_uvd_entity_init - init entity 325 * 326 * @adev: amdgpu_device pointer 327 * 328 */ 329 int amdgpu_uvd_entity_init(struct amdgpu_device *adev) 330 { 331 struct amdgpu_ring *ring; 332 struct drm_sched_rq *rq; 333 int r; 334 335 ring = &adev->uvd.inst[0].ring; 336 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL]; 337 r = drm_sched_entity_init(&adev->uvd.entity, &rq, 1, NULL); 338 if (r) { 339 DRM_ERROR("Failed setting up UVD kernel entity.\n"); 340 return r; 341 } 342 343 return 0; 344 } 345 346 int amdgpu_uvd_suspend(struct amdgpu_device *adev) 347 { 348 unsigned size; 349 void *ptr; 350 int i, j; 351 352 cancel_delayed_work_sync(&adev->uvd.idle_work); 353 354 /* only valid for physical mode */ 355 if (adev->asic_type < CHIP_POLARIS10) { 356 for (i = 0; i < adev->uvd.max_handles; ++i) 357 if (atomic_read(&adev->uvd.handles[i])) 358 break; 359 360 if (i == adev->uvd.max_handles) 361 return 0; 362 } 363 364 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 365 if (adev->uvd.harvest_config & (1 << j)) 366 continue; 367 if (adev->uvd.inst[j].vcpu_bo == NULL) 368 continue; 369 370 size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo); 371 ptr = adev->uvd.inst[j].cpu_addr; 372 373 adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL); 374 if (!adev->uvd.inst[j].saved_bo) 375 return -ENOMEM; 376 377 /* re-write 0 since err_event_athub will corrupt VCPU buffer */ 378 if (amdgpu_ras_intr_triggered()) { 379 DRM_WARN("UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n"); 380 memset(adev->uvd.inst[j].saved_bo, 0, size); 381 } else { 382 memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size); 383 } 384 } 385 return 0; 386 } 387 388 int amdgpu_uvd_resume(struct amdgpu_device *adev) 389 { 390 unsigned size; 391 void *ptr; 392 int i; 393 394 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 395 if (adev->uvd.harvest_config & (1 << i)) 396 continue; 397 if (adev->uvd.inst[i].vcpu_bo == NULL) 398 return -EINVAL; 399 400 size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo); 401 ptr = adev->uvd.inst[i].cpu_addr; 402 403 if (adev->uvd.inst[i].saved_bo != NULL) { 404 memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size); 405 kvfree(adev->uvd.inst[i].saved_bo); 406 adev->uvd.inst[i].saved_bo = NULL; 407 } else { 408 const struct common_firmware_header *hdr; 409 unsigned offset; 410 411 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 412 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 413 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 414 memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset, 415 le32_to_cpu(hdr->ucode_size_bytes)); 416 size -= le32_to_cpu(hdr->ucode_size_bytes); 417 ptr += le32_to_cpu(hdr->ucode_size_bytes); 418 } 419 memset_io(ptr, 0, size); 420 /* to restore uvd fence seq */ 421 amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring); 422 } 423 } 424 return 0; 425 } 426 427 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) 428 { 429 struct amdgpu_ring *ring = &adev->uvd.inst[0].ring; 430 int i, r; 431 432 for (i = 0; i < adev->uvd.max_handles; ++i) { 433 uint32_t handle = atomic_read(&adev->uvd.handles[i]); 434 435 if (handle != 0 && adev->uvd.filp[i] == filp) { 436 struct dma_fence *fence; 437 438 r = amdgpu_uvd_get_destroy_msg(ring, handle, false, 439 &fence); 440 if (r) { 441 DRM_ERROR("Error destroying UVD %d!\n", r); 442 continue; 443 } 444 445 dma_fence_wait(fence, false); 446 dma_fence_put(fence); 447 448 adev->uvd.filp[i] = NULL; 449 atomic_set(&adev->uvd.handles[i], 0); 450 } 451 } 452 } 453 454 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo) 455 { 456 int i; 457 for (i = 0; i < abo->placement.num_placement; ++i) { 458 abo->placements[i].fpfn = 0 >> PAGE_SHIFT; 459 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 460 } 461 } 462 463 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx) 464 { 465 uint32_t lo, hi; 466 uint64_t addr; 467 468 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); 469 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); 470 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 471 472 return addr; 473 } 474 475 /** 476 * amdgpu_uvd_cs_pass1 - first parsing round 477 * 478 * @ctx: UVD parser context 479 * 480 * Make sure UVD message and feedback buffers are in VRAM and 481 * nobody is violating an 256MB boundary. 482 */ 483 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) 484 { 485 struct ttm_operation_ctx tctx = { false, false }; 486 struct amdgpu_bo_va_mapping *mapping; 487 struct amdgpu_bo *bo; 488 uint32_t cmd; 489 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 490 int r = 0; 491 492 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 493 if (r) { 494 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 495 return r; 496 } 497 498 if (!ctx->parser->adev->uvd.address_64_bit) { 499 /* check if it's a message or feedback command */ 500 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 501 if (cmd == 0x0 || cmd == 0x3) { 502 /* yes, force it into VRAM */ 503 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 504 amdgpu_bo_placement_from_domain(bo, domain); 505 } 506 amdgpu_uvd_force_into_uvd_segment(bo); 507 508 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx); 509 } 510 511 return r; 512 } 513 514 /** 515 * amdgpu_uvd_cs_msg_decode - handle UVD decode message 516 * 517 * @msg: pointer to message structure 518 * @buf_sizes: returned buffer sizes 519 * 520 * Peek into the decode message and calculate the necessary buffer sizes. 521 */ 522 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, 523 unsigned buf_sizes[]) 524 { 525 unsigned stream_type = msg[4]; 526 unsigned width = msg[6]; 527 unsigned height = msg[7]; 528 unsigned dpb_size = msg[9]; 529 unsigned pitch = msg[28]; 530 unsigned level = msg[57]; 531 532 unsigned width_in_mb = width / 16; 533 unsigned height_in_mb = ALIGN(height / 16, 2); 534 unsigned fs_in_mb = width_in_mb * height_in_mb; 535 536 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; 537 unsigned min_ctx_size = ~0; 538 539 image_size = width * height; 540 image_size += image_size / 2; 541 image_size = ALIGN(image_size, 1024); 542 543 switch (stream_type) { 544 case 0: /* H264 */ 545 switch(level) { 546 case 30: 547 num_dpb_buffer = 8100 / fs_in_mb; 548 break; 549 case 31: 550 num_dpb_buffer = 18000 / fs_in_mb; 551 break; 552 case 32: 553 num_dpb_buffer = 20480 / fs_in_mb; 554 break; 555 case 41: 556 num_dpb_buffer = 32768 / fs_in_mb; 557 break; 558 case 42: 559 num_dpb_buffer = 34816 / fs_in_mb; 560 break; 561 case 50: 562 num_dpb_buffer = 110400 / fs_in_mb; 563 break; 564 case 51: 565 num_dpb_buffer = 184320 / fs_in_mb; 566 break; 567 default: 568 num_dpb_buffer = 184320 / fs_in_mb; 569 break; 570 } 571 num_dpb_buffer++; 572 if (num_dpb_buffer > 17) 573 num_dpb_buffer = 17; 574 575 /* reference picture buffer */ 576 min_dpb_size = image_size * num_dpb_buffer; 577 578 /* macroblock context buffer */ 579 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; 580 581 /* IT surface buffer */ 582 min_dpb_size += width_in_mb * height_in_mb * 32; 583 break; 584 585 case 1: /* VC1 */ 586 587 /* reference picture buffer */ 588 min_dpb_size = image_size * 3; 589 590 /* CONTEXT_BUFFER */ 591 min_dpb_size += width_in_mb * height_in_mb * 128; 592 593 /* IT surface buffer */ 594 min_dpb_size += width_in_mb * 64; 595 596 /* DB surface buffer */ 597 min_dpb_size += width_in_mb * 128; 598 599 /* BP */ 600 tmp = max(width_in_mb, height_in_mb); 601 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 602 break; 603 604 case 3: /* MPEG2 */ 605 606 /* reference picture buffer */ 607 min_dpb_size = image_size * 3; 608 break; 609 610 case 4: /* MPEG4 */ 611 612 /* reference picture buffer */ 613 min_dpb_size = image_size * 3; 614 615 /* CM */ 616 min_dpb_size += width_in_mb * height_in_mb * 64; 617 618 /* IT surface buffer */ 619 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 620 break; 621 622 case 7: /* H264 Perf */ 623 switch(level) { 624 case 30: 625 num_dpb_buffer = 8100 / fs_in_mb; 626 break; 627 case 31: 628 num_dpb_buffer = 18000 / fs_in_mb; 629 break; 630 case 32: 631 num_dpb_buffer = 20480 / fs_in_mb; 632 break; 633 case 41: 634 num_dpb_buffer = 32768 / fs_in_mb; 635 break; 636 case 42: 637 num_dpb_buffer = 34816 / fs_in_mb; 638 break; 639 case 50: 640 num_dpb_buffer = 110400 / fs_in_mb; 641 break; 642 case 51: 643 num_dpb_buffer = 184320 / fs_in_mb; 644 break; 645 default: 646 num_dpb_buffer = 184320 / fs_in_mb; 647 break; 648 } 649 num_dpb_buffer++; 650 if (num_dpb_buffer > 17) 651 num_dpb_buffer = 17; 652 653 /* reference picture buffer */ 654 min_dpb_size = image_size * num_dpb_buffer; 655 656 if (!adev->uvd.use_ctx_buf){ 657 /* macroblock context buffer */ 658 min_dpb_size += 659 width_in_mb * height_in_mb * num_dpb_buffer * 192; 660 661 /* IT surface buffer */ 662 min_dpb_size += width_in_mb * height_in_mb * 32; 663 } else { 664 /* macroblock context buffer */ 665 min_ctx_size = 666 width_in_mb * height_in_mb * num_dpb_buffer * 192; 667 } 668 break; 669 670 case 8: /* MJPEG */ 671 min_dpb_size = 0; 672 break; 673 674 case 16: /* H265 */ 675 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; 676 image_size = ALIGN(image_size, 256); 677 678 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; 679 min_dpb_size = image_size * num_dpb_buffer; 680 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) 681 * 16 * num_dpb_buffer + 52 * 1024; 682 break; 683 684 default: 685 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 686 return -EINVAL; 687 } 688 689 if (width > pitch) { 690 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 691 return -EINVAL; 692 } 693 694 if (dpb_size < min_dpb_size) { 695 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 696 dpb_size, min_dpb_size); 697 return -EINVAL; 698 } 699 700 buf_sizes[0x1] = dpb_size; 701 buf_sizes[0x2] = image_size; 702 buf_sizes[0x4] = min_ctx_size; 703 /* store image width to adjust nb memory pstate */ 704 adev->uvd.decode_image_width = width; 705 return 0; 706 } 707 708 /** 709 * amdgpu_uvd_cs_msg - handle UVD message 710 * 711 * @ctx: UVD parser context 712 * @bo: buffer object containing the message 713 * @offset: offset into the buffer object 714 * 715 * Peek into the UVD message and extract the session id. 716 * Make sure that we don't open up to many sessions. 717 */ 718 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, 719 struct amdgpu_bo *bo, unsigned offset) 720 { 721 struct amdgpu_device *adev = ctx->parser->adev; 722 int32_t *msg, msg_type, handle; 723 void *ptr; 724 long r; 725 int i; 726 727 if (offset & 0x3F) { 728 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 729 return -EINVAL; 730 } 731 732 r = amdgpu_bo_kmap(bo, &ptr); 733 if (r) { 734 DRM_ERROR("Failed mapping the UVD) message (%ld)!\n", r); 735 return r; 736 } 737 738 msg = ptr + offset; 739 740 msg_type = msg[1]; 741 handle = msg[2]; 742 743 if (handle == 0) { 744 DRM_ERROR("Invalid UVD handle!\n"); 745 return -EINVAL; 746 } 747 748 switch (msg_type) { 749 case 0: 750 /* it's a create msg, calc image size (width * height) */ 751 amdgpu_bo_kunmap(bo); 752 753 /* try to alloc a new handle */ 754 for (i = 0; i < adev->uvd.max_handles; ++i) { 755 if (atomic_read(&adev->uvd.handles[i]) == handle) { 756 DRM_ERROR(")Handle 0x%x already in use!\n", 757 handle); 758 return -EINVAL; 759 } 760 761 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { 762 adev->uvd.filp[i] = ctx->parser->filp; 763 return 0; 764 } 765 } 766 767 DRM_ERROR("No more free UVD handles!\n"); 768 return -ENOSPC; 769 770 case 1: 771 /* it's a decode msg, calc buffer sizes */ 772 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); 773 amdgpu_bo_kunmap(bo); 774 if (r) 775 return r; 776 777 /* validate the handle */ 778 for (i = 0; i < adev->uvd.max_handles; ++i) { 779 if (atomic_read(&adev->uvd.handles[i]) == handle) { 780 if (adev->uvd.filp[i] != ctx->parser->filp) { 781 DRM_ERROR("UVD handle collision detected!\n"); 782 return -EINVAL; 783 } 784 return 0; 785 } 786 } 787 788 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); 789 return -ENOENT; 790 791 case 2: 792 /* it's a destroy msg, free the handle */ 793 for (i = 0; i < adev->uvd.max_handles; ++i) 794 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); 795 amdgpu_bo_kunmap(bo); 796 return 0; 797 798 default: 799 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 800 return -EINVAL; 801 } 802 BUG(); 803 return -EINVAL; 804 } 805 806 /** 807 * amdgpu_uvd_cs_pass2 - second parsing round 808 * 809 * @ctx: UVD parser context 810 * 811 * Patch buffer addresses, make sure buffer sizes are correct. 812 */ 813 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) 814 { 815 struct amdgpu_bo_va_mapping *mapping; 816 struct amdgpu_bo *bo; 817 uint32_t cmd; 818 uint64_t start, end; 819 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 820 int r; 821 822 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 823 if (r) { 824 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 825 return r; 826 } 827 828 start = amdgpu_bo_gpu_offset(bo); 829 830 end = (mapping->last + 1 - mapping->start); 831 end = end * AMDGPU_GPU_PAGE_SIZE + start; 832 833 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE; 834 start += addr; 835 836 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0, 837 lower_32_bits(start)); 838 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1, 839 upper_32_bits(start)); 840 841 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 842 if (cmd < 0x4) { 843 if ((end - start) < ctx->buf_sizes[cmd]) { 844 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 845 (unsigned)(end - start), 846 ctx->buf_sizes[cmd]); 847 return -EINVAL; 848 } 849 850 } else if (cmd == 0x206) { 851 if ((end - start) < ctx->buf_sizes[4]) { 852 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 853 (unsigned)(end - start), 854 ctx->buf_sizes[4]); 855 return -EINVAL; 856 } 857 } else if ((cmd != 0x100) && (cmd != 0x204)) { 858 DRM_ERROR("invalid UVD command %X!\n", cmd); 859 return -EINVAL; 860 } 861 862 if (!ctx->parser->adev->uvd.address_64_bit) { 863 if ((start >> 28) != ((end - 1) >> 28)) { 864 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", 865 start, end); 866 return -EINVAL; 867 } 868 869 if ((cmd == 0 || cmd == 0x3) && 870 (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) { 871 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", 872 start, end); 873 return -EINVAL; 874 } 875 } 876 877 if (cmd == 0) { 878 ctx->has_msg_cmd = true; 879 r = amdgpu_uvd_cs_msg(ctx, bo, addr); 880 if (r) 881 return r; 882 } else if (!ctx->has_msg_cmd) { 883 DRM_ERROR("Message needed before other commands are send!\n"); 884 return -EINVAL; 885 } 886 887 return 0; 888 } 889 890 /** 891 * amdgpu_uvd_cs_reg - parse register writes 892 * 893 * @ctx: UVD parser context 894 * @cb: callback function 895 * 896 * Parse the register writes, call cb on each complete command. 897 */ 898 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, 899 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 900 { 901 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 902 int i, r; 903 904 ctx->idx++; 905 for (i = 0; i <= ctx->count; ++i) { 906 unsigned reg = ctx->reg + i; 907 908 if (ctx->idx >= ib->length_dw) { 909 DRM_ERROR("Register command after end of CS!\n"); 910 return -EINVAL; 911 } 912 913 switch (reg) { 914 case mmUVD_GPCOM_VCPU_DATA0: 915 ctx->data0 = ctx->idx; 916 break; 917 case mmUVD_GPCOM_VCPU_DATA1: 918 ctx->data1 = ctx->idx; 919 break; 920 case mmUVD_GPCOM_VCPU_CMD: 921 r = cb(ctx); 922 if (r) 923 return r; 924 break; 925 case mmUVD_ENGINE_CNTL: 926 case mmUVD_NO_OP: 927 break; 928 default: 929 DRM_ERROR("Invalid reg 0x%X!\n", reg); 930 return -EINVAL; 931 } 932 ctx->idx++; 933 } 934 return 0; 935 } 936 937 /** 938 * amdgpu_uvd_cs_packets - parse UVD packets 939 * 940 * @ctx: UVD parser context 941 * @cb: callback function 942 * 943 * Parse the command stream packets. 944 */ 945 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, 946 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 947 { 948 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 949 int r; 950 951 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) { 952 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx); 953 unsigned type = CP_PACKET_GET_TYPE(cmd); 954 switch (type) { 955 case PACKET_TYPE0: 956 ctx->reg = CP_PACKET0_GET_REG(cmd); 957 ctx->count = CP_PACKET_GET_COUNT(cmd); 958 r = amdgpu_uvd_cs_reg(ctx, cb); 959 if (r) 960 return r; 961 break; 962 case PACKET_TYPE2: 963 ++ctx->idx; 964 break; 965 default: 966 DRM_ERROR("Unknown packet type %d !\n", type); 967 return -EINVAL; 968 } 969 } 970 return 0; 971 } 972 973 /** 974 * amdgpu_uvd_ring_parse_cs - UVD command submission parser 975 * 976 * @parser: Command submission parser context 977 * 978 * Parse the command stream, patch in addresses as necessary. 979 */ 980 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) 981 { 982 struct amdgpu_uvd_cs_ctx ctx = {}; 983 unsigned buf_sizes[] = { 984 [0x00000000] = 2048, 985 [0x00000001] = 0xFFFFFFFF, 986 [0x00000002] = 0xFFFFFFFF, 987 [0x00000003] = 2048, 988 [0x00000004] = 0xFFFFFFFF, 989 }; 990 struct amdgpu_ib *ib = &parser->job->ibs[ib_idx]; 991 int r; 992 993 parser->job->vm = NULL; 994 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 995 996 if (ib->length_dw % 16) { 997 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 998 ib->length_dw); 999 return -EINVAL; 1000 } 1001 1002 ctx.parser = parser; 1003 ctx.buf_sizes = buf_sizes; 1004 ctx.ib_idx = ib_idx; 1005 1006 /* first round only required on chips without UVD 64 bit address support */ 1007 if (!parser->adev->uvd.address_64_bit) { 1008 /* first round, make sure the buffers are actually in the UVD segment */ 1009 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); 1010 if (r) 1011 return r; 1012 } 1013 1014 /* second round, patch buffer addresses into the command stream */ 1015 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); 1016 if (r) 1017 return r; 1018 1019 if (!ctx.has_msg_cmd) { 1020 DRM_ERROR("UVD-IBs need a msg command!\n"); 1021 return -EINVAL; 1022 } 1023 1024 return 0; 1025 } 1026 1027 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, 1028 bool direct, struct dma_fence **fence) 1029 { 1030 struct amdgpu_device *adev = ring->adev; 1031 struct dma_fence *f = NULL; 1032 struct amdgpu_job *job; 1033 struct amdgpu_ib *ib; 1034 uint32_t data[4]; 1035 uint64_t addr; 1036 long r; 1037 int i; 1038 unsigned offset_idx = 0; 1039 unsigned offset[3] = { UVD_BASE_SI, 0, 0 }; 1040 1041 amdgpu_bo_kunmap(bo); 1042 amdgpu_bo_unpin(bo); 1043 1044 if (!ring->adev->uvd.address_64_bit) { 1045 struct ttm_operation_ctx ctx = { true, false }; 1046 1047 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); 1048 amdgpu_uvd_force_into_uvd_segment(bo); 1049 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1050 if (r) 1051 goto err; 1052 } 1053 1054 r = amdgpu_job_alloc_with_ib(adev, 64, &job); 1055 if (r) 1056 goto err; 1057 1058 if (adev->asic_type >= CHIP_VEGA10) { 1059 offset_idx = 1 + ring->me; 1060 offset[1] = adev->reg_offset[UVD_HWIP][0][1]; 1061 offset[2] = adev->reg_offset[UVD_HWIP][1][1]; 1062 } 1063 1064 data[0] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA0, 0); 1065 data[1] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA1, 0); 1066 data[2] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_CMD, 0); 1067 data[3] = PACKET0(offset[offset_idx] + UVD_NO_OP, 0); 1068 1069 ib = &job->ibs[0]; 1070 addr = amdgpu_bo_gpu_offset(bo); 1071 ib->ptr[0] = data[0]; 1072 ib->ptr[1] = addr; 1073 ib->ptr[2] = data[1]; 1074 ib->ptr[3] = addr >> 32; 1075 ib->ptr[4] = data[2]; 1076 ib->ptr[5] = 0; 1077 for (i = 6; i < 16; i += 2) { 1078 ib->ptr[i] = data[3]; 1079 ib->ptr[i+1] = 0; 1080 } 1081 ib->length_dw = 16; 1082 1083 if (direct) { 1084 r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, 1085 true, false, 1086 msecs_to_jiffies(10)); 1087 if (r == 0) 1088 r = -ETIMEDOUT; 1089 if (r < 0) 1090 goto err_free; 1091 1092 r = amdgpu_job_submit_direct(job, ring, &f); 1093 if (r) 1094 goto err_free; 1095 } else { 1096 r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.base.resv, 1097 AMDGPU_FENCE_OWNER_UNDEFINED, false); 1098 if (r) 1099 goto err_free; 1100 1101 r = amdgpu_job_submit(job, &adev->uvd.entity, 1102 AMDGPU_FENCE_OWNER_UNDEFINED, &f); 1103 if (r) 1104 goto err_free; 1105 } 1106 1107 amdgpu_bo_fence(bo, f, false); 1108 amdgpu_bo_unreserve(bo); 1109 amdgpu_bo_unref(&bo); 1110 1111 if (fence) 1112 *fence = dma_fence_get(f); 1113 dma_fence_put(f); 1114 1115 return 0; 1116 1117 err_free: 1118 amdgpu_job_free(job); 1119 1120 err: 1121 amdgpu_bo_unreserve(bo); 1122 amdgpu_bo_unref(&bo); 1123 return r; 1124 } 1125 1126 /* multiple fence commands without any stream commands in between can 1127 crash the vcpu so just try to emmit a dummy create/destroy msg to 1128 avoid this */ 1129 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 1130 struct dma_fence **fence) 1131 { 1132 struct amdgpu_device *adev = ring->adev; 1133 struct amdgpu_bo *bo = NULL; 1134 uint32_t *msg; 1135 int r, i; 1136 1137 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 1138 AMDGPU_GEM_DOMAIN_VRAM, 1139 &bo, NULL, (void **)&msg); 1140 if (r) 1141 return r; 1142 1143 /* stitch together an UVD create msg */ 1144 msg[0] = cpu_to_le32(0x00000de4); 1145 msg[1] = cpu_to_le32(0x00000000); 1146 msg[2] = cpu_to_le32(handle); 1147 msg[3] = cpu_to_le32(0x00000000); 1148 msg[4] = cpu_to_le32(0x00000000); 1149 msg[5] = cpu_to_le32(0x00000000); 1150 msg[6] = cpu_to_le32(0x00000000); 1151 msg[7] = cpu_to_le32(0x00000780); 1152 msg[8] = cpu_to_le32(0x00000440); 1153 msg[9] = cpu_to_le32(0x00000000); 1154 msg[10] = cpu_to_le32(0x01b37000); 1155 for (i = 11; i < 1024; ++i) 1156 msg[i] = cpu_to_le32(0x0); 1157 1158 return amdgpu_uvd_send_msg(ring, bo, true, fence); 1159 } 1160 1161 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 1162 bool direct, struct dma_fence **fence) 1163 { 1164 struct amdgpu_device *adev = ring->adev; 1165 struct amdgpu_bo *bo = NULL; 1166 uint32_t *msg; 1167 int r, i; 1168 1169 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 1170 AMDGPU_GEM_DOMAIN_VRAM, 1171 &bo, NULL, (void **)&msg); 1172 if (r) 1173 return r; 1174 1175 /* stitch together an UVD destroy msg */ 1176 msg[0] = cpu_to_le32(0x00000de4); 1177 msg[1] = cpu_to_le32(0x00000002); 1178 msg[2] = cpu_to_le32(handle); 1179 msg[3] = cpu_to_le32(0x00000000); 1180 for (i = 4; i < 1024; ++i) 1181 msg[i] = cpu_to_le32(0x0); 1182 1183 return amdgpu_uvd_send_msg(ring, bo, direct, fence); 1184 } 1185 1186 static void amdgpu_uvd_idle_work_handler(struct work_struct *work) 1187 { 1188 struct amdgpu_device *adev = 1189 container_of(work, struct amdgpu_device, uvd.idle_work.work); 1190 unsigned fences = 0, i, j; 1191 1192 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 1193 if (adev->uvd.harvest_config & (1 << i)) 1194 continue; 1195 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring); 1196 for (j = 0; j < adev->uvd.num_enc_rings; ++j) { 1197 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]); 1198 } 1199 } 1200 1201 if (fences == 0) { 1202 if (adev->pm.dpm_enabled) { 1203 amdgpu_dpm_enable_uvd(adev, false); 1204 } else { 1205 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 1206 /* shutdown the UVD block */ 1207 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1208 AMD_PG_STATE_GATE); 1209 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1210 AMD_CG_STATE_GATE); 1211 } 1212 } else { 1213 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1214 } 1215 } 1216 1217 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) 1218 { 1219 struct amdgpu_device *adev = ring->adev; 1220 bool set_clocks; 1221 1222 if (amdgpu_sriov_vf(adev)) 1223 return; 1224 1225 set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); 1226 if (set_clocks) { 1227 if (adev->pm.dpm_enabled) { 1228 amdgpu_dpm_enable_uvd(adev, true); 1229 } else { 1230 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 1231 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1232 AMD_CG_STATE_UNGATE); 1233 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1234 AMD_PG_STATE_UNGATE); 1235 } 1236 } 1237 } 1238 1239 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring) 1240 { 1241 if (!amdgpu_sriov_vf(ring->adev)) 1242 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1243 } 1244 1245 /** 1246 * amdgpu_uvd_ring_test_ib - test ib execution 1247 * 1248 * @ring: amdgpu_ring pointer 1249 * 1250 * Test if we can successfully execute an IB 1251 */ 1252 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1253 { 1254 struct dma_fence *fence; 1255 long r; 1256 1257 r = amdgpu_uvd_get_create_msg(ring, 1, NULL); 1258 if (r) 1259 goto error; 1260 1261 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); 1262 if (r) 1263 goto error; 1264 1265 r = dma_fence_wait_timeout(fence, false, timeout); 1266 if (r == 0) 1267 r = -ETIMEDOUT; 1268 else if (r > 0) 1269 r = 0; 1270 1271 dma_fence_put(fence); 1272 1273 error: 1274 return r; 1275 } 1276 1277 /** 1278 * amdgpu_uvd_used_handles - returns used UVD handles 1279 * 1280 * @adev: amdgpu_device pointer 1281 * 1282 * Returns the number of UVD handles in use 1283 */ 1284 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev) 1285 { 1286 unsigned i; 1287 uint32_t used_handles = 0; 1288 1289 for (i = 0; i < adev->uvd.max_handles; ++i) { 1290 /* 1291 * Handles can be freed in any order, and not 1292 * necessarily linear. So we need to count 1293 * all non-zero handles. 1294 */ 1295 if (atomic_read(&adev->uvd.handles[i])) 1296 used_handles++; 1297 } 1298 1299 return used_handles; 1300 } 1301