1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/slab.h> 26 #include <linux/module.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_ucode.h" 30 31 static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr) 32 { 33 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes)); 34 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes)); 35 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major)); 36 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor)); 37 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major)); 38 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor)); 39 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version)); 40 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes)); 41 DRM_DEBUG("ucode_array_offset_bytes: %u\n", 42 le32_to_cpu(hdr->ucode_array_offset_bytes)); 43 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32)); 44 } 45 46 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr) 47 { 48 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 49 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 50 51 DRM_DEBUG("MC\n"); 52 amdgpu_ucode_print_common_hdr(hdr); 53 54 if (version_major == 1) { 55 const struct mc_firmware_header_v1_0 *mc_hdr = 56 container_of(hdr, struct mc_firmware_header_v1_0, header); 57 58 DRM_DEBUG("io_debug_size_bytes: %u\n", 59 le32_to_cpu(mc_hdr->io_debug_size_bytes)); 60 DRM_DEBUG("io_debug_array_offset_bytes: %u\n", 61 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes)); 62 } else { 63 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor); 64 } 65 } 66 67 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr) 68 { 69 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 70 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 71 const struct smc_firmware_header_v1_0 *v1_0_hdr; 72 const struct smc_firmware_header_v2_0 *v2_0_hdr; 73 const struct smc_firmware_header_v2_1 *v2_1_hdr; 74 75 DRM_DEBUG("SMC\n"); 76 amdgpu_ucode_print_common_hdr(hdr); 77 78 if (version_major == 1) { 79 v1_0_hdr = container_of(hdr, struct smc_firmware_header_v1_0, header); 80 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(v1_0_hdr->ucode_start_addr)); 81 } else if (version_major == 2) { 82 switch (version_minor) { 83 case 0: 84 v2_0_hdr = container_of(hdr, struct smc_firmware_header_v2_0, v1_0.header); 85 DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_offset_bytes)); 86 DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_size_bytes)); 87 break; 88 case 1: 89 v2_1_hdr = container_of(hdr, struct smc_firmware_header_v2_1, v1_0.header); 90 DRM_DEBUG("pptable_count: %u\n", le32_to_cpu(v2_1_hdr->pptable_count)); 91 DRM_DEBUG("pptable_entry_offset: %u\n", le32_to_cpu(v2_1_hdr->pptable_entry_offset)); 92 break; 93 default: 94 break; 95 } 96 97 } else { 98 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor); 99 } 100 } 101 102 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr) 103 { 104 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 105 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 106 107 DRM_DEBUG("GFX\n"); 108 amdgpu_ucode_print_common_hdr(hdr); 109 110 if (version_major == 1) { 111 const struct gfx_firmware_header_v1_0 *gfx_hdr = 112 container_of(hdr, struct gfx_firmware_header_v1_0, header); 113 114 DRM_DEBUG("ucode_feature_version: %u\n", 115 le32_to_cpu(gfx_hdr->ucode_feature_version)); 116 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset)); 117 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size)); 118 } else if (version_major == 2) { 119 const struct gfx_firmware_header_v2_0 *gfx_hdr = 120 container_of(hdr, struct gfx_firmware_header_v2_0, header); 121 122 DRM_DEBUG("ucode_feature_version: %u\n", 123 le32_to_cpu(gfx_hdr->ucode_feature_version)); 124 } else { 125 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); 126 } 127 } 128 129 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr) 130 { 131 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 132 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 133 134 DRM_DEBUG("RLC\n"); 135 amdgpu_ucode_print_common_hdr(hdr); 136 137 if (version_major == 1) { 138 const struct rlc_firmware_header_v1_0 *rlc_hdr = 139 container_of(hdr, struct rlc_firmware_header_v1_0, header); 140 141 DRM_DEBUG("ucode_feature_version: %u\n", 142 le32_to_cpu(rlc_hdr->ucode_feature_version)); 143 DRM_DEBUG("save_and_restore_offset: %u\n", 144 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 145 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 146 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 147 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 148 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 149 DRM_DEBUG("master_pkt_description_offset: %u\n", 150 le32_to_cpu(rlc_hdr->master_pkt_description_offset)); 151 } else if (version_major == 2) { 152 const struct rlc_firmware_header_v2_0 *rlc_hdr = 153 container_of(hdr, struct rlc_firmware_header_v2_0, header); 154 const struct rlc_firmware_header_v2_1 *rlc_hdr_v2_1 = 155 container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0); 156 const struct rlc_firmware_header_v2_2 *rlc_hdr_v2_2 = 157 container_of(rlc_hdr_v2_1, struct rlc_firmware_header_v2_2, v2_1); 158 const struct rlc_firmware_header_v2_3 *rlc_hdr_v2_3 = 159 container_of(rlc_hdr_v2_2, struct rlc_firmware_header_v2_3, v2_2); 160 const struct rlc_firmware_header_v2_4 *rlc_hdr_v2_4 = 161 container_of(rlc_hdr_v2_3, struct rlc_firmware_header_v2_4, v2_3); 162 163 switch (version_minor) { 164 case 0: 165 /* rlc_hdr v2_0 */ 166 DRM_DEBUG("ucode_feature_version: %u\n", 167 le32_to_cpu(rlc_hdr->ucode_feature_version)); 168 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset)); 169 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size)); 170 DRM_DEBUG("save_and_restore_offset: %u\n", 171 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 172 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 173 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 174 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 175 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 176 DRM_DEBUG("reg_restore_list_size: %u\n", 177 le32_to_cpu(rlc_hdr->reg_restore_list_size)); 178 DRM_DEBUG("reg_list_format_start: %u\n", 179 le32_to_cpu(rlc_hdr->reg_list_format_start)); 180 DRM_DEBUG("reg_list_format_separate_start: %u\n", 181 le32_to_cpu(rlc_hdr->reg_list_format_separate_start)); 182 DRM_DEBUG("starting_offsets_start: %u\n", 183 le32_to_cpu(rlc_hdr->starting_offsets_start)); 184 DRM_DEBUG("reg_list_format_size_bytes: %u\n", 185 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes)); 186 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n", 187 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 188 DRM_DEBUG("reg_list_size_bytes: %u\n", 189 le32_to_cpu(rlc_hdr->reg_list_size_bytes)); 190 DRM_DEBUG("reg_list_array_offset_bytes: %u\n", 191 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 192 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n", 193 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes)); 194 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n", 195 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes)); 196 DRM_DEBUG("reg_list_separate_size_bytes: %u\n", 197 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes)); 198 DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n", 199 le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes)); 200 break; 201 case 1: 202 /* rlc_hdr v2_1 */ 203 DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n", 204 le32_to_cpu(rlc_hdr_v2_1->reg_list_format_direct_reg_list_length)); 205 DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n", 206 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_ucode_ver)); 207 DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n", 208 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_feature_ver)); 209 DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n", 210 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_size_bytes)); 211 DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n", 212 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_offset_bytes)); 213 DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n", 214 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_ucode_ver)); 215 DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n", 216 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_feature_ver)); 217 DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n", 218 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_size_bytes)); 219 DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n", 220 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_offset_bytes)); 221 DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n", 222 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_ucode_ver)); 223 DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n", 224 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_feature_ver)); 225 DRM_DEBUG("save_restore_list_srm_size_bytes %u\n", 226 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_size_bytes)); 227 DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n", 228 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_offset_bytes)); 229 break; 230 case 2: 231 /* rlc_hdr v2_2 */ 232 DRM_DEBUG("rlc_iram_ucode_size_bytes: %u\n", 233 le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_size_bytes)); 234 DRM_DEBUG("rlc_iram_ucode_offset_bytes: %u\n", 235 le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_offset_bytes)); 236 DRM_DEBUG("rlc_dram_ucode_size_bytes: %u\n", 237 le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_size_bytes)); 238 DRM_DEBUG("rlc_dram_ucode_offset_bytes: %u\n", 239 le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_offset_bytes)); 240 break; 241 case 3: 242 /* rlc_hdr v2_3 */ 243 DRM_DEBUG("rlcp_ucode_version: %u\n", 244 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_version)); 245 DRM_DEBUG("rlcp_ucode_feature_version: %u\n", 246 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_feature_version)); 247 DRM_DEBUG("rlcp_ucode_size_bytes: %u\n", 248 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_size_bytes)); 249 DRM_DEBUG("rlcp_ucode_offset_bytes: %u\n", 250 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_offset_bytes)); 251 DRM_DEBUG("rlcv_ucode_version: %u\n", 252 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_version)); 253 DRM_DEBUG("rlcv_ucode_feature_version: %u\n", 254 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_feature_version)); 255 DRM_DEBUG("rlcv_ucode_size_bytes: %u\n", 256 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_size_bytes)); 257 DRM_DEBUG("rlcv_ucode_offset_bytes: %u\n", 258 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_offset_bytes)); 259 break; 260 case 4: 261 /* rlc_hdr v2_4 */ 262 DRM_DEBUG("global_tap_delays_ucode_size_bytes :%u\n", 263 le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_size_bytes)); 264 DRM_DEBUG("global_tap_delays_ucode_offset_bytes: %u\n", 265 le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_offset_bytes)); 266 DRM_DEBUG("se0_tap_delays_ucode_size_bytes :%u\n", 267 le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_size_bytes)); 268 DRM_DEBUG("se0_tap_delays_ucode_offset_bytes: %u\n", 269 le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_offset_bytes)); 270 DRM_DEBUG("se1_tap_delays_ucode_size_bytes :%u\n", 271 le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_size_bytes)); 272 DRM_DEBUG("se1_tap_delays_ucode_offset_bytes: %u\n", 273 le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_offset_bytes)); 274 DRM_DEBUG("se2_tap_delays_ucode_size_bytes :%u\n", 275 le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_size_bytes)); 276 DRM_DEBUG("se2_tap_delays_ucode_offset_bytes: %u\n", 277 le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_offset_bytes)); 278 DRM_DEBUG("se3_tap_delays_ucode_size_bytes :%u\n", 279 le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_size_bytes)); 280 DRM_DEBUG("se3_tap_delays_ucode_offset_bytes: %u\n", 281 le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_offset_bytes)); 282 break; 283 default: 284 DRM_ERROR("Unknown RLC v2 ucode: v2.%u\n", version_minor); 285 break; 286 } 287 } else { 288 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor); 289 } 290 } 291 292 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr) 293 { 294 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 295 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 296 297 DRM_DEBUG("SDMA\n"); 298 amdgpu_ucode_print_common_hdr(hdr); 299 300 if (version_major == 1) { 301 const struct sdma_firmware_header_v1_0 *sdma_hdr = 302 container_of(hdr, struct sdma_firmware_header_v1_0, header); 303 304 DRM_DEBUG("ucode_feature_version: %u\n", 305 le32_to_cpu(sdma_hdr->ucode_feature_version)); 306 DRM_DEBUG("ucode_change_version: %u\n", 307 le32_to_cpu(sdma_hdr->ucode_change_version)); 308 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset)); 309 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size)); 310 if (version_minor >= 1) { 311 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr = 312 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0); 313 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size)); 314 } 315 } else if (version_major == 2) { 316 const struct sdma_firmware_header_v2_0 *sdma_hdr = 317 container_of(hdr, struct sdma_firmware_header_v2_0, header); 318 319 DRM_DEBUG("ucode_feature_version: %u\n", 320 le32_to_cpu(sdma_hdr->ucode_feature_version)); 321 DRM_DEBUG("ctx_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_offset)); 322 DRM_DEBUG("ctx_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_size)); 323 DRM_DEBUG("ctl_ucode_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 324 DRM_DEBUG("ctl_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_offset)); 325 DRM_DEBUG("ctl_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_size)); 326 } else if (version_major == 3) { 327 const struct sdma_firmware_header_v3_0 *sdma_hdr = 328 container_of(hdr, struct sdma_firmware_header_v3_0, header); 329 330 DRM_DEBUG("ucode_reversion: %u\n", 331 le32_to_cpu(sdma_hdr->ucode_feature_version)); 332 } else { 333 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n", 334 version_major, version_minor); 335 } 336 } 337 338 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr) 339 { 340 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 341 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 342 uint32_t fw_index; 343 const struct psp_fw_bin_desc *desc; 344 345 DRM_DEBUG("PSP\n"); 346 amdgpu_ucode_print_common_hdr(hdr); 347 348 if (version_major == 1) { 349 const struct psp_firmware_header_v1_0 *psp_hdr = 350 container_of(hdr, struct psp_firmware_header_v1_0, header); 351 352 DRM_DEBUG("ucode_feature_version: %u\n", 353 le32_to_cpu(psp_hdr->sos.fw_version)); 354 DRM_DEBUG("sos_offset_bytes: %u\n", 355 le32_to_cpu(psp_hdr->sos.offset_bytes)); 356 DRM_DEBUG("sos_size_bytes: %u\n", 357 le32_to_cpu(psp_hdr->sos.size_bytes)); 358 if (version_minor == 1) { 359 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = 360 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); 361 DRM_DEBUG("toc_header_version: %u\n", 362 le32_to_cpu(psp_hdr_v1_1->toc.fw_version)); 363 DRM_DEBUG("toc_offset_bytes: %u\n", 364 le32_to_cpu(psp_hdr_v1_1->toc.offset_bytes)); 365 DRM_DEBUG("toc_size_bytes: %u\n", 366 le32_to_cpu(psp_hdr_v1_1->toc.size_bytes)); 367 DRM_DEBUG("kdb_header_version: %u\n", 368 le32_to_cpu(psp_hdr_v1_1->kdb.fw_version)); 369 DRM_DEBUG("kdb_offset_bytes: %u\n", 370 le32_to_cpu(psp_hdr_v1_1->kdb.offset_bytes)); 371 DRM_DEBUG("kdb_size_bytes: %u\n", 372 le32_to_cpu(psp_hdr_v1_1->kdb.size_bytes)); 373 } 374 if (version_minor == 2) { 375 const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 = 376 container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0); 377 DRM_DEBUG("kdb_header_version: %u\n", 378 le32_to_cpu(psp_hdr_v1_2->kdb.fw_version)); 379 DRM_DEBUG("kdb_offset_bytes: %u\n", 380 le32_to_cpu(psp_hdr_v1_2->kdb.offset_bytes)); 381 DRM_DEBUG("kdb_size_bytes: %u\n", 382 le32_to_cpu(psp_hdr_v1_2->kdb.size_bytes)); 383 } 384 if (version_minor == 3) { 385 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = 386 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); 387 const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 = 388 container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1); 389 DRM_DEBUG("toc_header_version: %u\n", 390 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.fw_version)); 391 DRM_DEBUG("toc_offset_bytes: %u\n", 392 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.offset_bytes)); 393 DRM_DEBUG("toc_size_bytes: %u\n", 394 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.size_bytes)); 395 DRM_DEBUG("kdb_header_version: %u\n", 396 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.fw_version)); 397 DRM_DEBUG("kdb_offset_bytes: %u\n", 398 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.offset_bytes)); 399 DRM_DEBUG("kdb_size_bytes: %u\n", 400 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.size_bytes)); 401 DRM_DEBUG("spl_header_version: %u\n", 402 le32_to_cpu(psp_hdr_v1_3->spl.fw_version)); 403 DRM_DEBUG("spl_offset_bytes: %u\n", 404 le32_to_cpu(psp_hdr_v1_3->spl.offset_bytes)); 405 DRM_DEBUG("spl_size_bytes: %u\n", 406 le32_to_cpu(psp_hdr_v1_3->spl.size_bytes)); 407 } 408 } else if (version_major == 2) { 409 const struct psp_firmware_header_v2_0 *psp_hdr_v2_0 = 410 container_of(hdr, struct psp_firmware_header_v2_0, header); 411 for (fw_index = 0; fw_index < le32_to_cpu(psp_hdr_v2_0->psp_fw_bin_count); fw_index++) { 412 desc = &(psp_hdr_v2_0->psp_fw_bin[fw_index]); 413 switch (desc->fw_type) { 414 case PSP_FW_TYPE_PSP_SOS: 415 DRM_DEBUG("psp_sos_version: %u\n", 416 le32_to_cpu(desc->fw_version)); 417 DRM_DEBUG("psp_sos_size_bytes: %u\n", 418 le32_to_cpu(desc->size_bytes)); 419 break; 420 case PSP_FW_TYPE_PSP_SYS_DRV: 421 DRM_DEBUG("psp_sys_drv_version: %u\n", 422 le32_to_cpu(desc->fw_version)); 423 DRM_DEBUG("psp_sys_drv_size_bytes: %u\n", 424 le32_to_cpu(desc->size_bytes)); 425 break; 426 case PSP_FW_TYPE_PSP_KDB: 427 DRM_DEBUG("psp_kdb_version: %u\n", 428 le32_to_cpu(desc->fw_version)); 429 DRM_DEBUG("psp_kdb_size_bytes: %u\n", 430 le32_to_cpu(desc->size_bytes)); 431 break; 432 case PSP_FW_TYPE_PSP_TOC: 433 DRM_DEBUG("psp_toc_version: %u\n", 434 le32_to_cpu(desc->fw_version)); 435 DRM_DEBUG("psp_toc_size_bytes: %u\n", 436 le32_to_cpu(desc->size_bytes)); 437 break; 438 case PSP_FW_TYPE_PSP_SPL: 439 DRM_DEBUG("psp_spl_version: %u\n", 440 le32_to_cpu(desc->fw_version)); 441 DRM_DEBUG("psp_spl_size_bytes: %u\n", 442 le32_to_cpu(desc->size_bytes)); 443 break; 444 case PSP_FW_TYPE_PSP_RL: 445 DRM_DEBUG("psp_rl_version: %u\n", 446 le32_to_cpu(desc->fw_version)); 447 DRM_DEBUG("psp_rl_size_bytes: %u\n", 448 le32_to_cpu(desc->size_bytes)); 449 break; 450 case PSP_FW_TYPE_PSP_SOC_DRV: 451 DRM_DEBUG("psp_soc_drv_version: %u\n", 452 le32_to_cpu(desc->fw_version)); 453 DRM_DEBUG("psp_soc_drv_size_bytes: %u\n", 454 le32_to_cpu(desc->size_bytes)); 455 break; 456 case PSP_FW_TYPE_PSP_INTF_DRV: 457 DRM_DEBUG("psp_intf_drv_version: %u\n", 458 le32_to_cpu(desc->fw_version)); 459 DRM_DEBUG("psp_intf_drv_size_bytes: %u\n", 460 le32_to_cpu(desc->size_bytes)); 461 break; 462 case PSP_FW_TYPE_PSP_DBG_DRV: 463 DRM_DEBUG("psp_dbg_drv_version: %u\n", 464 le32_to_cpu(desc->fw_version)); 465 DRM_DEBUG("psp_dbg_drv_size_bytes: %u\n", 466 le32_to_cpu(desc->size_bytes)); 467 break; 468 case PSP_FW_TYPE_PSP_RAS_DRV: 469 DRM_DEBUG("psp_ras_drv_version: %u\n", 470 le32_to_cpu(desc->fw_version)); 471 DRM_DEBUG("psp_ras_drv_size_bytes: %u\n", 472 le32_to_cpu(desc->size_bytes)); 473 break; 474 default: 475 DRM_DEBUG("Unsupported PSP fw type: %d\n", desc->fw_type); 476 break; 477 } 478 } 479 } else { 480 DRM_ERROR("Unknown PSP ucode version: %u.%u\n", 481 version_major, version_minor); 482 } 483 } 484 485 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr) 486 { 487 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 488 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 489 490 DRM_DEBUG("GPU_INFO\n"); 491 amdgpu_ucode_print_common_hdr(hdr); 492 493 if (version_major == 1) { 494 const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr = 495 container_of(hdr, struct gpu_info_firmware_header_v1_0, header); 496 497 DRM_DEBUG("version_major: %u\n", 498 le16_to_cpu(gpu_info_hdr->version_major)); 499 DRM_DEBUG("version_minor: %u\n", 500 le16_to_cpu(gpu_info_hdr->version_minor)); 501 } else { 502 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor); 503 } 504 } 505 506 static int amdgpu_ucode_validate(const struct firmware *fw) 507 { 508 const struct common_firmware_header *hdr = 509 (const struct common_firmware_header *)fw->data; 510 511 if (fw->size == le32_to_cpu(hdr->size_bytes)) 512 return 0; 513 514 return -EINVAL; 515 } 516 517 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 518 uint16_t hdr_major, uint16_t hdr_minor) 519 { 520 if ((hdr->common.header_version_major == hdr_major) && 521 (hdr->common.header_version_minor == hdr_minor)) 522 return true; 523 return false; 524 } 525 526 enum amdgpu_firmware_load_type 527 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) 528 { 529 switch (adev->asic_type) { 530 #ifdef CONFIG_DRM_AMDGPU_SI 531 case CHIP_TAHITI: 532 case CHIP_PITCAIRN: 533 case CHIP_VERDE: 534 case CHIP_OLAND: 535 case CHIP_HAINAN: 536 return AMDGPU_FW_LOAD_DIRECT; 537 #endif 538 #ifdef CONFIG_DRM_AMDGPU_CIK 539 case CHIP_BONAIRE: 540 case CHIP_KAVERI: 541 case CHIP_KABINI: 542 case CHIP_HAWAII: 543 case CHIP_MULLINS: 544 return AMDGPU_FW_LOAD_DIRECT; 545 #endif 546 case CHIP_TOPAZ: 547 case CHIP_TONGA: 548 case CHIP_FIJI: 549 case CHIP_CARRIZO: 550 case CHIP_STONEY: 551 case CHIP_POLARIS10: 552 case CHIP_POLARIS11: 553 case CHIP_POLARIS12: 554 case CHIP_VEGAM: 555 return AMDGPU_FW_LOAD_SMU; 556 case CHIP_CYAN_SKILLFISH: 557 if (!(load_type && 558 adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)) 559 return AMDGPU_FW_LOAD_DIRECT; 560 else 561 return AMDGPU_FW_LOAD_PSP; 562 default: 563 if (!load_type) 564 return AMDGPU_FW_LOAD_DIRECT; 565 else if (load_type == 3) 566 return AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO; 567 else 568 return AMDGPU_FW_LOAD_PSP; 569 } 570 } 571 572 const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id) 573 { 574 switch (ucode_id) { 575 case AMDGPU_UCODE_ID_SDMA0: 576 return "SDMA0"; 577 case AMDGPU_UCODE_ID_SDMA1: 578 return "SDMA1"; 579 case AMDGPU_UCODE_ID_SDMA2: 580 return "SDMA2"; 581 case AMDGPU_UCODE_ID_SDMA3: 582 return "SDMA3"; 583 case AMDGPU_UCODE_ID_SDMA4: 584 return "SDMA4"; 585 case AMDGPU_UCODE_ID_SDMA5: 586 return "SDMA5"; 587 case AMDGPU_UCODE_ID_SDMA6: 588 return "SDMA6"; 589 case AMDGPU_UCODE_ID_SDMA7: 590 return "SDMA7"; 591 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 592 return "SDMA_CTX"; 593 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 594 return "SDMA_CTL"; 595 case AMDGPU_UCODE_ID_CP_CE: 596 return "CP_CE"; 597 case AMDGPU_UCODE_ID_CP_PFP: 598 return "CP_PFP"; 599 case AMDGPU_UCODE_ID_CP_ME: 600 return "CP_ME"; 601 case AMDGPU_UCODE_ID_CP_MEC1: 602 return "CP_MEC1"; 603 case AMDGPU_UCODE_ID_CP_MEC1_JT: 604 return "CP_MEC1_JT"; 605 case AMDGPU_UCODE_ID_CP_MEC2: 606 return "CP_MEC2"; 607 case AMDGPU_UCODE_ID_CP_MEC2_JT: 608 return "CP_MEC2_JT"; 609 case AMDGPU_UCODE_ID_CP_MES: 610 return "CP_MES"; 611 case AMDGPU_UCODE_ID_CP_MES_DATA: 612 return "CP_MES_DATA"; 613 case AMDGPU_UCODE_ID_CP_MES1: 614 return "CP_MES_KIQ"; 615 case AMDGPU_UCODE_ID_CP_MES1_DATA: 616 return "CP_MES_KIQ_DATA"; 617 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 618 return "RLC_RESTORE_LIST_CNTL"; 619 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 620 return "RLC_RESTORE_LIST_GPM_MEM"; 621 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 622 return "RLC_RESTORE_LIST_SRM_MEM"; 623 case AMDGPU_UCODE_ID_RLC_IRAM: 624 return "RLC_IRAM"; 625 case AMDGPU_UCODE_ID_RLC_DRAM: 626 return "RLC_DRAM"; 627 case AMDGPU_UCODE_ID_RLC_G: 628 return "RLC_G"; 629 case AMDGPU_UCODE_ID_RLC_P: 630 return "RLC_P"; 631 case AMDGPU_UCODE_ID_RLC_V: 632 return "RLC_V"; 633 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 634 return "GLOBAL_TAP_DELAYS"; 635 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 636 return "SE0_TAP_DELAYS"; 637 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 638 return "SE1_TAP_DELAYS"; 639 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 640 return "SE2_TAP_DELAYS"; 641 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 642 return "SE3_TAP_DELAYS"; 643 case AMDGPU_UCODE_ID_IMU_I: 644 return "IMU_I"; 645 case AMDGPU_UCODE_ID_IMU_D: 646 return "IMU_D"; 647 case AMDGPU_UCODE_ID_STORAGE: 648 return "STORAGE"; 649 case AMDGPU_UCODE_ID_SMC: 650 return "SMC"; 651 case AMDGPU_UCODE_ID_PPTABLE: 652 return "PPTABLE"; 653 case AMDGPU_UCODE_ID_P2S_TABLE: 654 return "P2STABLE"; 655 case AMDGPU_UCODE_ID_UVD: 656 return "UVD"; 657 case AMDGPU_UCODE_ID_UVD1: 658 return "UVD1"; 659 case AMDGPU_UCODE_ID_VCE: 660 return "VCE"; 661 case AMDGPU_UCODE_ID_VCN: 662 return "VCN"; 663 case AMDGPU_UCODE_ID_VCN1: 664 return "VCN1"; 665 case AMDGPU_UCODE_ID_DMCU_ERAM: 666 return "DMCU_ERAM"; 667 case AMDGPU_UCODE_ID_DMCU_INTV: 668 return "DMCU_INTV"; 669 case AMDGPU_UCODE_ID_VCN0_RAM: 670 return "VCN0_RAM"; 671 case AMDGPU_UCODE_ID_VCN1_RAM: 672 return "VCN1_RAM"; 673 case AMDGPU_UCODE_ID_DMCUB: 674 return "DMCUB"; 675 case AMDGPU_UCODE_ID_CAP: 676 return "CAP"; 677 case AMDGPU_UCODE_ID_VPE_CTX: 678 return "VPE_CTX"; 679 case AMDGPU_UCODE_ID_VPE_CTL: 680 return "VPE_CTL"; 681 case AMDGPU_UCODE_ID_VPE: 682 return "VPE"; 683 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 684 return "UMSCH_MM_UCODE"; 685 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 686 return "UMSCH_MM_DATA"; 687 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: 688 return "UMSCH_MM_CMD_BUFFER"; 689 case AMDGPU_UCODE_ID_JPEG_RAM: 690 return "JPEG"; 691 default: 692 return "UNKNOWN UCODE"; 693 } 694 } 695 696 static inline int amdgpu_ucode_is_valid(uint32_t fw_version) 697 { 698 if (!fw_version) 699 return -EINVAL; 700 701 return 0; 702 } 703 704 #define FW_VERSION_ATTR(name, mode, field) \ 705 static ssize_t show_##name(struct device *dev, \ 706 struct device_attribute *attr, char *buf) \ 707 { \ 708 struct drm_device *ddev = dev_get_drvdata(dev); \ 709 struct amdgpu_device *adev = drm_to_adev(ddev); \ 710 \ 711 if (!buf) \ 712 return amdgpu_ucode_is_valid(adev->field); \ 713 \ 714 return sysfs_emit(buf, "0x%08x\n", adev->field); \ 715 } \ 716 static DEVICE_ATTR(name, mode, show_##name, NULL) 717 718 FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version); 719 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version); 720 FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version); 721 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version); 722 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version); 723 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version); 724 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version); 725 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version); 726 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version); 727 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version); 728 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version); 729 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version); 730 FW_VERSION_ATTR(imu_fw_version, 0444, gfx.imu_fw_version); 731 FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos.fw_version); 732 FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_context.bin_desc.fw_version); 733 FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ras_context.context.bin_desc.fw_version); 734 FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.xgmi_context.context.bin_desc.fw_version); 735 FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version); 736 FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version); 737 FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version); 738 FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version); 739 FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version); 740 FW_VERSION_ATTR(mes_fw_version, 0444, mes.sched_version & AMDGPU_MES_VERSION_MASK); 741 FW_VERSION_ATTR(mes_kiq_fw_version, 0444, mes.kiq_version & AMDGPU_MES_VERSION_MASK); 742 743 static struct attribute *fw_attrs[] = { 744 &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr, 745 &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr, 746 &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr, 747 &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr, 748 &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr, 749 &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr, 750 &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr, 751 &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr, 752 &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr, 753 &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr, 754 &dev_attr_dmcu_fw_version.attr, &dev_attr_imu_fw_version.attr, 755 &dev_attr_mes_fw_version.attr, &dev_attr_mes_kiq_fw_version.attr, 756 NULL 757 }; 758 759 #define to_dev_attr(x) container_of(x, struct device_attribute, attr) 760 761 static umode_t amdgpu_ucode_sys_visible(struct kobject *kobj, 762 struct attribute *attr, int idx) 763 { 764 struct device_attribute *dev_attr = to_dev_attr(attr); 765 struct device *dev = kobj_to_dev(kobj); 766 767 if (dev_attr->show(dev, dev_attr, NULL) == -EINVAL) 768 return 0; 769 770 return attr->mode; 771 } 772 773 static const struct attribute_group fw_attr_group = { 774 .name = "fw_version", 775 .attrs = fw_attrs, 776 .is_visible = amdgpu_ucode_sys_visible 777 }; 778 779 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev) 780 { 781 return sysfs_create_group(&adev->dev->kobj, &fw_attr_group); 782 } 783 784 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev) 785 { 786 sysfs_remove_group(&adev->dev->kobj, &fw_attr_group); 787 } 788 789 static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, 790 struct amdgpu_firmware_info *ucode, 791 uint64_t mc_addr, void *kptr) 792 { 793 const struct common_firmware_header *header = NULL; 794 const struct gfx_firmware_header_v1_0 *cp_hdr = NULL; 795 const struct gfx_firmware_header_v2_0 *cpv2_hdr = NULL; 796 const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL; 797 const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL; 798 const struct mes_firmware_header_v1_0 *mes_hdr = NULL; 799 const struct sdma_firmware_header_v2_0 *sdma_hdr = NULL; 800 const struct sdma_firmware_header_v3_0 *sdmav3_hdr = NULL; 801 const struct imu_firmware_header_v1_0 *imu_hdr = NULL; 802 const struct vpe_firmware_header_v1_0 *vpe_hdr = NULL; 803 const struct umsch_mm_firmware_header_v1_0 *umsch_mm_hdr = NULL; 804 u8 *ucode_addr; 805 806 if (!ucode->fw) 807 return 0; 808 809 ucode->mc_addr = mc_addr; 810 ucode->kaddr = kptr; 811 812 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE) 813 return 0; 814 815 header = (const struct common_firmware_header *)ucode->fw->data; 816 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 817 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)ucode->fw->data; 818 dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data; 819 dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data; 820 mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data; 821 sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode->fw->data; 822 sdmav3_hdr = (const struct sdma_firmware_header_v3_0 *)ucode->fw->data; 823 imu_hdr = (const struct imu_firmware_header_v1_0 *)ucode->fw->data; 824 vpe_hdr = (const struct vpe_firmware_header_v1_0 *)ucode->fw->data; 825 umsch_mm_hdr = (const struct umsch_mm_firmware_header_v1_0 *)ucode->fw->data; 826 827 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 828 switch (ucode->ucode_id) { 829 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 830 ucode->ucode_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 831 ucode_addr = (u8 *)ucode->fw->data + 832 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes); 833 break; 834 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 835 ucode->ucode_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 836 ucode_addr = (u8 *)ucode->fw->data + 837 le32_to_cpu(sdma_hdr->ctl_ucode_offset); 838 break; 839 case AMDGPU_UCODE_ID_SDMA_RS64: 840 ucode->ucode_size = le32_to_cpu(sdmav3_hdr->ucode_size_bytes); 841 ucode_addr = (u8 *)ucode->fw->data + 842 le32_to_cpu(sdmav3_hdr->header.ucode_array_offset_bytes); 843 break; 844 case AMDGPU_UCODE_ID_CP_MEC1: 845 case AMDGPU_UCODE_ID_CP_MEC2: 846 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - 847 le32_to_cpu(cp_hdr->jt_size) * 4; 848 ucode_addr = (u8 *)ucode->fw->data + 849 le32_to_cpu(header->ucode_array_offset_bytes); 850 break; 851 case AMDGPU_UCODE_ID_CP_MEC1_JT: 852 case AMDGPU_UCODE_ID_CP_MEC2_JT: 853 ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4; 854 ucode_addr = (u8 *)ucode->fw->data + 855 le32_to_cpu(header->ucode_array_offset_bytes) + 856 le32_to_cpu(cp_hdr->jt_offset) * 4; 857 break; 858 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 859 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; 860 ucode_addr = adev->gfx.rlc.save_restore_list_cntl; 861 break; 862 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 863 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes; 864 ucode_addr = adev->gfx.rlc.save_restore_list_gpm; 865 break; 866 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 867 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes; 868 ucode_addr = adev->gfx.rlc.save_restore_list_srm; 869 break; 870 case AMDGPU_UCODE_ID_RLC_IRAM: 871 ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes; 872 ucode_addr = adev->gfx.rlc.rlc_iram_ucode; 873 break; 874 case AMDGPU_UCODE_ID_RLC_DRAM: 875 ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes; 876 ucode_addr = adev->gfx.rlc.rlc_dram_ucode; 877 break; 878 case AMDGPU_UCODE_ID_RLC_P: 879 ucode->ucode_size = adev->gfx.rlc.rlcp_ucode_size_bytes; 880 ucode_addr = adev->gfx.rlc.rlcp_ucode; 881 break; 882 case AMDGPU_UCODE_ID_RLC_V: 883 ucode->ucode_size = adev->gfx.rlc.rlcv_ucode_size_bytes; 884 ucode_addr = adev->gfx.rlc.rlcv_ucode; 885 break; 886 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 887 ucode->ucode_size = adev->gfx.rlc.global_tap_delays_ucode_size_bytes; 888 ucode_addr = adev->gfx.rlc.global_tap_delays_ucode; 889 break; 890 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 891 ucode->ucode_size = adev->gfx.rlc.se0_tap_delays_ucode_size_bytes; 892 ucode_addr = adev->gfx.rlc.se0_tap_delays_ucode; 893 break; 894 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 895 ucode->ucode_size = adev->gfx.rlc.se1_tap_delays_ucode_size_bytes; 896 ucode_addr = adev->gfx.rlc.se1_tap_delays_ucode; 897 break; 898 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 899 ucode->ucode_size = adev->gfx.rlc.se2_tap_delays_ucode_size_bytes; 900 ucode_addr = adev->gfx.rlc.se2_tap_delays_ucode; 901 break; 902 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 903 ucode->ucode_size = adev->gfx.rlc.se3_tap_delays_ucode_size_bytes; 904 ucode_addr = adev->gfx.rlc.se3_tap_delays_ucode; 905 break; 906 case AMDGPU_UCODE_ID_CP_MES: 907 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 908 ucode_addr = (u8 *)ucode->fw->data + 909 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes); 910 break; 911 case AMDGPU_UCODE_ID_CP_MES_DATA: 912 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 913 ucode_addr = (u8 *)ucode->fw->data + 914 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes); 915 break; 916 case AMDGPU_UCODE_ID_CP_MES1: 917 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 918 ucode_addr = (u8 *)ucode->fw->data + 919 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes); 920 break; 921 case AMDGPU_UCODE_ID_CP_MES1_DATA: 922 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 923 ucode_addr = (u8 *)ucode->fw->data + 924 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes); 925 break; 926 case AMDGPU_UCODE_ID_DMCU_ERAM: 927 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - 928 le32_to_cpu(dmcu_hdr->intv_size_bytes); 929 ucode_addr = (u8 *)ucode->fw->data + 930 le32_to_cpu(header->ucode_array_offset_bytes); 931 break; 932 case AMDGPU_UCODE_ID_DMCU_INTV: 933 ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes); 934 ucode_addr = (u8 *)ucode->fw->data + 935 le32_to_cpu(header->ucode_array_offset_bytes) + 936 le32_to_cpu(dmcu_hdr->intv_offset_bytes); 937 break; 938 case AMDGPU_UCODE_ID_DMCUB: 939 ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes); 940 ucode_addr = (u8 *)ucode->fw->data + 941 le32_to_cpu(header->ucode_array_offset_bytes); 942 break; 943 case AMDGPU_UCODE_ID_PPTABLE: 944 ucode->ucode_size = ucode->fw->size; 945 ucode_addr = (u8 *)ucode->fw->data; 946 break; 947 case AMDGPU_UCODE_ID_P2S_TABLE: 948 ucode->ucode_size = ucode->fw->size; 949 ucode_addr = (u8 *)ucode->fw->data; 950 break; 951 case AMDGPU_UCODE_ID_IMU_I: 952 ucode->ucode_size = le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes); 953 ucode_addr = (u8 *)ucode->fw->data + 954 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes); 955 break; 956 case AMDGPU_UCODE_ID_IMU_D: 957 ucode->ucode_size = le32_to_cpu(imu_hdr->imu_dram_ucode_size_bytes); 958 ucode_addr = (u8 *)ucode->fw->data + 959 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes) + 960 le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes); 961 break; 962 case AMDGPU_UCODE_ID_CP_RS64_PFP: 963 ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 964 ucode_addr = (u8 *)ucode->fw->data + 965 le32_to_cpu(header->ucode_array_offset_bytes); 966 break; 967 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 968 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 969 ucode_addr = (u8 *)ucode->fw->data + 970 le32_to_cpu(cpv2_hdr->data_offset_bytes); 971 break; 972 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 973 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 974 ucode_addr = (u8 *)ucode->fw->data + 975 le32_to_cpu(cpv2_hdr->data_offset_bytes); 976 break; 977 case AMDGPU_UCODE_ID_CP_RS64_ME: 978 ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 979 ucode_addr = (u8 *)ucode->fw->data + 980 le32_to_cpu(header->ucode_array_offset_bytes); 981 break; 982 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 983 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 984 ucode_addr = (u8 *)ucode->fw->data + 985 le32_to_cpu(cpv2_hdr->data_offset_bytes); 986 break; 987 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 988 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 989 ucode_addr = (u8 *)ucode->fw->data + 990 le32_to_cpu(cpv2_hdr->data_offset_bytes); 991 break; 992 case AMDGPU_UCODE_ID_CP_RS64_MEC: 993 ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 994 ucode_addr = (u8 *)ucode->fw->data + 995 le32_to_cpu(header->ucode_array_offset_bytes); 996 break; 997 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 998 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 999 ucode_addr = (u8 *)ucode->fw->data + 1000 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1001 break; 1002 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 1003 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1004 ucode_addr = (u8 *)ucode->fw->data + 1005 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1006 break; 1007 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 1008 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1009 ucode_addr = (u8 *)ucode->fw->data + 1010 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1011 break; 1012 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 1013 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1014 ucode_addr = (u8 *)ucode->fw->data + 1015 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1016 break; 1017 case AMDGPU_UCODE_ID_VPE_CTX: 1018 ucode->ucode_size = le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes); 1019 ucode_addr = (u8 *)ucode->fw->data + 1020 le32_to_cpu(vpe_hdr->header.ucode_array_offset_bytes); 1021 break; 1022 case AMDGPU_UCODE_ID_VPE_CTL: 1023 ucode->ucode_size = le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes); 1024 ucode_addr = (u8 *)ucode->fw->data + 1025 le32_to_cpu(vpe_hdr->ctl_ucode_offset); 1026 break; 1027 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 1028 ucode->ucode_size = le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_size_bytes); 1029 ucode_addr = (u8 *)ucode->fw->data + 1030 le32_to_cpu(umsch_mm_hdr->header.ucode_array_offset_bytes); 1031 break; 1032 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 1033 ucode->ucode_size = le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_data_size_bytes); 1034 ucode_addr = (u8 *)ucode->fw->data + 1035 le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_data_offset_bytes); 1036 break; 1037 default: 1038 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); 1039 ucode_addr = (u8 *)ucode->fw->data + 1040 le32_to_cpu(header->ucode_array_offset_bytes); 1041 break; 1042 } 1043 } else { 1044 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); 1045 ucode_addr = (u8 *)ucode->fw->data + 1046 le32_to_cpu(header->ucode_array_offset_bytes); 1047 } 1048 1049 memcpy(ucode->kaddr, ucode_addr, ucode->ucode_size); 1050 1051 return 0; 1052 } 1053 1054 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode, 1055 uint64_t mc_addr, void *kptr) 1056 { 1057 const struct gfx_firmware_header_v1_0 *header = NULL; 1058 const struct common_firmware_header *comm_hdr = NULL; 1059 uint8_t *src_addr = NULL; 1060 uint8_t *dst_addr = NULL; 1061 1062 if (!ucode->fw) 1063 return 0; 1064 1065 comm_hdr = (const struct common_firmware_header *)ucode->fw->data; 1066 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 1067 dst_addr = ucode->kaddr + 1068 ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes), 1069 PAGE_SIZE); 1070 src_addr = (uint8_t *)ucode->fw->data + 1071 le32_to_cpu(comm_hdr->ucode_array_offset_bytes) + 1072 (le32_to_cpu(header->jt_offset) * 4); 1073 memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4); 1074 1075 return 0; 1076 } 1077 1078 int amdgpu_ucode_create_bo(struct amdgpu_device *adev) 1079 { 1080 if ((adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) && 1081 (adev->firmware.load_type != AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)) { 1082 amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE, 1083 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf) ? 1084 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 1085 &adev->firmware.fw_buf, 1086 &adev->firmware.fw_buf_mc, 1087 &adev->firmware.fw_buf_ptr); 1088 if (!adev->firmware.fw_buf) { 1089 dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n"); 1090 return -ENOMEM; 1091 } else if (amdgpu_sriov_vf(adev)) { 1092 memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size); 1093 } 1094 } 1095 return 0; 1096 } 1097 1098 void amdgpu_ucode_free_bo(struct amdgpu_device *adev) 1099 { 1100 amdgpu_bo_free_kernel(&adev->firmware.fw_buf, 1101 &adev->firmware.fw_buf_mc, 1102 &adev->firmware.fw_buf_ptr); 1103 } 1104 1105 int amdgpu_ucode_init_bo(struct amdgpu_device *adev) 1106 { 1107 uint64_t fw_offset = 0; 1108 int i; 1109 struct amdgpu_firmware_info *ucode = NULL; 1110 1111 /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */ 1112 if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend)) 1113 return 0; 1114 /* 1115 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE 1116 * ucode info here 1117 */ 1118 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1119 if (amdgpu_sriov_vf(adev)) 1120 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3; 1121 else 1122 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4; 1123 } else { 1124 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM; 1125 } 1126 1127 for (i = 0; i < adev->firmware.max_ucodes; i++) { 1128 ucode = &adev->firmware.ucode[i]; 1129 if (ucode->fw) { 1130 amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset, 1131 adev->firmware.fw_buf_ptr + fw_offset); 1132 if (i == AMDGPU_UCODE_ID_CP_MEC1 && 1133 adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1134 const struct gfx_firmware_header_v1_0 *cp_hdr; 1135 1136 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 1137 amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset, 1138 adev->firmware.fw_buf_ptr + fw_offset); 1139 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE); 1140 } 1141 fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE); 1142 } 1143 } 1144 return 0; 1145 } 1146 1147 static const char *amdgpu_ucode_legacy_naming(struct amdgpu_device *adev, int block_type) 1148 { 1149 if (block_type == MP0_HWIP) { 1150 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 1151 case IP_VERSION(9, 0, 0): 1152 switch (adev->asic_type) { 1153 case CHIP_VEGA10: 1154 return "vega10"; 1155 case CHIP_VEGA12: 1156 return "vega12"; 1157 default: 1158 return NULL; 1159 } 1160 case IP_VERSION(10, 0, 0): 1161 case IP_VERSION(10, 0, 1): 1162 if (adev->asic_type == CHIP_RAVEN) { 1163 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1164 return "raven2"; 1165 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1166 return "picasso"; 1167 return "raven"; 1168 } 1169 break; 1170 case IP_VERSION(11, 0, 0): 1171 return "navi10"; 1172 case IP_VERSION(11, 0, 2): 1173 return "vega20"; 1174 case IP_VERSION(11, 0, 3): 1175 return "renoir"; 1176 case IP_VERSION(11, 0, 4): 1177 return "arcturus"; 1178 case IP_VERSION(11, 0, 5): 1179 return "navi14"; 1180 case IP_VERSION(11, 0, 7): 1181 return "sienna_cichlid"; 1182 case IP_VERSION(11, 0, 9): 1183 return "navi12"; 1184 case IP_VERSION(11, 0, 11): 1185 return "navy_flounder"; 1186 case IP_VERSION(11, 0, 12): 1187 return "dimgrey_cavefish"; 1188 case IP_VERSION(11, 0, 13): 1189 return "beige_goby"; 1190 case IP_VERSION(11, 5, 0): 1191 return "vangogh"; 1192 case IP_VERSION(12, 0, 1): 1193 return "green_sardine"; 1194 case IP_VERSION(13, 0, 2): 1195 return "aldebaran"; 1196 case IP_VERSION(13, 0, 1): 1197 case IP_VERSION(13, 0, 3): 1198 return "yellow_carp"; 1199 } 1200 } else if (block_type == MP1_HWIP) { 1201 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1202 case IP_VERSION(9, 0, 0): 1203 case IP_VERSION(10, 0, 0): 1204 case IP_VERSION(10, 0, 1): 1205 case IP_VERSION(11, 0, 2): 1206 if (adev->asic_type == CHIP_ARCTURUS) 1207 return "arcturus_smc"; 1208 return NULL; 1209 case IP_VERSION(11, 0, 0): 1210 return "navi10_smc"; 1211 case IP_VERSION(11, 0, 5): 1212 return "navi14_smc"; 1213 case IP_VERSION(11, 0, 9): 1214 return "navi12_smc"; 1215 case IP_VERSION(11, 0, 7): 1216 return "sienna_cichlid_smc"; 1217 case IP_VERSION(11, 0, 11): 1218 return "navy_flounder_smc"; 1219 case IP_VERSION(11, 0, 12): 1220 return "dimgrey_cavefish_smc"; 1221 case IP_VERSION(11, 0, 13): 1222 return "beige_goby_smc"; 1223 case IP_VERSION(13, 0, 2): 1224 return "aldebaran_smc"; 1225 } 1226 } else if (block_type == SDMA0_HWIP) { 1227 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1228 case IP_VERSION(4, 0, 0): 1229 return "vega10_sdma"; 1230 case IP_VERSION(4, 0, 1): 1231 return "vega12_sdma"; 1232 case IP_VERSION(4, 1, 0): 1233 case IP_VERSION(4, 1, 1): 1234 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1235 return "raven2_sdma"; 1236 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1237 return "picasso_sdma"; 1238 return "raven_sdma"; 1239 case IP_VERSION(4, 1, 2): 1240 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1241 return "renoir_sdma"; 1242 return "green_sardine_sdma"; 1243 case IP_VERSION(4, 2, 0): 1244 return "vega20_sdma"; 1245 case IP_VERSION(4, 2, 2): 1246 return "arcturus_sdma"; 1247 case IP_VERSION(4, 4, 0): 1248 return "aldebaran_sdma"; 1249 case IP_VERSION(5, 0, 0): 1250 return "navi10_sdma"; 1251 case IP_VERSION(5, 0, 1): 1252 return "cyan_skillfish2_sdma"; 1253 case IP_VERSION(5, 0, 2): 1254 return "navi14_sdma"; 1255 case IP_VERSION(5, 0, 5): 1256 return "navi12_sdma"; 1257 case IP_VERSION(5, 2, 0): 1258 return "sienna_cichlid_sdma"; 1259 case IP_VERSION(5, 2, 2): 1260 return "navy_flounder_sdma"; 1261 case IP_VERSION(5, 2, 4): 1262 return "dimgrey_cavefish_sdma"; 1263 case IP_VERSION(5, 2, 5): 1264 return "beige_goby_sdma"; 1265 case IP_VERSION(5, 2, 3): 1266 return "yellow_carp_sdma"; 1267 case IP_VERSION(5, 2, 1): 1268 return "vangogh_sdma"; 1269 } 1270 } else if (block_type == UVD_HWIP) { 1271 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 1272 case IP_VERSION(1, 0, 0): 1273 case IP_VERSION(1, 0, 1): 1274 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1275 return "raven2_vcn"; 1276 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1277 return "picasso_vcn"; 1278 return "raven_vcn"; 1279 case IP_VERSION(2, 5, 0): 1280 return "arcturus_vcn"; 1281 case IP_VERSION(2, 2, 0): 1282 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1283 return "renoir_vcn"; 1284 return "green_sardine_vcn"; 1285 case IP_VERSION(2, 6, 0): 1286 return "aldebaran_vcn"; 1287 case IP_VERSION(2, 0, 0): 1288 return "navi10_vcn"; 1289 case IP_VERSION(2, 0, 2): 1290 if (adev->asic_type == CHIP_NAVI12) 1291 return "navi12_vcn"; 1292 return "navi14_vcn"; 1293 case IP_VERSION(3, 0, 0): 1294 case IP_VERSION(3, 0, 64): 1295 case IP_VERSION(3, 0, 192): 1296 if (amdgpu_ip_version(adev, GC_HWIP, 0) == 1297 IP_VERSION(10, 3, 0)) 1298 return "sienna_cichlid_vcn"; 1299 return "navy_flounder_vcn"; 1300 case IP_VERSION(3, 0, 2): 1301 return "vangogh_vcn"; 1302 case IP_VERSION(3, 0, 16): 1303 return "dimgrey_cavefish_vcn"; 1304 case IP_VERSION(3, 0, 33): 1305 return "beige_goby_vcn"; 1306 case IP_VERSION(3, 1, 1): 1307 return "yellow_carp_vcn"; 1308 } 1309 } else if (block_type == GC_HWIP) { 1310 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1311 case IP_VERSION(9, 0, 1): 1312 return "vega10"; 1313 case IP_VERSION(9, 2, 1): 1314 return "vega12"; 1315 case IP_VERSION(9, 4, 0): 1316 return "vega20"; 1317 case IP_VERSION(9, 2, 2): 1318 case IP_VERSION(9, 1, 0): 1319 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1320 return "raven2"; 1321 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1322 return "picasso"; 1323 return "raven"; 1324 case IP_VERSION(9, 4, 1): 1325 return "arcturus"; 1326 case IP_VERSION(9, 3, 0): 1327 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1328 return "renoir"; 1329 return "green_sardine"; 1330 case IP_VERSION(9, 4, 2): 1331 return "aldebaran"; 1332 case IP_VERSION(10, 1, 10): 1333 return "navi10"; 1334 case IP_VERSION(10, 1, 1): 1335 return "navi14"; 1336 case IP_VERSION(10, 1, 2): 1337 return "navi12"; 1338 case IP_VERSION(10, 3, 0): 1339 return "sienna_cichlid"; 1340 case IP_VERSION(10, 3, 2): 1341 return "navy_flounder"; 1342 case IP_VERSION(10, 3, 1): 1343 return "vangogh"; 1344 case IP_VERSION(10, 3, 4): 1345 return "dimgrey_cavefish"; 1346 case IP_VERSION(10, 3, 5): 1347 return "beige_goby"; 1348 case IP_VERSION(10, 3, 3): 1349 return "yellow_carp"; 1350 case IP_VERSION(10, 1, 3): 1351 case IP_VERSION(10, 1, 4): 1352 return "cyan_skillfish2"; 1353 } 1354 } 1355 return NULL; 1356 } 1357 1358 void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len) 1359 { 1360 int maj, min, rev; 1361 char *ip_name; 1362 const char *legacy; 1363 uint32_t version = amdgpu_ip_version(adev, block_type, 0); 1364 1365 legacy = amdgpu_ucode_legacy_naming(adev, block_type); 1366 if (legacy) { 1367 snprintf(ucode_prefix, len, "%s", legacy); 1368 return; 1369 } 1370 1371 switch (block_type) { 1372 case GC_HWIP: 1373 ip_name = "gc"; 1374 break; 1375 case SDMA0_HWIP: 1376 ip_name = "sdma"; 1377 break; 1378 case MP0_HWIP: 1379 ip_name = "psp"; 1380 break; 1381 case MP1_HWIP: 1382 ip_name = "smu"; 1383 break; 1384 case UVD_HWIP: 1385 ip_name = "vcn"; 1386 break; 1387 case VPE_HWIP: 1388 ip_name = "vpe"; 1389 break; 1390 default: 1391 BUG(); 1392 } 1393 1394 maj = IP_VERSION_MAJ(version); 1395 min = IP_VERSION_MIN(version); 1396 rev = IP_VERSION_REV(version); 1397 1398 snprintf(ucode_prefix, len, "%s_%d_%d_%d", ip_name, maj, min, rev); 1399 } 1400 1401 /* 1402 * amdgpu_ucode_request - Fetch and validate amdgpu microcode 1403 * 1404 * @adev: amdgpu device 1405 * @fw: pointer to load firmware to 1406 * @fw_name: firmware to load 1407 * 1408 * This is a helper that will use request_firmware and amdgpu_ucode_validate 1409 * to load and run basic validation on firmware. If the load fails, remap 1410 * the error code to -ENODEV, so that early_init functions will fail to load. 1411 */ 1412 int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw, 1413 const char *fw_name) 1414 { 1415 int err = request_firmware(fw, fw_name, adev->dev); 1416 1417 if (err) 1418 return -ENODEV; 1419 1420 err = amdgpu_ucode_validate(*fw); 1421 if (err) { 1422 dev_dbg(adev->dev, "\"%s\" failed to validate\n", fw_name); 1423 release_firmware(*fw); 1424 *fw = NULL; 1425 } 1426 1427 return err; 1428 } 1429 1430 /* 1431 * amdgpu_ucode_release - Release firmware microcode 1432 * 1433 * @fw: pointer to firmware to release 1434 */ 1435 void amdgpu_ucode_release(const struct firmware **fw) 1436 { 1437 release_firmware(*fw); 1438 *fw = NULL; 1439 } 1440