1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_SDMA_H__ 25 #define __AMDGPU_SDMA_H__ 26 #include "amdgpu_ras.h" 27 28 /* max number of IP instances */ 29 #define AMDGPU_MAX_SDMA_INSTANCES 16 30 31 enum amdgpu_sdma_irq { 32 AMDGPU_SDMA_IRQ_INSTANCE0 = 0, 33 AMDGPU_SDMA_IRQ_INSTANCE1, 34 AMDGPU_SDMA_IRQ_INSTANCE2, 35 AMDGPU_SDMA_IRQ_INSTANCE3, 36 AMDGPU_SDMA_IRQ_INSTANCE4, 37 AMDGPU_SDMA_IRQ_INSTANCE5, 38 AMDGPU_SDMA_IRQ_INSTANCE6, 39 AMDGPU_SDMA_IRQ_INSTANCE7, 40 AMDGPU_SDMA_IRQ_INSTANCE8, 41 AMDGPU_SDMA_IRQ_INSTANCE9, 42 AMDGPU_SDMA_IRQ_INSTANCE10, 43 AMDGPU_SDMA_IRQ_INSTANCE11, 44 AMDGPU_SDMA_IRQ_INSTANCE12, 45 AMDGPU_SDMA_IRQ_INSTANCE13, 46 AMDGPU_SDMA_IRQ_INSTANCE14, 47 AMDGPU_SDMA_IRQ_INSTANCE15, 48 AMDGPU_SDMA_IRQ_LAST 49 }; 50 51 #define NUM_SDMA(x) hweight32(x) 52 53 struct amdgpu_sdma_instance { 54 /* SDMA firmware */ 55 const struct firmware *fw; 56 uint32_t fw_version; 57 uint32_t feature_version; 58 59 struct amdgpu_ring ring; 60 struct amdgpu_ring page; 61 bool burst_nop; 62 uint32_t aid_id; 63 }; 64 65 struct amdgpu_sdma_ras { 66 struct amdgpu_ras_block_object ras_block; 67 }; 68 69 struct amdgpu_sdma { 70 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 71 struct amdgpu_irq_src trap_irq; 72 struct amdgpu_irq_src illegal_inst_irq; 73 struct amdgpu_irq_src ecc_irq; 74 struct amdgpu_irq_src vm_hole_irq; 75 struct amdgpu_irq_src doorbell_invalid_irq; 76 struct amdgpu_irq_src pool_timeout_irq; 77 struct amdgpu_irq_src srbm_write_irq; 78 79 int num_instances; 80 uint32_t sdma_mask; 81 int num_inst_per_aid; 82 uint32_t srbm_soft_reset; 83 bool has_page_queue; 84 struct ras_common_if *ras_if; 85 struct amdgpu_sdma_ras *ras; 86 }; 87 88 /* 89 * Provided by hw blocks that can move/clear data. e.g., gfx or sdma 90 * But currently, we use sdma to move data. 91 */ 92 struct amdgpu_buffer_funcs { 93 /* maximum bytes in a single operation */ 94 uint32_t copy_max_bytes; 95 96 /* number of dw to reserve per operation */ 97 unsigned copy_num_dw; 98 99 /* used for buffer migration */ 100 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 101 /* src addr in bytes */ 102 uint64_t src_offset, 103 /* dst addr in bytes */ 104 uint64_t dst_offset, 105 /* number of byte to transfer */ 106 uint32_t byte_count, 107 bool tmz); 108 109 /* maximum bytes in a single operation */ 110 uint32_t fill_max_bytes; 111 112 /* number of dw to reserve per operation */ 113 unsigned fill_num_dw; 114 115 /* used for buffer clearing */ 116 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 117 /* value to write to memory */ 118 uint32_t src_data, 119 /* dst addr in bytes */ 120 uint64_t dst_offset, 121 /* number of byte to fill */ 122 uint32_t byte_count); 123 }; 124 125 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b), (t)) 126 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 127 128 struct amdgpu_sdma_instance * 129 amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring); 130 int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index); 131 uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid); 132 int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev, 133 struct ras_common_if *ras_block); 134 int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev, 135 void *err_data, 136 struct amdgpu_iv_entry *entry); 137 int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev, 138 struct amdgpu_irq_src *source, 139 struct amdgpu_iv_entry *entry); 140 int amdgpu_sdma_init_microcode(struct amdgpu_device *adev, u32 instance, 141 bool duplicate); 142 void amdgpu_sdma_destroy_inst_ctx(struct amdgpu_device *adev, 143 bool duplicate); 144 void amdgpu_sdma_unset_buffer_funcs_helper(struct amdgpu_device *adev); 145 int amdgpu_sdma_ras_sw_init(struct amdgpu_device *adev); 146 147 #endif 148