1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_SDMA_H__ 25 #define __AMDGPU_SDMA_H__ 26 #include "amdgpu_ras.h" 27 28 /* max number of IP instances */ 29 #define AMDGPU_MAX_SDMA_INSTANCES 16 30 31 enum amdgpu_sdma_irq { 32 AMDGPU_SDMA_IRQ_INSTANCE0 = 0, 33 AMDGPU_SDMA_IRQ_INSTANCE1, 34 AMDGPU_SDMA_IRQ_INSTANCE2, 35 AMDGPU_SDMA_IRQ_INSTANCE3, 36 AMDGPU_SDMA_IRQ_INSTANCE4, 37 AMDGPU_SDMA_IRQ_INSTANCE5, 38 AMDGPU_SDMA_IRQ_INSTANCE6, 39 AMDGPU_SDMA_IRQ_INSTANCE7, 40 AMDGPU_SDMA_IRQ_INSTANCE8, 41 AMDGPU_SDMA_IRQ_INSTANCE9, 42 AMDGPU_SDMA_IRQ_INSTANCE10, 43 AMDGPU_SDMA_IRQ_INSTANCE11, 44 AMDGPU_SDMA_IRQ_INSTANCE12, 45 AMDGPU_SDMA_IRQ_INSTANCE13, 46 AMDGPU_SDMA_IRQ_INSTANCE14, 47 AMDGPU_SDMA_IRQ_INSTANCE15, 48 AMDGPU_SDMA_IRQ_LAST 49 }; 50 51 #define NUM_SDMA(x) hweight32(x) 52 53 struct amdgpu_sdma_instance { 54 /* SDMA firmware */ 55 const struct firmware *fw; 56 uint32_t fw_version; 57 uint32_t feature_version; 58 59 struct amdgpu_ring ring; 60 struct amdgpu_ring page; 61 bool burst_nop; 62 uint32_t aid_id; 63 64 struct amdgpu_bo *sdma_fw_obj; 65 uint64_t sdma_fw_gpu_addr; 66 uint32_t *sdma_fw_ptr; 67 }; 68 69 enum amdgpu_sdma_ras_memory_id { 70 AMDGPU_SDMA_MBANK_DATA_BUF0 = 1, 71 AMDGPU_SDMA_MBANK_DATA_BUF1 = 2, 72 AMDGPU_SDMA_MBANK_DATA_BUF2 = 3, 73 AMDGPU_SDMA_MBANK_DATA_BUF3 = 4, 74 AMDGPU_SDMA_MBANK_DATA_BUF4 = 5, 75 AMDGPU_SDMA_MBANK_DATA_BUF5 = 6, 76 AMDGPU_SDMA_MBANK_DATA_BUF6 = 7, 77 AMDGPU_SDMA_MBANK_DATA_BUF7 = 8, 78 AMDGPU_SDMA_MBANK_DATA_BUF8 = 9, 79 AMDGPU_SDMA_MBANK_DATA_BUF9 = 10, 80 AMDGPU_SDMA_MBANK_DATA_BUF10 = 11, 81 AMDGPU_SDMA_MBANK_DATA_BUF11 = 12, 82 AMDGPU_SDMA_MBANK_DATA_BUF12 = 13, 83 AMDGPU_SDMA_MBANK_DATA_BUF13 = 14, 84 AMDGPU_SDMA_MBANK_DATA_BUF14 = 15, 85 AMDGPU_SDMA_MBANK_DATA_BUF15 = 16, 86 AMDGPU_SDMA_UCODE_BUF = 17, 87 AMDGPU_SDMA_RB_CMD_BUF = 18, 88 AMDGPU_SDMA_IB_CMD_BUF = 19, 89 AMDGPU_SDMA_UTCL1_RD_FIFO = 20, 90 AMDGPU_SDMA_UTCL1_RDBST_FIFO = 21, 91 AMDGPU_SDMA_UTCL1_WR_FIFO = 22, 92 AMDGPU_SDMA_DATA_LUT_FIFO = 23, 93 AMDGPU_SDMA_SPLIT_DAT_BUF = 24, 94 AMDGPU_SDMA_MEMORY_BLOCK_LAST, 95 }; 96 97 struct amdgpu_sdma_ras { 98 struct amdgpu_ras_block_object ras_block; 99 }; 100 101 struct sdma_on_reset_funcs { 102 int (*pre_reset)(struct amdgpu_device *adev, uint32_t instance_id); 103 int (*post_reset)(struct amdgpu_device *adev, uint32_t instance_id); 104 /* Linked list node to store this structure in a list; */ 105 struct list_head list; 106 }; 107 108 struct amdgpu_sdma { 109 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 110 struct amdgpu_irq_src trap_irq; 111 struct amdgpu_irq_src illegal_inst_irq; 112 struct amdgpu_irq_src ecc_irq; 113 struct amdgpu_irq_src vm_hole_irq; 114 struct amdgpu_irq_src doorbell_invalid_irq; 115 struct amdgpu_irq_src pool_timeout_irq; 116 struct amdgpu_irq_src srbm_write_irq; 117 struct amdgpu_irq_src ctxt_empty_irq; 118 119 int num_instances; 120 uint32_t sdma_mask; 121 int num_inst_per_aid; 122 uint32_t srbm_soft_reset; 123 bool has_page_queue; 124 struct ras_common_if *ras_if; 125 struct amdgpu_sdma_ras *ras; 126 uint32_t *ip_dump; 127 uint32_t supported_reset; 128 struct list_head reset_callback_list; 129 }; 130 131 /* 132 * Provided by hw blocks that can move/clear data. e.g., gfx or sdma 133 * But currently, we use sdma to move data. 134 */ 135 struct amdgpu_buffer_funcs { 136 /* maximum bytes in a single operation */ 137 uint32_t copy_max_bytes; 138 139 /* number of dw to reserve per operation */ 140 unsigned copy_num_dw; 141 142 /* used for buffer migration */ 143 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 144 /* src addr in bytes */ 145 uint64_t src_offset, 146 /* dst addr in bytes */ 147 uint64_t dst_offset, 148 /* number of byte to transfer */ 149 uint32_t byte_count, 150 uint32_t copy_flags); 151 152 /* maximum bytes in a single operation */ 153 uint32_t fill_max_bytes; 154 155 /* number of dw to reserve per operation */ 156 unsigned fill_num_dw; 157 158 /* used for buffer clearing */ 159 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 160 /* value to write to memory */ 161 uint32_t src_data, 162 /* dst addr in bytes */ 163 uint64_t dst_offset, 164 /* number of byte to fill */ 165 uint32_t byte_count); 166 }; 167 168 void amdgpu_sdma_register_on_reset_callbacks(struct amdgpu_device *adev, struct sdma_on_reset_funcs *funcs); 169 int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id); 170 171 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b), (t)) 172 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 173 174 struct amdgpu_sdma_instance * 175 amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring); 176 int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index); 177 uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid); 178 int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev, 179 struct ras_common_if *ras_block); 180 int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev, 181 void *err_data, 182 struct amdgpu_iv_entry *entry); 183 int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev, 184 struct amdgpu_irq_src *source, 185 struct amdgpu_iv_entry *entry); 186 int amdgpu_sdma_init_microcode(struct amdgpu_device *adev, u32 instance, 187 bool duplicate); 188 void amdgpu_sdma_destroy_inst_ctx(struct amdgpu_device *adev, 189 bool duplicate); 190 int amdgpu_sdma_ras_sw_init(struct amdgpu_device *adev); 191 void amdgpu_debugfs_sdma_sched_mask_init(struct amdgpu_device *adev); 192 int amdgpu_sdma_sysfs_reset_mask_init(struct amdgpu_device *adev); 193 void amdgpu_sdma_sysfs_reset_mask_fini(struct amdgpu_device *adev); 194 #endif 195