152c6a62cSAndres Rodriguez /*
252c6a62cSAndres Rodriguez  * Copyright 2017 Valve Corporation
352c6a62cSAndres Rodriguez  *
452c6a62cSAndres Rodriguez  * Permission is hereby granted, free of charge, to any person obtaining a
552c6a62cSAndres Rodriguez  * copy of this software and associated documentation files (the "Software"),
652c6a62cSAndres Rodriguez  * to deal in the Software without restriction, including without limitation
752c6a62cSAndres Rodriguez  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
852c6a62cSAndres Rodriguez  * and/or sell copies of the Software, and to permit persons to whom the
952c6a62cSAndres Rodriguez  * Software is furnished to do so, subject to the following conditions:
1052c6a62cSAndres Rodriguez  *
1152c6a62cSAndres Rodriguez  * The above copyright notice and this permission notice shall be included in
1252c6a62cSAndres Rodriguez  * all copies or substantial portions of the Software.
1352c6a62cSAndres Rodriguez  *
1452c6a62cSAndres Rodriguez  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1552c6a62cSAndres Rodriguez  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1652c6a62cSAndres Rodriguez  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
1752c6a62cSAndres Rodriguez  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
1852c6a62cSAndres Rodriguez  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
1952c6a62cSAndres Rodriguez  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2052c6a62cSAndres Rodriguez  * OTHER DEALINGS IN THE SOFTWARE.
2152c6a62cSAndres Rodriguez  *
2252c6a62cSAndres Rodriguez  * Authors: Andres Rodriguez <[email protected]>
2352c6a62cSAndres Rodriguez  */
2452c6a62cSAndres Rodriguez 
25f867723bSSam Ravnborg #include <linux/file.h>
2652c6a62cSAndres Rodriguez #include <linux/pid.h>
27f867723bSSam Ravnborg 
2852c6a62cSAndres Rodriguez #include <drm/amdgpu_drm.h>
29f867723bSSam Ravnborg 
3052c6a62cSAndres Rodriguez #include "amdgpu.h"
31793c8571SLee Jones #include "amdgpu_sched.h"
3252c6a62cSAndres Rodriguez #include "amdgpu_vm.h"
3352c6a62cSAndres Rodriguez 
amdgpu_sched_process_priority_override(struct amdgpu_device * adev,int fd,int32_t priority)3452c6a62cSAndres Rodriguez static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev,
3552c6a62cSAndres Rodriguez 						  int fd,
3684d588c3SNirmoy Das 						  int32_t priority)
3752c6a62cSAndres Rodriguez {
38*6348be02SAl Viro 	CLASS(fd, f)(fd);
3952c6a62cSAndres Rodriguez 	struct amdgpu_fpriv *fpriv;
402397e3d8SChia-I Wu 	struct amdgpu_ctx_mgr *mgr;
4152c6a62cSAndres Rodriguez 	struct amdgpu_ctx *ctx;
4252c6a62cSAndres Rodriguez 	uint32_t id;
43021830d2SBas Nieuwenhuizen 	int r;
4452c6a62cSAndres Rodriguez 
45*6348be02SAl Viro 	if (fd_empty(f))
4652c6a62cSAndres Rodriguez 		return -EINVAL;
4752c6a62cSAndres Rodriguez 
481da91ea8SAl Viro 	r = amdgpu_file_to_fpriv(fd_file(f), &fpriv);
49*6348be02SAl Viro 	if (r)
50021830d2SBas Nieuwenhuizen 		return r;
51021830d2SBas Nieuwenhuizen 
522397e3d8SChia-I Wu 	mgr = &fpriv->ctx_mgr;
532397e3d8SChia-I Wu 	mutex_lock(&mgr->lock);
542397e3d8SChia-I Wu 	idr_for_each_entry(&mgr->ctx_handles, ctx, id)
5552c6a62cSAndres Rodriguez 		amdgpu_ctx_priority_override(ctx, priority);
562397e3d8SChia-I Wu 	mutex_unlock(&mgr->lock);
5752c6a62cSAndres Rodriguez 
5852c6a62cSAndres Rodriguez 	return 0;
5952c6a62cSAndres Rodriguez }
6052c6a62cSAndres Rodriguez 
amdgpu_sched_context_priority_override(struct amdgpu_device * adev,int fd,unsigned ctx_id,int32_t priority)61b5bb37edSBas Nieuwenhuizen static int amdgpu_sched_context_priority_override(struct amdgpu_device *adev,
62b5bb37edSBas Nieuwenhuizen 						  int fd,
63b5bb37edSBas Nieuwenhuizen 						  unsigned ctx_id,
6484d588c3SNirmoy Das 						  int32_t priority)
65b5bb37edSBas Nieuwenhuizen {
66*6348be02SAl Viro 	CLASS(fd, f)(fd);
67b5bb37edSBas Nieuwenhuizen 	struct amdgpu_fpriv *fpriv;
68b5bb37edSBas Nieuwenhuizen 	struct amdgpu_ctx *ctx;
69b5bb37edSBas Nieuwenhuizen 	int r;
70b5bb37edSBas Nieuwenhuizen 
71*6348be02SAl Viro 	if (fd_empty(f))
72b5bb37edSBas Nieuwenhuizen 		return -EINVAL;
73b5bb37edSBas Nieuwenhuizen 
741da91ea8SAl Viro 	r = amdgpu_file_to_fpriv(fd_file(f), &fpriv);
75*6348be02SAl Viro 	if (r)
76b5bb37edSBas Nieuwenhuizen 		return r;
77b5bb37edSBas Nieuwenhuizen 
78b5bb37edSBas Nieuwenhuizen 	ctx = amdgpu_ctx_get(fpriv, ctx_id);
79b5bb37edSBas Nieuwenhuizen 
80*6348be02SAl Viro 	if (!ctx)
81b5bb37edSBas Nieuwenhuizen 		return -EINVAL;
82b5bb37edSBas Nieuwenhuizen 
83b5bb37edSBas Nieuwenhuizen 	amdgpu_ctx_priority_override(ctx, priority);
84b5bb37edSBas Nieuwenhuizen 	amdgpu_ctx_put(ctx);
85b5bb37edSBas Nieuwenhuizen 	return 0;
86b5bb37edSBas Nieuwenhuizen }
87b5bb37edSBas Nieuwenhuizen 
amdgpu_sched_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)8852c6a62cSAndres Rodriguez int amdgpu_sched_ioctl(struct drm_device *dev, void *data,
8952c6a62cSAndres Rodriguez 		       struct drm_file *filp)
9052c6a62cSAndres Rodriguez {
9152c6a62cSAndres Rodriguez 	union drm_amdgpu_sched *args = data;
921348969aSLuben Tuikov 	struct amdgpu_device *adev = drm_to_adev(dev);
9352c6a62cSAndres Rodriguez 	int r;
9452c6a62cSAndres Rodriguez 
959af5e21dSLuben Tuikov 	/* First check the op, then the op's argument.
969af5e21dSLuben Tuikov 	 */
979af5e21dSLuben Tuikov 	switch (args->in.op) {
989af5e21dSLuben Tuikov 	case AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE:
999af5e21dSLuben Tuikov 	case AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE:
1009af5e21dSLuben Tuikov 		break;
1019af5e21dSLuben Tuikov 	default:
1029af5e21dSLuben Tuikov 		DRM_ERROR("Invalid sched op specified: %d\n", args->in.op);
10352c6a62cSAndres Rodriguez 		return -EINVAL;
1049af5e21dSLuben Tuikov 	}
1059af5e21dSLuben Tuikov 
10684d588c3SNirmoy Das 	if (!amdgpu_ctx_priority_is_valid(args->in.priority)) {
10784d588c3SNirmoy Das 		WARN(1, "Invalid context priority %d\n", args->in.priority);
10884d588c3SNirmoy Das 		return -EINVAL;
10984d588c3SNirmoy Das 	}
11052c6a62cSAndres Rodriguez 
11152c6a62cSAndres Rodriguez 	switch (args->in.op) {
11252c6a62cSAndres Rodriguez 	case AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE:
11352c6a62cSAndres Rodriguez 		r = amdgpu_sched_process_priority_override(adev,
11452c6a62cSAndres Rodriguez 							   args->in.fd,
11584d588c3SNirmoy Das 							   args->in.priority);
11652c6a62cSAndres Rodriguez 		break;
117b5bb37edSBas Nieuwenhuizen 	case AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE:
118b5bb37edSBas Nieuwenhuizen 		r = amdgpu_sched_context_priority_override(adev,
119b5bb37edSBas Nieuwenhuizen 							   args->in.fd,
120b5bb37edSBas Nieuwenhuizen 							   args->in.ctx_id,
12184d588c3SNirmoy Das 							   args->in.priority);
122b5bb37edSBas Nieuwenhuizen 		break;
12352c6a62cSAndres Rodriguez 	default:
1249af5e21dSLuben Tuikov 		/* Impossible.
1259af5e21dSLuben Tuikov 		 */
12652c6a62cSAndres Rodriguez 		r = -EINVAL;
12752c6a62cSAndres Rodriguez 		break;
12852c6a62cSAndres Rodriguez 	}
12952c6a62cSAndres Rodriguez 
13052c6a62cSAndres Rodriguez 	return r;
13152c6a62cSAndres Rodriguez }
132