1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  *          Christian König
28  */
29 #include <linux/seq_file.h>
30 #include <linux/slab.h>
31 #include <linux/debugfs.h>
32 #include <drm/drmP.h>
33 #include <drm/amdgpu_drm.h>
34 #include "amdgpu.h"
35 #include "atom.h"
36 
37 /*
38  * Rings
39  * Most engines on the GPU are fed via ring buffers.  Ring
40  * buffers are areas of GPU accessible memory that the host
41  * writes commands into and the GPU reads commands out of.
42  * There is a rptr (read pointer) that determines where the
43  * GPU is currently reading, and a wptr (write pointer)
44  * which determines where the host has written.  When the
45  * pointers are equal, the ring is idle.  When the host
46  * writes commands to the ring buffer, it increments the
47  * wptr.  The GPU then starts fetching commands and executes
48  * them until the pointers are equal again.
49  */
50 static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
51 				    struct amdgpu_ring *ring);
52 static void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring);
53 
54 /**
55  * amdgpu_ring_alloc - allocate space on the ring buffer
56  *
57  * @adev: amdgpu_device pointer
58  * @ring: amdgpu_ring structure holding ring information
59  * @ndw: number of dwords to allocate in the ring buffer
60  *
61  * Allocate @ndw dwords in the ring buffer (all asics).
62  * Returns 0 on success, error on failure.
63  */
64 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
65 {
66 	/* Align requested size with padding so unlock_commit can
67 	 * pad safely */
68 	ndw = (ndw + ring->align_mask) & ~ring->align_mask;
69 
70 	/* Make sure we aren't trying to allocate more space
71 	 * than the maximum for one submission
72 	 */
73 	if (WARN_ON_ONCE(ndw > ring->max_dw))
74 		return -ENOMEM;
75 
76 	ring->count_dw = ndw;
77 	ring->wptr_old = ring->wptr;
78 	return 0;
79 }
80 
81 /** amdgpu_ring_insert_nop - insert NOP packets
82  *
83  * @ring: amdgpu_ring structure holding ring information
84  * @count: the number of NOP packets to insert
85  *
86  * This is the generic insert_nop function for rings except SDMA
87  */
88 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
89 {
90 	int i;
91 
92 	for (i = 0; i < count; i++)
93 		amdgpu_ring_write(ring, ring->nop);
94 }
95 
96 /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets
97  *
98  * @ring: amdgpu_ring structure holding ring information
99  * @ib: IB to add NOP packets to
100  *
101  * This is the generic pad_ib function for rings except SDMA
102  */
103 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
104 {
105 	while (ib->length_dw & ring->align_mask)
106 		ib->ptr[ib->length_dw++] = ring->nop;
107 }
108 
109 /**
110  * amdgpu_ring_commit - tell the GPU to execute the new
111  * commands on the ring buffer
112  *
113  * @adev: amdgpu_device pointer
114  * @ring: amdgpu_ring structure holding ring information
115  *
116  * Update the wptr (write pointer) to tell the GPU to
117  * execute new commands on the ring buffer (all asics).
118  */
119 void amdgpu_ring_commit(struct amdgpu_ring *ring)
120 {
121 	uint32_t count;
122 
123 	/* We pad to match fetch size */
124 	count = ring->align_mask + 1 - (ring->wptr & ring->align_mask);
125 	count %= ring->align_mask + 1;
126 	ring->funcs->insert_nop(ring, count);
127 
128 	mb();
129 	amdgpu_ring_set_wptr(ring);
130 }
131 
132 /**
133  * amdgpu_ring_undo - reset the wptr
134  *
135  * @ring: amdgpu_ring structure holding ring information
136  *
137  * Reset the driver's copy of the wptr (all asics).
138  */
139 void amdgpu_ring_undo(struct amdgpu_ring *ring)
140 {
141 	ring->wptr = ring->wptr_old;
142 }
143 
144 /**
145  * amdgpu_ring_init - init driver ring struct.
146  *
147  * @adev: amdgpu_device pointer
148  * @ring: amdgpu_ring structure holding ring information
149  * @max_ndw: maximum number of dw for ring alloc
150  * @nop: nop packet for this ring
151  *
152  * Initialize the driver information for the selected ring (all asics).
153  * Returns 0 on success, error on failure.
154  */
155 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
156 		     unsigned max_dw, u32 nop, u32 align_mask,
157 		     struct amdgpu_irq_src *irq_src, unsigned irq_type,
158 		     enum amdgpu_ring_type ring_type)
159 {
160 	int r;
161 
162 	if (ring->adev == NULL) {
163 		if (adev->num_rings >= AMDGPU_MAX_RINGS)
164 			return -EINVAL;
165 
166 		ring->adev = adev;
167 		ring->idx = adev->num_rings++;
168 		adev->rings[ring->idx] = ring;
169 		r = amdgpu_fence_driver_init_ring(ring,
170 			amdgpu_sched_hw_submission);
171 		if (r)
172 			return r;
173 	}
174 
175 	r = amdgpu_wb_get(adev, &ring->rptr_offs);
176 	if (r) {
177 		dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
178 		return r;
179 	}
180 
181 	r = amdgpu_wb_get(adev, &ring->wptr_offs);
182 	if (r) {
183 		dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
184 		return r;
185 	}
186 
187 	r = amdgpu_wb_get(adev, &ring->fence_offs);
188 	if (r) {
189 		dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
190 		return r;
191 	}
192 
193 	r = amdgpu_wb_get(adev, &ring->cond_exe_offs);
194 	if (r) {
195 		dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
196 		return r;
197 	}
198 	ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4);
199 	ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs];
200 
201 	spin_lock_init(&ring->fence_lock);
202 	r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
203 	if (r) {
204 		dev_err(adev->dev, "failed initializing fences (%d).\n", r);
205 		return r;
206 	}
207 
208 	ring->ring_size = roundup_pow_of_two(max_dw * 4 *
209 					     amdgpu_sched_hw_submission);
210 	ring->align_mask = align_mask;
211 	ring->nop = nop;
212 	ring->type = ring_type;
213 
214 	/* Allocate ring buffer */
215 	if (ring->ring_obj == NULL) {
216 		r = amdgpu_bo_create(adev, ring->ring_size, PAGE_SIZE, true,
217 				     AMDGPU_GEM_DOMAIN_GTT, 0,
218 				     NULL, NULL, &ring->ring_obj);
219 		if (r) {
220 			dev_err(adev->dev, "(%d) ring create failed\n", r);
221 			return r;
222 		}
223 		r = amdgpu_bo_reserve(ring->ring_obj, false);
224 		if (unlikely(r != 0))
225 			return r;
226 		r = amdgpu_bo_pin(ring->ring_obj, AMDGPU_GEM_DOMAIN_GTT,
227 					&ring->gpu_addr);
228 		if (r) {
229 			amdgpu_bo_unreserve(ring->ring_obj);
230 			dev_err(adev->dev, "(%d) ring pin failed\n", r);
231 			return r;
232 		}
233 		r = amdgpu_bo_kmap(ring->ring_obj,
234 				       (void **)&ring->ring);
235 
236 		memset((void *)ring->ring, 0, ring->ring_size);
237 
238 		amdgpu_bo_unreserve(ring->ring_obj);
239 		if (r) {
240 			dev_err(adev->dev, "(%d) ring map failed\n", r);
241 			return r;
242 		}
243 	}
244 	ring->ptr_mask = (ring->ring_size / 4) - 1;
245 	ring->max_dw = max_dw;
246 
247 	if (amdgpu_debugfs_ring_init(adev, ring)) {
248 		DRM_ERROR("Failed to register debugfs file for rings !\n");
249 	}
250 	return 0;
251 }
252 
253 /**
254  * amdgpu_ring_fini - tear down the driver ring struct.
255  *
256  * @adev: amdgpu_device pointer
257  * @ring: amdgpu_ring structure holding ring information
258  *
259  * Tear down the driver information for the selected ring (all asics).
260  */
261 void amdgpu_ring_fini(struct amdgpu_ring *ring)
262 {
263 	int r;
264 	struct amdgpu_bo *ring_obj;
265 
266 	ring_obj = ring->ring_obj;
267 	ring->ready = false;
268 	ring->ring = NULL;
269 	ring->ring_obj = NULL;
270 
271 	amdgpu_wb_free(ring->adev, ring->cond_exe_offs);
272 	amdgpu_wb_free(ring->adev, ring->fence_offs);
273 	amdgpu_wb_free(ring->adev, ring->rptr_offs);
274 	amdgpu_wb_free(ring->adev, ring->wptr_offs);
275 
276 	if (ring_obj) {
277 		r = amdgpu_bo_reserve(ring_obj, false);
278 		if (likely(r == 0)) {
279 			amdgpu_bo_kunmap(ring_obj);
280 			amdgpu_bo_unpin(ring_obj);
281 			amdgpu_bo_unreserve(ring_obj);
282 		}
283 		amdgpu_bo_unref(&ring_obj);
284 	}
285 	amdgpu_debugfs_ring_fini(ring);
286 }
287 
288 /*
289  * Debugfs info
290  */
291 #if defined(CONFIG_DEBUG_FS)
292 
293 /* Layout of file is 12 bytes consisting of
294  * - rptr
295  * - wptr
296  * - driver's copy of wptr
297  *
298  * followed by n-words of ring data
299  */
300 static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
301 					size_t size, loff_t *pos)
302 {
303 	struct amdgpu_ring *ring = (struct amdgpu_ring*)f->f_inode->i_private;
304 	int r, i;
305 	uint32_t value, result, early[3];
306 
307 	if (*pos & 3 || size & 3)
308 		return -EINVAL;
309 
310 	result = 0;
311 
312 	if (*pos < 12) {
313 		early[0] = amdgpu_ring_get_rptr(ring);
314 		early[1] = amdgpu_ring_get_wptr(ring);
315 		early[2] = ring->wptr;
316 		for (i = *pos / 4; i < 3 && size; i++) {
317 			r = put_user(early[i], (uint32_t *)buf);
318 			if (r)
319 				return r;
320 			buf += 4;
321 			result += 4;
322 			size -= 4;
323 			*pos += 4;
324 		}
325 	}
326 
327 	while (size) {
328 		if (*pos >= (ring->ring_size + 12))
329 			return result;
330 
331 		value = ring->ring[(*pos - 12)/4];
332 		r = put_user(value, (uint32_t*)buf);
333 		if (r)
334 			return r;
335 		buf += 4;
336 		result += 4;
337 		size -= 4;
338 		*pos += 4;
339 	}
340 
341 	return result;
342 }
343 
344 static const struct file_operations amdgpu_debugfs_ring_fops = {
345 	.owner = THIS_MODULE,
346 	.read = amdgpu_debugfs_ring_read,
347 	.llseek = default_llseek
348 };
349 
350 #endif
351 
352 static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
353 				    struct amdgpu_ring *ring)
354 {
355 #if defined(CONFIG_DEBUG_FS)
356 	struct drm_minor *minor = adev->ddev->primary;
357 	struct dentry *ent, *root = minor->debugfs_root;
358 	char name[32];
359 
360 	sprintf(name, "amdgpu_ring_%s", ring->name);
361 
362 	ent = debugfs_create_file(name,
363 				  S_IFREG | S_IRUGO, root,
364 				  ring, &amdgpu_debugfs_ring_fops);
365 	if (IS_ERR(ent))
366 		return PTR_ERR(ent);
367 
368 	i_size_write(ent->d_inode, ring->ring_size + 12);
369 	ring->ent = ent;
370 #endif
371 	return 0;
372 }
373 
374 static void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring)
375 {
376 #if defined(CONFIG_DEBUG_FS)
377 	debugfs_remove(ring->ent);
378 #endif
379 }
380