1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 #ifndef __AMDGPU_PSP_H__ 26 #define __AMDGPU_PSP_H__ 27 28 #include "amdgpu.h" 29 #include "psp_gfx_if.h" 30 #include "ta_xgmi_if.h" 31 #include "ta_ras_if.h" 32 33 #define PSP_FENCE_BUFFER_SIZE 0x1000 34 #define PSP_CMD_BUFFER_SIZE 0x1000 35 #define PSP_XGMI_SHARED_MEM_SIZE 0x4000 36 #define PSP_RAS_SHARED_MEM_SIZE 0x4000 37 #define PSP_1_MEG 0x100000 38 #define PSP_TMR_SIZE 0x400000 39 #define PSP_HDCP_SHARED_MEM_SIZE 0x4000 40 #define PSP_DTM_SHARED_MEM_SIZE 0x4000 41 #define PSP_SHARED_MEM_SIZE 0x4000 42 43 struct psp_context; 44 struct psp_xgmi_node_info; 45 struct psp_xgmi_topology_info; 46 47 enum psp_bootloader_cmd { 48 PSP_BL__LOAD_SYSDRV = 0x10000, 49 PSP_BL__LOAD_SOSDRV = 0x20000, 50 PSP_BL__LOAD_KEY_DATABASE = 0x80000, 51 PSP_BL__DRAM_LONG_TRAIN = 0x100000, 52 PSP_BL__DRAM_SHORT_TRAIN = 0x200000, 53 }; 54 55 enum psp_ring_type 56 { 57 PSP_RING_TYPE__INVALID = 0, 58 /* 59 * These values map to the way the PSP kernel identifies the 60 * rings. 61 */ 62 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ 63 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ 64 }; 65 66 struct psp_ring 67 { 68 enum psp_ring_type ring_type; 69 struct psp_gfx_rb_frame *ring_mem; 70 uint64_t ring_mem_mc_addr; 71 void *ring_mem_handle; 72 uint32_t ring_size; 73 }; 74 75 /* More registers may will be supported */ 76 enum psp_reg_prog_id { 77 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */ 78 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */ 79 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */ 80 PSP_REG_LAST 81 }; 82 83 struct psp_funcs 84 { 85 int (*init_microcode)(struct psp_context *psp); 86 int (*bootloader_load_kdb)(struct psp_context *psp); 87 int (*bootloader_load_sysdrv)(struct psp_context *psp); 88 int (*bootloader_load_sos)(struct psp_context *psp); 89 int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type); 90 int (*ring_create)(struct psp_context *psp, 91 enum psp_ring_type ring_type); 92 int (*ring_stop)(struct psp_context *psp, 93 enum psp_ring_type ring_type); 94 int (*ring_destroy)(struct psp_context *psp, 95 enum psp_ring_type ring_type); 96 bool (*compare_sram_data)(struct psp_context *psp, 97 struct amdgpu_firmware_info *ucode, 98 enum AMDGPU_UCODE_ID ucode_type); 99 bool (*smu_reload_quirk)(struct psp_context *psp); 100 int (*mode1_reset)(struct psp_context *psp); 101 int (*xgmi_get_node_id)(struct psp_context *psp, uint64_t *node_id); 102 int (*xgmi_get_hive_id)(struct psp_context *psp, uint64_t *hive_id); 103 int (*xgmi_get_topology_info)(struct psp_context *psp, int number_devices, 104 struct psp_xgmi_topology_info *topology); 105 int (*xgmi_set_topology_info)(struct psp_context *psp, int number_devices, 106 struct psp_xgmi_topology_info *topology); 107 bool (*support_vmr_ring)(struct psp_context *psp); 108 int (*ras_trigger_error)(struct psp_context *psp, 109 struct ta_ras_trigger_error_input *info); 110 int (*ras_cure_posion)(struct psp_context *psp, uint64_t *mode_ptr); 111 int (*rlc_autoload_start)(struct psp_context *psp); 112 int (*mem_training_init)(struct psp_context *psp); 113 void (*mem_training_fini)(struct psp_context *psp); 114 int (*mem_training)(struct psp_context *psp, uint32_t ops); 115 uint32_t (*ring_get_wptr)(struct psp_context *psp); 116 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value); 117 int (*load_usbc_pd_fw)(struct psp_context *psp, dma_addr_t dma_addr); 118 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver); 119 }; 120 121 #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64 122 struct psp_xgmi_node_info { 123 uint64_t node_id; 124 uint8_t num_hops; 125 uint8_t is_sharing_enabled; 126 enum ta_xgmi_assigned_sdma_engine sdma_engine; 127 }; 128 129 struct psp_xgmi_topology_info { 130 uint32_t num_nodes; 131 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES]; 132 }; 133 134 struct psp_asd_context { 135 bool asd_initialized; 136 uint32_t session_id; 137 }; 138 139 struct psp_xgmi_context { 140 uint8_t initialized; 141 uint32_t session_id; 142 struct amdgpu_bo *xgmi_shared_bo; 143 uint64_t xgmi_shared_mc_addr; 144 void *xgmi_shared_buf; 145 struct psp_xgmi_topology_info top_info; 146 }; 147 148 struct psp_ras_context { 149 /*ras fw*/ 150 bool ras_initialized; 151 uint32_t session_id; 152 struct amdgpu_bo *ras_shared_bo; 153 uint64_t ras_shared_mc_addr; 154 void *ras_shared_buf; 155 struct amdgpu_ras *ras; 156 }; 157 158 struct psp_hdcp_context { 159 bool hdcp_initialized; 160 uint32_t session_id; 161 struct amdgpu_bo *hdcp_shared_bo; 162 uint64_t hdcp_shared_mc_addr; 163 void *hdcp_shared_buf; 164 }; 165 166 struct psp_dtm_context { 167 bool dtm_initialized; 168 uint32_t session_id; 169 struct amdgpu_bo *dtm_shared_bo; 170 uint64_t dtm_shared_mc_addr; 171 void *dtm_shared_buf; 172 }; 173 174 #define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942 175 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000 176 #define GDDR6_MEM_TRAINING_OFFSET 0x8000 177 /*Define the VRAM size that will be encroached by BIST training.*/ 178 #define GDDR6_MEM_TRAINING_ENCROACHED_SIZE 0x2000000 179 180 enum psp_memory_training_init_flag { 181 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0, 182 PSP_MEM_TRAIN_SUPPORT = 0x1, 183 PSP_MEM_TRAIN_INIT_FAILED = 0x2, 184 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4, 185 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8, 186 }; 187 188 enum psp_memory_training_ops { 189 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1, 190 PSP_MEM_TRAIN_SAVE = 0x2, 191 PSP_MEM_TRAIN_RESTORE = 0x4, 192 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8, 193 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG, 194 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG, 195 }; 196 197 struct psp_memory_training_context { 198 /*training data size*/ 199 u64 train_data_size; 200 /* 201 * sys_cache 202 * cpu virtual address 203 * system memory buffer that used to store the training data. 204 */ 205 void *sys_cache; 206 207 /*vram offset of the p2c training data*/ 208 u64 p2c_train_data_offset; 209 210 /*vram offset of the c2p training data*/ 211 u64 c2p_train_data_offset; 212 struct amdgpu_bo *c2p_bo; 213 214 enum psp_memory_training_init_flag init; 215 u32 training_cnt; 216 }; 217 218 struct psp_context 219 { 220 struct amdgpu_device *adev; 221 struct psp_ring km_ring; 222 struct psp_gfx_cmd_resp *cmd; 223 224 const struct psp_funcs *funcs; 225 226 /* firmware buffer */ 227 struct amdgpu_bo *fw_pri_bo; 228 uint64_t fw_pri_mc_addr; 229 void *fw_pri_buf; 230 231 /* sos firmware */ 232 const struct firmware *sos_fw; 233 uint32_t sos_fw_version; 234 uint32_t sos_feature_version; 235 uint32_t sys_bin_size; 236 uint32_t sos_bin_size; 237 uint32_t toc_bin_size; 238 uint32_t kdb_bin_size; 239 uint8_t *sys_start_addr; 240 uint8_t *sos_start_addr; 241 uint8_t *toc_start_addr; 242 uint8_t *kdb_start_addr; 243 244 /* tmr buffer */ 245 struct amdgpu_bo *tmr_bo; 246 uint64_t tmr_mc_addr; 247 248 /* asd firmware */ 249 const struct firmware *asd_fw; 250 uint32_t asd_fw_version; 251 uint32_t asd_feature_version; 252 uint32_t asd_ucode_size; 253 uint8_t *asd_start_addr; 254 255 /* cap firmware */ 256 const struct firmware *cap_fw; 257 258 /* fence buffer */ 259 struct amdgpu_bo *fence_buf_bo; 260 uint64_t fence_buf_mc_addr; 261 void *fence_buf; 262 263 /* cmd buffer */ 264 struct amdgpu_bo *cmd_buf_bo; 265 uint64_t cmd_buf_mc_addr; 266 struct psp_gfx_cmd_resp *cmd_buf_mem; 267 268 /* fence value associated with cmd buffer */ 269 atomic_t fence_value; 270 /* flag to mark whether gfx fw autoload is supported or not */ 271 bool autoload_supported; 272 /* flag to mark whether df cstate management centralized to PMFW */ 273 bool pmfw_centralized_cstate_management; 274 275 /* xgmi ta firmware and buffer */ 276 const struct firmware *ta_fw; 277 uint32_t ta_fw_version; 278 uint32_t ta_xgmi_ucode_version; 279 uint32_t ta_xgmi_ucode_size; 280 uint8_t *ta_xgmi_start_addr; 281 uint32_t ta_ras_ucode_version; 282 uint32_t ta_ras_ucode_size; 283 uint8_t *ta_ras_start_addr; 284 285 uint32_t ta_hdcp_ucode_version; 286 uint32_t ta_hdcp_ucode_size; 287 uint8_t *ta_hdcp_start_addr; 288 289 uint32_t ta_dtm_ucode_version; 290 uint32_t ta_dtm_ucode_size; 291 uint8_t *ta_dtm_start_addr; 292 293 struct psp_asd_context asd_context; 294 struct psp_xgmi_context xgmi_context; 295 struct psp_ras_context ras; 296 struct psp_hdcp_context hdcp_context; 297 struct psp_dtm_context dtm_context; 298 struct mutex mutex; 299 struct psp_memory_training_context mem_train_ctx; 300 }; 301 302 struct amdgpu_psp_funcs { 303 bool (*check_fw_loading_status)(struct amdgpu_device *adev, 304 enum AMDGPU_UCODE_ID); 305 }; 306 307 308 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type)) 309 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) 310 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) 311 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) 312 #define psp_compare_sram_data(psp, ucode, type) \ 313 (psp)->funcs->compare_sram_data((psp), (ucode), (type)) 314 #define psp_init_microcode(psp) \ 315 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) 316 #define psp_bootloader_load_kdb(psp) \ 317 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0) 318 #define psp_bootloader_load_sysdrv(psp) \ 319 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) 320 #define psp_bootloader_load_sos(psp) \ 321 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) 322 #define psp_smu_reload_quirk(psp) \ 323 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) 324 #define psp_support_vmr_ring(psp) \ 325 ((psp)->funcs->support_vmr_ring ? (psp)->funcs->support_vmr_ring((psp)) : false) 326 #define psp_mode1_reset(psp) \ 327 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) 328 #define psp_xgmi_get_node_id(psp, node_id) \ 329 ((psp)->funcs->xgmi_get_node_id ? (psp)->funcs->xgmi_get_node_id((psp), (node_id)) : -EINVAL) 330 #define psp_xgmi_get_hive_id(psp, hive_id) \ 331 ((psp)->funcs->xgmi_get_hive_id ? (psp)->funcs->xgmi_get_hive_id((psp), (hive_id)) : -EINVAL) 332 #define psp_xgmi_get_topology_info(psp, num_device, topology) \ 333 ((psp)->funcs->xgmi_get_topology_info ? \ 334 (psp)->funcs->xgmi_get_topology_info((psp), (num_device), (topology)) : -EINVAL) 335 #define psp_xgmi_set_topology_info(psp, num_device, topology) \ 336 ((psp)->funcs->xgmi_set_topology_info ? \ 337 (psp)->funcs->xgmi_set_topology_info((psp), (num_device), (topology)) : -EINVAL) 338 #define psp_rlc_autoload(psp) \ 339 ((psp)->funcs->rlc_autoload_start ? (psp)->funcs->rlc_autoload_start((psp)) : 0) 340 #define psp_mem_training_init(psp) \ 341 ((psp)->funcs->mem_training_init ? (psp)->funcs->mem_training_init((psp)) : 0) 342 #define psp_mem_training_fini(psp) \ 343 ((psp)->funcs->mem_training_fini ? (psp)->funcs->mem_training_fini((psp)) : 0) 344 #define psp_mem_training(psp, ops) \ 345 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0) 346 347 #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i)) 348 349 #define psp_ras_trigger_error(psp, info) \ 350 ((psp)->funcs->ras_trigger_error ? \ 351 (psp)->funcs->ras_trigger_error((psp), (info)) : -EINVAL) 352 #define psp_ras_cure_posion(psp, addr) \ 353 ((psp)->funcs->ras_cure_posion ? \ 354 (psp)->funcs->ras_cure_posion(psp, (addr)) : -EINVAL) 355 356 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp)) 357 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value)) 358 359 #define psp_load_usbc_pd_fw(psp, dma_addr) \ 360 ((psp)->funcs->load_usbc_pd_fw ? \ 361 (psp)->funcs->load_usbc_pd_fw((psp), (dma_addr)) : -EINVAL) 362 363 #define psp_read_usbc_pd_fw(psp, fw_ver) \ 364 ((psp)->funcs->read_usbc_pd_fw ? \ 365 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL) 366 367 extern const struct amd_ip_funcs psp_ip_funcs; 368 369 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; 370 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 371 uint32_t field_val, uint32_t mask, bool check_changed); 372 373 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; 374 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block; 375 376 int psp_gpu_reset(struct amdgpu_device *adev); 377 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 378 uint64_t cmd_gpu_addr, int cmd_size); 379 380 int psp_xgmi_initialize(struct psp_context *psp); 381 int psp_xgmi_terminate(struct psp_context *psp); 382 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 383 384 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 385 int psp_ras_enable_features(struct psp_context *psp, 386 union ta_ras_cmd_input *info, bool enable); 387 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 388 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 389 390 int psp_rlc_autoload_start(struct psp_context *psp); 391 392 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; 393 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 394 uint32_t value); 395 int psp_ring_cmd_submit(struct psp_context *psp, 396 uint64_t cmd_buf_mc_addr, 397 uint64_t fence_mc_addr, 398 int index); 399 #endif 400