1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 #include "psp_v14_0.h" 42 43 #include "amdgpu_ras.h" 44 #include "amdgpu_securedisplay.h" 45 #include "amdgpu_atomfirmware.h" 46 47 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3) 48 49 static int psp_load_smu_fw(struct psp_context *psp); 50 static int psp_rap_terminate(struct psp_context *psp); 51 static int psp_securedisplay_terminate(struct psp_context *psp); 52 53 static int psp_ring_init(struct psp_context *psp, 54 enum psp_ring_type ring_type) 55 { 56 int ret = 0; 57 struct psp_ring *ring; 58 struct amdgpu_device *adev = psp->adev; 59 60 ring = &psp->km_ring; 61 62 ring->ring_type = ring_type; 63 64 /* allocate 4k Page of Local Frame Buffer memory for ring */ 65 ring->ring_size = 0x1000; 66 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 67 AMDGPU_GEM_DOMAIN_VRAM | 68 AMDGPU_GEM_DOMAIN_GTT, 69 &adev->firmware.rbuf, 70 &ring->ring_mem_mc_addr, 71 (void **)&ring->ring_mem); 72 if (ret) { 73 ring->ring_size = 0; 74 return ret; 75 } 76 77 return 0; 78 } 79 80 /* 81 * Due to DF Cstate management centralized to PMFW, the firmware 82 * loading sequence will be updated as below: 83 * - Load KDB 84 * - Load SYS_DRV 85 * - Load tOS 86 * - Load PMFW 87 * - Setup TMR 88 * - Load other non-psp fw 89 * - Load ASD 90 * - Load XGMI/RAS/HDCP/DTM TA if any 91 * 92 * This new sequence is required for 93 * - Arcturus and onwards 94 */ 95 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 96 { 97 struct amdgpu_device *adev = psp->adev; 98 99 if (amdgpu_sriov_vf(adev)) { 100 psp->pmfw_centralized_cstate_management = false; 101 return; 102 } 103 104 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 105 case IP_VERSION(11, 0, 0): 106 case IP_VERSION(11, 0, 4): 107 case IP_VERSION(11, 0, 5): 108 case IP_VERSION(11, 0, 7): 109 case IP_VERSION(11, 0, 9): 110 case IP_VERSION(11, 0, 11): 111 case IP_VERSION(11, 0, 12): 112 case IP_VERSION(11, 0, 13): 113 case IP_VERSION(13, 0, 0): 114 case IP_VERSION(13, 0, 2): 115 case IP_VERSION(13, 0, 7): 116 psp->pmfw_centralized_cstate_management = true; 117 break; 118 default: 119 psp->pmfw_centralized_cstate_management = false; 120 break; 121 } 122 } 123 124 static int psp_init_sriov_microcode(struct psp_context *psp) 125 { 126 struct amdgpu_device *adev = psp->adev; 127 char ucode_prefix[30]; 128 int ret = 0; 129 130 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 131 132 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 133 case IP_VERSION(9, 0, 0): 134 case IP_VERSION(11, 0, 7): 135 case IP_VERSION(11, 0, 9): 136 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 137 ret = psp_init_cap_microcode(psp, ucode_prefix); 138 break; 139 case IP_VERSION(13, 0, 2): 140 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 141 ret = psp_init_cap_microcode(psp, ucode_prefix); 142 ret &= psp_init_ta_microcode(psp, ucode_prefix); 143 break; 144 case IP_VERSION(13, 0, 0): 145 adev->virt.autoload_ucode_id = 0; 146 break; 147 case IP_VERSION(13, 0, 6): 148 case IP_VERSION(13, 0, 14): 149 ret = psp_init_cap_microcode(psp, ucode_prefix); 150 ret &= psp_init_ta_microcode(psp, ucode_prefix); 151 break; 152 case IP_VERSION(13, 0, 10): 153 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 154 ret = psp_init_cap_microcode(psp, ucode_prefix); 155 break; 156 default: 157 return -EINVAL; 158 } 159 return ret; 160 } 161 162 static int psp_early_init(void *handle) 163 { 164 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 165 struct psp_context *psp = &adev->psp; 166 167 psp->autoload_supported = true; 168 psp->boot_time_tmr = true; 169 170 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 171 case IP_VERSION(9, 0, 0): 172 psp_v3_1_set_psp_funcs(psp); 173 psp->autoload_supported = false; 174 psp->boot_time_tmr = false; 175 break; 176 case IP_VERSION(10, 0, 0): 177 case IP_VERSION(10, 0, 1): 178 psp_v10_0_set_psp_funcs(psp); 179 psp->autoload_supported = false; 180 psp->boot_time_tmr = false; 181 break; 182 case IP_VERSION(11, 0, 2): 183 case IP_VERSION(11, 0, 4): 184 psp_v11_0_set_psp_funcs(psp); 185 psp->autoload_supported = false; 186 psp->boot_time_tmr = false; 187 break; 188 case IP_VERSION(11, 0, 0): 189 case IP_VERSION(11, 0, 7): 190 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev); 191 fallthrough; 192 case IP_VERSION(11, 0, 5): 193 case IP_VERSION(11, 0, 9): 194 case IP_VERSION(11, 0, 11): 195 case IP_VERSION(11, 5, 0): 196 case IP_VERSION(11, 0, 12): 197 case IP_VERSION(11, 0, 13): 198 psp_v11_0_set_psp_funcs(psp); 199 psp->boot_time_tmr = false; 200 break; 201 case IP_VERSION(11, 0, 3): 202 case IP_VERSION(12, 0, 1): 203 psp_v12_0_set_psp_funcs(psp); 204 psp->autoload_supported = false; 205 psp->boot_time_tmr = false; 206 break; 207 case IP_VERSION(13, 0, 2): 208 psp->boot_time_tmr = false; 209 fallthrough; 210 case IP_VERSION(13, 0, 6): 211 case IP_VERSION(13, 0, 14): 212 psp_v13_0_set_psp_funcs(psp); 213 psp->autoload_supported = false; 214 break; 215 case IP_VERSION(13, 0, 1): 216 case IP_VERSION(13, 0, 3): 217 case IP_VERSION(13, 0, 5): 218 case IP_VERSION(13, 0, 8): 219 case IP_VERSION(13, 0, 11): 220 case IP_VERSION(14, 0, 0): 221 case IP_VERSION(14, 0, 1): 222 case IP_VERSION(14, 0, 4): 223 psp_v13_0_set_psp_funcs(psp); 224 psp->boot_time_tmr = false; 225 break; 226 case IP_VERSION(11, 0, 8): 227 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 228 psp_v11_0_8_set_psp_funcs(psp); 229 } 230 psp->autoload_supported = false; 231 psp->boot_time_tmr = false; 232 break; 233 case IP_VERSION(13, 0, 0): 234 case IP_VERSION(13, 0, 7): 235 case IP_VERSION(13, 0, 10): 236 psp_v13_0_set_psp_funcs(psp); 237 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 238 psp->boot_time_tmr = false; 239 break; 240 case IP_VERSION(13, 0, 4): 241 psp_v13_0_4_set_psp_funcs(psp); 242 psp->boot_time_tmr = false; 243 break; 244 case IP_VERSION(14, 0, 2): 245 case IP_VERSION(14, 0, 3): 246 psp_v14_0_set_psp_funcs(psp); 247 break; 248 default: 249 return -EINVAL; 250 } 251 252 psp->adev = adev; 253 254 adev->psp_timeout = 20000; 255 256 psp_check_pmfw_centralized_cstate_management(psp); 257 258 if (amdgpu_sriov_vf(adev)) 259 return psp_init_sriov_microcode(psp); 260 else 261 return psp_init_microcode(psp); 262 } 263 264 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 265 { 266 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 267 &mem_ctx->shared_buf); 268 mem_ctx->shared_bo = NULL; 269 } 270 271 static void psp_free_shared_bufs(struct psp_context *psp) 272 { 273 void *tmr_buf; 274 void **pptr; 275 276 /* free TMR memory buffer */ 277 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 278 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 279 psp->tmr_bo = NULL; 280 281 /* free xgmi shared memory */ 282 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 283 284 /* free ras shared memory */ 285 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 286 287 /* free hdcp shared memory */ 288 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 289 290 /* free dtm shared memory */ 291 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 292 293 /* free rap shared memory */ 294 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 295 296 /* free securedisplay shared memory */ 297 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 298 299 300 } 301 302 static void psp_memory_training_fini(struct psp_context *psp) 303 { 304 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 305 306 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 307 kfree(ctx->sys_cache); 308 ctx->sys_cache = NULL; 309 } 310 311 static int psp_memory_training_init(struct psp_context *psp) 312 { 313 int ret; 314 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 315 316 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 317 dev_dbg(psp->adev->dev, "memory training is not supported!\n"); 318 return 0; 319 } 320 321 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 322 if (ctx->sys_cache == NULL) { 323 dev_err(psp->adev->dev, "alloc mem_train_ctx.sys_cache failed!\n"); 324 ret = -ENOMEM; 325 goto Err_out; 326 } 327 328 dev_dbg(psp->adev->dev, 329 "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 330 ctx->train_data_size, 331 ctx->p2c_train_data_offset, 332 ctx->c2p_train_data_offset); 333 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 334 return 0; 335 336 Err_out: 337 psp_memory_training_fini(psp); 338 return ret; 339 } 340 341 /* 342 * Helper funciton to query psp runtime database entry 343 * 344 * @adev: amdgpu_device pointer 345 * @entry_type: the type of psp runtime database entry 346 * @db_entry: runtime database entry pointer 347 * 348 * Return false if runtime database doesn't exit or entry is invalid 349 * or true if the specific database entry is found, and copy to @db_entry 350 */ 351 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 352 enum psp_runtime_entry_type entry_type, 353 void *db_entry) 354 { 355 uint64_t db_header_pos, db_dir_pos; 356 struct psp_runtime_data_header db_header = {0}; 357 struct psp_runtime_data_directory db_dir = {0}; 358 bool ret = false; 359 int i; 360 361 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 362 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) 363 return false; 364 365 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 366 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 367 368 /* read runtime db header from vram */ 369 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 370 sizeof(struct psp_runtime_data_header), false); 371 372 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 373 /* runtime db doesn't exist, exit */ 374 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 375 return false; 376 } 377 378 /* read runtime database entry from vram */ 379 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 380 sizeof(struct psp_runtime_data_directory), false); 381 382 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 383 /* invalid db entry count, exit */ 384 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 385 return false; 386 } 387 388 /* look up for requested entry type */ 389 for (i = 0; i < db_dir.entry_count && !ret; i++) { 390 if (db_dir.entry_list[i].entry_type == entry_type) { 391 switch (entry_type) { 392 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 393 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 394 /* invalid db entry size */ 395 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 396 return false; 397 } 398 /* read runtime database entry */ 399 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 400 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 401 ret = true; 402 break; 403 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 404 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 405 /* invalid db entry size */ 406 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 407 return false; 408 } 409 /* read runtime database entry */ 410 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 411 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 412 ret = true; 413 break; 414 default: 415 ret = false; 416 break; 417 } 418 } 419 } 420 421 return ret; 422 } 423 424 static int psp_sw_init(void *handle) 425 { 426 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 427 struct psp_context *psp = &adev->psp; 428 int ret; 429 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 430 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 431 struct psp_runtime_scpm_entry scpm_entry; 432 433 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 434 if (!psp->cmd) { 435 dev_err(adev->dev, "Failed to allocate memory to command buffer!\n"); 436 ret = -ENOMEM; 437 } 438 439 adev->psp.xgmi_context.supports_extended_data = 440 !adev->gmc.xgmi.connected_to_cpu && 441 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2); 442 443 memset(&scpm_entry, 0, sizeof(scpm_entry)); 444 if ((psp_get_runtime_db_entry(adev, 445 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 446 &scpm_entry)) && 447 (scpm_entry.scpm_status != SCPM_DISABLE)) { 448 adev->scpm_enabled = true; 449 adev->scpm_status = scpm_entry.scpm_status; 450 } else { 451 adev->scpm_enabled = false; 452 adev->scpm_status = SCPM_DISABLE; 453 } 454 455 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 456 457 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 458 if (psp_get_runtime_db_entry(adev, 459 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 460 &boot_cfg_entry)) { 461 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 462 if ((psp->boot_cfg_bitmask) & 463 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 464 /* If psp runtime database exists, then 465 * only enable two stage memory training 466 * when TWO_STAGE_DRAM_TRAINING bit is set 467 * in runtime database 468 */ 469 mem_training_ctx->enable_mem_training = true; 470 } 471 472 } else { 473 /* If psp runtime database doesn't exist or is 474 * invalid, force enable two stage memory training 475 */ 476 mem_training_ctx->enable_mem_training = true; 477 } 478 479 if (mem_training_ctx->enable_mem_training) { 480 ret = psp_memory_training_init(psp); 481 if (ret) { 482 dev_err(adev->dev, "Failed to initialize memory training!\n"); 483 return ret; 484 } 485 486 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 487 if (ret) { 488 dev_err(adev->dev, "Failed to process memory training!\n"); 489 return ret; 490 } 491 } 492 493 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 494 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf) ? 495 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 496 &psp->fw_pri_bo, 497 &psp->fw_pri_mc_addr, 498 &psp->fw_pri_buf); 499 if (ret) 500 return ret; 501 502 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 503 AMDGPU_GEM_DOMAIN_VRAM | 504 AMDGPU_GEM_DOMAIN_GTT, 505 &psp->fence_buf_bo, 506 &psp->fence_buf_mc_addr, 507 &psp->fence_buf); 508 if (ret) 509 goto failed1; 510 511 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 512 AMDGPU_GEM_DOMAIN_VRAM | 513 AMDGPU_GEM_DOMAIN_GTT, 514 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 515 (void **)&psp->cmd_buf_mem); 516 if (ret) 517 goto failed2; 518 519 return 0; 520 521 failed2: 522 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 523 &psp->fence_buf_mc_addr, &psp->fence_buf); 524 failed1: 525 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 526 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 527 return ret; 528 } 529 530 static int psp_sw_fini(void *handle) 531 { 532 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 533 struct psp_context *psp = &adev->psp; 534 struct psp_gfx_cmd_resp *cmd = psp->cmd; 535 536 psp_memory_training_fini(psp); 537 538 amdgpu_ucode_release(&psp->sos_fw); 539 amdgpu_ucode_release(&psp->asd_fw); 540 amdgpu_ucode_release(&psp->ta_fw); 541 amdgpu_ucode_release(&psp->cap_fw); 542 amdgpu_ucode_release(&psp->toc_fw); 543 544 kfree(cmd); 545 cmd = NULL; 546 547 psp_free_shared_bufs(psp); 548 549 if (psp->km_ring.ring_mem) 550 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 551 &psp->km_ring.ring_mem_mc_addr, 552 (void **)&psp->km_ring.ring_mem); 553 554 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 555 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 556 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 557 &psp->fence_buf_mc_addr, &psp->fence_buf); 558 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 559 (void **)&psp->cmd_buf_mem); 560 561 return 0; 562 } 563 564 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 565 uint32_t reg_val, uint32_t mask, bool check_changed) 566 { 567 uint32_t val; 568 int i; 569 struct amdgpu_device *adev = psp->adev; 570 571 if (psp->adev->no_hw_access) 572 return 0; 573 574 for (i = 0; i < adev->usec_timeout; i++) { 575 val = RREG32(reg_index); 576 if (check_changed) { 577 if (val != reg_val) 578 return 0; 579 } else { 580 if ((val & mask) == reg_val) 581 return 0; 582 } 583 udelay(1); 584 } 585 586 return -ETIME; 587 } 588 589 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 590 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout) 591 { 592 uint32_t val; 593 int i; 594 struct amdgpu_device *adev = psp->adev; 595 596 if (psp->adev->no_hw_access) 597 return 0; 598 599 for (i = 0; i < msec_timeout; i++) { 600 val = RREG32(reg_index); 601 if ((val & mask) == reg_val) 602 return 0; 603 msleep(1); 604 } 605 606 return -ETIME; 607 } 608 609 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 610 { 611 switch (cmd_id) { 612 case GFX_CMD_ID_LOAD_TA: 613 return "LOAD_TA"; 614 case GFX_CMD_ID_UNLOAD_TA: 615 return "UNLOAD_TA"; 616 case GFX_CMD_ID_INVOKE_CMD: 617 return "INVOKE_CMD"; 618 case GFX_CMD_ID_LOAD_ASD: 619 return "LOAD_ASD"; 620 case GFX_CMD_ID_SETUP_TMR: 621 return "SETUP_TMR"; 622 case GFX_CMD_ID_LOAD_IP_FW: 623 return "LOAD_IP_FW"; 624 case GFX_CMD_ID_DESTROY_TMR: 625 return "DESTROY_TMR"; 626 case GFX_CMD_ID_SAVE_RESTORE: 627 return "SAVE_RESTORE_IP_FW"; 628 case GFX_CMD_ID_SETUP_VMR: 629 return "SETUP_VMR"; 630 case GFX_CMD_ID_DESTROY_VMR: 631 return "DESTROY_VMR"; 632 case GFX_CMD_ID_PROG_REG: 633 return "PROG_REG"; 634 case GFX_CMD_ID_GET_FW_ATTESTATION: 635 return "GET_FW_ATTESTATION"; 636 case GFX_CMD_ID_LOAD_TOC: 637 return "ID_LOAD_TOC"; 638 case GFX_CMD_ID_AUTOLOAD_RLC: 639 return "AUTOLOAD_RLC"; 640 case GFX_CMD_ID_BOOT_CFG: 641 return "BOOT_CFG"; 642 case GFX_CMD_ID_CONFIG_SQ_PERFMON: 643 return "CONFIG_SQ_PERFMON"; 644 default: 645 return "UNKNOWN CMD"; 646 } 647 } 648 649 static bool psp_err_warn(struct psp_context *psp) 650 { 651 struct psp_gfx_cmd_resp *cmd = psp->cmd_buf_mem; 652 653 /* This response indicates reg list is already loaded */ 654 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 655 cmd->cmd_id == GFX_CMD_ID_LOAD_IP_FW && 656 cmd->cmd.cmd_load_ip_fw.fw_type == GFX_FW_TYPE_REG_LIST && 657 cmd->resp.status == TEE_ERROR_CANCEL) 658 return false; 659 660 return true; 661 } 662 663 static int 664 psp_cmd_submit_buf(struct psp_context *psp, 665 struct amdgpu_firmware_info *ucode, 666 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 667 { 668 int ret; 669 int index; 670 int timeout = psp->adev->psp_timeout; 671 bool ras_intr = false; 672 bool skip_unsupport = false; 673 674 if (psp->adev->no_hw_access) 675 return 0; 676 677 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 678 679 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 680 681 index = atomic_inc_return(&psp->fence_value); 682 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 683 if (ret) { 684 atomic_dec(&psp->fence_value); 685 goto exit; 686 } 687 688 amdgpu_device_invalidate_hdp(psp->adev, NULL); 689 while (*((unsigned int *)psp->fence_buf) != index) { 690 if (--timeout == 0) 691 break; 692 /* 693 * Shouldn't wait for timeout when err_event_athub occurs, 694 * because gpu reset thread triggered and lock resource should 695 * be released for psp resume sequence. 696 */ 697 ras_intr = amdgpu_ras_intr_triggered(); 698 if (ras_intr) 699 break; 700 usleep_range(10, 100); 701 amdgpu_device_invalidate_hdp(psp->adev, NULL); 702 } 703 704 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 705 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 706 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 707 708 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 709 710 /* In some cases, psp response status is not 0 even there is no 711 * problem while the command is submitted. Some version of PSP FW 712 * doesn't write 0 to that field. 713 * So here we would like to only print a warning instead of an error 714 * during psp initialization to avoid breaking hw_init and it doesn't 715 * return -EINVAL. 716 */ 717 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 718 if (ucode) 719 dev_warn(psp->adev->dev, 720 "failed to load ucode %s(0x%X) ", 721 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 722 if (psp_err_warn(psp)) 723 dev_warn( 724 psp->adev->dev, 725 "psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 726 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), 727 psp->cmd_buf_mem->cmd_id, 728 psp->cmd_buf_mem->resp.status); 729 /* If any firmware (including CAP) load fails under SRIOV, it should 730 * return failure to stop the VF from initializing. 731 * Also return failure in case of timeout 732 */ 733 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 734 ret = -EINVAL; 735 goto exit; 736 } 737 } 738 739 if (ucode) { 740 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 741 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 742 } 743 744 exit: 745 return ret; 746 } 747 748 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 749 { 750 struct psp_gfx_cmd_resp *cmd = psp->cmd; 751 752 mutex_lock(&psp->mutex); 753 754 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 755 756 return cmd; 757 } 758 759 static void release_psp_cmd_buf(struct psp_context *psp) 760 { 761 mutex_unlock(&psp->mutex); 762 } 763 764 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 765 struct psp_gfx_cmd_resp *cmd, 766 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 767 { 768 struct amdgpu_device *adev = psp->adev; 769 uint32_t size = 0; 770 uint64_t tmr_pa = 0; 771 772 if (tmr_bo) { 773 size = amdgpu_bo_size(tmr_bo); 774 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 775 } 776 777 if (amdgpu_sriov_vf(psp->adev)) 778 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 779 else 780 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 781 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 782 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 783 cmd->cmd.cmd_setup_tmr.buf_size = size; 784 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 785 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 786 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 787 } 788 789 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 790 uint64_t pri_buf_mc, uint32_t size) 791 { 792 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 793 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 794 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 795 cmd->cmd.cmd_load_toc.toc_size = size; 796 } 797 798 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 799 static int psp_load_toc(struct psp_context *psp, 800 uint32_t *tmr_size) 801 { 802 int ret; 803 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 804 805 /* Copy toc to psp firmware private buffer */ 806 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 807 808 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 809 810 ret = psp_cmd_submit_buf(psp, NULL, cmd, 811 psp->fence_buf_mc_addr); 812 if (!ret) 813 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 814 815 release_psp_cmd_buf(psp); 816 817 return ret; 818 } 819 820 /* Set up Trusted Memory Region */ 821 static int psp_tmr_init(struct psp_context *psp) 822 { 823 int ret = 0; 824 int tmr_size; 825 void *tmr_buf; 826 void **pptr; 827 828 /* 829 * According to HW engineer, they prefer the TMR address be "naturally 830 * aligned" , e.g. the start address be an integer divide of TMR size. 831 * 832 * Note: this memory need be reserved till the driver 833 * uninitializes. 834 */ 835 tmr_size = PSP_TMR_SIZE(psp->adev); 836 837 /* For ASICs support RLC autoload, psp will parse the toc 838 * and calculate the total size of TMR needed 839 */ 840 if (!amdgpu_sriov_vf(psp->adev) && 841 psp->toc.start_addr && 842 psp->toc.size_bytes && 843 psp->fw_pri_buf) { 844 ret = psp_load_toc(psp, &tmr_size); 845 if (ret) { 846 dev_err(psp->adev->dev, "Failed to load toc\n"); 847 return ret; 848 } 849 } 850 851 if (!psp->tmr_bo && !psp->boot_time_tmr) { 852 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 853 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 854 PSP_TMR_ALIGNMENT, 855 AMDGPU_HAS_VRAM(psp->adev) ? 856 AMDGPU_GEM_DOMAIN_VRAM : 857 AMDGPU_GEM_DOMAIN_GTT, 858 &psp->tmr_bo, &psp->tmr_mc_addr, 859 pptr); 860 } 861 862 return ret; 863 } 864 865 static bool psp_skip_tmr(struct psp_context *psp) 866 { 867 switch (amdgpu_ip_version(psp->adev, MP0_HWIP, 0)) { 868 case IP_VERSION(11, 0, 9): 869 case IP_VERSION(11, 0, 7): 870 case IP_VERSION(13, 0, 2): 871 case IP_VERSION(13, 0, 6): 872 case IP_VERSION(13, 0, 10): 873 case IP_VERSION(13, 0, 14): 874 return true; 875 default: 876 return false; 877 } 878 } 879 880 static int psp_tmr_load(struct psp_context *psp) 881 { 882 int ret; 883 struct psp_gfx_cmd_resp *cmd; 884 885 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 886 * Already set up by host driver. 887 */ 888 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 889 return 0; 890 891 cmd = acquire_psp_cmd_buf(psp); 892 893 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 894 if (psp->tmr_bo) 895 dev_info(psp->adev->dev, "reserve 0x%lx from 0x%llx for PSP TMR\n", 896 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 897 898 ret = psp_cmd_submit_buf(psp, NULL, cmd, 899 psp->fence_buf_mc_addr); 900 901 release_psp_cmd_buf(psp); 902 903 return ret; 904 } 905 906 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 907 struct psp_gfx_cmd_resp *cmd) 908 { 909 if (amdgpu_sriov_vf(psp->adev)) 910 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 911 else 912 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 913 } 914 915 static int psp_tmr_unload(struct psp_context *psp) 916 { 917 int ret; 918 struct psp_gfx_cmd_resp *cmd; 919 920 /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV, 921 * as TMR is not loaded at all 922 */ 923 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 924 return 0; 925 926 cmd = acquire_psp_cmd_buf(psp); 927 928 psp_prep_tmr_unload_cmd_buf(psp, cmd); 929 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 930 931 ret = psp_cmd_submit_buf(psp, NULL, cmd, 932 psp->fence_buf_mc_addr); 933 934 release_psp_cmd_buf(psp); 935 936 return ret; 937 } 938 939 static int psp_tmr_terminate(struct psp_context *psp) 940 { 941 return psp_tmr_unload(psp); 942 } 943 944 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 945 uint64_t *output_ptr) 946 { 947 int ret; 948 struct psp_gfx_cmd_resp *cmd; 949 950 if (!output_ptr) 951 return -EINVAL; 952 953 if (amdgpu_sriov_vf(psp->adev)) 954 return 0; 955 956 cmd = acquire_psp_cmd_buf(psp); 957 958 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 959 960 ret = psp_cmd_submit_buf(psp, NULL, cmd, 961 psp->fence_buf_mc_addr); 962 963 if (!ret) { 964 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 965 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 966 } 967 968 release_psp_cmd_buf(psp); 969 970 return ret; 971 } 972 973 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 974 { 975 struct psp_context *psp = &adev->psp; 976 struct psp_gfx_cmd_resp *cmd; 977 int ret; 978 979 if (amdgpu_sriov_vf(adev)) 980 return 0; 981 982 cmd = acquire_psp_cmd_buf(psp); 983 984 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 985 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 986 987 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 988 if (!ret) { 989 *boot_cfg = 990 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 991 } 992 993 release_psp_cmd_buf(psp); 994 995 return ret; 996 } 997 998 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 999 { 1000 int ret; 1001 struct psp_context *psp = &adev->psp; 1002 struct psp_gfx_cmd_resp *cmd; 1003 1004 if (amdgpu_sriov_vf(adev)) 1005 return 0; 1006 1007 cmd = acquire_psp_cmd_buf(psp); 1008 1009 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1010 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 1011 cmd->cmd.boot_cfg.boot_config = boot_cfg; 1012 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 1013 1014 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1015 1016 release_psp_cmd_buf(psp); 1017 1018 return ret; 1019 } 1020 1021 static int psp_rl_load(struct amdgpu_device *adev) 1022 { 1023 int ret; 1024 struct psp_context *psp = &adev->psp; 1025 struct psp_gfx_cmd_resp *cmd; 1026 1027 if (!is_psp_fw_valid(psp->rl)) 1028 return 0; 1029 1030 cmd = acquire_psp_cmd_buf(psp); 1031 1032 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1033 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 1034 1035 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1036 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 1037 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 1038 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 1039 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 1040 1041 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1042 1043 release_psp_cmd_buf(psp); 1044 1045 return ret; 1046 } 1047 1048 int psp_spatial_partition(struct psp_context *psp, int mode) 1049 { 1050 struct psp_gfx_cmd_resp *cmd; 1051 int ret; 1052 1053 if (amdgpu_sriov_vf(psp->adev)) 1054 return 0; 1055 1056 cmd = acquire_psp_cmd_buf(psp); 1057 1058 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART; 1059 cmd->cmd.cmd_spatial_part.mode = mode; 1060 1061 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode); 1062 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1063 1064 release_psp_cmd_buf(psp); 1065 1066 return ret; 1067 } 1068 1069 static int psp_asd_initialize(struct psp_context *psp) 1070 { 1071 int ret; 1072 1073 /* If PSP version doesn't match ASD version, asd loading will be failed. 1074 * add workaround to bypass it for sriov now. 1075 * TODO: add version check to make it common 1076 */ 1077 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 1078 return 0; 1079 1080 /* bypass asd if display hardware is not available */ 1081 if (!amdgpu_device_has_display_hardware(psp->adev) && 1082 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= IP_VERSION(13, 0, 10)) 1083 return 0; 1084 1085 psp->asd_context.mem_context.shared_mc_addr = 0; 1086 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 1087 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 1088 1089 ret = psp_ta_load(psp, &psp->asd_context); 1090 if (!ret) 1091 psp->asd_context.initialized = true; 1092 1093 return ret; 1094 } 1095 1096 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1097 uint32_t session_id) 1098 { 1099 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 1100 cmd->cmd.cmd_unload_ta.session_id = session_id; 1101 } 1102 1103 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1104 { 1105 int ret; 1106 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1107 1108 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1109 1110 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1111 1112 context->resp_status = cmd->resp.status; 1113 1114 release_psp_cmd_buf(psp); 1115 1116 return ret; 1117 } 1118 1119 static int psp_asd_terminate(struct psp_context *psp) 1120 { 1121 int ret; 1122 1123 if (amdgpu_sriov_vf(psp->adev)) 1124 return 0; 1125 1126 if (!psp->asd_context.initialized) 1127 return 0; 1128 1129 ret = psp_ta_unload(psp, &psp->asd_context); 1130 if (!ret) 1131 psp->asd_context.initialized = false; 1132 1133 return ret; 1134 } 1135 1136 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1137 uint32_t id, uint32_t value) 1138 { 1139 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1140 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1141 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1142 } 1143 1144 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1145 uint32_t value) 1146 { 1147 struct psp_gfx_cmd_resp *cmd; 1148 int ret = 0; 1149 1150 if (reg >= PSP_REG_LAST) 1151 return -EINVAL; 1152 1153 cmd = acquire_psp_cmd_buf(psp); 1154 1155 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1156 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1157 if (ret) 1158 dev_err(psp->adev->dev, "PSP failed to program reg id %d\n", reg); 1159 1160 release_psp_cmd_buf(psp); 1161 1162 return ret; 1163 } 1164 1165 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1166 uint64_t ta_bin_mc, 1167 struct ta_context *context) 1168 { 1169 cmd->cmd_id = context->ta_load_type; 1170 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1171 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1172 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1173 1174 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1175 lower_32_bits(context->mem_context.shared_mc_addr); 1176 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1177 upper_32_bits(context->mem_context.shared_mc_addr); 1178 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1179 } 1180 1181 int psp_ta_init_shared_buf(struct psp_context *psp, 1182 struct ta_mem_context *mem_ctx) 1183 { 1184 /* 1185 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1186 * physical) for ta to host memory 1187 */ 1188 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1189 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1190 AMDGPU_GEM_DOMAIN_GTT, 1191 &mem_ctx->shared_bo, 1192 &mem_ctx->shared_mc_addr, 1193 &mem_ctx->shared_buf); 1194 } 1195 1196 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1197 uint32_t ta_cmd_id, 1198 uint32_t session_id) 1199 { 1200 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1201 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1202 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1203 } 1204 1205 int psp_ta_invoke(struct psp_context *psp, 1206 uint32_t ta_cmd_id, 1207 struct ta_context *context) 1208 { 1209 int ret; 1210 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1211 1212 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1213 1214 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1215 psp->fence_buf_mc_addr); 1216 1217 context->resp_status = cmd->resp.status; 1218 1219 release_psp_cmd_buf(psp); 1220 1221 return ret; 1222 } 1223 1224 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1225 { 1226 int ret; 1227 struct psp_gfx_cmd_resp *cmd; 1228 1229 cmd = acquire_psp_cmd_buf(psp); 1230 1231 psp_copy_fw(psp, context->bin_desc.start_addr, 1232 context->bin_desc.size_bytes); 1233 1234 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1235 1236 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1237 psp->fence_buf_mc_addr); 1238 1239 context->resp_status = cmd->resp.status; 1240 1241 if (!ret) 1242 context->session_id = cmd->resp.session_id; 1243 1244 release_psp_cmd_buf(psp); 1245 1246 return ret; 1247 } 1248 1249 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1250 { 1251 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1252 } 1253 1254 int psp_xgmi_terminate(struct psp_context *psp) 1255 { 1256 int ret; 1257 struct amdgpu_device *adev = psp->adev; 1258 1259 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1260 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 1261 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 1262 adev->gmc.xgmi.connected_to_cpu)) 1263 return 0; 1264 1265 if (!psp->xgmi_context.context.initialized) 1266 return 0; 1267 1268 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1269 1270 psp->xgmi_context.context.initialized = false; 1271 1272 return ret; 1273 } 1274 1275 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1276 { 1277 struct ta_xgmi_shared_memory *xgmi_cmd; 1278 int ret; 1279 1280 if (!psp->ta_fw || 1281 !psp->xgmi_context.context.bin_desc.size_bytes || 1282 !psp->xgmi_context.context.bin_desc.start_addr) 1283 return -ENOENT; 1284 1285 if (!load_ta) 1286 goto invoke; 1287 1288 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1289 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1290 1291 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1292 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1293 if (ret) 1294 return ret; 1295 } 1296 1297 /* Load XGMI TA */ 1298 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1299 if (!ret) 1300 psp->xgmi_context.context.initialized = true; 1301 else 1302 return ret; 1303 1304 invoke: 1305 /* Initialize XGMI session */ 1306 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1307 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1308 xgmi_cmd->flag_extend_link_record = set_extended_data; 1309 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1310 1311 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1312 /* note down the capbility flag for XGMI TA */ 1313 psp->xgmi_context.xgmi_ta_caps = xgmi_cmd->caps_flag; 1314 1315 return ret; 1316 } 1317 1318 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1319 { 1320 struct ta_xgmi_shared_memory *xgmi_cmd; 1321 int ret; 1322 1323 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1324 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1325 1326 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1327 1328 /* Invoke xgmi ta to get hive id */ 1329 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1330 if (ret) 1331 return ret; 1332 1333 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1334 1335 return 0; 1336 } 1337 1338 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1339 { 1340 struct ta_xgmi_shared_memory *xgmi_cmd; 1341 int ret; 1342 1343 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1344 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1345 1346 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1347 1348 /* Invoke xgmi ta to get the node id */ 1349 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1350 if (ret) 1351 return ret; 1352 1353 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1354 1355 return 0; 1356 } 1357 1358 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1359 { 1360 return (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1361 IP_VERSION(13, 0, 2) && 1362 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) || 1363 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= 1364 IP_VERSION(13, 0, 6); 1365 } 1366 1367 /* 1368 * Chips that support extended topology information require the driver to 1369 * reflect topology information in the opposite direction. This is 1370 * because the TA has already exceeded its link record limit and if the 1371 * TA holds bi-directional information, the driver would have to do 1372 * multiple fetches instead of just two. 1373 */ 1374 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1375 struct psp_xgmi_node_info node_info) 1376 { 1377 struct amdgpu_device *mirror_adev; 1378 struct amdgpu_hive_info *hive; 1379 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1380 uint64_t dst_node_id = node_info.node_id; 1381 uint8_t dst_num_hops = node_info.num_hops; 1382 uint8_t dst_num_links = node_info.num_links; 1383 1384 hive = amdgpu_get_xgmi_hive(psp->adev); 1385 if (WARN_ON(!hive)) 1386 return; 1387 1388 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1389 struct psp_xgmi_topology_info *mirror_top_info; 1390 int j; 1391 1392 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1393 continue; 1394 1395 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1396 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1397 if (mirror_top_info->nodes[j].node_id != src_node_id) 1398 continue; 1399 1400 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1401 /* 1402 * prevent 0 num_links value re-reflection since reflection 1403 * criteria is based on num_hops (direct or indirect). 1404 * 1405 */ 1406 if (dst_num_links) 1407 mirror_top_info->nodes[j].num_links = dst_num_links; 1408 1409 break; 1410 } 1411 1412 break; 1413 } 1414 1415 amdgpu_put_xgmi_hive(hive); 1416 } 1417 1418 int psp_xgmi_get_topology_info(struct psp_context *psp, 1419 int number_devices, 1420 struct psp_xgmi_topology_info *topology, 1421 bool get_extended_data) 1422 { 1423 struct ta_xgmi_shared_memory *xgmi_cmd; 1424 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1425 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1426 int i; 1427 int ret; 1428 1429 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1430 return -EINVAL; 1431 1432 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1433 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1434 xgmi_cmd->flag_extend_link_record = get_extended_data; 1435 1436 /* Fill in the shared memory with topology information as input */ 1437 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1438 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_TOPOLOGY_INFO; 1439 topology_info_input->num_nodes = number_devices; 1440 1441 for (i = 0; i < topology_info_input->num_nodes; i++) { 1442 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1443 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1444 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1445 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1446 } 1447 1448 /* Invoke xgmi ta to get the topology information */ 1449 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_TOPOLOGY_INFO); 1450 if (ret) 1451 return ret; 1452 1453 /* Read the output topology information from the shared memory */ 1454 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1455 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1456 for (i = 0; i < topology->num_nodes; i++) { 1457 /* extended data will either be 0 or equal to non-extended data */ 1458 if (topology_info_output->nodes[i].num_hops) 1459 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1460 1461 /* non-extended data gets everything here so no need to update */ 1462 if (!get_extended_data) { 1463 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1464 topology->nodes[i].is_sharing_enabled = 1465 topology_info_output->nodes[i].is_sharing_enabled; 1466 topology->nodes[i].sdma_engine = 1467 topology_info_output->nodes[i].sdma_engine; 1468 } 1469 1470 } 1471 1472 /* Invoke xgmi ta again to get the link information */ 1473 if (psp_xgmi_peer_link_info_supported(psp)) { 1474 struct ta_xgmi_cmd_get_peer_link_info *link_info_output; 1475 struct ta_xgmi_cmd_get_extend_peer_link_info *link_extend_info_output; 1476 bool requires_reflection = 1477 (psp->xgmi_context.supports_extended_data && 1478 get_extended_data) || 1479 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1480 IP_VERSION(13, 0, 6) || 1481 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1482 IP_VERSION(13, 0, 14); 1483 bool ta_port_num_support = amdgpu_sriov_vf(psp->adev) ? 0 : 1484 psp->xgmi_context.xgmi_ta_caps & EXTEND_PEER_LINK_INFO_CMD_FLAG; 1485 1486 /* popluate the shared output buffer rather than the cmd input buffer 1487 * with node_ids as the input for GET_PEER_LINKS command execution. 1488 * This is required for GET_PEER_LINKS per xgmi ta implementation. 1489 * The same requirement for GET_EXTEND_PEER_LINKS command. 1490 */ 1491 if (ta_port_num_support) { 1492 link_extend_info_output = &xgmi_cmd->xgmi_out_message.get_extend_link_info; 1493 1494 for (i = 0; i < topology->num_nodes; i++) 1495 link_extend_info_output->nodes[i].node_id = topology->nodes[i].node_id; 1496 1497 link_extend_info_output->num_nodes = topology->num_nodes; 1498 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_EXTEND_PEER_LINKS; 1499 } else { 1500 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1501 1502 for (i = 0; i < topology->num_nodes; i++) 1503 link_info_output->nodes[i].node_id = topology->nodes[i].node_id; 1504 1505 link_info_output->num_nodes = topology->num_nodes; 1506 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1507 } 1508 1509 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1510 if (ret) 1511 return ret; 1512 1513 for (i = 0; i < topology->num_nodes; i++) { 1514 uint8_t node_num_links = ta_port_num_support ? 1515 link_extend_info_output->nodes[i].num_links : link_info_output->nodes[i].num_links; 1516 /* accumulate num_links on extended data */ 1517 if (get_extended_data) { 1518 topology->nodes[i].num_links = topology->nodes[i].num_links + node_num_links; 1519 } else { 1520 topology->nodes[i].num_links = (requires_reflection && topology->nodes[i].num_links) ? 1521 topology->nodes[i].num_links : node_num_links; 1522 } 1523 /* popluate the connected port num info if supported and available */ 1524 if (ta_port_num_support && topology->nodes[i].num_links) { 1525 memcpy(topology->nodes[i].port_num, link_extend_info_output->nodes[i].port_num, 1526 sizeof(struct xgmi_connected_port_num) * TA_XGMI__MAX_PORT_NUM); 1527 } 1528 1529 /* reflect the topology information for bi-directionality */ 1530 if (requires_reflection && topology->nodes[i].num_hops) 1531 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1532 } 1533 } 1534 1535 return 0; 1536 } 1537 1538 int psp_xgmi_set_topology_info(struct psp_context *psp, 1539 int number_devices, 1540 struct psp_xgmi_topology_info *topology) 1541 { 1542 struct ta_xgmi_shared_memory *xgmi_cmd; 1543 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1544 int i; 1545 1546 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1547 return -EINVAL; 1548 1549 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1550 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1551 1552 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1553 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1554 topology_info_input->num_nodes = number_devices; 1555 1556 for (i = 0; i < topology_info_input->num_nodes; i++) { 1557 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1558 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1559 topology_info_input->nodes[i].is_sharing_enabled = 1; 1560 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1561 } 1562 1563 /* Invoke xgmi ta to set topology information */ 1564 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1565 } 1566 1567 // ras begin 1568 static void psp_ras_ta_check_status(struct psp_context *psp) 1569 { 1570 struct ta_ras_shared_memory *ras_cmd = 1571 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1572 1573 switch (ras_cmd->ras_status) { 1574 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1575 dev_warn(psp->adev->dev, 1576 "RAS WARNING: cmd failed due to unsupported ip\n"); 1577 break; 1578 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1579 dev_warn(psp->adev->dev, 1580 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1581 break; 1582 case TA_RAS_STATUS__SUCCESS: 1583 break; 1584 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1585 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1586 dev_warn(psp->adev->dev, 1587 "RAS WARNING: Inject error to critical region is not allowed\n"); 1588 break; 1589 default: 1590 dev_warn(psp->adev->dev, 1591 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1592 break; 1593 } 1594 } 1595 1596 static int psp_ras_send_cmd(struct psp_context *psp, 1597 enum ras_command cmd_id, void *in, void *out) 1598 { 1599 struct ta_ras_shared_memory *ras_cmd; 1600 uint32_t cmd = cmd_id; 1601 int ret = 0; 1602 1603 if (!in) 1604 return -EINVAL; 1605 1606 mutex_lock(&psp->ras_context.mutex); 1607 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1608 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1609 1610 switch (cmd) { 1611 case TA_RAS_COMMAND__ENABLE_FEATURES: 1612 case TA_RAS_COMMAND__DISABLE_FEATURES: 1613 memcpy(&ras_cmd->ras_in_message, 1614 in, sizeof(ras_cmd->ras_in_message)); 1615 break; 1616 case TA_RAS_COMMAND__TRIGGER_ERROR: 1617 memcpy(&ras_cmd->ras_in_message.trigger_error, 1618 in, sizeof(ras_cmd->ras_in_message.trigger_error)); 1619 break; 1620 case TA_RAS_COMMAND__QUERY_ADDRESS: 1621 memcpy(&ras_cmd->ras_in_message.address, 1622 in, sizeof(ras_cmd->ras_in_message.address)); 1623 break; 1624 default: 1625 dev_err(psp->adev->dev, "Invalid ras cmd id: %u\n", cmd); 1626 ret = -EINVAL; 1627 goto err_out; 1628 } 1629 1630 ras_cmd->cmd_id = cmd; 1631 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1632 1633 switch (cmd) { 1634 case TA_RAS_COMMAND__TRIGGER_ERROR: 1635 if (!ret && out) 1636 memcpy(out, &ras_cmd->ras_status, sizeof(ras_cmd->ras_status)); 1637 break; 1638 case TA_RAS_COMMAND__QUERY_ADDRESS: 1639 if (ret || ras_cmd->ras_status || psp->cmd_buf_mem->resp.status) 1640 ret = -EINVAL; 1641 else if (out) 1642 memcpy(out, 1643 &ras_cmd->ras_out_message.address, 1644 sizeof(ras_cmd->ras_out_message.address)); 1645 break; 1646 default: 1647 break; 1648 } 1649 1650 err_out: 1651 mutex_unlock(&psp->ras_context.mutex); 1652 1653 return ret; 1654 } 1655 1656 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1657 { 1658 struct ta_ras_shared_memory *ras_cmd; 1659 int ret; 1660 1661 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1662 1663 /* 1664 * TODO: bypass the loading in sriov for now 1665 */ 1666 if (amdgpu_sriov_vf(psp->adev)) 1667 return 0; 1668 1669 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1670 1671 if (amdgpu_ras_intr_triggered()) 1672 return ret; 1673 1674 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { 1675 dev_warn(psp->adev->dev, "RAS: Unsupported Interface\n"); 1676 return -EINVAL; 1677 } 1678 1679 if (!ret) { 1680 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1681 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1682 1683 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1684 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1685 dev_warn(psp->adev->dev, 1686 "RAS internal register access blocked\n"); 1687 1688 psp_ras_ta_check_status(psp); 1689 } 1690 1691 return ret; 1692 } 1693 1694 int psp_ras_enable_features(struct psp_context *psp, 1695 union ta_ras_cmd_input *info, bool enable) 1696 { 1697 enum ras_command cmd_id; 1698 int ret; 1699 1700 if (!psp->ras_context.context.initialized || !info) 1701 return -EINVAL; 1702 1703 cmd_id = enable ? 1704 TA_RAS_COMMAND__ENABLE_FEATURES : TA_RAS_COMMAND__DISABLE_FEATURES; 1705 ret = psp_ras_send_cmd(psp, cmd_id, info, NULL); 1706 if (ret) 1707 return -EINVAL; 1708 1709 return 0; 1710 } 1711 1712 int psp_ras_terminate(struct psp_context *psp) 1713 { 1714 int ret; 1715 1716 /* 1717 * TODO: bypass the terminate in sriov for now 1718 */ 1719 if (amdgpu_sriov_vf(psp->adev)) 1720 return 0; 1721 1722 if (!psp->ras_context.context.initialized) 1723 return 0; 1724 1725 ret = psp_ta_unload(psp, &psp->ras_context.context); 1726 1727 psp->ras_context.context.initialized = false; 1728 1729 mutex_destroy(&psp->ras_context.mutex); 1730 1731 return ret; 1732 } 1733 1734 int psp_ras_initialize(struct psp_context *psp) 1735 { 1736 int ret; 1737 uint32_t boot_cfg = 0xFF; 1738 struct amdgpu_device *adev = psp->adev; 1739 struct ta_ras_shared_memory *ras_cmd; 1740 1741 /* 1742 * TODO: bypass the initialize in sriov for now 1743 */ 1744 if (amdgpu_sriov_vf(adev)) 1745 return 0; 1746 1747 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1748 !adev->psp.ras_context.context.bin_desc.start_addr) { 1749 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1750 return 0; 1751 } 1752 1753 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1754 /* query GECC enablement status from boot config 1755 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1756 */ 1757 ret = psp_boot_config_get(adev, &boot_cfg); 1758 if (ret) 1759 dev_warn(adev->dev, "PSP get boot config failed\n"); 1760 1761 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1762 if (!boot_cfg) { 1763 dev_info(adev->dev, "GECC is disabled\n"); 1764 } else { 1765 /* disable GECC in next boot cycle if ras is 1766 * disabled by module parameter amdgpu_ras_enable 1767 * and/or amdgpu_ras_mask, or boot_config_get call 1768 * is failed 1769 */ 1770 ret = psp_boot_config_set(adev, 0); 1771 if (ret) 1772 dev_warn(adev->dev, "PSP set boot config failed\n"); 1773 else 1774 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1775 } 1776 } else { 1777 if (boot_cfg == 1) { 1778 dev_info(adev->dev, "GECC is enabled\n"); 1779 } else { 1780 /* enable GECC in next boot cycle if it is disabled 1781 * in boot config, or force enable GECC if failed to 1782 * get boot configuration 1783 */ 1784 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1785 if (ret) 1786 dev_warn(adev->dev, "PSP set boot config failed\n"); 1787 else 1788 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1789 } 1790 } 1791 } 1792 1793 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1794 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1795 1796 if (!psp->ras_context.context.mem_context.shared_buf) { 1797 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1798 if (ret) 1799 return ret; 1800 } 1801 1802 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1803 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1804 1805 if (amdgpu_ras_is_poison_mode_supported(adev)) 1806 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1807 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1808 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1809 ras_cmd->ras_in_message.init_flags.xcc_mask = 1810 adev->gfx.xcc_mask; 1811 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; 1812 1813 ret = psp_ta_load(psp, &psp->ras_context.context); 1814 1815 if (!ret && !ras_cmd->ras_status) { 1816 psp->ras_context.context.initialized = true; 1817 mutex_init(&psp->ras_context.mutex); 1818 } else { 1819 if (ras_cmd->ras_status) 1820 dev_warn(adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1821 1822 /* fail to load RAS TA */ 1823 psp->ras_context.context.initialized = false; 1824 } 1825 1826 return ret; 1827 } 1828 1829 int psp_ras_trigger_error(struct psp_context *psp, 1830 struct ta_ras_trigger_error_input *info, uint32_t instance_mask) 1831 { 1832 struct amdgpu_device *adev = psp->adev; 1833 int ret; 1834 uint32_t dev_mask; 1835 uint32_t ras_status = 0; 1836 1837 if (!psp->ras_context.context.initialized || !info) 1838 return -EINVAL; 1839 1840 switch (info->block_id) { 1841 case TA_RAS_BLOCK__GFX: 1842 dev_mask = GET_MASK(GC, instance_mask); 1843 break; 1844 case TA_RAS_BLOCK__SDMA: 1845 dev_mask = GET_MASK(SDMA0, instance_mask); 1846 break; 1847 case TA_RAS_BLOCK__VCN: 1848 case TA_RAS_BLOCK__JPEG: 1849 dev_mask = GET_MASK(VCN, instance_mask); 1850 break; 1851 default: 1852 dev_mask = instance_mask; 1853 break; 1854 } 1855 1856 /* reuse sub_block_index for backward compatibility */ 1857 dev_mask <<= AMDGPU_RAS_INST_SHIFT; 1858 dev_mask &= AMDGPU_RAS_INST_MASK; 1859 info->sub_block_index |= dev_mask; 1860 1861 ret = psp_ras_send_cmd(psp, 1862 TA_RAS_COMMAND__TRIGGER_ERROR, info, &ras_status); 1863 if (ret) 1864 return -EINVAL; 1865 1866 /* If err_event_athub occurs error inject was successful, however 1867 * return status from TA is no long reliable 1868 */ 1869 if (amdgpu_ras_intr_triggered()) 1870 return 0; 1871 1872 if (ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1873 return -EACCES; 1874 else if (ras_status) 1875 return -EINVAL; 1876 1877 return 0; 1878 } 1879 1880 int psp_ras_query_address(struct psp_context *psp, 1881 struct ta_ras_query_address_input *addr_in, 1882 struct ta_ras_query_address_output *addr_out) 1883 { 1884 int ret; 1885 1886 if (!psp->ras_context.context.initialized || 1887 !addr_in || !addr_out) 1888 return -EINVAL; 1889 1890 ret = psp_ras_send_cmd(psp, 1891 TA_RAS_COMMAND__QUERY_ADDRESS, addr_in, addr_out); 1892 1893 return ret; 1894 } 1895 // ras end 1896 1897 // HDCP start 1898 static int psp_hdcp_initialize(struct psp_context *psp) 1899 { 1900 int ret; 1901 1902 /* 1903 * TODO: bypass the initialize in sriov for now 1904 */ 1905 if (amdgpu_sriov_vf(psp->adev)) 1906 return 0; 1907 1908 /* bypass hdcp initialization if dmu is harvested */ 1909 if (!amdgpu_device_has_display_hardware(psp->adev)) 1910 return 0; 1911 1912 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1913 !psp->hdcp_context.context.bin_desc.start_addr) { 1914 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1915 return 0; 1916 } 1917 1918 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1919 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1920 1921 if (!psp->hdcp_context.context.mem_context.shared_buf) { 1922 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1923 if (ret) 1924 return ret; 1925 } 1926 1927 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1928 if (!ret) { 1929 psp->hdcp_context.context.initialized = true; 1930 mutex_init(&psp->hdcp_context.mutex); 1931 } 1932 1933 return ret; 1934 } 1935 1936 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1937 { 1938 /* 1939 * TODO: bypass the loading in sriov for now 1940 */ 1941 if (amdgpu_sriov_vf(psp->adev)) 1942 return 0; 1943 1944 if (!psp->hdcp_context.context.initialized) 1945 return 0; 1946 1947 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1948 } 1949 1950 static int psp_hdcp_terminate(struct psp_context *psp) 1951 { 1952 int ret; 1953 1954 /* 1955 * TODO: bypass the terminate in sriov for now 1956 */ 1957 if (amdgpu_sriov_vf(psp->adev)) 1958 return 0; 1959 1960 if (!psp->hdcp_context.context.initialized) 1961 return 0; 1962 1963 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1964 1965 psp->hdcp_context.context.initialized = false; 1966 1967 return ret; 1968 } 1969 // HDCP end 1970 1971 // DTM start 1972 static int psp_dtm_initialize(struct psp_context *psp) 1973 { 1974 int ret; 1975 1976 /* 1977 * TODO: bypass the initialize in sriov for now 1978 */ 1979 if (amdgpu_sriov_vf(psp->adev)) 1980 return 0; 1981 1982 /* bypass dtm initialization if dmu is harvested */ 1983 if (!amdgpu_device_has_display_hardware(psp->adev)) 1984 return 0; 1985 1986 if (!psp->dtm_context.context.bin_desc.size_bytes || 1987 !psp->dtm_context.context.bin_desc.start_addr) { 1988 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1989 return 0; 1990 } 1991 1992 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1993 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1994 1995 if (!psp->dtm_context.context.mem_context.shared_buf) { 1996 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1997 if (ret) 1998 return ret; 1999 } 2000 2001 ret = psp_ta_load(psp, &psp->dtm_context.context); 2002 if (!ret) { 2003 psp->dtm_context.context.initialized = true; 2004 mutex_init(&psp->dtm_context.mutex); 2005 } 2006 2007 return ret; 2008 } 2009 2010 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2011 { 2012 /* 2013 * TODO: bypass the loading in sriov for now 2014 */ 2015 if (amdgpu_sriov_vf(psp->adev)) 2016 return 0; 2017 2018 if (!psp->dtm_context.context.initialized) 2019 return 0; 2020 2021 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 2022 } 2023 2024 static int psp_dtm_terminate(struct psp_context *psp) 2025 { 2026 int ret; 2027 2028 /* 2029 * TODO: bypass the terminate in sriov for now 2030 */ 2031 if (amdgpu_sriov_vf(psp->adev)) 2032 return 0; 2033 2034 if (!psp->dtm_context.context.initialized) 2035 return 0; 2036 2037 ret = psp_ta_unload(psp, &psp->dtm_context.context); 2038 2039 psp->dtm_context.context.initialized = false; 2040 2041 return ret; 2042 } 2043 // DTM end 2044 2045 // RAP start 2046 static int psp_rap_initialize(struct psp_context *psp) 2047 { 2048 int ret; 2049 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 2050 2051 /* 2052 * TODO: bypass the initialize in sriov for now 2053 */ 2054 if (amdgpu_sriov_vf(psp->adev)) 2055 return 0; 2056 2057 if (!psp->rap_context.context.bin_desc.size_bytes || 2058 !psp->rap_context.context.bin_desc.start_addr) { 2059 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 2060 return 0; 2061 } 2062 2063 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 2064 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2065 2066 if (!psp->rap_context.context.mem_context.shared_buf) { 2067 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 2068 if (ret) 2069 return ret; 2070 } 2071 2072 ret = psp_ta_load(psp, &psp->rap_context.context); 2073 if (!ret) { 2074 psp->rap_context.context.initialized = true; 2075 mutex_init(&psp->rap_context.mutex); 2076 } else 2077 return ret; 2078 2079 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 2080 if (ret || status != TA_RAP_STATUS__SUCCESS) { 2081 psp_rap_terminate(psp); 2082 /* free rap shared memory */ 2083 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 2084 2085 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 2086 ret, status); 2087 2088 return ret; 2089 } 2090 2091 return 0; 2092 } 2093 2094 static int psp_rap_terminate(struct psp_context *psp) 2095 { 2096 int ret; 2097 2098 if (!psp->rap_context.context.initialized) 2099 return 0; 2100 2101 ret = psp_ta_unload(psp, &psp->rap_context.context); 2102 2103 psp->rap_context.context.initialized = false; 2104 2105 return ret; 2106 } 2107 2108 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 2109 { 2110 struct ta_rap_shared_memory *rap_cmd; 2111 int ret = 0; 2112 2113 if (!psp->rap_context.context.initialized) 2114 return 0; 2115 2116 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 2117 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 2118 return -EINVAL; 2119 2120 mutex_lock(&psp->rap_context.mutex); 2121 2122 rap_cmd = (struct ta_rap_shared_memory *) 2123 psp->rap_context.context.mem_context.shared_buf; 2124 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 2125 2126 rap_cmd->cmd_id = ta_cmd_id; 2127 rap_cmd->validation_method_id = METHOD_A; 2128 2129 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 2130 if (ret) 2131 goto out_unlock; 2132 2133 if (status) 2134 *status = rap_cmd->rap_status; 2135 2136 out_unlock: 2137 mutex_unlock(&psp->rap_context.mutex); 2138 2139 return ret; 2140 } 2141 // RAP end 2142 2143 /* securedisplay start */ 2144 static int psp_securedisplay_initialize(struct psp_context *psp) 2145 { 2146 int ret; 2147 struct ta_securedisplay_cmd *securedisplay_cmd; 2148 2149 /* 2150 * TODO: bypass the initialize in sriov for now 2151 */ 2152 if (amdgpu_sriov_vf(psp->adev)) 2153 return 0; 2154 2155 /* bypass securedisplay initialization if dmu is harvested */ 2156 if (!amdgpu_device_has_display_hardware(psp->adev)) 2157 return 0; 2158 2159 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 2160 !psp->securedisplay_context.context.bin_desc.start_addr) { 2161 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 2162 return 0; 2163 } 2164 2165 psp->securedisplay_context.context.mem_context.shared_mem_size = 2166 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 2167 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2168 2169 if (!psp->securedisplay_context.context.initialized) { 2170 ret = psp_ta_init_shared_buf(psp, 2171 &psp->securedisplay_context.context.mem_context); 2172 if (ret) 2173 return ret; 2174 } 2175 2176 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 2177 if (!ret) { 2178 psp->securedisplay_context.context.initialized = true; 2179 mutex_init(&psp->securedisplay_context.mutex); 2180 } else 2181 return ret; 2182 2183 mutex_lock(&psp->securedisplay_context.mutex); 2184 2185 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2186 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2187 2188 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2189 2190 mutex_unlock(&psp->securedisplay_context.mutex); 2191 2192 if (ret) { 2193 psp_securedisplay_terminate(psp); 2194 /* free securedisplay shared memory */ 2195 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 2196 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2197 return -EINVAL; 2198 } 2199 2200 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2201 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2202 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2203 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2204 /* don't try again */ 2205 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2206 } 2207 2208 return 0; 2209 } 2210 2211 static int psp_securedisplay_terminate(struct psp_context *psp) 2212 { 2213 int ret; 2214 2215 /* 2216 * TODO:bypass the terminate in sriov for now 2217 */ 2218 if (amdgpu_sriov_vf(psp->adev)) 2219 return 0; 2220 2221 if (!psp->securedisplay_context.context.initialized) 2222 return 0; 2223 2224 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 2225 2226 psp->securedisplay_context.context.initialized = false; 2227 2228 return ret; 2229 } 2230 2231 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2232 { 2233 int ret; 2234 2235 if (!psp->securedisplay_context.context.initialized) 2236 return -EINVAL; 2237 2238 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2239 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 2240 return -EINVAL; 2241 2242 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2243 2244 return ret; 2245 } 2246 /* SECUREDISPLAY end */ 2247 2248 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev) 2249 { 2250 struct psp_context *psp = &adev->psp; 2251 int ret = 0; 2252 2253 if (!amdgpu_sriov_vf(adev) && psp->funcs && psp->funcs->wait_for_bootloader != NULL) 2254 ret = psp->funcs->wait_for_bootloader(psp); 2255 2256 return ret; 2257 } 2258 2259 bool amdgpu_psp_get_ras_capability(struct psp_context *psp) 2260 { 2261 if (psp->funcs && 2262 psp->funcs->get_ras_capability) { 2263 return psp->funcs->get_ras_capability(psp); 2264 } else { 2265 return false; 2266 } 2267 } 2268 2269 bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev) 2270 { 2271 struct psp_context *psp = &adev->psp; 2272 2273 if (amdgpu_sriov_vf(adev)) 2274 return false; 2275 2276 if (psp->funcs && psp->funcs->is_reload_needed) 2277 return psp->funcs->is_reload_needed(psp); 2278 2279 return false; 2280 } 2281 2282 static int psp_hw_start(struct psp_context *psp) 2283 { 2284 struct amdgpu_device *adev = psp->adev; 2285 int ret; 2286 2287 if (!amdgpu_sriov_vf(adev)) { 2288 if ((is_psp_fw_valid(psp->kdb)) && 2289 (psp->funcs->bootloader_load_kdb != NULL)) { 2290 ret = psp_bootloader_load_kdb(psp); 2291 if (ret) { 2292 dev_err(adev->dev, "PSP load kdb failed!\n"); 2293 return ret; 2294 } 2295 } 2296 2297 if ((is_psp_fw_valid(psp->spl)) && 2298 (psp->funcs->bootloader_load_spl != NULL)) { 2299 ret = psp_bootloader_load_spl(psp); 2300 if (ret) { 2301 dev_err(adev->dev, "PSP load spl failed!\n"); 2302 return ret; 2303 } 2304 } 2305 2306 if ((is_psp_fw_valid(psp->sys)) && 2307 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2308 ret = psp_bootloader_load_sysdrv(psp); 2309 if (ret) { 2310 dev_err(adev->dev, "PSP load sys drv failed!\n"); 2311 return ret; 2312 } 2313 } 2314 2315 if ((is_psp_fw_valid(psp->soc_drv)) && 2316 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2317 ret = psp_bootloader_load_soc_drv(psp); 2318 if (ret) { 2319 dev_err(adev->dev, "PSP load soc drv failed!\n"); 2320 return ret; 2321 } 2322 } 2323 2324 if ((is_psp_fw_valid(psp->intf_drv)) && 2325 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2326 ret = psp_bootloader_load_intf_drv(psp); 2327 if (ret) { 2328 dev_err(adev->dev, "PSP load intf drv failed!\n"); 2329 return ret; 2330 } 2331 } 2332 2333 if ((is_psp_fw_valid(psp->dbg_drv)) && 2334 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2335 ret = psp_bootloader_load_dbg_drv(psp); 2336 if (ret) { 2337 dev_err(adev->dev, "PSP load dbg drv failed!\n"); 2338 return ret; 2339 } 2340 } 2341 2342 if ((is_psp_fw_valid(psp->ras_drv)) && 2343 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2344 ret = psp_bootloader_load_ras_drv(psp); 2345 if (ret) { 2346 dev_err(adev->dev, "PSP load ras_drv failed!\n"); 2347 return ret; 2348 } 2349 } 2350 2351 if ((is_psp_fw_valid(psp->ipkeymgr_drv)) && 2352 (psp->funcs->bootloader_load_ipkeymgr_drv != NULL)) { 2353 ret = psp_bootloader_load_ipkeymgr_drv(psp); 2354 if (ret) { 2355 dev_err(adev->dev, "PSP load ipkeymgr_drv failed!\n"); 2356 return ret; 2357 } 2358 } 2359 2360 if ((is_psp_fw_valid(psp->sos)) && 2361 (psp->funcs->bootloader_load_sos != NULL)) { 2362 ret = psp_bootloader_load_sos(psp); 2363 if (ret) { 2364 dev_err(adev->dev, "PSP load sos failed!\n"); 2365 return ret; 2366 } 2367 } 2368 } 2369 2370 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2371 if (ret) { 2372 dev_err(adev->dev, "PSP create ring failed!\n"); 2373 return ret; 2374 } 2375 2376 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2377 goto skip_pin_bo; 2378 2379 if (!psp->boot_time_tmr || psp->autoload_supported) { 2380 ret = psp_tmr_init(psp); 2381 if (ret) { 2382 dev_err(adev->dev, "PSP tmr init failed!\n"); 2383 return ret; 2384 } 2385 } 2386 2387 skip_pin_bo: 2388 /* 2389 * For ASICs with DF Cstate management centralized 2390 * to PMFW, TMR setup should be performed after PMFW 2391 * loaded and before other non-psp firmware loaded. 2392 */ 2393 if (psp->pmfw_centralized_cstate_management) { 2394 ret = psp_load_smu_fw(psp); 2395 if (ret) 2396 return ret; 2397 } 2398 2399 if (!psp->boot_time_tmr || !psp->autoload_supported) { 2400 ret = psp_tmr_load(psp); 2401 if (ret) { 2402 dev_err(adev->dev, "PSP load tmr failed!\n"); 2403 return ret; 2404 } 2405 } 2406 2407 return 0; 2408 } 2409 2410 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2411 enum psp_gfx_fw_type *type) 2412 { 2413 switch (ucode->ucode_id) { 2414 case AMDGPU_UCODE_ID_CAP: 2415 *type = GFX_FW_TYPE_CAP; 2416 break; 2417 case AMDGPU_UCODE_ID_SDMA0: 2418 *type = GFX_FW_TYPE_SDMA0; 2419 break; 2420 case AMDGPU_UCODE_ID_SDMA1: 2421 *type = GFX_FW_TYPE_SDMA1; 2422 break; 2423 case AMDGPU_UCODE_ID_SDMA2: 2424 *type = GFX_FW_TYPE_SDMA2; 2425 break; 2426 case AMDGPU_UCODE_ID_SDMA3: 2427 *type = GFX_FW_TYPE_SDMA3; 2428 break; 2429 case AMDGPU_UCODE_ID_SDMA4: 2430 *type = GFX_FW_TYPE_SDMA4; 2431 break; 2432 case AMDGPU_UCODE_ID_SDMA5: 2433 *type = GFX_FW_TYPE_SDMA5; 2434 break; 2435 case AMDGPU_UCODE_ID_SDMA6: 2436 *type = GFX_FW_TYPE_SDMA6; 2437 break; 2438 case AMDGPU_UCODE_ID_SDMA7: 2439 *type = GFX_FW_TYPE_SDMA7; 2440 break; 2441 case AMDGPU_UCODE_ID_CP_MES: 2442 *type = GFX_FW_TYPE_CP_MES; 2443 break; 2444 case AMDGPU_UCODE_ID_CP_MES_DATA: 2445 *type = GFX_FW_TYPE_MES_STACK; 2446 break; 2447 case AMDGPU_UCODE_ID_CP_MES1: 2448 *type = GFX_FW_TYPE_CP_MES_KIQ; 2449 break; 2450 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2451 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2452 break; 2453 case AMDGPU_UCODE_ID_CP_CE: 2454 *type = GFX_FW_TYPE_CP_CE; 2455 break; 2456 case AMDGPU_UCODE_ID_CP_PFP: 2457 *type = GFX_FW_TYPE_CP_PFP; 2458 break; 2459 case AMDGPU_UCODE_ID_CP_ME: 2460 *type = GFX_FW_TYPE_CP_ME; 2461 break; 2462 case AMDGPU_UCODE_ID_CP_MEC1: 2463 *type = GFX_FW_TYPE_CP_MEC; 2464 break; 2465 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2466 *type = GFX_FW_TYPE_CP_MEC_ME1; 2467 break; 2468 case AMDGPU_UCODE_ID_CP_MEC2: 2469 *type = GFX_FW_TYPE_CP_MEC; 2470 break; 2471 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2472 *type = GFX_FW_TYPE_CP_MEC_ME2; 2473 break; 2474 case AMDGPU_UCODE_ID_RLC_P: 2475 *type = GFX_FW_TYPE_RLC_P; 2476 break; 2477 case AMDGPU_UCODE_ID_RLC_V: 2478 *type = GFX_FW_TYPE_RLC_V; 2479 break; 2480 case AMDGPU_UCODE_ID_RLC_G: 2481 *type = GFX_FW_TYPE_RLC_G; 2482 break; 2483 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2484 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2485 break; 2486 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2487 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2488 break; 2489 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2490 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2491 break; 2492 case AMDGPU_UCODE_ID_RLC_IRAM: 2493 *type = GFX_FW_TYPE_RLC_IRAM; 2494 break; 2495 case AMDGPU_UCODE_ID_RLC_DRAM: 2496 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2497 break; 2498 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2499 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2500 break; 2501 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2502 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2503 break; 2504 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2505 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2506 break; 2507 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2508 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2509 break; 2510 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2511 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2512 break; 2513 case AMDGPU_UCODE_ID_SMC: 2514 *type = GFX_FW_TYPE_SMU; 2515 break; 2516 case AMDGPU_UCODE_ID_PPTABLE: 2517 *type = GFX_FW_TYPE_PPTABLE; 2518 break; 2519 case AMDGPU_UCODE_ID_UVD: 2520 *type = GFX_FW_TYPE_UVD; 2521 break; 2522 case AMDGPU_UCODE_ID_UVD1: 2523 *type = GFX_FW_TYPE_UVD1; 2524 break; 2525 case AMDGPU_UCODE_ID_VCE: 2526 *type = GFX_FW_TYPE_VCE; 2527 break; 2528 case AMDGPU_UCODE_ID_VCN: 2529 *type = GFX_FW_TYPE_VCN; 2530 break; 2531 case AMDGPU_UCODE_ID_VCN1: 2532 *type = GFX_FW_TYPE_VCN1; 2533 break; 2534 case AMDGPU_UCODE_ID_DMCU_ERAM: 2535 *type = GFX_FW_TYPE_DMCU_ERAM; 2536 break; 2537 case AMDGPU_UCODE_ID_DMCU_INTV: 2538 *type = GFX_FW_TYPE_DMCU_ISR; 2539 break; 2540 case AMDGPU_UCODE_ID_VCN0_RAM: 2541 *type = GFX_FW_TYPE_VCN0_RAM; 2542 break; 2543 case AMDGPU_UCODE_ID_VCN1_RAM: 2544 *type = GFX_FW_TYPE_VCN1_RAM; 2545 break; 2546 case AMDGPU_UCODE_ID_DMCUB: 2547 *type = GFX_FW_TYPE_DMUB; 2548 break; 2549 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2550 case AMDGPU_UCODE_ID_SDMA_RS64: 2551 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2552 break; 2553 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2554 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2555 break; 2556 case AMDGPU_UCODE_ID_IMU_I: 2557 *type = GFX_FW_TYPE_IMU_I; 2558 break; 2559 case AMDGPU_UCODE_ID_IMU_D: 2560 *type = GFX_FW_TYPE_IMU_D; 2561 break; 2562 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2563 *type = GFX_FW_TYPE_RS64_PFP; 2564 break; 2565 case AMDGPU_UCODE_ID_CP_RS64_ME: 2566 *type = GFX_FW_TYPE_RS64_ME; 2567 break; 2568 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2569 *type = GFX_FW_TYPE_RS64_MEC; 2570 break; 2571 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2572 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2573 break; 2574 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2575 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2576 break; 2577 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2578 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2579 break; 2580 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2581 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2582 break; 2583 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2584 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2585 break; 2586 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2587 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2588 break; 2589 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2590 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2591 break; 2592 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2593 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2594 break; 2595 case AMDGPU_UCODE_ID_VPE_CTX: 2596 *type = GFX_FW_TYPE_VPEC_FW1; 2597 break; 2598 case AMDGPU_UCODE_ID_VPE_CTL: 2599 *type = GFX_FW_TYPE_VPEC_FW2; 2600 break; 2601 case AMDGPU_UCODE_ID_VPE: 2602 *type = GFX_FW_TYPE_VPE; 2603 break; 2604 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 2605 *type = GFX_FW_TYPE_UMSCH_UCODE; 2606 break; 2607 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 2608 *type = GFX_FW_TYPE_UMSCH_DATA; 2609 break; 2610 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: 2611 *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER; 2612 break; 2613 case AMDGPU_UCODE_ID_P2S_TABLE: 2614 *type = GFX_FW_TYPE_P2S_TABLE; 2615 break; 2616 case AMDGPU_UCODE_ID_JPEG_RAM: 2617 *type = GFX_FW_TYPE_JPEG_RAM; 2618 break; 2619 case AMDGPU_UCODE_ID_ISP: 2620 *type = GFX_FW_TYPE_ISP; 2621 break; 2622 case AMDGPU_UCODE_ID_MAXIMUM: 2623 default: 2624 return -EINVAL; 2625 } 2626 2627 return 0; 2628 } 2629 2630 static void psp_print_fw_hdr(struct psp_context *psp, 2631 struct amdgpu_firmware_info *ucode) 2632 { 2633 struct amdgpu_device *adev = psp->adev; 2634 struct common_firmware_header *hdr; 2635 2636 switch (ucode->ucode_id) { 2637 case AMDGPU_UCODE_ID_SDMA0: 2638 case AMDGPU_UCODE_ID_SDMA1: 2639 case AMDGPU_UCODE_ID_SDMA2: 2640 case AMDGPU_UCODE_ID_SDMA3: 2641 case AMDGPU_UCODE_ID_SDMA4: 2642 case AMDGPU_UCODE_ID_SDMA5: 2643 case AMDGPU_UCODE_ID_SDMA6: 2644 case AMDGPU_UCODE_ID_SDMA7: 2645 hdr = (struct common_firmware_header *) 2646 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2647 amdgpu_ucode_print_sdma_hdr(hdr); 2648 break; 2649 case AMDGPU_UCODE_ID_CP_CE: 2650 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2651 amdgpu_ucode_print_gfx_hdr(hdr); 2652 break; 2653 case AMDGPU_UCODE_ID_CP_PFP: 2654 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2655 amdgpu_ucode_print_gfx_hdr(hdr); 2656 break; 2657 case AMDGPU_UCODE_ID_CP_ME: 2658 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2659 amdgpu_ucode_print_gfx_hdr(hdr); 2660 break; 2661 case AMDGPU_UCODE_ID_CP_MEC1: 2662 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2663 amdgpu_ucode_print_gfx_hdr(hdr); 2664 break; 2665 case AMDGPU_UCODE_ID_RLC_G: 2666 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2667 amdgpu_ucode_print_rlc_hdr(hdr); 2668 break; 2669 case AMDGPU_UCODE_ID_SMC: 2670 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2671 amdgpu_ucode_print_smc_hdr(hdr); 2672 break; 2673 default: 2674 break; 2675 } 2676 } 2677 2678 static int psp_prep_load_ip_fw_cmd_buf(struct psp_context *psp, 2679 struct amdgpu_firmware_info *ucode, 2680 struct psp_gfx_cmd_resp *cmd) 2681 { 2682 int ret; 2683 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2684 2685 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2686 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2687 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2688 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2689 2690 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2691 if (ret) 2692 dev_err(psp->adev->dev, "Unknown firmware type\n"); 2693 2694 return ret; 2695 } 2696 2697 int psp_execute_ip_fw_load(struct psp_context *psp, 2698 struct amdgpu_firmware_info *ucode) 2699 { 2700 int ret = 0; 2701 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2702 2703 ret = psp_prep_load_ip_fw_cmd_buf(psp, ucode, cmd); 2704 if (!ret) { 2705 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2706 psp->fence_buf_mc_addr); 2707 } 2708 2709 release_psp_cmd_buf(psp); 2710 2711 return ret; 2712 } 2713 2714 static int psp_load_p2s_table(struct psp_context *psp) 2715 { 2716 int ret; 2717 struct amdgpu_device *adev = psp->adev; 2718 struct amdgpu_firmware_info *ucode = 2719 &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE]; 2720 2721 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2722 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 2723 return 0; 2724 2725 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 2726 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { 2727 uint32_t supp_vers = adev->flags & AMD_IS_APU ? 0x0036013D : 2728 0x0036003C; 2729 if (psp->sos.fw_version < supp_vers) 2730 return 0; 2731 } 2732 2733 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2734 return 0; 2735 2736 ret = psp_execute_ip_fw_load(psp, ucode); 2737 2738 return ret; 2739 } 2740 2741 static int psp_load_smu_fw(struct psp_context *psp) 2742 { 2743 int ret; 2744 struct amdgpu_device *adev = psp->adev; 2745 struct amdgpu_firmware_info *ucode = 2746 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2747 struct amdgpu_ras *ras = psp->ras_context.ras; 2748 2749 /* 2750 * Skip SMU FW reloading in case of using BACO for runpm only, 2751 * as SMU is always alive. 2752 */ 2753 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2754 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 2755 return 0; 2756 2757 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2758 return 0; 2759 2760 if ((amdgpu_in_reset(adev) && ras && adev->ras_enabled && 2761 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 2762 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 2)))) { 2763 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2764 if (ret) 2765 dev_err(adev->dev, "Failed to set MP1 state prepare for reload\n"); 2766 } 2767 2768 ret = psp_execute_ip_fw_load(psp, ucode); 2769 2770 if (ret) 2771 dev_err(adev->dev, "PSP load smu failed!\n"); 2772 2773 return ret; 2774 } 2775 2776 static bool fw_load_skip_check(struct psp_context *psp, 2777 struct amdgpu_firmware_info *ucode) 2778 { 2779 if (!ucode->fw || !ucode->ucode_size) 2780 return true; 2781 2782 if (ucode->ucode_id == AMDGPU_UCODE_ID_P2S_TABLE) 2783 return true; 2784 2785 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2786 (psp_smu_reload_quirk(psp) || 2787 psp->autoload_supported || 2788 psp->pmfw_centralized_cstate_management)) 2789 return true; 2790 2791 if (amdgpu_sriov_vf(psp->adev) && 2792 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 2793 return true; 2794 2795 if (psp->autoload_supported && 2796 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2797 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2798 /* skip mec JT when autoload is enabled */ 2799 return true; 2800 2801 return false; 2802 } 2803 2804 int psp_load_fw_list(struct psp_context *psp, 2805 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2806 { 2807 int ret = 0, i; 2808 struct amdgpu_firmware_info *ucode; 2809 2810 for (i = 0; i < ucode_count; ++i) { 2811 ucode = ucode_list[i]; 2812 psp_print_fw_hdr(psp, ucode); 2813 ret = psp_execute_ip_fw_load(psp, ucode); 2814 if (ret) 2815 return ret; 2816 } 2817 return ret; 2818 } 2819 2820 static int psp_load_non_psp_fw(struct psp_context *psp) 2821 { 2822 int i, ret; 2823 struct amdgpu_firmware_info *ucode; 2824 struct amdgpu_device *adev = psp->adev; 2825 2826 if (psp->autoload_supported && 2827 !psp->pmfw_centralized_cstate_management) { 2828 ret = psp_load_smu_fw(psp); 2829 if (ret) 2830 return ret; 2831 } 2832 2833 /* Load P2S table first if it's available */ 2834 psp_load_p2s_table(psp); 2835 2836 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2837 ucode = &adev->firmware.ucode[i]; 2838 2839 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2840 !fw_load_skip_check(psp, ucode)) { 2841 ret = psp_load_smu_fw(psp); 2842 if (ret) 2843 return ret; 2844 continue; 2845 } 2846 2847 if (fw_load_skip_check(psp, ucode)) 2848 continue; 2849 2850 if (psp->autoload_supported && 2851 (amdgpu_ip_version(adev, MP0_HWIP, 0) == 2852 IP_VERSION(11, 0, 7) || 2853 amdgpu_ip_version(adev, MP0_HWIP, 0) == 2854 IP_VERSION(11, 0, 11) || 2855 amdgpu_ip_version(adev, MP0_HWIP, 0) == 2856 IP_VERSION(11, 0, 12)) && 2857 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2858 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2859 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2860 /* PSP only receive one SDMA fw for sienna_cichlid, 2861 * as all four sdma fw are same 2862 */ 2863 continue; 2864 2865 psp_print_fw_hdr(psp, ucode); 2866 2867 ret = psp_execute_ip_fw_load(psp, ucode); 2868 if (ret) 2869 return ret; 2870 2871 /* Start rlc autoload after psp received all the gfx firmware */ 2872 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2873 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 2874 ret = psp_rlc_autoload_start(psp); 2875 if (ret) { 2876 dev_err(adev->dev, "Failed to start rlc autoload\n"); 2877 return ret; 2878 } 2879 } 2880 } 2881 2882 return 0; 2883 } 2884 2885 static int psp_load_fw(struct amdgpu_device *adev) 2886 { 2887 int ret; 2888 struct psp_context *psp = &adev->psp; 2889 2890 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2891 /* should not destroy ring, only stop */ 2892 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2893 } else { 2894 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2895 2896 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2897 if (ret) { 2898 dev_err(adev->dev, "PSP ring init failed!\n"); 2899 goto failed; 2900 } 2901 } 2902 2903 ret = psp_hw_start(psp); 2904 if (ret) 2905 goto failed; 2906 2907 ret = psp_load_non_psp_fw(psp); 2908 if (ret) 2909 goto failed1; 2910 2911 ret = psp_asd_initialize(psp); 2912 if (ret) { 2913 dev_err(adev->dev, "PSP load asd failed!\n"); 2914 goto failed1; 2915 } 2916 2917 ret = psp_rl_load(adev); 2918 if (ret) { 2919 dev_err(adev->dev, "PSP load RL failed!\n"); 2920 goto failed1; 2921 } 2922 2923 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2924 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2925 ret = psp_xgmi_initialize(psp, false, true); 2926 /* Warning the XGMI seesion initialize failure 2927 * Instead of stop driver initialization 2928 */ 2929 if (ret) 2930 dev_err(psp->adev->dev, 2931 "XGMI: Failed to initialize XGMI session\n"); 2932 } 2933 } 2934 2935 if (psp->ta_fw) { 2936 ret = psp_ras_initialize(psp); 2937 if (ret) 2938 dev_err(psp->adev->dev, 2939 "RAS: Failed to initialize RAS\n"); 2940 2941 ret = psp_hdcp_initialize(psp); 2942 if (ret) 2943 dev_err(psp->adev->dev, 2944 "HDCP: Failed to initialize HDCP\n"); 2945 2946 ret = psp_dtm_initialize(psp); 2947 if (ret) 2948 dev_err(psp->adev->dev, 2949 "DTM: Failed to initialize DTM\n"); 2950 2951 ret = psp_rap_initialize(psp); 2952 if (ret) 2953 dev_err(psp->adev->dev, 2954 "RAP: Failed to initialize RAP\n"); 2955 2956 ret = psp_securedisplay_initialize(psp); 2957 if (ret) 2958 dev_err(psp->adev->dev, 2959 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2960 } 2961 2962 return 0; 2963 2964 failed1: 2965 psp_free_shared_bufs(psp); 2966 failed: 2967 /* 2968 * all cleanup jobs (xgmi terminate, ras terminate, 2969 * ring destroy, cmd/fence/fw buffers destory, 2970 * psp->cmd destory) are delayed to psp_hw_fini 2971 */ 2972 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2973 return ret; 2974 } 2975 2976 static int psp_hw_init(void *handle) 2977 { 2978 int ret; 2979 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2980 2981 mutex_lock(&adev->firmware.mutex); 2982 /* 2983 * This sequence is just used on hw_init only once, no need on 2984 * resume. 2985 */ 2986 ret = amdgpu_ucode_init_bo(adev); 2987 if (ret) 2988 goto failed; 2989 2990 ret = psp_load_fw(adev); 2991 if (ret) { 2992 dev_err(adev->dev, "PSP firmware loading failed\n"); 2993 goto failed; 2994 } 2995 2996 mutex_unlock(&adev->firmware.mutex); 2997 return 0; 2998 2999 failed: 3000 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 3001 mutex_unlock(&adev->firmware.mutex); 3002 return -EINVAL; 3003 } 3004 3005 static int psp_hw_fini(void *handle) 3006 { 3007 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3008 struct psp_context *psp = &adev->psp; 3009 3010 if (psp->ta_fw) { 3011 psp_ras_terminate(psp); 3012 psp_securedisplay_terminate(psp); 3013 psp_rap_terminate(psp); 3014 psp_dtm_terminate(psp); 3015 psp_hdcp_terminate(psp); 3016 3017 if (adev->gmc.xgmi.num_physical_nodes > 1) 3018 psp_xgmi_terminate(psp); 3019 } 3020 3021 psp_asd_terminate(psp); 3022 psp_tmr_terminate(psp); 3023 3024 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 3025 3026 return 0; 3027 } 3028 3029 static int psp_suspend(void *handle) 3030 { 3031 int ret = 0; 3032 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3033 struct psp_context *psp = &adev->psp; 3034 3035 if (adev->gmc.xgmi.num_physical_nodes > 1 && 3036 psp->xgmi_context.context.initialized) { 3037 ret = psp_xgmi_terminate(psp); 3038 if (ret) { 3039 dev_err(adev->dev, "Failed to terminate xgmi ta\n"); 3040 goto out; 3041 } 3042 } 3043 3044 if (psp->ta_fw) { 3045 ret = psp_ras_terminate(psp); 3046 if (ret) { 3047 dev_err(adev->dev, "Failed to terminate ras ta\n"); 3048 goto out; 3049 } 3050 ret = psp_hdcp_terminate(psp); 3051 if (ret) { 3052 dev_err(adev->dev, "Failed to terminate hdcp ta\n"); 3053 goto out; 3054 } 3055 ret = psp_dtm_terminate(psp); 3056 if (ret) { 3057 dev_err(adev->dev, "Failed to terminate dtm ta\n"); 3058 goto out; 3059 } 3060 ret = psp_rap_terminate(psp); 3061 if (ret) { 3062 dev_err(adev->dev, "Failed to terminate rap ta\n"); 3063 goto out; 3064 } 3065 ret = psp_securedisplay_terminate(psp); 3066 if (ret) { 3067 dev_err(adev->dev, "Failed to terminate securedisplay ta\n"); 3068 goto out; 3069 } 3070 } 3071 3072 ret = psp_asd_terminate(psp); 3073 if (ret) { 3074 dev_err(adev->dev, "Failed to terminate asd\n"); 3075 goto out; 3076 } 3077 3078 ret = psp_tmr_terminate(psp); 3079 if (ret) { 3080 dev_err(adev->dev, "Failed to terminate tmr\n"); 3081 goto out; 3082 } 3083 3084 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 3085 if (ret) 3086 dev_err(adev->dev, "PSP ring stop failed\n"); 3087 3088 out: 3089 return ret; 3090 } 3091 3092 static int psp_resume(void *handle) 3093 { 3094 int ret; 3095 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3096 struct psp_context *psp = &adev->psp; 3097 3098 dev_info(adev->dev, "PSP is resuming...\n"); 3099 3100 if (psp->mem_train_ctx.enable_mem_training) { 3101 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 3102 if (ret) { 3103 dev_err(adev->dev, "Failed to process memory training!\n"); 3104 return ret; 3105 } 3106 } 3107 3108 mutex_lock(&adev->firmware.mutex); 3109 3110 ret = psp_hw_start(psp); 3111 if (ret) 3112 goto failed; 3113 3114 ret = psp_load_non_psp_fw(psp); 3115 if (ret) 3116 goto failed; 3117 3118 ret = psp_asd_initialize(psp); 3119 if (ret) { 3120 dev_err(adev->dev, "PSP load asd failed!\n"); 3121 goto failed; 3122 } 3123 3124 ret = psp_rl_load(adev); 3125 if (ret) { 3126 dev_err(adev->dev, "PSP load RL failed!\n"); 3127 goto failed; 3128 } 3129 3130 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3131 ret = psp_xgmi_initialize(psp, false, true); 3132 /* Warning the XGMI seesion initialize failure 3133 * Instead of stop driver initialization 3134 */ 3135 if (ret) 3136 dev_err(psp->adev->dev, 3137 "XGMI: Failed to initialize XGMI session\n"); 3138 } 3139 3140 if (psp->ta_fw) { 3141 ret = psp_ras_initialize(psp); 3142 if (ret) 3143 dev_err(psp->adev->dev, 3144 "RAS: Failed to initialize RAS\n"); 3145 3146 ret = psp_hdcp_initialize(psp); 3147 if (ret) 3148 dev_err(psp->adev->dev, 3149 "HDCP: Failed to initialize HDCP\n"); 3150 3151 ret = psp_dtm_initialize(psp); 3152 if (ret) 3153 dev_err(psp->adev->dev, 3154 "DTM: Failed to initialize DTM\n"); 3155 3156 ret = psp_rap_initialize(psp); 3157 if (ret) 3158 dev_err(psp->adev->dev, 3159 "RAP: Failed to initialize RAP\n"); 3160 3161 ret = psp_securedisplay_initialize(psp); 3162 if (ret) 3163 dev_err(psp->adev->dev, 3164 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3165 } 3166 3167 mutex_unlock(&adev->firmware.mutex); 3168 3169 return 0; 3170 3171 failed: 3172 dev_err(adev->dev, "PSP resume failed\n"); 3173 mutex_unlock(&adev->firmware.mutex); 3174 return ret; 3175 } 3176 3177 int psp_gpu_reset(struct amdgpu_device *adev) 3178 { 3179 int ret; 3180 3181 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 3182 return 0; 3183 3184 mutex_lock(&adev->psp.mutex); 3185 ret = psp_mode1_reset(&adev->psp); 3186 mutex_unlock(&adev->psp.mutex); 3187 3188 return ret; 3189 } 3190 3191 int psp_rlc_autoload_start(struct psp_context *psp) 3192 { 3193 int ret; 3194 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3195 3196 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 3197 3198 ret = psp_cmd_submit_buf(psp, NULL, cmd, 3199 psp->fence_buf_mc_addr); 3200 3201 release_psp_cmd_buf(psp); 3202 3203 return ret; 3204 } 3205 3206 int psp_ring_cmd_submit(struct psp_context *psp, 3207 uint64_t cmd_buf_mc_addr, 3208 uint64_t fence_mc_addr, 3209 int index) 3210 { 3211 unsigned int psp_write_ptr_reg = 0; 3212 struct psp_gfx_rb_frame *write_frame; 3213 struct psp_ring *ring = &psp->km_ring; 3214 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 3215 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 3216 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 3217 struct amdgpu_device *adev = psp->adev; 3218 uint32_t ring_size_dw = ring->ring_size / 4; 3219 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 3220 3221 /* KM (GPCOM) prepare write pointer */ 3222 psp_write_ptr_reg = psp_ring_get_wptr(psp); 3223 3224 /* Update KM RB frame pointer to new frame */ 3225 /* write_frame ptr increments by size of rb_frame in bytes */ 3226 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 3227 if ((psp_write_ptr_reg % ring_size_dw) == 0) 3228 write_frame = ring_buffer_start; 3229 else 3230 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 3231 /* Check invalid write_frame ptr address */ 3232 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 3233 dev_err(adev->dev, 3234 "ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 3235 ring_buffer_start, ring_buffer_end, write_frame); 3236 dev_err(adev->dev, 3237 "write_frame is pointing to address out of bounds\n"); 3238 return -EINVAL; 3239 } 3240 3241 /* Initialize KM RB frame */ 3242 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 3243 3244 /* Update KM RB frame */ 3245 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 3246 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 3247 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 3248 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 3249 write_frame->fence_value = index; 3250 amdgpu_device_flush_hdp(adev, NULL); 3251 3252 /* Update the write Pointer in DWORDs */ 3253 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 3254 psp_ring_set_wptr(psp, psp_write_ptr_reg); 3255 return 0; 3256 } 3257 3258 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 3259 { 3260 struct amdgpu_device *adev = psp->adev; 3261 const struct psp_firmware_header_v1_0 *asd_hdr; 3262 int err = 0; 3263 3264 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, "amdgpu/%s_asd.bin", chip_name); 3265 if (err) 3266 goto out; 3267 3268 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 3269 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 3270 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 3271 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 3272 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 3273 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 3274 return 0; 3275 out: 3276 amdgpu_ucode_release(&adev->psp.asd_fw); 3277 return err; 3278 } 3279 3280 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 3281 { 3282 struct amdgpu_device *adev = psp->adev; 3283 const struct psp_firmware_header_v1_0 *toc_hdr; 3284 int err = 0; 3285 3286 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, "amdgpu/%s_toc.bin", chip_name); 3287 if (err) 3288 goto out; 3289 3290 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 3291 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 3292 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 3293 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 3294 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 3295 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 3296 return 0; 3297 out: 3298 amdgpu_ucode_release(&adev->psp.toc_fw); 3299 return err; 3300 } 3301 3302 static int parse_sos_bin_descriptor(struct psp_context *psp, 3303 const struct psp_fw_bin_desc *desc, 3304 const struct psp_firmware_header_v2_0 *sos_hdr) 3305 { 3306 uint8_t *ucode_start_addr = NULL; 3307 3308 if (!psp || !desc || !sos_hdr) 3309 return -EINVAL; 3310 3311 ucode_start_addr = (uint8_t *)sos_hdr + 3312 le32_to_cpu(desc->offset_bytes) + 3313 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3314 3315 switch (desc->fw_type) { 3316 case PSP_FW_TYPE_PSP_SOS: 3317 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3318 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3319 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3320 psp->sos.start_addr = ucode_start_addr; 3321 break; 3322 case PSP_FW_TYPE_PSP_SYS_DRV: 3323 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3324 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3325 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3326 psp->sys.start_addr = ucode_start_addr; 3327 break; 3328 case PSP_FW_TYPE_PSP_KDB: 3329 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 3330 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 3331 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 3332 psp->kdb.start_addr = ucode_start_addr; 3333 break; 3334 case PSP_FW_TYPE_PSP_TOC: 3335 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3336 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3337 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3338 psp->toc.start_addr = ucode_start_addr; 3339 break; 3340 case PSP_FW_TYPE_PSP_SPL: 3341 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3342 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3343 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3344 psp->spl.start_addr = ucode_start_addr; 3345 break; 3346 case PSP_FW_TYPE_PSP_RL: 3347 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3348 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3349 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3350 psp->rl.start_addr = ucode_start_addr; 3351 break; 3352 case PSP_FW_TYPE_PSP_SOC_DRV: 3353 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3354 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3355 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3356 psp->soc_drv.start_addr = ucode_start_addr; 3357 break; 3358 case PSP_FW_TYPE_PSP_INTF_DRV: 3359 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3360 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3361 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3362 psp->intf_drv.start_addr = ucode_start_addr; 3363 break; 3364 case PSP_FW_TYPE_PSP_DBG_DRV: 3365 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3366 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3367 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3368 psp->dbg_drv.start_addr = ucode_start_addr; 3369 break; 3370 case PSP_FW_TYPE_PSP_RAS_DRV: 3371 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3372 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3373 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3374 psp->ras_drv.start_addr = ucode_start_addr; 3375 break; 3376 case PSP_FW_TYPE_PSP_IPKEYMGR_DRV: 3377 psp->ipkeymgr_drv.fw_version = le32_to_cpu(desc->fw_version); 3378 psp->ipkeymgr_drv.feature_version = le32_to_cpu(desc->fw_version); 3379 psp->ipkeymgr_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3380 psp->ipkeymgr_drv.start_addr = ucode_start_addr; 3381 break; 3382 default: 3383 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3384 break; 3385 } 3386 3387 return 0; 3388 } 3389 3390 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3391 { 3392 const struct psp_firmware_header_v1_0 *sos_hdr; 3393 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3394 uint8_t *ucode_array_start_addr; 3395 3396 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3397 ucode_array_start_addr = (uint8_t *)sos_hdr + 3398 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3399 3400 if (adev->gmc.xgmi.connected_to_cpu || 3401 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2))) { 3402 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3403 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3404 3405 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3406 adev->psp.sys.start_addr = ucode_array_start_addr; 3407 3408 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3409 adev->psp.sos.start_addr = ucode_array_start_addr + 3410 le32_to_cpu(sos_hdr->sos.offset_bytes); 3411 } else { 3412 /* Load alternate PSP SOS FW */ 3413 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3414 3415 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3416 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3417 3418 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3419 adev->psp.sys.start_addr = ucode_array_start_addr + 3420 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3421 3422 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3423 adev->psp.sos.start_addr = ucode_array_start_addr + 3424 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3425 } 3426 3427 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3428 dev_warn(adev->dev, "PSP SOS FW not available"); 3429 return -EINVAL; 3430 } 3431 3432 return 0; 3433 } 3434 3435 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 3436 { 3437 struct amdgpu_device *adev = psp->adev; 3438 const struct psp_firmware_header_v1_0 *sos_hdr; 3439 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3440 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3441 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3442 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3443 const struct psp_firmware_header_v2_1 *sos_hdr_v2_1; 3444 int fw_index, fw_bin_count, start_index = 0; 3445 const struct psp_fw_bin_desc *fw_bin; 3446 uint8_t *ucode_array_start_addr; 3447 int err = 0; 3448 3449 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, "amdgpu/%s_sos.bin", chip_name); 3450 if (err) 3451 goto out; 3452 3453 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3454 ucode_array_start_addr = (uint8_t *)sos_hdr + 3455 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3456 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3457 3458 switch (sos_hdr->header.header_version_major) { 3459 case 1: 3460 err = psp_init_sos_base_fw(adev); 3461 if (err) 3462 goto out; 3463 3464 if (sos_hdr->header.header_version_minor == 1) { 3465 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3466 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3467 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3468 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3469 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3470 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3471 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3472 } 3473 if (sos_hdr->header.header_version_minor == 2) { 3474 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3475 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3476 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3477 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3478 } 3479 if (sos_hdr->header.header_version_minor == 3) { 3480 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3481 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3482 adev->psp.toc.start_addr = ucode_array_start_addr + 3483 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3484 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3485 adev->psp.kdb.start_addr = ucode_array_start_addr + 3486 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3487 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3488 adev->psp.spl.start_addr = ucode_array_start_addr + 3489 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3490 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3491 adev->psp.rl.start_addr = ucode_array_start_addr + 3492 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3493 } 3494 break; 3495 case 2: 3496 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3497 3498 fw_bin_count = le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); 3499 3500 if (fw_bin_count >= UCODE_MAX_PSP_PACKAGING) { 3501 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3502 err = -EINVAL; 3503 goto out; 3504 } 3505 3506 if (sos_hdr_v2_0->header.header_version_minor == 1) { 3507 sos_hdr_v2_1 = (const struct psp_firmware_header_v2_1 *)adev->psp.sos_fw->data; 3508 3509 fw_bin = sos_hdr_v2_1->psp_fw_bin; 3510 3511 if (psp_is_aux_sos_load_required(psp)) 3512 start_index = le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 3513 else 3514 fw_bin_count -= le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 3515 3516 } else { 3517 fw_bin = sos_hdr_v2_0->psp_fw_bin; 3518 } 3519 3520 for (fw_index = start_index; fw_index < fw_bin_count; fw_index++) { 3521 err = parse_sos_bin_descriptor(psp, fw_bin + fw_index, 3522 sos_hdr_v2_0); 3523 if (err) 3524 goto out; 3525 } 3526 break; 3527 default: 3528 dev_err(adev->dev, 3529 "unsupported psp sos firmware\n"); 3530 err = -EINVAL; 3531 goto out; 3532 } 3533 3534 return 0; 3535 out: 3536 amdgpu_ucode_release(&adev->psp.sos_fw); 3537 3538 return err; 3539 } 3540 3541 static int parse_ta_bin_descriptor(struct psp_context *psp, 3542 const struct psp_fw_bin_desc *desc, 3543 const struct ta_firmware_header_v2_0 *ta_hdr) 3544 { 3545 uint8_t *ucode_start_addr = NULL; 3546 3547 if (!psp || !desc || !ta_hdr) 3548 return -EINVAL; 3549 3550 ucode_start_addr = (uint8_t *)ta_hdr + 3551 le32_to_cpu(desc->offset_bytes) + 3552 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3553 3554 switch (desc->fw_type) { 3555 case TA_FW_TYPE_PSP_ASD: 3556 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3557 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3558 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3559 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3560 break; 3561 case TA_FW_TYPE_PSP_XGMI: 3562 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3563 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3564 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3565 break; 3566 case TA_FW_TYPE_PSP_RAS: 3567 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3568 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3569 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3570 break; 3571 case TA_FW_TYPE_PSP_HDCP: 3572 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3573 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3574 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3575 break; 3576 case TA_FW_TYPE_PSP_DTM: 3577 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3578 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3579 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3580 break; 3581 case TA_FW_TYPE_PSP_RAP: 3582 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3583 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3584 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3585 break; 3586 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3587 psp->securedisplay_context.context.bin_desc.fw_version = 3588 le32_to_cpu(desc->fw_version); 3589 psp->securedisplay_context.context.bin_desc.size_bytes = 3590 le32_to_cpu(desc->size_bytes); 3591 psp->securedisplay_context.context.bin_desc.start_addr = 3592 ucode_start_addr; 3593 break; 3594 default: 3595 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3596 break; 3597 } 3598 3599 return 0; 3600 } 3601 3602 static int parse_ta_v1_microcode(struct psp_context *psp) 3603 { 3604 const struct ta_firmware_header_v1_0 *ta_hdr; 3605 struct amdgpu_device *adev = psp->adev; 3606 3607 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 3608 3609 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 3610 return -EINVAL; 3611 3612 adev->psp.xgmi_context.context.bin_desc.fw_version = 3613 le32_to_cpu(ta_hdr->xgmi.fw_version); 3614 adev->psp.xgmi_context.context.bin_desc.size_bytes = 3615 le32_to_cpu(ta_hdr->xgmi.size_bytes); 3616 adev->psp.xgmi_context.context.bin_desc.start_addr = 3617 (uint8_t *)ta_hdr + 3618 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3619 3620 adev->psp.ras_context.context.bin_desc.fw_version = 3621 le32_to_cpu(ta_hdr->ras.fw_version); 3622 adev->psp.ras_context.context.bin_desc.size_bytes = 3623 le32_to_cpu(ta_hdr->ras.size_bytes); 3624 adev->psp.ras_context.context.bin_desc.start_addr = 3625 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 3626 le32_to_cpu(ta_hdr->ras.offset_bytes); 3627 3628 adev->psp.hdcp_context.context.bin_desc.fw_version = 3629 le32_to_cpu(ta_hdr->hdcp.fw_version); 3630 adev->psp.hdcp_context.context.bin_desc.size_bytes = 3631 le32_to_cpu(ta_hdr->hdcp.size_bytes); 3632 adev->psp.hdcp_context.context.bin_desc.start_addr = 3633 (uint8_t *)ta_hdr + 3634 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3635 3636 adev->psp.dtm_context.context.bin_desc.fw_version = 3637 le32_to_cpu(ta_hdr->dtm.fw_version); 3638 adev->psp.dtm_context.context.bin_desc.size_bytes = 3639 le32_to_cpu(ta_hdr->dtm.size_bytes); 3640 adev->psp.dtm_context.context.bin_desc.start_addr = 3641 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3642 le32_to_cpu(ta_hdr->dtm.offset_bytes); 3643 3644 adev->psp.securedisplay_context.context.bin_desc.fw_version = 3645 le32_to_cpu(ta_hdr->securedisplay.fw_version); 3646 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 3647 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 3648 adev->psp.securedisplay_context.context.bin_desc.start_addr = 3649 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3650 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 3651 3652 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 3653 3654 return 0; 3655 } 3656 3657 static int parse_ta_v2_microcode(struct psp_context *psp) 3658 { 3659 const struct ta_firmware_header_v2_0 *ta_hdr; 3660 struct amdgpu_device *adev = psp->adev; 3661 int err = 0; 3662 int ta_index = 0; 3663 3664 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3665 3666 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 3667 return -EINVAL; 3668 3669 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3670 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3671 return -EINVAL; 3672 } 3673 3674 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3675 err = parse_ta_bin_descriptor(psp, 3676 &ta_hdr->ta_fw_bin[ta_index], 3677 ta_hdr); 3678 if (err) 3679 return err; 3680 } 3681 3682 return 0; 3683 } 3684 3685 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 3686 { 3687 const struct common_firmware_header *hdr; 3688 struct amdgpu_device *adev = psp->adev; 3689 int err; 3690 3691 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, "amdgpu/%s_ta.bin", chip_name); 3692 if (err) 3693 return err; 3694 3695 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 3696 switch (le16_to_cpu(hdr->header_version_major)) { 3697 case 1: 3698 err = parse_ta_v1_microcode(psp); 3699 break; 3700 case 2: 3701 err = parse_ta_v2_microcode(psp); 3702 break; 3703 default: 3704 dev_err(adev->dev, "unsupported TA header version\n"); 3705 err = -EINVAL; 3706 } 3707 3708 if (err) 3709 amdgpu_ucode_release(&adev->psp.ta_fw); 3710 3711 return err; 3712 } 3713 3714 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 3715 { 3716 struct amdgpu_device *adev = psp->adev; 3717 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3718 struct amdgpu_firmware_info *info = NULL; 3719 int err = 0; 3720 3721 if (!amdgpu_sriov_vf(adev)) { 3722 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3723 return -EINVAL; 3724 } 3725 3726 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, "amdgpu/%s_cap.bin", chip_name); 3727 if (err) { 3728 if (err == -ENODEV) { 3729 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3730 err = 0; 3731 goto out; 3732 } 3733 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3734 } 3735 3736 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3737 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3738 info->fw = adev->psp.cap_fw; 3739 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3740 adev->psp.cap_fw->data; 3741 adev->firmware.fw_size += ALIGN( 3742 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3743 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3744 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3745 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3746 3747 return 0; 3748 3749 out: 3750 amdgpu_ucode_release(&adev->psp.cap_fw); 3751 return err; 3752 } 3753 3754 int psp_config_sq_perfmon(struct psp_context *psp, 3755 uint32_t xcp_id, bool core_override_enable, 3756 bool reg_override_enable, bool perfmon_override_enable) 3757 { 3758 int ret; 3759 3760 if (amdgpu_sriov_vf(psp->adev)) 3761 return 0; 3762 3763 if (xcp_id > MAX_XCP) { 3764 dev_err(psp->adev->dev, "invalid xcp_id %d\n", xcp_id); 3765 return -EINVAL; 3766 } 3767 3768 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) { 3769 dev_err(psp->adev->dev, "Unsupported MP0 version 0x%x for CONFIG_SQ_PERFMON command\n", 3770 amdgpu_ip_version(psp->adev, MP0_HWIP, 0)); 3771 return -EINVAL; 3772 } 3773 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3774 3775 cmd->cmd_id = GFX_CMD_ID_CONFIG_SQ_PERFMON; 3776 cmd->cmd.config_sq_perfmon.gfx_xcp_mask = BIT_MASK(xcp_id); 3777 cmd->cmd.config_sq_perfmon.core_override = core_override_enable; 3778 cmd->cmd.config_sq_perfmon.reg_override = reg_override_enable; 3779 cmd->cmd.config_sq_perfmon.perfmon_override = perfmon_override_enable; 3780 3781 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 3782 if (ret) 3783 dev_warn(psp->adev->dev, "PSP failed to config sq: xcp%d core%d reg%d perfmon%d\n", 3784 xcp_id, core_override_enable, reg_override_enable, perfmon_override_enable); 3785 3786 release_psp_cmd_buf(psp); 3787 return ret; 3788 } 3789 3790 static int psp_set_clockgating_state(void *handle, 3791 enum amd_clockgating_state state) 3792 { 3793 return 0; 3794 } 3795 3796 static int psp_set_powergating_state(void *handle, 3797 enum amd_powergating_state state) 3798 { 3799 return 0; 3800 } 3801 3802 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3803 struct device_attribute *attr, 3804 char *buf) 3805 { 3806 struct drm_device *ddev = dev_get_drvdata(dev); 3807 struct amdgpu_device *adev = drm_to_adev(ddev); 3808 uint32_t fw_ver; 3809 int ret; 3810 3811 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3812 dev_info(adev->dev, "PSP block is not ready yet\n."); 3813 return -EBUSY; 3814 } 3815 3816 mutex_lock(&adev->psp.mutex); 3817 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3818 mutex_unlock(&adev->psp.mutex); 3819 3820 if (ret) { 3821 dev_err(adev->dev, "Failed to read USBC PD FW, err = %d\n", ret); 3822 return ret; 3823 } 3824 3825 return sysfs_emit(buf, "%x\n", fw_ver); 3826 } 3827 3828 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3829 struct device_attribute *attr, 3830 const char *buf, 3831 size_t count) 3832 { 3833 struct drm_device *ddev = dev_get_drvdata(dev); 3834 struct amdgpu_device *adev = drm_to_adev(ddev); 3835 int ret, idx; 3836 const struct firmware *usbc_pd_fw; 3837 struct amdgpu_bo *fw_buf_bo = NULL; 3838 uint64_t fw_pri_mc_addr; 3839 void *fw_pri_cpu_addr; 3840 3841 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3842 dev_err(adev->dev, "PSP block is not ready yet."); 3843 return -EBUSY; 3844 } 3845 3846 if (!drm_dev_enter(ddev, &idx)) 3847 return -ENODEV; 3848 3849 ret = amdgpu_ucode_request(adev, &usbc_pd_fw, "amdgpu/%s", buf); 3850 if (ret) 3851 goto fail; 3852 3853 /* LFB address which is aligned to 1MB boundary per PSP request */ 3854 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3855 AMDGPU_GEM_DOMAIN_VRAM | 3856 AMDGPU_GEM_DOMAIN_GTT, 3857 &fw_buf_bo, &fw_pri_mc_addr, 3858 &fw_pri_cpu_addr); 3859 if (ret) 3860 goto rel_buf; 3861 3862 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3863 3864 mutex_lock(&adev->psp.mutex); 3865 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3866 mutex_unlock(&adev->psp.mutex); 3867 3868 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3869 3870 rel_buf: 3871 amdgpu_ucode_release(&usbc_pd_fw); 3872 fail: 3873 if (ret) { 3874 dev_err(adev->dev, "Failed to load USBC PD FW, err = %d", ret); 3875 count = ret; 3876 } 3877 3878 drm_dev_exit(idx); 3879 return count; 3880 } 3881 3882 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3883 { 3884 int idx; 3885 3886 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3887 return; 3888 3889 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3890 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3891 3892 drm_dev_exit(idx); 3893 } 3894 3895 /** 3896 * DOC: usbc_pd_fw 3897 * Reading from this file will retrieve the USB-C PD firmware version. Writing to 3898 * this file will trigger the update process. 3899 */ 3900 static DEVICE_ATTR(usbc_pd_fw, 0644, 3901 psp_usbc_pd_fw_sysfs_read, 3902 psp_usbc_pd_fw_sysfs_write); 3903 3904 int is_psp_fw_valid(struct psp_bin_desc bin) 3905 { 3906 return bin.size_bytes; 3907 } 3908 3909 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 3910 struct bin_attribute *bin_attr, 3911 char *buffer, loff_t pos, size_t count) 3912 { 3913 struct device *dev = kobj_to_dev(kobj); 3914 struct drm_device *ddev = dev_get_drvdata(dev); 3915 struct amdgpu_device *adev = drm_to_adev(ddev); 3916 3917 adev->psp.vbflash_done = false; 3918 3919 /* Safeguard against memory drain */ 3920 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 3921 dev_err(adev->dev, "File size cannot exceed %u\n", AMD_VBIOS_FILE_MAX_SIZE_B); 3922 kvfree(adev->psp.vbflash_tmp_buf); 3923 adev->psp.vbflash_tmp_buf = NULL; 3924 adev->psp.vbflash_image_size = 0; 3925 return -ENOMEM; 3926 } 3927 3928 /* TODO Just allocate max for now and optimize to realloc later if needed */ 3929 if (!adev->psp.vbflash_tmp_buf) { 3930 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 3931 if (!adev->psp.vbflash_tmp_buf) 3932 return -ENOMEM; 3933 } 3934 3935 mutex_lock(&adev->psp.mutex); 3936 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 3937 adev->psp.vbflash_image_size += count; 3938 mutex_unlock(&adev->psp.mutex); 3939 3940 dev_dbg(adev->dev, "IFWI staged for update\n"); 3941 3942 return count; 3943 } 3944 3945 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 3946 struct bin_attribute *bin_attr, char *buffer, 3947 loff_t pos, size_t count) 3948 { 3949 struct device *dev = kobj_to_dev(kobj); 3950 struct drm_device *ddev = dev_get_drvdata(dev); 3951 struct amdgpu_device *adev = drm_to_adev(ddev); 3952 struct amdgpu_bo *fw_buf_bo = NULL; 3953 uint64_t fw_pri_mc_addr; 3954 void *fw_pri_cpu_addr; 3955 int ret; 3956 3957 if (adev->psp.vbflash_image_size == 0) 3958 return -EINVAL; 3959 3960 dev_dbg(adev->dev, "PSP IFWI flash process initiated\n"); 3961 3962 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 3963 AMDGPU_GPU_PAGE_SIZE, 3964 AMDGPU_GEM_DOMAIN_VRAM, 3965 &fw_buf_bo, 3966 &fw_pri_mc_addr, 3967 &fw_pri_cpu_addr); 3968 if (ret) 3969 goto rel_buf; 3970 3971 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 3972 3973 mutex_lock(&adev->psp.mutex); 3974 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 3975 mutex_unlock(&adev->psp.mutex); 3976 3977 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3978 3979 rel_buf: 3980 kvfree(adev->psp.vbflash_tmp_buf); 3981 adev->psp.vbflash_tmp_buf = NULL; 3982 adev->psp.vbflash_image_size = 0; 3983 3984 if (ret) { 3985 dev_err(adev->dev, "Failed to load IFWI, err = %d\n", ret); 3986 return ret; 3987 } 3988 3989 dev_dbg(adev->dev, "PSP IFWI flash process done\n"); 3990 return 0; 3991 } 3992 3993 /** 3994 * DOC: psp_vbflash 3995 * Writing to this file will stage an IFWI for update. Reading from this file 3996 * will trigger the update process. 3997 */ 3998 static struct bin_attribute psp_vbflash_bin_attr = { 3999 .attr = {.name = "psp_vbflash", .mode = 0660}, 4000 .size = 0, 4001 .write = amdgpu_psp_vbflash_write, 4002 .read = amdgpu_psp_vbflash_read, 4003 }; 4004 4005 /** 4006 * DOC: psp_vbflash_status 4007 * The status of the flash process. 4008 * 0: IFWI flash not complete. 4009 * 1: IFWI flash complete. 4010 */ 4011 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 4012 struct device_attribute *attr, 4013 char *buf) 4014 { 4015 struct drm_device *ddev = dev_get_drvdata(dev); 4016 struct amdgpu_device *adev = drm_to_adev(ddev); 4017 uint32_t vbflash_status; 4018 4019 vbflash_status = psp_vbflash_status(&adev->psp); 4020 if (!adev->psp.vbflash_done) 4021 vbflash_status = 0; 4022 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 4023 vbflash_status = 1; 4024 4025 return sysfs_emit(buf, "0x%x\n", vbflash_status); 4026 } 4027 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); 4028 4029 static struct bin_attribute *bin_flash_attrs[] = { 4030 &psp_vbflash_bin_attr, 4031 NULL 4032 }; 4033 4034 static struct attribute *flash_attrs[] = { 4035 &dev_attr_psp_vbflash_status.attr, 4036 &dev_attr_usbc_pd_fw.attr, 4037 NULL 4038 }; 4039 4040 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 4041 { 4042 struct device *dev = kobj_to_dev(kobj); 4043 struct drm_device *ddev = dev_get_drvdata(dev); 4044 struct amdgpu_device *adev = drm_to_adev(ddev); 4045 4046 if (attr == &dev_attr_usbc_pd_fw.attr) 4047 return adev->psp.sup_pd_fw_up ? 0660 : 0; 4048 4049 return adev->psp.sup_ifwi_up ? 0440 : 0; 4050 } 4051 4052 static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, 4053 struct bin_attribute *attr, 4054 int idx) 4055 { 4056 struct device *dev = kobj_to_dev(kobj); 4057 struct drm_device *ddev = dev_get_drvdata(dev); 4058 struct amdgpu_device *adev = drm_to_adev(ddev); 4059 4060 return adev->psp.sup_ifwi_up ? 0660 : 0; 4061 } 4062 4063 const struct attribute_group amdgpu_flash_attr_group = { 4064 .attrs = flash_attrs, 4065 .bin_attrs = bin_flash_attrs, 4066 .is_bin_visible = amdgpu_bin_flash_attr_is_visible, 4067 .is_visible = amdgpu_flash_attr_is_visible, 4068 }; 4069 4070 const struct amd_ip_funcs psp_ip_funcs = { 4071 .name = "psp", 4072 .early_init = psp_early_init, 4073 .late_init = NULL, 4074 .sw_init = psp_sw_init, 4075 .sw_fini = psp_sw_fini, 4076 .hw_init = psp_hw_init, 4077 .hw_fini = psp_hw_fini, 4078 .suspend = psp_suspend, 4079 .resume = psp_resume, 4080 .is_idle = NULL, 4081 .check_soft_reset = NULL, 4082 .wait_for_idle = NULL, 4083 .soft_reset = NULL, 4084 .set_clockgating_state = psp_set_clockgating_state, 4085 .set_powergating_state = psp_set_powergating_state, 4086 }; 4087 4088 const struct amdgpu_ip_block_version psp_v3_1_ip_block = { 4089 .type = AMD_IP_BLOCK_TYPE_PSP, 4090 .major = 3, 4091 .minor = 1, 4092 .rev = 0, 4093 .funcs = &psp_ip_funcs, 4094 }; 4095 4096 const struct amdgpu_ip_block_version psp_v10_0_ip_block = { 4097 .type = AMD_IP_BLOCK_TYPE_PSP, 4098 .major = 10, 4099 .minor = 0, 4100 .rev = 0, 4101 .funcs = &psp_ip_funcs, 4102 }; 4103 4104 const struct amdgpu_ip_block_version psp_v11_0_ip_block = { 4105 .type = AMD_IP_BLOCK_TYPE_PSP, 4106 .major = 11, 4107 .minor = 0, 4108 .rev = 0, 4109 .funcs = &psp_ip_funcs, 4110 }; 4111 4112 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 4113 .type = AMD_IP_BLOCK_TYPE_PSP, 4114 .major = 11, 4115 .minor = 0, 4116 .rev = 8, 4117 .funcs = &psp_ip_funcs, 4118 }; 4119 4120 const struct amdgpu_ip_block_version psp_v12_0_ip_block = { 4121 .type = AMD_IP_BLOCK_TYPE_PSP, 4122 .major = 12, 4123 .minor = 0, 4124 .rev = 0, 4125 .funcs = &psp_ip_funcs, 4126 }; 4127 4128 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 4129 .type = AMD_IP_BLOCK_TYPE_PSP, 4130 .major = 13, 4131 .minor = 0, 4132 .rev = 0, 4133 .funcs = &psp_ip_funcs, 4134 }; 4135 4136 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 4137 .type = AMD_IP_BLOCK_TYPE_PSP, 4138 .major = 13, 4139 .minor = 0, 4140 .rev = 4, 4141 .funcs = &psp_ip_funcs, 4142 }; 4143 4144 const struct amdgpu_ip_block_version psp_v14_0_ip_block = { 4145 .type = AMD_IP_BLOCK_TYPE_PSP, 4146 .major = 14, 4147 .minor = 0, 4148 .rev = 0, 4149 .funcs = &psp_ip_funcs, 4150 }; 4151