1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "soc15_common.h" 33 #include "psp_v3_1.h" 34 #include "psp_v10_0.h" 35 #include "psp_v11_0.h" 36 #include "psp_v11_0_8.h" 37 #include "psp_v12_0.h" 38 #include "psp_v13_0.h" 39 40 #include "amdgpu_ras.h" 41 #include "amdgpu_securedisplay.h" 42 #include "amdgpu_atomfirmware.h" 43 44 #include <drm/drm_drv.h> 45 46 static int psp_sysfs_init(struct amdgpu_device *adev); 47 static void psp_sysfs_fini(struct amdgpu_device *adev); 48 49 static int psp_load_smu_fw(struct psp_context *psp); 50 51 /* 52 * Due to DF Cstate management centralized to PMFW, the firmware 53 * loading sequence will be updated as below: 54 * - Load KDB 55 * - Load SYS_DRV 56 * - Load tOS 57 * - Load PMFW 58 * - Setup TMR 59 * - Load other non-psp fw 60 * - Load ASD 61 * - Load XGMI/RAS/HDCP/DTM TA if any 62 * 63 * This new sequence is required for 64 * - Arcturus and onwards 65 * - Navi12 and onwards 66 */ 67 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 68 { 69 struct amdgpu_device *adev = psp->adev; 70 71 psp->pmfw_centralized_cstate_management = false; 72 73 if (amdgpu_sriov_vf(adev)) 74 return; 75 76 if (adev->flags & AMD_IS_APU) 77 return; 78 79 if ((adev->asic_type >= CHIP_ARCTURUS) || 80 (adev->asic_type >= CHIP_NAVI12)) 81 psp->pmfw_centralized_cstate_management = true; 82 } 83 84 static int psp_early_init(void *handle) 85 { 86 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 87 struct psp_context *psp = &adev->psp; 88 89 switch (adev->asic_type) { 90 case CHIP_VEGA10: 91 case CHIP_VEGA12: 92 psp_v3_1_set_psp_funcs(psp); 93 psp->autoload_supported = false; 94 break; 95 case CHIP_RAVEN: 96 psp_v10_0_set_psp_funcs(psp); 97 psp->autoload_supported = false; 98 break; 99 case CHIP_VEGA20: 100 case CHIP_ARCTURUS: 101 psp_v11_0_set_psp_funcs(psp); 102 psp->autoload_supported = false; 103 break; 104 case CHIP_NAVI10: 105 case CHIP_NAVI14: 106 case CHIP_NAVI12: 107 case CHIP_SIENNA_CICHLID: 108 case CHIP_NAVY_FLOUNDER: 109 case CHIP_VANGOGH: 110 case CHIP_DIMGREY_CAVEFISH: 111 case CHIP_BEIGE_GOBY: 112 psp_v11_0_set_psp_funcs(psp); 113 psp->autoload_supported = true; 114 break; 115 case CHIP_RENOIR: 116 psp_v12_0_set_psp_funcs(psp); 117 break; 118 case CHIP_ALDEBARAN: 119 psp_v13_0_set_psp_funcs(psp); 120 break; 121 case CHIP_YELLOW_CARP: 122 psp_v13_0_set_psp_funcs(psp); 123 psp->autoload_supported = true; 124 break; 125 case CHIP_CYAN_SKILLFISH: 126 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 127 psp_v11_0_8_set_psp_funcs(psp); 128 psp->autoload_supported = false; 129 } 130 break; 131 default: 132 return -EINVAL; 133 } 134 135 psp->adev = adev; 136 137 psp_check_pmfw_centralized_cstate_management(psp); 138 139 return 0; 140 } 141 142 static void psp_memory_training_fini(struct psp_context *psp) 143 { 144 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 145 146 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 147 kfree(ctx->sys_cache); 148 ctx->sys_cache = NULL; 149 } 150 151 static int psp_memory_training_init(struct psp_context *psp) 152 { 153 int ret; 154 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 155 156 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 157 DRM_DEBUG("memory training is not supported!\n"); 158 return 0; 159 } 160 161 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 162 if (ctx->sys_cache == NULL) { 163 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 164 ret = -ENOMEM; 165 goto Err_out; 166 } 167 168 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 169 ctx->train_data_size, 170 ctx->p2c_train_data_offset, 171 ctx->c2p_train_data_offset); 172 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 173 return 0; 174 175 Err_out: 176 psp_memory_training_fini(psp); 177 return ret; 178 } 179 180 /* 181 * Helper funciton to query psp runtime database entry 182 * 183 * @adev: amdgpu_device pointer 184 * @entry_type: the type of psp runtime database entry 185 * @db_entry: runtime database entry pointer 186 * 187 * Return false if runtime database doesn't exit or entry is invalid 188 * or true if the specific database entry is found, and copy to @db_entry 189 */ 190 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 191 enum psp_runtime_entry_type entry_type, 192 void *db_entry) 193 { 194 uint64_t db_header_pos, db_dir_pos; 195 struct psp_runtime_data_header db_header = {0}; 196 struct psp_runtime_data_directory db_dir = {0}; 197 bool ret = false; 198 int i; 199 200 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 201 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 202 203 /* read runtime db header from vram */ 204 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 205 sizeof(struct psp_runtime_data_header), false); 206 207 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 208 /* runtime db doesn't exist, exit */ 209 dev_warn(adev->dev, "PSP runtime database doesn't exist\n"); 210 return false; 211 } 212 213 /* read runtime database entry from vram */ 214 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 215 sizeof(struct psp_runtime_data_directory), false); 216 217 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 218 /* invalid db entry count, exit */ 219 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 220 return false; 221 } 222 223 /* look up for requested entry type */ 224 for (i = 0; i < db_dir.entry_count && !ret; i++) { 225 if (db_dir.entry_list[i].entry_type == entry_type) { 226 switch (entry_type) { 227 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 228 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 229 /* invalid db entry size */ 230 dev_warn(adev->dev, "Invalid PSP runtime database entry size\n"); 231 return false; 232 } 233 /* read runtime database entry */ 234 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 235 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 236 ret = true; 237 break; 238 default: 239 ret = false; 240 break; 241 } 242 } 243 } 244 245 return ret; 246 } 247 248 static int psp_sw_init(void *handle) 249 { 250 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 251 struct psp_context *psp = &adev->psp; 252 int ret; 253 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 254 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 255 256 if (!amdgpu_sriov_vf(adev)) { 257 ret = psp_init_microcode(psp); 258 if (ret) { 259 DRM_ERROR("Failed to load psp firmware!\n"); 260 return ret; 261 } 262 } else if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_ALDEBARAN) { 263 ret = psp_init_ta_microcode(psp, "aldebaran"); 264 if (ret) { 265 DRM_ERROR("Failed to initialize ta microcode!\n"); 266 return ret; 267 } 268 } 269 270 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 271 if (psp_get_runtime_db_entry(adev, 272 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 273 &boot_cfg_entry)) { 274 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 275 if ((psp->boot_cfg_bitmask) & 276 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 277 /* If psp runtime database exists, then 278 * only enable two stage memory training 279 * when TWO_STAGE_DRAM_TRAINING bit is set 280 * in runtime database */ 281 mem_training_ctx->enable_mem_training = true; 282 } 283 284 } else { 285 /* If psp runtime database doesn't exist or 286 * is invalid, force enable two stage memory 287 * training */ 288 mem_training_ctx->enable_mem_training = true; 289 } 290 291 if (mem_training_ctx->enable_mem_training) { 292 ret = psp_memory_training_init(psp); 293 if (ret) { 294 DRM_ERROR("Failed to initialize memory training!\n"); 295 return ret; 296 } 297 298 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 299 if (ret) { 300 DRM_ERROR("Failed to process memory training!\n"); 301 return ret; 302 } 303 } 304 305 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) { 306 ret= psp_sysfs_init(adev); 307 if (ret) { 308 return ret; 309 } 310 } 311 312 return 0; 313 } 314 315 static int psp_sw_fini(void *handle) 316 { 317 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 318 319 psp_memory_training_fini(&adev->psp); 320 if (adev->psp.sos_fw) { 321 release_firmware(adev->psp.sos_fw); 322 adev->psp.sos_fw = NULL; 323 } 324 if (adev->psp.asd_fw) { 325 release_firmware(adev->psp.asd_fw); 326 adev->psp.asd_fw = NULL; 327 } 328 if (adev->psp.ta_fw) { 329 release_firmware(adev->psp.ta_fw); 330 adev->psp.ta_fw = NULL; 331 } 332 333 if (adev->asic_type == CHIP_NAVI10 || 334 adev->asic_type == CHIP_SIENNA_CICHLID) 335 psp_sysfs_fini(adev); 336 337 return 0; 338 } 339 340 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 341 uint32_t reg_val, uint32_t mask, bool check_changed) 342 { 343 uint32_t val; 344 int i; 345 struct amdgpu_device *adev = psp->adev; 346 347 if (psp->adev->no_hw_access) 348 return 0; 349 350 for (i = 0; i < adev->usec_timeout; i++) { 351 val = RREG32(reg_index); 352 if (check_changed) { 353 if (val != reg_val) 354 return 0; 355 } else { 356 if ((val & mask) == reg_val) 357 return 0; 358 } 359 udelay(1); 360 } 361 362 return -ETIME; 363 } 364 365 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 366 { 367 switch (cmd_id) { 368 case GFX_CMD_ID_LOAD_TA: 369 return "LOAD_TA"; 370 case GFX_CMD_ID_UNLOAD_TA: 371 return "UNLOAD_TA"; 372 case GFX_CMD_ID_INVOKE_CMD: 373 return "INVOKE_CMD"; 374 case GFX_CMD_ID_LOAD_ASD: 375 return "LOAD_ASD"; 376 case GFX_CMD_ID_SETUP_TMR: 377 return "SETUP_TMR"; 378 case GFX_CMD_ID_LOAD_IP_FW: 379 return "LOAD_IP_FW"; 380 case GFX_CMD_ID_DESTROY_TMR: 381 return "DESTROY_TMR"; 382 case GFX_CMD_ID_SAVE_RESTORE: 383 return "SAVE_RESTORE_IP_FW"; 384 case GFX_CMD_ID_SETUP_VMR: 385 return "SETUP_VMR"; 386 case GFX_CMD_ID_DESTROY_VMR: 387 return "DESTROY_VMR"; 388 case GFX_CMD_ID_PROG_REG: 389 return "PROG_REG"; 390 case GFX_CMD_ID_GET_FW_ATTESTATION: 391 return "GET_FW_ATTESTATION"; 392 case GFX_CMD_ID_LOAD_TOC: 393 return "ID_LOAD_TOC"; 394 case GFX_CMD_ID_AUTOLOAD_RLC: 395 return "AUTOLOAD_RLC"; 396 case GFX_CMD_ID_BOOT_CFG: 397 return "BOOT_CFG"; 398 default: 399 return "UNKNOWN CMD"; 400 } 401 } 402 403 static int 404 psp_cmd_submit_buf(struct psp_context *psp, 405 struct amdgpu_firmware_info *ucode, 406 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 407 { 408 int ret; 409 int index, idx; 410 int timeout = 20000; 411 bool ras_intr = false; 412 bool skip_unsupport = false; 413 414 if (psp->adev->no_hw_access) 415 return 0; 416 417 if (!drm_dev_enter(&psp->adev->ddev, &idx)) 418 return 0; 419 420 mutex_lock(&psp->mutex); 421 422 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 423 424 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 425 426 index = atomic_inc_return(&psp->fence_value); 427 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 428 if (ret) { 429 atomic_dec(&psp->fence_value); 430 goto exit; 431 } 432 433 amdgpu_device_invalidate_hdp(psp->adev, NULL); 434 while (*((unsigned int *)psp->fence_buf) != index) { 435 if (--timeout == 0) 436 break; 437 /* 438 * Shouldn't wait for timeout when err_event_athub occurs, 439 * because gpu reset thread triggered and lock resource should 440 * be released for psp resume sequence. 441 */ 442 ras_intr = amdgpu_ras_intr_triggered(); 443 if (ras_intr) 444 break; 445 usleep_range(10, 100); 446 amdgpu_device_invalidate_hdp(psp->adev, NULL); 447 } 448 449 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 450 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 451 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 452 453 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 454 455 /* In some cases, psp response status is not 0 even there is no 456 * problem while the command is submitted. Some version of PSP FW 457 * doesn't write 0 to that field. 458 * So here we would like to only print a warning instead of an error 459 * during psp initialization to avoid breaking hw_init and it doesn't 460 * return -EINVAL. 461 */ 462 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 463 if (ucode) 464 DRM_WARN("failed to load ucode (%s) ", 465 amdgpu_ucode_name(ucode->ucode_id)); 466 DRM_WARN("psp gfx command (%s) failed and response status is (0x%X)\n", 467 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), 468 psp->cmd_buf_mem->resp.status); 469 if (!timeout) { 470 ret = -EINVAL; 471 goto exit; 472 } 473 } 474 475 if (ucode) { 476 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 477 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 478 } 479 480 exit: 481 mutex_unlock(&psp->mutex); 482 drm_dev_exit(idx); 483 return ret; 484 } 485 486 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 487 struct psp_gfx_cmd_resp *cmd, 488 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 489 { 490 struct amdgpu_device *adev = psp->adev; 491 uint32_t size = amdgpu_bo_size(tmr_bo); 492 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 493 494 if (amdgpu_sriov_vf(psp->adev)) 495 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 496 else 497 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 498 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 499 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 500 cmd->cmd.cmd_setup_tmr.buf_size = size; 501 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 502 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 503 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 504 } 505 506 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 507 uint64_t pri_buf_mc, uint32_t size) 508 { 509 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 510 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 511 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 512 cmd->cmd.cmd_load_toc.toc_size = size; 513 } 514 515 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 516 static int psp_load_toc(struct psp_context *psp, 517 uint32_t *tmr_size) 518 { 519 int ret; 520 struct psp_gfx_cmd_resp *cmd; 521 522 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 523 if (!cmd) 524 return -ENOMEM; 525 /* Copy toc to psp firmware private buffer */ 526 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 527 528 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 529 530 ret = psp_cmd_submit_buf(psp, NULL, cmd, 531 psp->fence_buf_mc_addr); 532 if (!ret) 533 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 534 kfree(cmd); 535 return ret; 536 } 537 538 /* Set up Trusted Memory Region */ 539 static int psp_tmr_init(struct psp_context *psp) 540 { 541 int ret; 542 int tmr_size; 543 void *tmr_buf; 544 void **pptr; 545 546 /* 547 * According to HW engineer, they prefer the TMR address be "naturally 548 * aligned" , e.g. the start address be an integer divide of TMR size. 549 * 550 * Note: this memory need be reserved till the driver 551 * uninitializes. 552 */ 553 tmr_size = PSP_TMR_SIZE(psp->adev); 554 555 /* For ASICs support RLC autoload, psp will parse the toc 556 * and calculate the total size of TMR needed */ 557 if (!amdgpu_sriov_vf(psp->adev) && 558 psp->toc.start_addr && 559 psp->toc.size_bytes && 560 psp->fw_pri_buf) { 561 ret = psp_load_toc(psp, &tmr_size); 562 if (ret) { 563 DRM_ERROR("Failed to load toc\n"); 564 return ret; 565 } 566 } 567 568 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 569 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 570 AMDGPU_GEM_DOMAIN_VRAM, 571 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 572 573 return ret; 574 } 575 576 static bool psp_skip_tmr(struct psp_context *psp) 577 { 578 switch (psp->adev->asic_type) { 579 case CHIP_NAVI12: 580 case CHIP_SIENNA_CICHLID: 581 case CHIP_ALDEBARAN: 582 return true; 583 default: 584 return false; 585 } 586 } 587 588 static int psp_tmr_load(struct psp_context *psp) 589 { 590 int ret; 591 struct psp_gfx_cmd_resp *cmd; 592 593 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 594 * Already set up by host driver. 595 */ 596 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 597 return 0; 598 599 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 600 if (!cmd) 601 return -ENOMEM; 602 603 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 604 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 605 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 606 607 ret = psp_cmd_submit_buf(psp, NULL, cmd, 608 psp->fence_buf_mc_addr); 609 610 kfree(cmd); 611 612 return ret; 613 } 614 615 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 616 struct psp_gfx_cmd_resp *cmd) 617 { 618 if (amdgpu_sriov_vf(psp->adev)) 619 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 620 else 621 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 622 } 623 624 static int psp_tmr_unload(struct psp_context *psp) 625 { 626 int ret; 627 struct psp_gfx_cmd_resp *cmd; 628 629 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 630 if (!cmd) 631 return -ENOMEM; 632 633 psp_prep_tmr_unload_cmd_buf(psp, cmd); 634 DRM_INFO("free PSP TMR buffer\n"); 635 636 ret = psp_cmd_submit_buf(psp, NULL, cmd, 637 psp->fence_buf_mc_addr); 638 639 kfree(cmd); 640 641 return ret; 642 } 643 644 static int psp_tmr_terminate(struct psp_context *psp) 645 { 646 int ret; 647 void *tmr_buf; 648 void **pptr; 649 650 ret = psp_tmr_unload(psp); 651 if (ret) 652 return ret; 653 654 /* free TMR memory buffer */ 655 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 656 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 657 658 return 0; 659 } 660 661 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 662 uint64_t *output_ptr) 663 { 664 int ret; 665 struct psp_gfx_cmd_resp *cmd; 666 667 if (!output_ptr) 668 return -EINVAL; 669 670 if (amdgpu_sriov_vf(psp->adev)) 671 return 0; 672 673 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 674 if (!cmd) 675 return -ENOMEM; 676 677 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 678 679 ret = psp_cmd_submit_buf(psp, NULL, cmd, 680 psp->fence_buf_mc_addr); 681 682 if (!ret) { 683 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 684 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 685 } 686 687 kfree(cmd); 688 689 return ret; 690 } 691 692 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 693 { 694 struct psp_context *psp = &adev->psp; 695 struct psp_gfx_cmd_resp *cmd = psp->cmd; 696 int ret; 697 698 if (amdgpu_sriov_vf(adev)) 699 return 0; 700 701 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 702 703 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 704 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 705 706 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 707 if (!ret) { 708 *boot_cfg = 709 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 710 } 711 712 return ret; 713 } 714 715 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 716 { 717 struct psp_context *psp = &adev->psp; 718 struct psp_gfx_cmd_resp *cmd = psp->cmd; 719 720 if (amdgpu_sriov_vf(adev)) 721 return 0; 722 723 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 724 725 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 726 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 727 cmd->cmd.boot_cfg.boot_config = boot_cfg; 728 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 729 730 return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 731 } 732 733 static int psp_rl_load(struct amdgpu_device *adev) 734 { 735 struct psp_context *psp = &adev->psp; 736 struct psp_gfx_cmd_resp *cmd = psp->cmd; 737 738 if (!is_psp_fw_valid(psp->rl)) 739 return 0; 740 741 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 742 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 743 744 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 745 746 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 747 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 748 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 749 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 750 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 751 752 return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 753 } 754 755 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 756 uint64_t asd_mc, uint32_t size) 757 { 758 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 759 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 760 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 761 cmd->cmd.cmd_load_ta.app_len = size; 762 763 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0; 764 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0; 765 cmd->cmd.cmd_load_ta.cmd_buf_len = 0; 766 } 767 768 static int psp_asd_load(struct psp_context *psp) 769 { 770 int ret; 771 struct psp_gfx_cmd_resp *cmd; 772 773 /* If PSP version doesn't match ASD version, asd loading will be failed. 774 * add workaround to bypass it for sriov now. 775 * TODO: add version check to make it common 776 */ 777 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_ucode_size) 778 return 0; 779 780 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 781 if (!cmd) 782 return -ENOMEM; 783 784 psp_copy_fw(psp, psp->asd_start_addr, psp->asd_ucode_size); 785 786 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 787 psp->asd_ucode_size); 788 789 ret = psp_cmd_submit_buf(psp, NULL, cmd, 790 psp->fence_buf_mc_addr); 791 if (!ret) { 792 psp->asd_context.asd_initialized = true; 793 psp->asd_context.session_id = cmd->resp.session_id; 794 } 795 796 kfree(cmd); 797 798 return ret; 799 } 800 801 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 802 uint32_t session_id) 803 { 804 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 805 cmd->cmd.cmd_unload_ta.session_id = session_id; 806 } 807 808 static int psp_asd_unload(struct psp_context *psp) 809 { 810 int ret; 811 struct psp_gfx_cmd_resp *cmd; 812 813 if (amdgpu_sriov_vf(psp->adev)) 814 return 0; 815 816 if (!psp->asd_context.asd_initialized) 817 return 0; 818 819 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 820 if (!cmd) 821 return -ENOMEM; 822 823 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id); 824 825 ret = psp_cmd_submit_buf(psp, NULL, cmd, 826 psp->fence_buf_mc_addr); 827 if (!ret) 828 psp->asd_context.asd_initialized = false; 829 830 kfree(cmd); 831 832 return ret; 833 } 834 835 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 836 uint32_t id, uint32_t value) 837 { 838 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 839 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 840 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 841 } 842 843 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 844 uint32_t value) 845 { 846 struct psp_gfx_cmd_resp *cmd = NULL; 847 int ret = 0; 848 849 if (reg >= PSP_REG_LAST) 850 return -EINVAL; 851 852 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 853 if (!cmd) 854 return -ENOMEM; 855 856 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 857 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 858 if (ret) 859 DRM_ERROR("PSP failed to program reg id %d", reg); 860 861 kfree(cmd); 862 return ret; 863 } 864 865 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 866 uint64_t ta_bin_mc, 867 uint32_t ta_bin_size, 868 uint64_t ta_shared_mc, 869 uint32_t ta_shared_size) 870 { 871 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 872 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 873 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 874 cmd->cmd.cmd_load_ta.app_len = ta_bin_size; 875 876 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc); 877 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc); 878 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size; 879 } 880 881 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 882 { 883 int ret; 884 885 /* 886 * Allocate 16k memory aligned to 4k from Frame Buffer (local 887 * physical) for xgmi ta <-> Driver 888 */ 889 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 890 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 891 &psp->xgmi_context.xgmi_shared_bo, 892 &psp->xgmi_context.xgmi_shared_mc_addr, 893 &psp->xgmi_context.xgmi_shared_buf); 894 895 return ret; 896 } 897 898 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 899 uint32_t ta_cmd_id, 900 uint32_t session_id) 901 { 902 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 903 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 904 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 905 } 906 907 static int psp_ta_invoke(struct psp_context *psp, 908 uint32_t ta_cmd_id, 909 uint32_t session_id) 910 { 911 int ret; 912 struct psp_gfx_cmd_resp *cmd; 913 914 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 915 if (!cmd) 916 return -ENOMEM; 917 918 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id); 919 920 ret = psp_cmd_submit_buf(psp, NULL, cmd, 921 psp->fence_buf_mc_addr); 922 923 kfree(cmd); 924 925 return ret; 926 } 927 928 static int psp_xgmi_load(struct psp_context *psp) 929 { 930 int ret; 931 struct psp_gfx_cmd_resp *cmd; 932 933 /* 934 * TODO: bypass the loading in sriov for now 935 */ 936 937 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 938 if (!cmd) 939 return -ENOMEM; 940 941 psp_copy_fw(psp, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 942 943 psp_prep_ta_load_cmd_buf(cmd, 944 psp->fw_pri_mc_addr, 945 psp->ta_xgmi_ucode_size, 946 psp->xgmi_context.xgmi_shared_mc_addr, 947 PSP_XGMI_SHARED_MEM_SIZE); 948 949 ret = psp_cmd_submit_buf(psp, NULL, cmd, 950 psp->fence_buf_mc_addr); 951 952 if (!ret) { 953 psp->xgmi_context.initialized = 1; 954 psp->xgmi_context.session_id = cmd->resp.session_id; 955 } 956 957 kfree(cmd); 958 959 return ret; 960 } 961 962 static int psp_xgmi_unload(struct psp_context *psp) 963 { 964 int ret; 965 struct psp_gfx_cmd_resp *cmd; 966 struct amdgpu_device *adev = psp->adev; 967 968 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 969 if (adev->asic_type == CHIP_ARCTURUS || 970 (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu)) 971 return 0; 972 973 /* 974 * TODO: bypass the unloading in sriov for now 975 */ 976 977 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 978 if (!cmd) 979 return -ENOMEM; 980 981 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 982 983 ret = psp_cmd_submit_buf(psp, NULL, cmd, 984 psp->fence_buf_mc_addr); 985 986 kfree(cmd); 987 988 return ret; 989 } 990 991 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 992 { 993 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id); 994 } 995 996 int psp_xgmi_terminate(struct psp_context *psp) 997 { 998 int ret; 999 1000 if (!psp->xgmi_context.initialized) 1001 return 0; 1002 1003 ret = psp_xgmi_unload(psp); 1004 if (ret) 1005 return ret; 1006 1007 psp->xgmi_context.initialized = 0; 1008 1009 /* free xgmi shared memory */ 1010 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 1011 &psp->xgmi_context.xgmi_shared_mc_addr, 1012 &psp->xgmi_context.xgmi_shared_buf); 1013 1014 return 0; 1015 } 1016 1017 int psp_xgmi_initialize(struct psp_context *psp) 1018 { 1019 struct ta_xgmi_shared_memory *xgmi_cmd; 1020 int ret; 1021 1022 if (!psp->adev->psp.ta_fw || 1023 !psp->adev->psp.ta_xgmi_ucode_size || 1024 !psp->adev->psp.ta_xgmi_start_addr) 1025 return -ENOENT; 1026 1027 if (!psp->xgmi_context.initialized) { 1028 ret = psp_xgmi_init_shared_buf(psp); 1029 if (ret) 1030 return ret; 1031 } 1032 1033 /* Load XGMI TA */ 1034 ret = psp_xgmi_load(psp); 1035 if (ret) 1036 return ret; 1037 1038 /* Initialize XGMI session */ 1039 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 1040 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1041 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1042 1043 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1044 1045 return ret; 1046 } 1047 1048 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1049 { 1050 struct ta_xgmi_shared_memory *xgmi_cmd; 1051 int ret; 1052 1053 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 1054 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1055 1056 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1057 1058 /* Invoke xgmi ta to get hive id */ 1059 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1060 if (ret) 1061 return ret; 1062 1063 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1064 1065 return 0; 1066 } 1067 1068 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1069 { 1070 struct ta_xgmi_shared_memory *xgmi_cmd; 1071 int ret; 1072 1073 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 1074 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1075 1076 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1077 1078 /* Invoke xgmi ta to get the node id */ 1079 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1080 if (ret) 1081 return ret; 1082 1083 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1084 1085 return 0; 1086 } 1087 1088 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1089 { 1090 return psp->adev->asic_type == CHIP_ALDEBARAN && 1091 psp->ta_xgmi_ucode_version >= 0x2000000b; 1092 } 1093 1094 int psp_xgmi_get_topology_info(struct psp_context *psp, 1095 int number_devices, 1096 struct psp_xgmi_topology_info *topology) 1097 { 1098 struct ta_xgmi_shared_memory *xgmi_cmd; 1099 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1100 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1101 int i; 1102 int ret; 1103 1104 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1105 return -EINVAL; 1106 1107 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 1108 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1109 1110 /* Fill in the shared memory with topology information as input */ 1111 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1112 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1113 topology_info_input->num_nodes = number_devices; 1114 1115 for (i = 0; i < topology_info_input->num_nodes; i++) { 1116 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1117 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1118 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1119 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1120 } 1121 1122 /* Invoke xgmi ta to get the topology information */ 1123 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1124 if (ret) 1125 return ret; 1126 1127 /* Read the output topology information from the shared memory */ 1128 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1129 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1130 for (i = 0; i < topology->num_nodes; i++) { 1131 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1132 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1133 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 1134 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 1135 } 1136 1137 /* Invoke xgmi ta again to get the link information */ 1138 if (psp_xgmi_peer_link_info_supported(psp)) { 1139 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1140 1141 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1142 1143 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1144 1145 if (ret) 1146 return ret; 1147 1148 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1149 for (i = 0; i < topology->num_nodes; i++) 1150 topology->nodes[i].num_links = 1151 link_info_output->nodes[i].num_links; 1152 } 1153 1154 return 0; 1155 } 1156 1157 int psp_xgmi_set_topology_info(struct psp_context *psp, 1158 int number_devices, 1159 struct psp_xgmi_topology_info *topology) 1160 { 1161 struct ta_xgmi_shared_memory *xgmi_cmd; 1162 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1163 int i; 1164 1165 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1166 return -EINVAL; 1167 1168 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 1169 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1170 1171 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1172 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1173 topology_info_input->num_nodes = number_devices; 1174 1175 for (i = 0; i < topology_info_input->num_nodes; i++) { 1176 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1177 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1178 topology_info_input->nodes[i].is_sharing_enabled = 1; 1179 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1180 } 1181 1182 /* Invoke xgmi ta to set topology information */ 1183 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1184 } 1185 1186 // ras begin 1187 static int psp_ras_init_shared_buf(struct psp_context *psp) 1188 { 1189 int ret; 1190 1191 /* 1192 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1193 * physical) for ras ta <-> Driver 1194 */ 1195 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 1196 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1197 &psp->ras.ras_shared_bo, 1198 &psp->ras.ras_shared_mc_addr, 1199 &psp->ras.ras_shared_buf); 1200 1201 return ret; 1202 } 1203 1204 static int psp_ras_load(struct psp_context *psp) 1205 { 1206 int ret; 1207 struct psp_gfx_cmd_resp *cmd; 1208 struct ta_ras_shared_memory *ras_cmd; 1209 1210 /* 1211 * TODO: bypass the loading in sriov for now 1212 */ 1213 if (amdgpu_sriov_vf(psp->adev)) 1214 return 0; 1215 1216 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1217 if (!cmd) 1218 return -ENOMEM; 1219 1220 psp_copy_fw(psp, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 1221 1222 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1223 1224 if (psp->adev->gmc.xgmi.connected_to_cpu) 1225 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1226 else 1227 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1228 1229 psp_prep_ta_load_cmd_buf(cmd, 1230 psp->fw_pri_mc_addr, 1231 psp->ta_ras_ucode_size, 1232 psp->ras.ras_shared_mc_addr, 1233 PSP_RAS_SHARED_MEM_SIZE); 1234 1235 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1236 psp->fence_buf_mc_addr); 1237 1238 if (!ret) { 1239 psp->ras.session_id = cmd->resp.session_id; 1240 1241 if (!ras_cmd->ras_status) 1242 psp->ras.ras_initialized = true; 1243 else 1244 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1245 } 1246 1247 if (ret || ras_cmd->ras_status) 1248 amdgpu_ras_fini(psp->adev); 1249 1250 kfree(cmd); 1251 1252 return ret; 1253 } 1254 1255 static int psp_ras_unload(struct psp_context *psp) 1256 { 1257 int ret; 1258 struct psp_gfx_cmd_resp *cmd; 1259 1260 /* 1261 * TODO: bypass the unloading in sriov for now 1262 */ 1263 if (amdgpu_sriov_vf(psp->adev)) 1264 return 0; 1265 1266 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1267 if (!cmd) 1268 return -ENOMEM; 1269 1270 psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id); 1271 1272 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1273 psp->fence_buf_mc_addr); 1274 1275 kfree(cmd); 1276 1277 return ret; 1278 } 1279 1280 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1281 { 1282 struct ta_ras_shared_memory *ras_cmd; 1283 int ret; 1284 1285 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1286 1287 /* 1288 * TODO: bypass the loading in sriov for now 1289 */ 1290 if (amdgpu_sriov_vf(psp->adev)) 1291 return 0; 1292 1293 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id); 1294 1295 if (amdgpu_ras_intr_triggered()) 1296 return ret; 1297 1298 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1299 { 1300 DRM_WARN("RAS: Unsupported Interface"); 1301 return -EINVAL; 1302 } 1303 1304 if (!ret) { 1305 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1306 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1307 1308 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1309 } 1310 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1311 dev_warn(psp->adev->dev, 1312 "RAS internal register access blocked\n"); 1313 } 1314 1315 return ret; 1316 } 1317 1318 static int psp_ras_status_to_errno(struct amdgpu_device *adev, 1319 enum ta_ras_status ras_status) 1320 { 1321 int ret = -EINVAL; 1322 1323 switch (ras_status) { 1324 case TA_RAS_STATUS__SUCCESS: 1325 ret = 0; 1326 break; 1327 case TA_RAS_STATUS__RESET_NEEDED: 1328 ret = -EAGAIN; 1329 break; 1330 case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE: 1331 dev_warn(adev->dev, "RAS WARN: ras function unavailable\n"); 1332 break; 1333 case TA_RAS_STATUS__ERROR_ASD_READ_WRITE: 1334 dev_warn(adev->dev, "RAS WARN: asd read or write failed\n"); 1335 break; 1336 default: 1337 dev_err(adev->dev, "RAS ERROR: ras function failed ret 0x%X\n", ret); 1338 } 1339 1340 return ret; 1341 } 1342 1343 int psp_ras_enable_features(struct psp_context *psp, 1344 union ta_ras_cmd_input *info, bool enable) 1345 { 1346 struct ta_ras_shared_memory *ras_cmd; 1347 int ret; 1348 1349 if (!psp->ras.ras_initialized) 1350 return -EINVAL; 1351 1352 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1353 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1354 1355 if (enable) 1356 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1357 else 1358 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1359 1360 ras_cmd->ras_in_message = *info; 1361 1362 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1363 if (ret) 1364 return -EINVAL; 1365 1366 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status); 1367 } 1368 1369 static int psp_ras_terminate(struct psp_context *psp) 1370 { 1371 int ret; 1372 1373 /* 1374 * TODO: bypass the terminate in sriov for now 1375 */ 1376 if (amdgpu_sriov_vf(psp->adev)) 1377 return 0; 1378 1379 if (!psp->ras.ras_initialized) 1380 return 0; 1381 1382 ret = psp_ras_unload(psp); 1383 if (ret) 1384 return ret; 1385 1386 psp->ras.ras_initialized = false; 1387 1388 /* free ras shared memory */ 1389 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 1390 &psp->ras.ras_shared_mc_addr, 1391 &psp->ras.ras_shared_buf); 1392 1393 return 0; 1394 } 1395 1396 static int psp_ras_initialize(struct psp_context *psp) 1397 { 1398 int ret; 1399 uint32_t boot_cfg = 0xFF; 1400 struct amdgpu_device *adev = psp->adev; 1401 1402 /* 1403 * TODO: bypass the initialize in sriov for now 1404 */ 1405 if (amdgpu_sriov_vf(adev)) 1406 return 0; 1407 1408 if (!adev->psp.ta_ras_ucode_size || 1409 !adev->psp.ta_ras_start_addr) { 1410 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1411 return 0; 1412 } 1413 1414 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1415 /* query GECC enablement status from boot config 1416 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1417 */ 1418 ret = psp_boot_config_get(adev, &boot_cfg); 1419 if (ret) 1420 dev_warn(adev->dev, "PSP get boot config failed\n"); 1421 1422 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1423 if (!boot_cfg) { 1424 dev_info(adev->dev, "GECC is disabled\n"); 1425 } else { 1426 /* disable GECC in next boot cycle if ras is 1427 * disabled by module parameter amdgpu_ras_enable 1428 * and/or amdgpu_ras_mask, or boot_config_get call 1429 * is failed 1430 */ 1431 ret = psp_boot_config_set(adev, 0); 1432 if (ret) 1433 dev_warn(adev->dev, "PSP set boot config failed\n"); 1434 else 1435 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1436 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1437 } 1438 } else { 1439 if (1 == boot_cfg) { 1440 dev_info(adev->dev, "GECC is enabled\n"); 1441 } else { 1442 /* enable GECC in next boot cycle if it is disabled 1443 * in boot config, or force enable GECC if failed to 1444 * get boot configuration 1445 */ 1446 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1447 if (ret) 1448 dev_warn(adev->dev, "PSP set boot config failed\n"); 1449 else 1450 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1451 } 1452 } 1453 } 1454 1455 if (!psp->ras.ras_initialized) { 1456 ret = psp_ras_init_shared_buf(psp); 1457 if (ret) 1458 return ret; 1459 } 1460 1461 ret = psp_ras_load(psp); 1462 if (ret) 1463 return ret; 1464 1465 return 0; 1466 } 1467 1468 int psp_ras_trigger_error(struct psp_context *psp, 1469 struct ta_ras_trigger_error_input *info) 1470 { 1471 struct ta_ras_shared_memory *ras_cmd; 1472 int ret; 1473 1474 if (!psp->ras.ras_initialized) 1475 return -EINVAL; 1476 1477 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1478 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1479 1480 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1481 ras_cmd->ras_in_message.trigger_error = *info; 1482 1483 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1484 if (ret) 1485 return -EINVAL; 1486 1487 /* If err_event_athub occurs error inject was successful, however 1488 return status from TA is no long reliable */ 1489 if (amdgpu_ras_intr_triggered()) 1490 return 0; 1491 1492 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status); 1493 } 1494 // ras end 1495 1496 // HDCP start 1497 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1498 { 1499 int ret; 1500 1501 /* 1502 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1503 * physical) for hdcp ta <-> Driver 1504 */ 1505 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE, 1506 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1507 &psp->hdcp_context.hdcp_shared_bo, 1508 &psp->hdcp_context.hdcp_shared_mc_addr, 1509 &psp->hdcp_context.hdcp_shared_buf); 1510 1511 return ret; 1512 } 1513 1514 static int psp_hdcp_load(struct psp_context *psp) 1515 { 1516 int ret; 1517 struct psp_gfx_cmd_resp *cmd; 1518 1519 /* 1520 * TODO: bypass the loading in sriov for now 1521 */ 1522 if (amdgpu_sriov_vf(psp->adev)) 1523 return 0; 1524 1525 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1526 if (!cmd) 1527 return -ENOMEM; 1528 1529 psp_copy_fw(psp, psp->ta_hdcp_start_addr, 1530 psp->ta_hdcp_ucode_size); 1531 1532 psp_prep_ta_load_cmd_buf(cmd, 1533 psp->fw_pri_mc_addr, 1534 psp->ta_hdcp_ucode_size, 1535 psp->hdcp_context.hdcp_shared_mc_addr, 1536 PSP_HDCP_SHARED_MEM_SIZE); 1537 1538 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1539 1540 if (!ret) { 1541 psp->hdcp_context.hdcp_initialized = true; 1542 psp->hdcp_context.session_id = cmd->resp.session_id; 1543 mutex_init(&psp->hdcp_context.mutex); 1544 } 1545 1546 kfree(cmd); 1547 1548 return ret; 1549 } 1550 static int psp_hdcp_initialize(struct psp_context *psp) 1551 { 1552 int ret; 1553 1554 /* 1555 * TODO: bypass the initialize in sriov for now 1556 */ 1557 if (amdgpu_sriov_vf(psp->adev)) 1558 return 0; 1559 1560 if (!psp->adev->psp.ta_hdcp_ucode_size || 1561 !psp->adev->psp.ta_hdcp_start_addr) { 1562 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1563 return 0; 1564 } 1565 1566 if (!psp->hdcp_context.hdcp_initialized) { 1567 ret = psp_hdcp_init_shared_buf(psp); 1568 if (ret) 1569 return ret; 1570 } 1571 1572 ret = psp_hdcp_load(psp); 1573 if (ret) 1574 return ret; 1575 1576 return 0; 1577 } 1578 1579 static int psp_hdcp_unload(struct psp_context *psp) 1580 { 1581 int ret; 1582 struct psp_gfx_cmd_resp *cmd; 1583 1584 /* 1585 * TODO: bypass the unloading in sriov for now 1586 */ 1587 if (amdgpu_sriov_vf(psp->adev)) 1588 return 0; 1589 1590 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1591 if (!cmd) 1592 return -ENOMEM; 1593 1594 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id); 1595 1596 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1597 1598 kfree(cmd); 1599 1600 return ret; 1601 } 1602 1603 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1604 { 1605 /* 1606 * TODO: bypass the loading in sriov for now 1607 */ 1608 if (amdgpu_sriov_vf(psp->adev)) 1609 return 0; 1610 1611 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id); 1612 } 1613 1614 static int psp_hdcp_terminate(struct psp_context *psp) 1615 { 1616 int ret; 1617 1618 /* 1619 * TODO: bypass the terminate in sriov for now 1620 */ 1621 if (amdgpu_sriov_vf(psp->adev)) 1622 return 0; 1623 1624 if (!psp->hdcp_context.hdcp_initialized) { 1625 if (psp->hdcp_context.hdcp_shared_buf) 1626 goto out; 1627 else 1628 return 0; 1629 } 1630 1631 ret = psp_hdcp_unload(psp); 1632 if (ret) 1633 return ret; 1634 1635 psp->hdcp_context.hdcp_initialized = false; 1636 1637 out: 1638 /* free hdcp shared memory */ 1639 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo, 1640 &psp->hdcp_context.hdcp_shared_mc_addr, 1641 &psp->hdcp_context.hdcp_shared_buf); 1642 1643 return 0; 1644 } 1645 // HDCP end 1646 1647 // DTM start 1648 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1649 { 1650 int ret; 1651 1652 /* 1653 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1654 * physical) for dtm ta <-> Driver 1655 */ 1656 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE, 1657 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1658 &psp->dtm_context.dtm_shared_bo, 1659 &psp->dtm_context.dtm_shared_mc_addr, 1660 &psp->dtm_context.dtm_shared_buf); 1661 1662 return ret; 1663 } 1664 1665 static int psp_dtm_load(struct psp_context *psp) 1666 { 1667 int ret; 1668 struct psp_gfx_cmd_resp *cmd; 1669 1670 /* 1671 * TODO: bypass the loading in sriov for now 1672 */ 1673 if (amdgpu_sriov_vf(psp->adev)) 1674 return 0; 1675 1676 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1677 if (!cmd) 1678 return -ENOMEM; 1679 1680 psp_copy_fw(psp, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); 1681 1682 psp_prep_ta_load_cmd_buf(cmd, 1683 psp->fw_pri_mc_addr, 1684 psp->ta_dtm_ucode_size, 1685 psp->dtm_context.dtm_shared_mc_addr, 1686 PSP_DTM_SHARED_MEM_SIZE); 1687 1688 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1689 1690 if (!ret) { 1691 psp->dtm_context.dtm_initialized = true; 1692 psp->dtm_context.session_id = cmd->resp.session_id; 1693 mutex_init(&psp->dtm_context.mutex); 1694 } 1695 1696 kfree(cmd); 1697 1698 return ret; 1699 } 1700 1701 static int psp_dtm_initialize(struct psp_context *psp) 1702 { 1703 int ret; 1704 1705 /* 1706 * TODO: bypass the initialize in sriov for now 1707 */ 1708 if (amdgpu_sriov_vf(psp->adev)) 1709 return 0; 1710 1711 if (!psp->adev->psp.ta_dtm_ucode_size || 1712 !psp->adev->psp.ta_dtm_start_addr) { 1713 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1714 return 0; 1715 } 1716 1717 if (!psp->dtm_context.dtm_initialized) { 1718 ret = psp_dtm_init_shared_buf(psp); 1719 if (ret) 1720 return ret; 1721 } 1722 1723 ret = psp_dtm_load(psp); 1724 if (ret) 1725 return ret; 1726 1727 return 0; 1728 } 1729 1730 static int psp_dtm_unload(struct psp_context *psp) 1731 { 1732 int ret; 1733 struct psp_gfx_cmd_resp *cmd; 1734 1735 /* 1736 * TODO: bypass the unloading in sriov for now 1737 */ 1738 if (amdgpu_sriov_vf(psp->adev)) 1739 return 0; 1740 1741 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1742 if (!cmd) 1743 return -ENOMEM; 1744 1745 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id); 1746 1747 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1748 1749 kfree(cmd); 1750 1751 return ret; 1752 } 1753 1754 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1755 { 1756 /* 1757 * TODO: bypass the loading in sriov for now 1758 */ 1759 if (amdgpu_sriov_vf(psp->adev)) 1760 return 0; 1761 1762 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id); 1763 } 1764 1765 static int psp_dtm_terminate(struct psp_context *psp) 1766 { 1767 int ret; 1768 1769 /* 1770 * TODO: bypass the terminate in sriov for now 1771 */ 1772 if (amdgpu_sriov_vf(psp->adev)) 1773 return 0; 1774 1775 if (!psp->dtm_context.dtm_initialized) { 1776 if (psp->dtm_context.dtm_shared_buf) 1777 goto out; 1778 else 1779 return 0; 1780 } 1781 1782 ret = psp_dtm_unload(psp); 1783 if (ret) 1784 return ret; 1785 1786 psp->dtm_context.dtm_initialized = false; 1787 1788 out: 1789 /* free hdcp shared memory */ 1790 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo, 1791 &psp->dtm_context.dtm_shared_mc_addr, 1792 &psp->dtm_context.dtm_shared_buf); 1793 1794 return 0; 1795 } 1796 // DTM end 1797 1798 // RAP start 1799 static int psp_rap_init_shared_buf(struct psp_context *psp) 1800 { 1801 int ret; 1802 1803 /* 1804 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1805 * physical) for rap ta <-> Driver 1806 */ 1807 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE, 1808 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1809 &psp->rap_context.rap_shared_bo, 1810 &psp->rap_context.rap_shared_mc_addr, 1811 &psp->rap_context.rap_shared_buf); 1812 1813 return ret; 1814 } 1815 1816 static int psp_rap_load(struct psp_context *psp) 1817 { 1818 int ret; 1819 struct psp_gfx_cmd_resp *cmd; 1820 1821 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1822 if (!cmd) 1823 return -ENOMEM; 1824 1825 psp_copy_fw(psp, psp->ta_rap_start_addr, psp->ta_rap_ucode_size); 1826 1827 psp_prep_ta_load_cmd_buf(cmd, 1828 psp->fw_pri_mc_addr, 1829 psp->ta_rap_ucode_size, 1830 psp->rap_context.rap_shared_mc_addr, 1831 PSP_RAP_SHARED_MEM_SIZE); 1832 1833 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1834 1835 if (!ret) { 1836 psp->rap_context.rap_initialized = true; 1837 psp->rap_context.session_id = cmd->resp.session_id; 1838 mutex_init(&psp->rap_context.mutex); 1839 } 1840 1841 kfree(cmd); 1842 1843 return ret; 1844 } 1845 1846 static int psp_rap_unload(struct psp_context *psp) 1847 { 1848 int ret; 1849 struct psp_gfx_cmd_resp *cmd; 1850 1851 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1852 if (!cmd) 1853 return -ENOMEM; 1854 1855 psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id); 1856 1857 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1858 1859 kfree(cmd); 1860 1861 return ret; 1862 } 1863 1864 static int psp_rap_initialize(struct psp_context *psp) 1865 { 1866 int ret; 1867 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1868 1869 /* 1870 * TODO: bypass the initialize in sriov for now 1871 */ 1872 if (amdgpu_sriov_vf(psp->adev)) 1873 return 0; 1874 1875 if (!psp->adev->psp.ta_rap_ucode_size || 1876 !psp->adev->psp.ta_rap_start_addr) { 1877 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1878 return 0; 1879 } 1880 1881 if (!psp->rap_context.rap_initialized) { 1882 ret = psp_rap_init_shared_buf(psp); 1883 if (ret) 1884 return ret; 1885 } 1886 1887 ret = psp_rap_load(psp); 1888 if (ret) 1889 return ret; 1890 1891 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1892 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1893 psp_rap_unload(psp); 1894 1895 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1896 &psp->rap_context.rap_shared_mc_addr, 1897 &psp->rap_context.rap_shared_buf); 1898 1899 psp->rap_context.rap_initialized = false; 1900 1901 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1902 ret, status); 1903 1904 return ret; 1905 } 1906 1907 return 0; 1908 } 1909 1910 static int psp_rap_terminate(struct psp_context *psp) 1911 { 1912 int ret; 1913 1914 if (!psp->rap_context.rap_initialized) 1915 return 0; 1916 1917 ret = psp_rap_unload(psp); 1918 1919 psp->rap_context.rap_initialized = false; 1920 1921 /* free rap shared memory */ 1922 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1923 &psp->rap_context.rap_shared_mc_addr, 1924 &psp->rap_context.rap_shared_buf); 1925 1926 return ret; 1927 } 1928 1929 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1930 { 1931 struct ta_rap_shared_memory *rap_cmd; 1932 int ret = 0; 1933 1934 if (!psp->rap_context.rap_initialized) 1935 return 0; 1936 1937 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1938 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1939 return -EINVAL; 1940 1941 mutex_lock(&psp->rap_context.mutex); 1942 1943 rap_cmd = (struct ta_rap_shared_memory *) 1944 psp->rap_context.rap_shared_buf; 1945 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1946 1947 rap_cmd->cmd_id = ta_cmd_id; 1948 rap_cmd->validation_method_id = METHOD_A; 1949 1950 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id); 1951 if (ret) 1952 goto out_unlock; 1953 1954 if (status) 1955 *status = rap_cmd->rap_status; 1956 1957 out_unlock: 1958 mutex_unlock(&psp->rap_context.mutex); 1959 1960 return ret; 1961 } 1962 // RAP end 1963 1964 /* securedisplay start */ 1965 static int psp_securedisplay_init_shared_buf(struct psp_context *psp) 1966 { 1967 int ret; 1968 1969 /* 1970 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1971 * physical) for sa ta <-> Driver 1972 */ 1973 ret = amdgpu_bo_create_kernel(psp->adev, PSP_SECUREDISPLAY_SHARED_MEM_SIZE, 1974 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1975 &psp->securedisplay_context.securedisplay_shared_bo, 1976 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1977 &psp->securedisplay_context.securedisplay_shared_buf); 1978 1979 return ret; 1980 } 1981 1982 static int psp_securedisplay_load(struct psp_context *psp) 1983 { 1984 int ret; 1985 struct psp_gfx_cmd_resp *cmd; 1986 1987 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1988 if (!cmd) 1989 return -ENOMEM; 1990 1991 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1992 memcpy(psp->fw_pri_buf, psp->ta_securedisplay_start_addr, psp->ta_securedisplay_ucode_size); 1993 1994 psp_prep_ta_load_cmd_buf(cmd, 1995 psp->fw_pri_mc_addr, 1996 psp->ta_securedisplay_ucode_size, 1997 psp->securedisplay_context.securedisplay_shared_mc_addr, 1998 PSP_SECUREDISPLAY_SHARED_MEM_SIZE); 1999 2000 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 2001 2002 if (ret) 2003 goto failed; 2004 2005 psp->securedisplay_context.securedisplay_initialized = true; 2006 psp->securedisplay_context.session_id = cmd->resp.session_id; 2007 mutex_init(&psp->securedisplay_context.mutex); 2008 2009 failed: 2010 kfree(cmd); 2011 return ret; 2012 } 2013 2014 static int psp_securedisplay_unload(struct psp_context *psp) 2015 { 2016 int ret; 2017 struct psp_gfx_cmd_resp *cmd; 2018 2019 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2020 if (!cmd) 2021 return -ENOMEM; 2022 2023 psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.session_id); 2024 2025 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 2026 2027 kfree(cmd); 2028 2029 return ret; 2030 } 2031 2032 static int psp_securedisplay_initialize(struct psp_context *psp) 2033 { 2034 int ret; 2035 struct securedisplay_cmd *securedisplay_cmd; 2036 2037 /* 2038 * TODO: bypass the initialize in sriov for now 2039 */ 2040 if (amdgpu_sriov_vf(psp->adev)) 2041 return 0; 2042 2043 if (!psp->adev->psp.ta_securedisplay_ucode_size || 2044 !psp->adev->psp.ta_securedisplay_start_addr) { 2045 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 2046 return 0; 2047 } 2048 2049 if (!psp->securedisplay_context.securedisplay_initialized) { 2050 ret = psp_securedisplay_init_shared_buf(psp); 2051 if (ret) 2052 return ret; 2053 } 2054 2055 ret = psp_securedisplay_load(psp); 2056 if (ret) 2057 return ret; 2058 2059 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2060 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2061 2062 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2063 if (ret) { 2064 psp_securedisplay_unload(psp); 2065 2066 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 2067 &psp->securedisplay_context.securedisplay_shared_mc_addr, 2068 &psp->securedisplay_context.securedisplay_shared_buf); 2069 2070 psp->securedisplay_context.securedisplay_initialized = false; 2071 2072 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2073 return -EINVAL; 2074 } 2075 2076 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2077 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2078 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2079 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2080 } 2081 2082 return 0; 2083 } 2084 2085 static int psp_securedisplay_terminate(struct psp_context *psp) 2086 { 2087 int ret; 2088 2089 /* 2090 * TODO:bypass the terminate in sriov for now 2091 */ 2092 if (amdgpu_sriov_vf(psp->adev)) 2093 return 0; 2094 2095 if (!psp->securedisplay_context.securedisplay_initialized) 2096 return 0; 2097 2098 ret = psp_securedisplay_unload(psp); 2099 if (ret) 2100 return ret; 2101 2102 psp->securedisplay_context.securedisplay_initialized = false; 2103 2104 /* free securedisplay shared memory */ 2105 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 2106 &psp->securedisplay_context.securedisplay_shared_mc_addr, 2107 &psp->securedisplay_context.securedisplay_shared_buf); 2108 2109 return ret; 2110 } 2111 2112 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2113 { 2114 int ret; 2115 2116 if (!psp->securedisplay_context.securedisplay_initialized) 2117 return -EINVAL; 2118 2119 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2120 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 2121 return -EINVAL; 2122 2123 mutex_lock(&psp->securedisplay_context.mutex); 2124 2125 ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.session_id); 2126 2127 mutex_unlock(&psp->securedisplay_context.mutex); 2128 2129 return ret; 2130 } 2131 /* SECUREDISPLAY end */ 2132 2133 static int psp_hw_start(struct psp_context *psp) 2134 { 2135 struct amdgpu_device *adev = psp->adev; 2136 int ret; 2137 2138 if (!amdgpu_sriov_vf(adev)) { 2139 if ((is_psp_fw_valid(psp->kdb)) && 2140 (psp->funcs->bootloader_load_kdb != NULL)) { 2141 ret = psp_bootloader_load_kdb(psp); 2142 if (ret) { 2143 DRM_ERROR("PSP load kdb failed!\n"); 2144 return ret; 2145 } 2146 } 2147 2148 if ((is_psp_fw_valid(psp->spl)) && 2149 (psp->funcs->bootloader_load_spl != NULL)) { 2150 ret = psp_bootloader_load_spl(psp); 2151 if (ret) { 2152 DRM_ERROR("PSP load spl failed!\n"); 2153 return ret; 2154 } 2155 } 2156 2157 if ((is_psp_fw_valid(psp->sys)) && 2158 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2159 ret = psp_bootloader_load_sysdrv(psp); 2160 if (ret) { 2161 DRM_ERROR("PSP load sys drv failed!\n"); 2162 return ret; 2163 } 2164 } 2165 2166 if ((is_psp_fw_valid(psp->soc_drv)) && 2167 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2168 ret = psp_bootloader_load_soc_drv(psp); 2169 if (ret) { 2170 DRM_ERROR("PSP load soc drv failed!\n"); 2171 return ret; 2172 } 2173 } 2174 2175 if ((is_psp_fw_valid(psp->intf_drv)) && 2176 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2177 ret = psp_bootloader_load_intf_drv(psp); 2178 if (ret) { 2179 DRM_ERROR("PSP load intf drv failed!\n"); 2180 return ret; 2181 } 2182 } 2183 2184 if ((is_psp_fw_valid(psp->dbg_drv)) && 2185 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2186 ret = psp_bootloader_load_dbg_drv(psp); 2187 if (ret) { 2188 DRM_ERROR("PSP load dbg drv failed!\n"); 2189 return ret; 2190 } 2191 } 2192 2193 if ((is_psp_fw_valid(psp->sos)) && 2194 (psp->funcs->bootloader_load_sos != NULL)) { 2195 ret = psp_bootloader_load_sos(psp); 2196 if (ret) { 2197 DRM_ERROR("PSP load sos failed!\n"); 2198 return ret; 2199 } 2200 } 2201 } 2202 2203 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2204 if (ret) { 2205 DRM_ERROR("PSP create ring failed!\n"); 2206 return ret; 2207 } 2208 2209 ret = psp_tmr_init(psp); 2210 if (ret) { 2211 DRM_ERROR("PSP tmr init failed!\n"); 2212 return ret; 2213 } 2214 2215 /* 2216 * For ASICs with DF Cstate management centralized 2217 * to PMFW, TMR setup should be performed after PMFW 2218 * loaded and before other non-psp firmware loaded. 2219 */ 2220 if (psp->pmfw_centralized_cstate_management) { 2221 ret = psp_load_smu_fw(psp); 2222 if (ret) 2223 return ret; 2224 } 2225 2226 ret = psp_tmr_load(psp); 2227 if (ret) { 2228 DRM_ERROR("PSP load tmr failed!\n"); 2229 return ret; 2230 } 2231 2232 return 0; 2233 } 2234 2235 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2236 enum psp_gfx_fw_type *type) 2237 { 2238 switch (ucode->ucode_id) { 2239 case AMDGPU_UCODE_ID_SDMA0: 2240 *type = GFX_FW_TYPE_SDMA0; 2241 break; 2242 case AMDGPU_UCODE_ID_SDMA1: 2243 *type = GFX_FW_TYPE_SDMA1; 2244 break; 2245 case AMDGPU_UCODE_ID_SDMA2: 2246 *type = GFX_FW_TYPE_SDMA2; 2247 break; 2248 case AMDGPU_UCODE_ID_SDMA3: 2249 *type = GFX_FW_TYPE_SDMA3; 2250 break; 2251 case AMDGPU_UCODE_ID_SDMA4: 2252 *type = GFX_FW_TYPE_SDMA4; 2253 break; 2254 case AMDGPU_UCODE_ID_SDMA5: 2255 *type = GFX_FW_TYPE_SDMA5; 2256 break; 2257 case AMDGPU_UCODE_ID_SDMA6: 2258 *type = GFX_FW_TYPE_SDMA6; 2259 break; 2260 case AMDGPU_UCODE_ID_SDMA7: 2261 *type = GFX_FW_TYPE_SDMA7; 2262 break; 2263 case AMDGPU_UCODE_ID_CP_MES: 2264 *type = GFX_FW_TYPE_CP_MES; 2265 break; 2266 case AMDGPU_UCODE_ID_CP_MES_DATA: 2267 *type = GFX_FW_TYPE_MES_STACK; 2268 break; 2269 case AMDGPU_UCODE_ID_CP_CE: 2270 *type = GFX_FW_TYPE_CP_CE; 2271 break; 2272 case AMDGPU_UCODE_ID_CP_PFP: 2273 *type = GFX_FW_TYPE_CP_PFP; 2274 break; 2275 case AMDGPU_UCODE_ID_CP_ME: 2276 *type = GFX_FW_TYPE_CP_ME; 2277 break; 2278 case AMDGPU_UCODE_ID_CP_MEC1: 2279 *type = GFX_FW_TYPE_CP_MEC; 2280 break; 2281 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2282 *type = GFX_FW_TYPE_CP_MEC_ME1; 2283 break; 2284 case AMDGPU_UCODE_ID_CP_MEC2: 2285 *type = GFX_FW_TYPE_CP_MEC; 2286 break; 2287 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2288 *type = GFX_FW_TYPE_CP_MEC_ME2; 2289 break; 2290 case AMDGPU_UCODE_ID_RLC_G: 2291 *type = GFX_FW_TYPE_RLC_G; 2292 break; 2293 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2294 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2295 break; 2296 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2297 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2298 break; 2299 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2300 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2301 break; 2302 case AMDGPU_UCODE_ID_RLC_IRAM: 2303 *type = GFX_FW_TYPE_RLC_IRAM; 2304 break; 2305 case AMDGPU_UCODE_ID_RLC_DRAM: 2306 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2307 break; 2308 case AMDGPU_UCODE_ID_SMC: 2309 *type = GFX_FW_TYPE_SMU; 2310 break; 2311 case AMDGPU_UCODE_ID_UVD: 2312 *type = GFX_FW_TYPE_UVD; 2313 break; 2314 case AMDGPU_UCODE_ID_UVD1: 2315 *type = GFX_FW_TYPE_UVD1; 2316 break; 2317 case AMDGPU_UCODE_ID_VCE: 2318 *type = GFX_FW_TYPE_VCE; 2319 break; 2320 case AMDGPU_UCODE_ID_VCN: 2321 *type = GFX_FW_TYPE_VCN; 2322 break; 2323 case AMDGPU_UCODE_ID_VCN1: 2324 *type = GFX_FW_TYPE_VCN1; 2325 break; 2326 case AMDGPU_UCODE_ID_DMCU_ERAM: 2327 *type = GFX_FW_TYPE_DMCU_ERAM; 2328 break; 2329 case AMDGPU_UCODE_ID_DMCU_INTV: 2330 *type = GFX_FW_TYPE_DMCU_ISR; 2331 break; 2332 case AMDGPU_UCODE_ID_VCN0_RAM: 2333 *type = GFX_FW_TYPE_VCN0_RAM; 2334 break; 2335 case AMDGPU_UCODE_ID_VCN1_RAM: 2336 *type = GFX_FW_TYPE_VCN1_RAM; 2337 break; 2338 case AMDGPU_UCODE_ID_DMCUB: 2339 *type = GFX_FW_TYPE_DMUB; 2340 break; 2341 case AMDGPU_UCODE_ID_MAXIMUM: 2342 default: 2343 return -EINVAL; 2344 } 2345 2346 return 0; 2347 } 2348 2349 static void psp_print_fw_hdr(struct psp_context *psp, 2350 struct amdgpu_firmware_info *ucode) 2351 { 2352 struct amdgpu_device *adev = psp->adev; 2353 struct common_firmware_header *hdr; 2354 2355 switch (ucode->ucode_id) { 2356 case AMDGPU_UCODE_ID_SDMA0: 2357 case AMDGPU_UCODE_ID_SDMA1: 2358 case AMDGPU_UCODE_ID_SDMA2: 2359 case AMDGPU_UCODE_ID_SDMA3: 2360 case AMDGPU_UCODE_ID_SDMA4: 2361 case AMDGPU_UCODE_ID_SDMA5: 2362 case AMDGPU_UCODE_ID_SDMA6: 2363 case AMDGPU_UCODE_ID_SDMA7: 2364 hdr = (struct common_firmware_header *) 2365 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2366 amdgpu_ucode_print_sdma_hdr(hdr); 2367 break; 2368 case AMDGPU_UCODE_ID_CP_CE: 2369 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2370 amdgpu_ucode_print_gfx_hdr(hdr); 2371 break; 2372 case AMDGPU_UCODE_ID_CP_PFP: 2373 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2374 amdgpu_ucode_print_gfx_hdr(hdr); 2375 break; 2376 case AMDGPU_UCODE_ID_CP_ME: 2377 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2378 amdgpu_ucode_print_gfx_hdr(hdr); 2379 break; 2380 case AMDGPU_UCODE_ID_CP_MEC1: 2381 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2382 amdgpu_ucode_print_gfx_hdr(hdr); 2383 break; 2384 case AMDGPU_UCODE_ID_RLC_G: 2385 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2386 amdgpu_ucode_print_rlc_hdr(hdr); 2387 break; 2388 case AMDGPU_UCODE_ID_SMC: 2389 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2390 amdgpu_ucode_print_smc_hdr(hdr); 2391 break; 2392 default: 2393 break; 2394 } 2395 } 2396 2397 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2398 struct psp_gfx_cmd_resp *cmd) 2399 { 2400 int ret; 2401 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2402 2403 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 2404 2405 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2406 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2407 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2408 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2409 2410 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2411 if (ret) 2412 DRM_ERROR("Unknown firmware type\n"); 2413 2414 return ret; 2415 } 2416 2417 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2418 struct amdgpu_firmware_info *ucode) 2419 { 2420 int ret = 0; 2421 2422 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 2423 if (ret) 2424 return ret; 2425 2426 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 2427 psp->fence_buf_mc_addr); 2428 2429 return ret; 2430 } 2431 2432 static int psp_load_smu_fw(struct psp_context *psp) 2433 { 2434 int ret; 2435 struct amdgpu_device *adev = psp->adev; 2436 struct amdgpu_firmware_info *ucode = 2437 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2438 struct amdgpu_ras *ras = psp->ras.ras; 2439 2440 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2441 return 0; 2442 2443 if ((amdgpu_in_reset(adev) && 2444 ras && adev->ras_enabled && 2445 (adev->asic_type == CHIP_ARCTURUS || 2446 adev->asic_type == CHIP_VEGA20))) { 2447 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2448 if (ret) { 2449 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2450 } 2451 } 2452 2453 ret = psp_execute_non_psp_fw_load(psp, ucode); 2454 2455 if (ret) 2456 DRM_ERROR("PSP load smu failed!\n"); 2457 2458 return ret; 2459 } 2460 2461 static bool fw_load_skip_check(struct psp_context *psp, 2462 struct amdgpu_firmware_info *ucode) 2463 { 2464 if (!ucode->fw) 2465 return true; 2466 2467 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2468 (psp_smu_reload_quirk(psp) || 2469 psp->autoload_supported || 2470 psp->pmfw_centralized_cstate_management)) 2471 return true; 2472 2473 if (amdgpu_sriov_vf(psp->adev) && 2474 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2475 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2476 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2477 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2478 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2479 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2480 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2481 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2482 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2483 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2484 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2485 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2486 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2487 /*skip ucode loading in SRIOV VF */ 2488 return true; 2489 2490 if (psp->autoload_supported && 2491 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2492 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2493 /* skip mec JT when autoload is enabled */ 2494 return true; 2495 2496 return false; 2497 } 2498 2499 int psp_load_fw_list(struct psp_context *psp, 2500 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2501 { 2502 int ret = 0, i; 2503 struct amdgpu_firmware_info *ucode; 2504 2505 for (i = 0; i < ucode_count; ++i) { 2506 ucode = ucode_list[i]; 2507 psp_print_fw_hdr(psp, ucode); 2508 ret = psp_execute_non_psp_fw_load(psp, ucode); 2509 if (ret) 2510 return ret; 2511 } 2512 return ret; 2513 } 2514 2515 static int psp_load_non_psp_fw(struct psp_context *psp) 2516 { 2517 int i, ret; 2518 struct amdgpu_firmware_info *ucode; 2519 struct amdgpu_device *adev = psp->adev; 2520 2521 if (psp->autoload_supported && 2522 !psp->pmfw_centralized_cstate_management) { 2523 ret = psp_load_smu_fw(psp); 2524 if (ret) 2525 return ret; 2526 } 2527 2528 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2529 ucode = &adev->firmware.ucode[i]; 2530 2531 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2532 !fw_load_skip_check(psp, ucode)) { 2533 ret = psp_load_smu_fw(psp); 2534 if (ret) 2535 return ret; 2536 continue; 2537 } 2538 2539 if (fw_load_skip_check(psp, ucode)) 2540 continue; 2541 2542 if (psp->autoload_supported && 2543 (adev->asic_type >= CHIP_SIENNA_CICHLID && 2544 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) && 2545 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2546 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2547 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2548 /* PSP only receive one SDMA fw for sienna_cichlid, 2549 * as all four sdma fw are same */ 2550 continue; 2551 2552 psp_print_fw_hdr(psp, ucode); 2553 2554 ret = psp_execute_non_psp_fw_load(psp, ucode); 2555 if (ret) 2556 return ret; 2557 2558 /* Start rlc autoload after psp recieved all the gfx firmware */ 2559 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2560 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2561 ret = psp_rlc_autoload_start(psp); 2562 if (ret) { 2563 DRM_ERROR("Failed to start rlc autoload\n"); 2564 return ret; 2565 } 2566 } 2567 } 2568 2569 return 0; 2570 } 2571 2572 static int psp_load_fw(struct amdgpu_device *adev) 2573 { 2574 int ret; 2575 struct psp_context *psp = &adev->psp; 2576 2577 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2578 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 2579 goto skip_memalloc; 2580 } 2581 2582 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2583 if (!psp->cmd) 2584 return -ENOMEM; 2585 2586 if (amdgpu_sriov_vf(adev)) { 2587 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2588 AMDGPU_GEM_DOMAIN_VRAM, 2589 &psp->fw_pri_bo, 2590 &psp->fw_pri_mc_addr, 2591 &psp->fw_pri_buf); 2592 } else { 2593 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2594 AMDGPU_GEM_DOMAIN_GTT, 2595 &psp->fw_pri_bo, 2596 &psp->fw_pri_mc_addr, 2597 &psp->fw_pri_buf); 2598 } 2599 2600 if (ret) 2601 goto failed; 2602 2603 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 2604 AMDGPU_GEM_DOMAIN_VRAM, 2605 &psp->fence_buf_bo, 2606 &psp->fence_buf_mc_addr, 2607 &psp->fence_buf); 2608 if (ret) 2609 goto failed; 2610 2611 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 2612 AMDGPU_GEM_DOMAIN_VRAM, 2613 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2614 (void **)&psp->cmd_buf_mem); 2615 if (ret) 2616 goto failed; 2617 2618 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2619 2620 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2621 if (ret) { 2622 DRM_ERROR("PSP ring init failed!\n"); 2623 goto failed; 2624 } 2625 2626 skip_memalloc: 2627 ret = psp_hw_start(psp); 2628 if (ret) 2629 goto failed; 2630 2631 ret = psp_load_non_psp_fw(psp); 2632 if (ret) 2633 goto failed; 2634 2635 ret = psp_asd_load(psp); 2636 if (ret) { 2637 DRM_ERROR("PSP load asd failed!\n"); 2638 return ret; 2639 } 2640 2641 ret = psp_rl_load(adev); 2642 if (ret) { 2643 DRM_ERROR("PSP load RL failed!\n"); 2644 return ret; 2645 } 2646 2647 if (psp->adev->psp.ta_fw) { 2648 ret = psp_ras_initialize(psp); 2649 if (ret) 2650 dev_err(psp->adev->dev, 2651 "RAS: Failed to initialize RAS\n"); 2652 2653 ret = psp_hdcp_initialize(psp); 2654 if (ret) 2655 dev_err(psp->adev->dev, 2656 "HDCP: Failed to initialize HDCP\n"); 2657 2658 ret = psp_dtm_initialize(psp); 2659 if (ret) 2660 dev_err(psp->adev->dev, 2661 "DTM: Failed to initialize DTM\n"); 2662 2663 ret = psp_rap_initialize(psp); 2664 if (ret) 2665 dev_err(psp->adev->dev, 2666 "RAP: Failed to initialize RAP\n"); 2667 2668 ret = psp_securedisplay_initialize(psp); 2669 if (ret) 2670 dev_err(psp->adev->dev, 2671 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2672 } 2673 2674 return 0; 2675 2676 failed: 2677 /* 2678 * all cleanup jobs (xgmi terminate, ras terminate, 2679 * ring destroy, cmd/fence/fw buffers destory, 2680 * psp->cmd destory) are delayed to psp_hw_fini 2681 */ 2682 return ret; 2683 } 2684 2685 static int psp_hw_init(void *handle) 2686 { 2687 int ret; 2688 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2689 2690 mutex_lock(&adev->firmware.mutex); 2691 /* 2692 * This sequence is just used on hw_init only once, no need on 2693 * resume. 2694 */ 2695 ret = amdgpu_ucode_init_bo(adev); 2696 if (ret) 2697 goto failed; 2698 2699 ret = psp_load_fw(adev); 2700 if (ret) { 2701 DRM_ERROR("PSP firmware loading failed\n"); 2702 goto failed; 2703 } 2704 2705 mutex_unlock(&adev->firmware.mutex); 2706 return 0; 2707 2708 failed: 2709 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2710 mutex_unlock(&adev->firmware.mutex); 2711 return -EINVAL; 2712 } 2713 2714 static int psp_hw_fini(void *handle) 2715 { 2716 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2717 struct psp_context *psp = &adev->psp; 2718 2719 if (psp->adev->psp.ta_fw) { 2720 psp_ras_terminate(psp); 2721 psp_securedisplay_terminate(psp); 2722 psp_rap_terminate(psp); 2723 psp_dtm_terminate(psp); 2724 psp_hdcp_terminate(psp); 2725 } 2726 2727 psp_asd_unload(psp); 2728 2729 psp_tmr_terminate(psp); 2730 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2731 2732 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 2733 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 2734 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 2735 &psp->fence_buf_mc_addr, &psp->fence_buf); 2736 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2737 (void **)&psp->cmd_buf_mem); 2738 2739 kfree(psp->cmd); 2740 psp->cmd = NULL; 2741 2742 return 0; 2743 } 2744 2745 static int psp_suspend(void *handle) 2746 { 2747 int ret; 2748 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2749 struct psp_context *psp = &adev->psp; 2750 2751 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2752 psp->xgmi_context.initialized == 1) { 2753 ret = psp_xgmi_terminate(psp); 2754 if (ret) { 2755 DRM_ERROR("Failed to terminate xgmi ta\n"); 2756 return ret; 2757 } 2758 } 2759 2760 if (psp->adev->psp.ta_fw) { 2761 ret = psp_ras_terminate(psp); 2762 if (ret) { 2763 DRM_ERROR("Failed to terminate ras ta\n"); 2764 return ret; 2765 } 2766 ret = psp_hdcp_terminate(psp); 2767 if (ret) { 2768 DRM_ERROR("Failed to terminate hdcp ta\n"); 2769 return ret; 2770 } 2771 ret = psp_dtm_terminate(psp); 2772 if (ret) { 2773 DRM_ERROR("Failed to terminate dtm ta\n"); 2774 return ret; 2775 } 2776 ret = psp_rap_terminate(psp); 2777 if (ret) { 2778 DRM_ERROR("Failed to terminate rap ta\n"); 2779 return ret; 2780 } 2781 ret = psp_securedisplay_terminate(psp); 2782 if (ret) { 2783 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2784 return ret; 2785 } 2786 } 2787 2788 ret = psp_asd_unload(psp); 2789 if (ret) { 2790 DRM_ERROR("Failed to unload asd\n"); 2791 return ret; 2792 } 2793 2794 ret = psp_tmr_terminate(psp); 2795 if (ret) { 2796 DRM_ERROR("Failed to terminate tmr\n"); 2797 return ret; 2798 } 2799 2800 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2801 if (ret) { 2802 DRM_ERROR("PSP ring stop failed\n"); 2803 return ret; 2804 } 2805 2806 return 0; 2807 } 2808 2809 static int psp_resume(void *handle) 2810 { 2811 int ret; 2812 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2813 struct psp_context *psp = &adev->psp; 2814 2815 DRM_INFO("PSP is resuming...\n"); 2816 2817 if (psp->mem_train_ctx.enable_mem_training) { 2818 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2819 if (ret) { 2820 DRM_ERROR("Failed to process memory training!\n"); 2821 return ret; 2822 } 2823 } 2824 2825 mutex_lock(&adev->firmware.mutex); 2826 2827 ret = psp_hw_start(psp); 2828 if (ret) 2829 goto failed; 2830 2831 ret = psp_load_non_psp_fw(psp); 2832 if (ret) 2833 goto failed; 2834 2835 ret = psp_asd_load(psp); 2836 if (ret) { 2837 DRM_ERROR("PSP load asd failed!\n"); 2838 goto failed; 2839 } 2840 2841 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2842 ret = psp_xgmi_initialize(psp); 2843 /* Warning the XGMI seesion initialize failure 2844 * Instead of stop driver initialization 2845 */ 2846 if (ret) 2847 dev_err(psp->adev->dev, 2848 "XGMI: Failed to initialize XGMI session\n"); 2849 } 2850 2851 if (psp->adev->psp.ta_fw) { 2852 ret = psp_ras_initialize(psp); 2853 if (ret) 2854 dev_err(psp->adev->dev, 2855 "RAS: Failed to initialize RAS\n"); 2856 2857 ret = psp_hdcp_initialize(psp); 2858 if (ret) 2859 dev_err(psp->adev->dev, 2860 "HDCP: Failed to initialize HDCP\n"); 2861 2862 ret = psp_dtm_initialize(psp); 2863 if (ret) 2864 dev_err(psp->adev->dev, 2865 "DTM: Failed to initialize DTM\n"); 2866 2867 ret = psp_rap_initialize(psp); 2868 if (ret) 2869 dev_err(psp->adev->dev, 2870 "RAP: Failed to initialize RAP\n"); 2871 2872 ret = psp_securedisplay_initialize(psp); 2873 if (ret) 2874 dev_err(psp->adev->dev, 2875 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2876 } 2877 2878 mutex_unlock(&adev->firmware.mutex); 2879 2880 return 0; 2881 2882 failed: 2883 DRM_ERROR("PSP resume failed\n"); 2884 mutex_unlock(&adev->firmware.mutex); 2885 return ret; 2886 } 2887 2888 int psp_gpu_reset(struct amdgpu_device *adev) 2889 { 2890 int ret; 2891 2892 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2893 return 0; 2894 2895 mutex_lock(&adev->psp.mutex); 2896 ret = psp_mode1_reset(&adev->psp); 2897 mutex_unlock(&adev->psp.mutex); 2898 2899 return ret; 2900 } 2901 2902 int psp_rlc_autoload_start(struct psp_context *psp) 2903 { 2904 int ret; 2905 struct psp_gfx_cmd_resp *cmd; 2906 2907 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2908 if (!cmd) 2909 return -ENOMEM; 2910 2911 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2912 2913 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2914 psp->fence_buf_mc_addr); 2915 kfree(cmd); 2916 return ret; 2917 } 2918 2919 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2920 uint64_t cmd_gpu_addr, int cmd_size) 2921 { 2922 struct amdgpu_firmware_info ucode = {0}; 2923 2924 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2925 AMDGPU_UCODE_ID_VCN0_RAM; 2926 ucode.mc_addr = cmd_gpu_addr; 2927 ucode.ucode_size = cmd_size; 2928 2929 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2930 } 2931 2932 int psp_ring_cmd_submit(struct psp_context *psp, 2933 uint64_t cmd_buf_mc_addr, 2934 uint64_t fence_mc_addr, 2935 int index) 2936 { 2937 unsigned int psp_write_ptr_reg = 0; 2938 struct psp_gfx_rb_frame *write_frame; 2939 struct psp_ring *ring = &psp->km_ring; 2940 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2941 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2942 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2943 struct amdgpu_device *adev = psp->adev; 2944 uint32_t ring_size_dw = ring->ring_size / 4; 2945 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2946 2947 /* KM (GPCOM) prepare write pointer */ 2948 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2949 2950 /* Update KM RB frame pointer to new frame */ 2951 /* write_frame ptr increments by size of rb_frame in bytes */ 2952 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2953 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2954 write_frame = ring_buffer_start; 2955 else 2956 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2957 /* Check invalid write_frame ptr address */ 2958 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2959 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2960 ring_buffer_start, ring_buffer_end, write_frame); 2961 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2962 return -EINVAL; 2963 } 2964 2965 /* Initialize KM RB frame */ 2966 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2967 2968 /* Update KM RB frame */ 2969 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2970 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2971 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2972 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2973 write_frame->fence_value = index; 2974 amdgpu_device_flush_hdp(adev, NULL); 2975 2976 /* Update the write Pointer in DWORDs */ 2977 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2978 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2979 return 0; 2980 } 2981 2982 int psp_init_asd_microcode(struct psp_context *psp, 2983 const char *chip_name) 2984 { 2985 struct amdgpu_device *adev = psp->adev; 2986 char fw_name[PSP_FW_NAME_LEN]; 2987 const struct psp_firmware_header_v1_0 *asd_hdr; 2988 int err = 0; 2989 2990 if (!chip_name) { 2991 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2992 return -EINVAL; 2993 } 2994 2995 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2996 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2997 if (err) 2998 goto out; 2999 3000 err = amdgpu_ucode_validate(adev->psp.asd_fw); 3001 if (err) 3002 goto out; 3003 3004 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 3005 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 3006 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 3007 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 3008 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 3009 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 3010 return 0; 3011 out: 3012 dev_err(adev->dev, "fail to initialize asd microcode\n"); 3013 release_firmware(adev->psp.asd_fw); 3014 adev->psp.asd_fw = NULL; 3015 return err; 3016 } 3017 3018 int psp_init_toc_microcode(struct psp_context *psp, 3019 const char *chip_name) 3020 { 3021 struct amdgpu_device *adev = psp->adev; 3022 char fw_name[PSP_FW_NAME_LEN]; 3023 const struct psp_firmware_header_v1_0 *toc_hdr; 3024 int err = 0; 3025 3026 if (!chip_name) { 3027 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 3028 return -EINVAL; 3029 } 3030 3031 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 3032 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 3033 if (err) 3034 goto out; 3035 3036 err = amdgpu_ucode_validate(adev->psp.toc_fw); 3037 if (err) 3038 goto out; 3039 3040 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 3041 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 3042 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 3043 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 3044 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 3045 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 3046 return 0; 3047 out: 3048 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 3049 release_firmware(adev->psp.toc_fw); 3050 adev->psp.toc_fw = NULL; 3051 return err; 3052 } 3053 3054 static int parse_sos_bin_descriptor(struct psp_context *psp, 3055 const struct psp_fw_bin_desc *desc, 3056 const struct psp_firmware_header_v2_0 *sos_hdr) 3057 { 3058 uint8_t *ucode_start_addr = NULL; 3059 3060 if (!psp || !desc || !sos_hdr) 3061 return -EINVAL; 3062 3063 ucode_start_addr = (uint8_t *)sos_hdr + 3064 le32_to_cpu(desc->offset_bytes) + 3065 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3066 3067 switch (desc->fw_type) { 3068 case PSP_FW_TYPE_PSP_SOS: 3069 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3070 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3071 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3072 psp->sos.start_addr = ucode_start_addr; 3073 break; 3074 case PSP_FW_TYPE_PSP_SYS_DRV: 3075 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3076 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3077 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3078 psp->sys.start_addr = ucode_start_addr; 3079 break; 3080 case PSP_FW_TYPE_PSP_KDB: 3081 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 3082 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 3083 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 3084 psp->kdb.start_addr = ucode_start_addr; 3085 break; 3086 case PSP_FW_TYPE_PSP_TOC: 3087 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3088 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3089 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3090 psp->toc.start_addr = ucode_start_addr; 3091 break; 3092 case PSP_FW_TYPE_PSP_SPL: 3093 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3094 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3095 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3096 psp->spl.start_addr = ucode_start_addr; 3097 break; 3098 case PSP_FW_TYPE_PSP_RL: 3099 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3100 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3101 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3102 psp->rl.start_addr = ucode_start_addr; 3103 break; 3104 case PSP_FW_TYPE_PSP_SOC_DRV: 3105 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3106 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3107 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3108 psp->soc_drv.start_addr = ucode_start_addr; 3109 break; 3110 case PSP_FW_TYPE_PSP_INTF_DRV: 3111 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3112 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3113 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3114 psp->intf_drv.start_addr = ucode_start_addr; 3115 break; 3116 case PSP_FW_TYPE_PSP_DBG_DRV: 3117 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3118 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3119 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3120 psp->dbg_drv.start_addr = ucode_start_addr; 3121 break; 3122 default: 3123 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3124 break; 3125 } 3126 3127 return 0; 3128 } 3129 3130 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3131 { 3132 const struct psp_firmware_header_v1_0 *sos_hdr; 3133 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3134 uint8_t *ucode_array_start_addr; 3135 3136 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3137 ucode_array_start_addr = (uint8_t *)sos_hdr + 3138 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3139 3140 if (adev->gmc.xgmi.connected_to_cpu || (adev->asic_type != CHIP_ALDEBARAN)) { 3141 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3142 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3143 3144 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3145 adev->psp.sys.start_addr = ucode_array_start_addr; 3146 3147 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3148 adev->psp.sos.start_addr = ucode_array_start_addr + 3149 le32_to_cpu(sos_hdr->sos.offset_bytes); 3150 } else { 3151 /* Load alternate PSP SOS FW */ 3152 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3153 3154 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3155 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3156 3157 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3158 adev->psp.sys.start_addr = ucode_array_start_addr + 3159 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3160 3161 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3162 adev->psp.sos.start_addr = ucode_array_start_addr + 3163 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3164 } 3165 3166 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3167 dev_warn(adev->dev, "PSP SOS FW not available"); 3168 return -EINVAL; 3169 } 3170 3171 return 0; 3172 } 3173 3174 int psp_init_sos_microcode(struct psp_context *psp, 3175 const char *chip_name) 3176 { 3177 struct amdgpu_device *adev = psp->adev; 3178 char fw_name[PSP_FW_NAME_LEN]; 3179 const struct psp_firmware_header_v1_0 *sos_hdr; 3180 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3181 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3182 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3183 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3184 int err = 0; 3185 uint8_t *ucode_array_start_addr; 3186 int fw_index = 0; 3187 3188 if (!chip_name) { 3189 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 3190 return -EINVAL; 3191 } 3192 3193 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3194 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 3195 if (err) 3196 goto out; 3197 3198 err = amdgpu_ucode_validate(adev->psp.sos_fw); 3199 if (err) 3200 goto out; 3201 3202 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3203 ucode_array_start_addr = (uint8_t *)sos_hdr + 3204 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3205 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3206 3207 switch (sos_hdr->header.header_version_major) { 3208 case 1: 3209 err = psp_init_sos_base_fw(adev); 3210 if (err) 3211 goto out; 3212 3213 if (sos_hdr->header.header_version_minor == 1) { 3214 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3215 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3216 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3217 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3218 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3219 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3220 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3221 } 3222 if (sos_hdr->header.header_version_minor == 2) { 3223 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3224 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3225 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3226 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3227 } 3228 if (sos_hdr->header.header_version_minor == 3) { 3229 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3230 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3231 adev->psp.toc.start_addr = ucode_array_start_addr + 3232 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3233 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3234 adev->psp.kdb.start_addr = ucode_array_start_addr + 3235 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3236 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3237 adev->psp.spl.start_addr = ucode_array_start_addr + 3238 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3239 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3240 adev->psp.rl.start_addr = ucode_array_start_addr + 3241 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3242 } 3243 break; 3244 case 2: 3245 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3246 3247 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3248 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3249 err = -EINVAL; 3250 goto out; 3251 } 3252 3253 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3254 err = parse_sos_bin_descriptor(psp, 3255 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3256 sos_hdr_v2_0); 3257 if (err) 3258 goto out; 3259 } 3260 break; 3261 default: 3262 dev_err(adev->dev, 3263 "unsupported psp sos firmware\n"); 3264 err = -EINVAL; 3265 goto out; 3266 } 3267 3268 return 0; 3269 out: 3270 dev_err(adev->dev, 3271 "failed to init sos firmware\n"); 3272 release_firmware(adev->psp.sos_fw); 3273 adev->psp.sos_fw = NULL; 3274 3275 return err; 3276 } 3277 3278 static int parse_ta_bin_descriptor(struct psp_context *psp, 3279 const struct psp_fw_bin_desc *desc, 3280 const struct ta_firmware_header_v2_0 *ta_hdr) 3281 { 3282 uint8_t *ucode_start_addr = NULL; 3283 3284 if (!psp || !desc || !ta_hdr) 3285 return -EINVAL; 3286 3287 ucode_start_addr = (uint8_t *)ta_hdr + 3288 le32_to_cpu(desc->offset_bytes) + 3289 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3290 3291 switch (desc->fw_type) { 3292 case TA_FW_TYPE_PSP_ASD: 3293 psp->asd_fw_version = le32_to_cpu(desc->fw_version); 3294 psp->asd_feature_version = le32_to_cpu(desc->fw_version); 3295 psp->asd_ucode_size = le32_to_cpu(desc->size_bytes); 3296 psp->asd_start_addr = ucode_start_addr; 3297 break; 3298 case TA_FW_TYPE_PSP_XGMI: 3299 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version); 3300 psp->ta_xgmi_ucode_size = le32_to_cpu(desc->size_bytes); 3301 psp->ta_xgmi_start_addr = ucode_start_addr; 3302 break; 3303 case TA_FW_TYPE_PSP_RAS: 3304 psp->ta_ras_ucode_version = le32_to_cpu(desc->fw_version); 3305 psp->ta_ras_ucode_size = le32_to_cpu(desc->size_bytes); 3306 psp->ta_ras_start_addr = ucode_start_addr; 3307 break; 3308 case TA_FW_TYPE_PSP_HDCP: 3309 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version); 3310 psp->ta_hdcp_ucode_size = le32_to_cpu(desc->size_bytes); 3311 psp->ta_hdcp_start_addr = ucode_start_addr; 3312 break; 3313 case TA_FW_TYPE_PSP_DTM: 3314 psp->ta_dtm_ucode_version = le32_to_cpu(desc->fw_version); 3315 psp->ta_dtm_ucode_size = le32_to_cpu(desc->size_bytes); 3316 psp->ta_dtm_start_addr = ucode_start_addr; 3317 break; 3318 case TA_FW_TYPE_PSP_RAP: 3319 psp->ta_rap_ucode_version = le32_to_cpu(desc->fw_version); 3320 psp->ta_rap_ucode_size = le32_to_cpu(desc->size_bytes); 3321 psp->ta_rap_start_addr = ucode_start_addr; 3322 break; 3323 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3324 psp->ta_securedisplay_ucode_version = le32_to_cpu(desc->fw_version); 3325 psp->ta_securedisplay_ucode_size = le32_to_cpu(desc->size_bytes); 3326 psp->ta_securedisplay_start_addr = ucode_start_addr; 3327 break; 3328 default: 3329 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3330 break; 3331 } 3332 3333 return 0; 3334 } 3335 3336 int psp_init_ta_microcode(struct psp_context *psp, 3337 const char *chip_name) 3338 { 3339 struct amdgpu_device *adev = psp->adev; 3340 char fw_name[PSP_FW_NAME_LEN]; 3341 const struct ta_firmware_header_v2_0 *ta_hdr; 3342 int err = 0; 3343 int ta_index = 0; 3344 3345 if (!chip_name) { 3346 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3347 return -EINVAL; 3348 } 3349 3350 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3351 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3352 if (err) 3353 goto out; 3354 3355 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3356 if (err) 3357 goto out; 3358 3359 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3360 3361 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3362 dev_err(adev->dev, "unsupported TA header version\n"); 3363 err = -EINVAL; 3364 goto out; 3365 } 3366 3367 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3368 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3369 err = -EINVAL; 3370 goto out; 3371 } 3372 3373 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3374 err = parse_ta_bin_descriptor(psp, 3375 &ta_hdr->ta_fw_bin[ta_index], 3376 ta_hdr); 3377 if (err) 3378 goto out; 3379 } 3380 3381 return 0; 3382 out: 3383 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3384 release_firmware(adev->psp.ta_fw); 3385 adev->psp.ta_fw = NULL; 3386 return err; 3387 } 3388 3389 static int psp_set_clockgating_state(void *handle, 3390 enum amd_clockgating_state state) 3391 { 3392 return 0; 3393 } 3394 3395 static int psp_set_powergating_state(void *handle, 3396 enum amd_powergating_state state) 3397 { 3398 return 0; 3399 } 3400 3401 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3402 struct device_attribute *attr, 3403 char *buf) 3404 { 3405 struct drm_device *ddev = dev_get_drvdata(dev); 3406 struct amdgpu_device *adev = drm_to_adev(ddev); 3407 uint32_t fw_ver; 3408 int ret; 3409 3410 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3411 DRM_INFO("PSP block is not ready yet."); 3412 return -EBUSY; 3413 } 3414 3415 mutex_lock(&adev->psp.mutex); 3416 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3417 mutex_unlock(&adev->psp.mutex); 3418 3419 if (ret) { 3420 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3421 return ret; 3422 } 3423 3424 return sysfs_emit(buf, "%x\n", fw_ver); 3425 } 3426 3427 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3428 struct device_attribute *attr, 3429 const char *buf, 3430 size_t count) 3431 { 3432 struct drm_device *ddev = dev_get_drvdata(dev); 3433 struct amdgpu_device *adev = drm_to_adev(ddev); 3434 int ret, idx; 3435 char fw_name[100]; 3436 const struct firmware *usbc_pd_fw; 3437 struct amdgpu_bo *fw_buf_bo = NULL; 3438 uint64_t fw_pri_mc_addr; 3439 void *fw_pri_cpu_addr; 3440 3441 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3442 DRM_INFO("PSP block is not ready yet."); 3443 return -EBUSY; 3444 } 3445 3446 if (!drm_dev_enter(ddev, &idx)) 3447 return -ENODEV; 3448 3449 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3450 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3451 if (ret) 3452 goto fail; 3453 3454 /* LFB address which is aligned to 1MB boundary per PSP request */ 3455 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3456 AMDGPU_GEM_DOMAIN_VRAM, 3457 &fw_buf_bo, 3458 &fw_pri_mc_addr, 3459 &fw_pri_cpu_addr); 3460 if (ret) 3461 goto rel_buf; 3462 3463 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3464 3465 mutex_lock(&adev->psp.mutex); 3466 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3467 mutex_unlock(&adev->psp.mutex); 3468 3469 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3470 3471 rel_buf: 3472 release_firmware(usbc_pd_fw); 3473 fail: 3474 if (ret) { 3475 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3476 count = ret; 3477 } 3478 3479 drm_dev_exit(idx); 3480 return count; 3481 } 3482 3483 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3484 { 3485 int idx; 3486 3487 if (!drm_dev_enter(&psp->adev->ddev, &idx)) 3488 return; 3489 3490 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3491 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3492 3493 drm_dev_exit(idx); 3494 } 3495 3496 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3497 psp_usbc_pd_fw_sysfs_read, 3498 psp_usbc_pd_fw_sysfs_write); 3499 3500 int is_psp_fw_valid(struct psp_bin_desc bin) 3501 { 3502 return bin.size_bytes; 3503 } 3504 3505 const struct amd_ip_funcs psp_ip_funcs = { 3506 .name = "psp", 3507 .early_init = psp_early_init, 3508 .late_init = NULL, 3509 .sw_init = psp_sw_init, 3510 .sw_fini = psp_sw_fini, 3511 .hw_init = psp_hw_init, 3512 .hw_fini = psp_hw_fini, 3513 .suspend = psp_suspend, 3514 .resume = psp_resume, 3515 .is_idle = NULL, 3516 .check_soft_reset = NULL, 3517 .wait_for_idle = NULL, 3518 .soft_reset = NULL, 3519 .set_clockgating_state = psp_set_clockgating_state, 3520 .set_powergating_state = psp_set_powergating_state, 3521 }; 3522 3523 static int psp_sysfs_init(struct amdgpu_device *adev) 3524 { 3525 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3526 3527 if (ret) 3528 DRM_ERROR("Failed to create USBC PD FW control file!"); 3529 3530 return ret; 3531 } 3532 3533 static void psp_sysfs_fini(struct amdgpu_device *adev) 3534 { 3535 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3536 } 3537 3538 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3539 { 3540 .type = AMD_IP_BLOCK_TYPE_PSP, 3541 .major = 3, 3542 .minor = 1, 3543 .rev = 0, 3544 .funcs = &psp_ip_funcs, 3545 }; 3546 3547 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3548 { 3549 .type = AMD_IP_BLOCK_TYPE_PSP, 3550 .major = 10, 3551 .minor = 0, 3552 .rev = 0, 3553 .funcs = &psp_ip_funcs, 3554 }; 3555 3556 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3557 { 3558 .type = AMD_IP_BLOCK_TYPE_PSP, 3559 .major = 11, 3560 .minor = 0, 3561 .rev = 0, 3562 .funcs = &psp_ip_funcs, 3563 }; 3564 3565 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3566 .type = AMD_IP_BLOCK_TYPE_PSP, 3567 .major = 11, 3568 .minor = 0, 3569 .rev = 8, 3570 .funcs = &psp_ip_funcs, 3571 }; 3572 3573 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3574 { 3575 .type = AMD_IP_BLOCK_TYPE_PSP, 3576 .major = 12, 3577 .minor = 0, 3578 .rev = 0, 3579 .funcs = &psp_ip_funcs, 3580 }; 3581 3582 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3583 .type = AMD_IP_BLOCK_TYPE_PSP, 3584 .major = 13, 3585 .minor = 0, 3586 .rev = 0, 3587 .funcs = &psp_ip_funcs, 3588 }; 3589