1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2014 Advanced Micro Devices, Inc. 3d38ceaf9SAlex Deucher * 4d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6d38ceaf9SAlex Deucher * to deal in the Software without restriction, including without limitation 7d38ceaf9SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8d38ceaf9SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9d38ceaf9SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10d38ceaf9SAlex Deucher * 11d38ceaf9SAlex Deucher * The above copyright notice and this permission notice shall be included in 12d38ceaf9SAlex Deucher * all copies or substantial portions of the Software. 13d38ceaf9SAlex Deucher * 14d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18d38ceaf9SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19d38ceaf9SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20d38ceaf9SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21d38ceaf9SAlex Deucher * 22d38ceaf9SAlex Deucher */ 23d38ceaf9SAlex Deucher 24d38ceaf9SAlex Deucher #ifndef __AMDGPU_PLL_H__ 25d38ceaf9SAlex Deucher #define __AMDGPU_PLL_H__ 26d38ceaf9SAlex Deucher 27*7301757eSShashank Sharma void amdgpu_pll_compute(struct amdgpu_device *adev, 28*7301757eSShashank Sharma struct amdgpu_pll *pll, 29d38ceaf9SAlex Deucher u32 freq, 30d38ceaf9SAlex Deucher u32 *dot_clock_p, 31d38ceaf9SAlex Deucher u32 *fb_div_p, 32d38ceaf9SAlex Deucher u32 *frac_fb_div_p, 33d38ceaf9SAlex Deucher u32 *ref_div_p, 34d38ceaf9SAlex Deucher u32 *post_div_p); 35d38ceaf9SAlex Deucher u32 amdgpu_pll_get_use_mask(struct drm_crtc *crtc); 36d38ceaf9SAlex Deucher int amdgpu_pll_get_shared_dp_ppll(struct drm_crtc *crtc); 37d38ceaf9SAlex Deucher int amdgpu_pll_get_shared_nondp_ppll(struct drm_crtc *crtc); 38d38ceaf9SAlex Deucher 39d38ceaf9SAlex Deucher #endif 40