1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Original Authors: 25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26 * 27 * Kernel port Author: Dave Airlie 28 */ 29 30 #ifndef AMDGPU_MODE_H 31 #define AMDGPU_MODE_H 32 33 #include <drm/display/drm_dp_helper.h> 34 #include <drm/drm_crtc.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_encoder.h> 37 #include <drm/drm_fixed.h> 38 #include <drm/drm_crtc_helper.h> 39 #include <drm/drm_fb_helper.h> 40 #include <drm/drm_framebuffer.h> 41 #include <drm/drm_plane_helper.h> 42 #include <drm/drm_probe_helper.h> 43 #include <linux/i2c.h> 44 #include <linux/i2c-algo-bit.h> 45 #include <linux/hrtimer.h> 46 #include "amdgpu_irq.h" 47 48 #include <drm/display/drm_dp_mst_helper.h> 49 #include "modules/inc/mod_freesync.h" 50 #include "amdgpu_dm_irq_params.h" 51 52 struct amdgpu_bo; 53 struct amdgpu_device; 54 struct amdgpu_encoder; 55 struct amdgpu_router; 56 struct amdgpu_hpd; 57 58 #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base) 59 #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base) 60 #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base) 61 #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base) 62 63 #define to_dm_plane_state(x) container_of(x, struct dm_plane_state, base) 64 65 #define AMDGPU_MAX_HPD_PINS 6 66 #define AMDGPU_MAX_CRTCS 6 67 #define AMDGPU_MAX_PLANES 6 68 #define AMDGPU_MAX_AFMT_BLOCKS 9 69 70 enum amdgpu_rmx_type { 71 RMX_OFF, 72 RMX_FULL, 73 RMX_CENTER, 74 RMX_ASPECT 75 }; 76 77 enum amdgpu_underscan_type { 78 UNDERSCAN_OFF, 79 UNDERSCAN_ON, 80 UNDERSCAN_AUTO, 81 }; 82 83 #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50 84 #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10 85 86 enum amdgpu_hpd_id { 87 AMDGPU_HPD_1 = 0, 88 AMDGPU_HPD_2, 89 AMDGPU_HPD_3, 90 AMDGPU_HPD_4, 91 AMDGPU_HPD_5, 92 AMDGPU_HPD_6, 93 AMDGPU_HPD_NONE = 0xff, 94 }; 95 96 enum amdgpu_crtc_irq { 97 AMDGPU_CRTC_IRQ_VBLANK1 = 0, 98 AMDGPU_CRTC_IRQ_VBLANK2, 99 AMDGPU_CRTC_IRQ_VBLANK3, 100 AMDGPU_CRTC_IRQ_VBLANK4, 101 AMDGPU_CRTC_IRQ_VBLANK5, 102 AMDGPU_CRTC_IRQ_VBLANK6, 103 AMDGPU_CRTC_IRQ_VLINE1, 104 AMDGPU_CRTC_IRQ_VLINE2, 105 AMDGPU_CRTC_IRQ_VLINE3, 106 AMDGPU_CRTC_IRQ_VLINE4, 107 AMDGPU_CRTC_IRQ_VLINE5, 108 AMDGPU_CRTC_IRQ_VLINE6, 109 AMDGPU_CRTC_IRQ_NONE = 0xff 110 }; 111 112 enum amdgpu_pageflip_irq { 113 AMDGPU_PAGEFLIP_IRQ_D1 = 0, 114 AMDGPU_PAGEFLIP_IRQ_D2, 115 AMDGPU_PAGEFLIP_IRQ_D3, 116 AMDGPU_PAGEFLIP_IRQ_D4, 117 AMDGPU_PAGEFLIP_IRQ_D5, 118 AMDGPU_PAGEFLIP_IRQ_D6, 119 AMDGPU_PAGEFLIP_IRQ_NONE = 0xff 120 }; 121 122 enum amdgpu_flip_status { 123 AMDGPU_FLIP_NONE, 124 AMDGPU_FLIP_PENDING, 125 AMDGPU_FLIP_SUBMITTED 126 }; 127 128 #define AMDGPU_MAX_I2C_BUS 16 129 130 /* amdgpu gpio-based i2c 131 * 1. "mask" reg and bits 132 * grabs the gpio pins for software use 133 * 0=not held 1=held 134 * 2. "a" reg and bits 135 * output pin value 136 * 0=low 1=high 137 * 3. "en" reg and bits 138 * sets the pin direction 139 * 0=input 1=output 140 * 4. "y" reg and bits 141 * input pin value 142 * 0=low 1=high 143 */ 144 struct amdgpu_i2c_bus_rec { 145 bool valid; 146 /* id used by atom */ 147 uint8_t i2c_id; 148 /* id used by atom */ 149 enum amdgpu_hpd_id hpd; 150 /* can be used with hw i2c engine */ 151 bool hw_capable; 152 /* uses multi-media i2c engine */ 153 bool mm_i2c; 154 /* regs and bits */ 155 uint32_t mask_clk_reg; 156 uint32_t mask_data_reg; 157 uint32_t a_clk_reg; 158 uint32_t a_data_reg; 159 uint32_t en_clk_reg; 160 uint32_t en_data_reg; 161 uint32_t y_clk_reg; 162 uint32_t y_data_reg; 163 uint32_t mask_clk_mask; 164 uint32_t mask_data_mask; 165 uint32_t a_clk_mask; 166 uint32_t a_data_mask; 167 uint32_t en_clk_mask; 168 uint32_t en_data_mask; 169 uint32_t y_clk_mask; 170 uint32_t y_data_mask; 171 }; 172 173 #define AMDGPU_MAX_BIOS_CONNECTOR 16 174 175 /* pll flags */ 176 #define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0) 177 #define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1) 178 #define AMDGPU_PLL_USE_REF_DIV (1 << 2) 179 #define AMDGPU_PLL_LEGACY (1 << 3) 180 #define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4) 181 #define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5) 182 #define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6) 183 #define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7) 184 #define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8) 185 #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9) 186 #define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10) 187 #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11) 188 #define AMDGPU_PLL_USE_POST_DIV (1 << 12) 189 #define AMDGPU_PLL_IS_LCD (1 << 13) 190 #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 191 192 struct amdgpu_pll { 193 /* reference frequency */ 194 uint32_t reference_freq; 195 196 /* fixed dividers */ 197 uint32_t reference_div; 198 uint32_t post_div; 199 200 /* pll in/out limits */ 201 uint32_t pll_in_min; 202 uint32_t pll_in_max; 203 uint32_t pll_out_min; 204 uint32_t pll_out_max; 205 uint32_t lcd_pll_out_min; 206 uint32_t lcd_pll_out_max; 207 uint32_t best_vco; 208 209 /* divider limits */ 210 uint32_t min_ref_div; 211 uint32_t max_ref_div; 212 uint32_t min_post_div; 213 uint32_t max_post_div; 214 uint32_t min_feedback_div; 215 uint32_t max_feedback_div; 216 uint32_t min_frac_feedback_div; 217 uint32_t max_frac_feedback_div; 218 219 /* flags for the current clock */ 220 uint32_t flags; 221 222 /* pll id */ 223 uint32_t id; 224 }; 225 226 struct amdgpu_i2c_chan { 227 struct i2c_adapter adapter; 228 struct drm_device *dev; 229 struct i2c_algo_bit_data bit; 230 struct amdgpu_i2c_bus_rec rec; 231 struct drm_dp_aux aux; 232 bool has_aux; 233 struct mutex mutex; 234 }; 235 236 struct amdgpu_afmt { 237 bool enabled; 238 int offset; 239 bool last_buffer_filled_status; 240 int id; 241 struct amdgpu_audio_pin *pin; 242 }; 243 244 /* 245 * Audio 246 */ 247 struct amdgpu_audio_pin { 248 int channels; 249 int rate; 250 int bits_per_sample; 251 u8 status_bits; 252 u8 category_code; 253 u32 offset; 254 bool connected; 255 u32 id; 256 }; 257 258 struct amdgpu_audio { 259 bool enabled; 260 struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS]; 261 int num_pins; 262 }; 263 264 struct amdgpu_display_funcs { 265 /* display watermarks */ 266 void (*bandwidth_update)(struct amdgpu_device *adev); 267 /* get frame count */ 268 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc); 269 /* set backlight level */ 270 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder, 271 u8 level); 272 /* get backlight level */ 273 u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder); 274 /* hotplug detect */ 275 bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd); 276 void (*hpd_set_polarity)(struct amdgpu_device *adev, 277 enum amdgpu_hpd_id hpd); 278 u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev); 279 /* pageflipping */ 280 void (*page_flip)(struct amdgpu_device *adev, 281 int crtc_id, u64 crtc_base, bool async); 282 int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc, 283 u32 *vbl, u32 *position); 284 /* display topology setup */ 285 void (*add_encoder)(struct amdgpu_device *adev, 286 uint32_t encoder_enum, 287 uint32_t supported_device, 288 u16 caps); 289 void (*add_connector)(struct amdgpu_device *adev, 290 uint32_t connector_id, 291 uint32_t supported_device, 292 int connector_type, 293 struct amdgpu_i2c_bus_rec *i2c_bus, 294 uint16_t connector_object_id, 295 struct amdgpu_hpd *hpd, 296 struct amdgpu_router *router); 297 298 299 }; 300 301 struct amdgpu_framebuffer { 302 struct drm_framebuffer base; 303 304 uint64_t tiling_flags; 305 bool tmz_surface; 306 307 /* caching for later use */ 308 uint64_t address; 309 }; 310 311 struct amdgpu_mode_info { 312 struct atom_context *atom_context; 313 struct card_info *atom_card_info; 314 bool mode_config_initialized; 315 struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS]; 316 struct drm_plane *planes[AMDGPU_MAX_PLANES]; 317 struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS]; 318 /* DVI-I properties */ 319 struct drm_property *coherent_mode_property; 320 /* DAC enable load detect */ 321 struct drm_property *load_detect_property; 322 /* underscan */ 323 struct drm_property *underscan_property; 324 struct drm_property *underscan_hborder_property; 325 struct drm_property *underscan_vborder_property; 326 /* audio */ 327 struct drm_property *audio_property; 328 /* FMT dithering */ 329 struct drm_property *dither_property; 330 /* Adaptive Backlight Modulation (power feature) */ 331 struct drm_property *abm_level_property; 332 /* hardcoded DFP edid from BIOS */ 333 struct edid *bios_hardcoded_edid; 334 int bios_hardcoded_edid_size; 335 336 /* firmware flags */ 337 u32 firmware_flags; 338 /* pointer to backlight encoder */ 339 struct amdgpu_encoder *bl_encoder; 340 u8 bl_level; /* saved backlight level */ 341 struct amdgpu_audio audio; /* audio stuff */ 342 int num_crtc; /* number of crtcs */ 343 int num_hpd; /* number of hpd pins */ 344 int num_dig; /* number of dig blocks */ 345 bool gpu_vm_support; /* supports display from GTT */ 346 int disp_priority; 347 const struct amdgpu_display_funcs *funcs; 348 const enum drm_plane_type *plane_type; 349 }; 350 351 #define AMDGPU_MAX_BL_LEVEL 0xFF 352 353 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 354 355 struct amdgpu_backlight_privdata { 356 struct amdgpu_encoder *encoder; 357 uint8_t negative; 358 }; 359 360 #endif 361 362 struct amdgpu_atom_ss { 363 uint16_t percentage; 364 uint16_t percentage_divider; 365 uint8_t type; 366 uint16_t step; 367 uint8_t delay; 368 uint8_t range; 369 uint8_t refdiv; 370 /* asic_ss */ 371 uint16_t rate; 372 uint16_t amount; 373 }; 374 375 struct amdgpu_crtc { 376 struct drm_crtc base; 377 int crtc_id; 378 bool enabled; 379 bool can_tile; 380 uint32_t crtc_offset; 381 struct drm_gem_object *cursor_bo; 382 uint64_t cursor_addr; 383 int cursor_x; 384 int cursor_y; 385 int cursor_hot_x; 386 int cursor_hot_y; 387 int cursor_width; 388 int cursor_height; 389 int max_cursor_width; 390 int max_cursor_height; 391 enum amdgpu_rmx_type rmx_type; 392 u8 h_border; 393 u8 v_border; 394 fixed20_12 vsc; 395 fixed20_12 hsc; 396 struct drm_display_mode native_mode; 397 u32 pll_id; 398 /* page flipping */ 399 struct amdgpu_flip_work *pflip_works; 400 enum amdgpu_flip_status pflip_status; 401 int deferred_flip_completion; 402 /* parameters access from DM IRQ handler */ 403 struct dm_irq_params dm_irq_params; 404 /* pll sharing */ 405 struct amdgpu_atom_ss ss; 406 bool ss_enabled; 407 u32 adjusted_clock; 408 int bpc; 409 u32 pll_reference_div; 410 u32 pll_post_div; 411 u32 pll_flags; 412 struct drm_encoder *encoder; 413 struct drm_connector *connector; 414 /* for dpm */ 415 u32 line_time; 416 u32 wm_low; 417 u32 wm_high; 418 u32 lb_vblank_lead_lines; 419 struct drm_display_mode hw_mode; 420 /* for virtual dce */ 421 struct hrtimer vblank_timer; 422 enum amdgpu_interrupt_state vsync_timer_enabled; 423 424 int otg_inst; 425 struct drm_pending_vblank_event *event; 426 }; 427 428 struct amdgpu_encoder_atom_dig { 429 bool linkb; 430 /* atom dig */ 431 bool coherent_mode; 432 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 433 /* atom lvds/edp */ 434 uint32_t lcd_misc; 435 uint16_t panel_pwr_delay; 436 uint32_t lcd_ss_id; 437 /* panel mode */ 438 struct drm_display_mode native_mode; 439 struct backlight_device *bl_dev; 440 int dpms_mode; 441 uint8_t backlight_level; 442 int panel_mode; 443 struct amdgpu_afmt *afmt; 444 }; 445 446 struct amdgpu_encoder { 447 struct drm_encoder base; 448 uint32_t encoder_enum; 449 uint32_t encoder_id; 450 uint32_t devices; 451 uint32_t active_device; 452 uint32_t flags; 453 uint32_t pixel_clock; 454 enum amdgpu_rmx_type rmx_type; 455 enum amdgpu_underscan_type underscan_type; 456 uint32_t underscan_hborder; 457 uint32_t underscan_vborder; 458 struct drm_display_mode native_mode; 459 void *enc_priv; 460 int audio_polling_active; 461 bool is_ext_encoder; 462 u16 caps; 463 }; 464 465 struct amdgpu_connector_atom_dig { 466 /* displayport */ 467 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 468 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 469 u8 dp_sink_type; 470 int dp_clock; 471 int dp_lane_count; 472 bool edp_on; 473 }; 474 475 struct amdgpu_gpio_rec { 476 bool valid; 477 u8 id; 478 u32 reg; 479 u32 mask; 480 u32 shift; 481 }; 482 483 struct amdgpu_hpd { 484 enum amdgpu_hpd_id hpd; 485 u8 plugged_state; 486 struct amdgpu_gpio_rec gpio; 487 }; 488 489 struct amdgpu_router { 490 u32 router_id; 491 struct amdgpu_i2c_bus_rec i2c_info; 492 u8 i2c_addr; 493 /* i2c mux */ 494 bool ddc_valid; 495 u8 ddc_mux_type; 496 u8 ddc_mux_control_pin; 497 u8 ddc_mux_state; 498 /* clock/data mux */ 499 bool cd_valid; 500 u8 cd_mux_type; 501 u8 cd_mux_control_pin; 502 u8 cd_mux_state; 503 }; 504 505 enum amdgpu_connector_audio { 506 AMDGPU_AUDIO_DISABLE = 0, 507 AMDGPU_AUDIO_ENABLE = 1, 508 AMDGPU_AUDIO_AUTO = 2 509 }; 510 511 enum amdgpu_connector_dither { 512 AMDGPU_FMT_DITHER_DISABLE = 0, 513 AMDGPU_FMT_DITHER_ENABLE = 1, 514 }; 515 516 struct amdgpu_dm_dp_aux { 517 struct drm_dp_aux aux; 518 struct ddc_service *ddc_service; 519 }; 520 521 struct amdgpu_i2c_adapter { 522 struct i2c_adapter base; 523 524 struct ddc_service *ddc_service; 525 }; 526 527 #define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux) 528 529 struct amdgpu_connector { 530 struct drm_connector base; 531 uint32_t connector_id; 532 uint32_t devices; 533 struct amdgpu_i2c_chan *ddc_bus; 534 /* some systems have an hdmi and vga port with a shared ddc line */ 535 bool shared_ddc; 536 bool use_digital; 537 /* we need to mind the EDID between detect 538 and get modes due to analog/digital/tvencoder */ 539 struct edid *edid; 540 void *con_priv; 541 bool dac_load_detect; 542 bool detected_by_load; /* if the connection status was determined by load */ 543 uint16_t connector_object_id; 544 struct amdgpu_hpd hpd; 545 struct amdgpu_router router; 546 struct amdgpu_i2c_chan *router_bus; 547 enum amdgpu_connector_audio audio; 548 enum amdgpu_connector_dither dither; 549 unsigned pixelclock_for_modeset; 550 }; 551 552 /* TODO: start to use this struct and remove same field from base one */ 553 struct amdgpu_mst_connector { 554 struct amdgpu_connector base; 555 556 struct drm_dp_mst_topology_mgr mst_mgr; 557 struct amdgpu_dm_dp_aux dm_dp_aux; 558 struct drm_dp_mst_port *port; 559 struct amdgpu_connector *mst_port; 560 bool is_mst_connector; 561 struct amdgpu_encoder *mst_encoder; 562 }; 563 564 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 565 ((em) == ATOM_ENCODER_MODE_DP_MST)) 566 567 /* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */ 568 #define DRM_SCANOUTPOS_VALID (1 << 0) 569 #define DRM_SCANOUTPOS_IN_VBLANK (1 << 1) 570 #define DRM_SCANOUTPOS_ACCURATE (1 << 2) 571 #define USE_REAL_VBLANKSTART (1 << 30) 572 #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) 573 574 void amdgpu_link_encoder_connector(struct drm_device *dev); 575 576 struct drm_connector * 577 amdgpu_get_connector_for_encoder(struct drm_encoder *encoder); 578 struct drm_connector * 579 amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder); 580 bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, 581 u32 pixel_clock); 582 583 u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 584 struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder); 585 586 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, 587 bool use_aux); 588 589 void amdgpu_encoder_set_active_device(struct drm_encoder *encoder); 590 591 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, 592 unsigned int pipe, unsigned int flags, int *vpos, 593 int *hpos, ktime_t *stime, ktime_t *etime, 594 const struct drm_display_mode *mode); 595 596 int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 597 598 void amdgpu_enc_destroy(struct drm_encoder *encoder); 599 void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 600 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 601 const struct drm_display_mode *mode, 602 struct drm_display_mode *adjusted_mode); 603 void amdgpu_panel_mode_fixup(struct drm_encoder *encoder, 604 struct drm_display_mode *adjusted_mode); 605 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc); 606 607 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, 608 bool in_vblank_irq, int *vpos, 609 int *hpos, ktime_t *stime, ktime_t *etime, 610 const struct drm_display_mode *mode); 611 612 /* amdgpu_display.c */ 613 void amdgpu_display_print_display_setup(struct drm_device *dev); 614 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev); 615 int amdgpu_display_crtc_set_config(struct drm_mode_set *set, 616 struct drm_modeset_acquire_ctx *ctx); 617 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, 618 struct drm_framebuffer *fb, 619 struct drm_pending_vblank_event *event, 620 uint32_t page_flip_flags, uint32_t target, 621 struct drm_modeset_acquire_ctx *ctx); 622 extern const struct drm_mode_config_funcs amdgpu_mode_funcs; 623 624 #endif 625