1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu_sched.h" 32 #include "amdgpu_uvd.h" 33 #include "amdgpu_vce.h" 34 35 #include <linux/vga_switcheroo.h> 36 #include <linux/slab.h> 37 #include <linux/pm_runtime.h> 38 #include "amdgpu_amdkfd.h" 39 40 /** 41 * amdgpu_driver_unload_kms - Main unload function for KMS. 42 * 43 * @dev: drm dev pointer 44 * 45 * This is the main unload function for KMS (all asics). 46 * Returns 0 on success. 47 */ 48 void amdgpu_driver_unload_kms(struct drm_device *dev) 49 { 50 struct amdgpu_device *adev = dev->dev_private; 51 52 if (adev == NULL) 53 return; 54 55 if (adev->rmmio == NULL) 56 goto done_free; 57 58 if (amdgpu_sriov_vf(adev)) 59 amdgpu_virt_request_full_gpu(adev, false); 60 61 if (amdgpu_device_is_px(dev)) { 62 pm_runtime_get_sync(dev->dev); 63 pm_runtime_forbid(dev->dev); 64 } 65 66 amdgpu_acpi_fini(adev); 67 68 amdgpu_device_fini(adev); 69 70 done_free: 71 kfree(adev); 72 dev->dev_private = NULL; 73 } 74 75 /** 76 * amdgpu_driver_load_kms - Main load function for KMS. 77 * 78 * @dev: drm dev pointer 79 * @flags: device flags 80 * 81 * This is the main load function for KMS (all asics). 82 * Returns 0 on success, error on failure. 83 */ 84 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) 85 { 86 struct amdgpu_device *adev; 87 int r, acpi_status; 88 89 #ifdef CONFIG_DRM_AMDGPU_SI 90 if (!amdgpu_si_support) { 91 switch (flags & AMD_ASIC_MASK) { 92 case CHIP_TAHITI: 93 case CHIP_PITCAIRN: 94 case CHIP_VERDE: 95 case CHIP_OLAND: 96 case CHIP_HAINAN: 97 dev_info(dev->dev, 98 "SI support provided by radeon.\n"); 99 dev_info(dev->dev, 100 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 101 ); 102 return -ENODEV; 103 } 104 } 105 #endif 106 #ifdef CONFIG_DRM_AMDGPU_CIK 107 if (!amdgpu_cik_support) { 108 switch (flags & AMD_ASIC_MASK) { 109 case CHIP_KAVERI: 110 case CHIP_BONAIRE: 111 case CHIP_HAWAII: 112 case CHIP_KABINI: 113 case CHIP_MULLINS: 114 dev_info(dev->dev, 115 "CIK support provided by radeon.\n"); 116 dev_info(dev->dev, 117 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 118 ); 119 return -ENODEV; 120 } 121 } 122 #endif 123 124 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); 125 if (adev == NULL) { 126 return -ENOMEM; 127 } 128 dev->dev_private = (void *)adev; 129 130 if ((amdgpu_runtime_pm != 0) && 131 amdgpu_has_atpx() && 132 (amdgpu_is_atpx_hybrid() || 133 amdgpu_has_atpx_dgpu_power_cntl()) && 134 ((flags & AMD_IS_APU) == 0) && 135 !pci_is_thunderbolt_attached(dev->pdev)) 136 flags |= AMD_IS_PX; 137 138 /* amdgpu_device_init should report only fatal error 139 * like memory allocation failure or iomapping failure, 140 * or memory manager initialization failure, it must 141 * properly initialize the GPU MC controller and permit 142 * VRAM allocation 143 */ 144 r = amdgpu_device_init(adev, dev, dev->pdev, flags); 145 if (r) { 146 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 147 goto out; 148 } 149 150 /* Call ACPI methods: require modeset init 151 * but failure is not fatal 152 */ 153 if (!r) { 154 acpi_status = amdgpu_acpi_init(adev); 155 if (acpi_status) 156 dev_dbg(&dev->pdev->dev, 157 "Error during ACPI methods call\n"); 158 } 159 160 if (amdgpu_device_is_px(dev)) { 161 pm_runtime_use_autosuspend(dev->dev); 162 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 163 pm_runtime_set_active(dev->dev); 164 pm_runtime_allow(dev->dev); 165 pm_runtime_mark_last_busy(dev->dev); 166 pm_runtime_put_autosuspend(dev->dev); 167 } 168 169 out: 170 if (r) { 171 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 172 if (adev->rmmio && amdgpu_device_is_px(dev)) 173 pm_runtime_put_noidle(dev->dev); 174 amdgpu_driver_unload_kms(dev); 175 } 176 177 return r; 178 } 179 180 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 181 struct drm_amdgpu_query_fw *query_fw, 182 struct amdgpu_device *adev) 183 { 184 switch (query_fw->fw_type) { 185 case AMDGPU_INFO_FW_VCE: 186 fw_info->ver = adev->vce.fw_version; 187 fw_info->feature = adev->vce.fb_version; 188 break; 189 case AMDGPU_INFO_FW_UVD: 190 fw_info->ver = adev->uvd.fw_version; 191 fw_info->feature = 0; 192 break; 193 case AMDGPU_INFO_FW_GMC: 194 fw_info->ver = adev->gmc.fw_version; 195 fw_info->feature = 0; 196 break; 197 case AMDGPU_INFO_FW_GFX_ME: 198 fw_info->ver = adev->gfx.me_fw_version; 199 fw_info->feature = adev->gfx.me_feature_version; 200 break; 201 case AMDGPU_INFO_FW_GFX_PFP: 202 fw_info->ver = adev->gfx.pfp_fw_version; 203 fw_info->feature = adev->gfx.pfp_feature_version; 204 break; 205 case AMDGPU_INFO_FW_GFX_CE: 206 fw_info->ver = adev->gfx.ce_fw_version; 207 fw_info->feature = adev->gfx.ce_feature_version; 208 break; 209 case AMDGPU_INFO_FW_GFX_RLC: 210 fw_info->ver = adev->gfx.rlc_fw_version; 211 fw_info->feature = adev->gfx.rlc_feature_version; 212 break; 213 case AMDGPU_INFO_FW_GFX_MEC: 214 if (query_fw->index == 0) { 215 fw_info->ver = adev->gfx.mec_fw_version; 216 fw_info->feature = adev->gfx.mec_feature_version; 217 } else if (query_fw->index == 1) { 218 fw_info->ver = adev->gfx.mec2_fw_version; 219 fw_info->feature = adev->gfx.mec2_feature_version; 220 } else 221 return -EINVAL; 222 break; 223 case AMDGPU_INFO_FW_SMC: 224 fw_info->ver = adev->pm.fw_version; 225 fw_info->feature = 0; 226 break; 227 case AMDGPU_INFO_FW_SDMA: 228 if (query_fw->index >= adev->sdma.num_instances) 229 return -EINVAL; 230 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 231 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 232 break; 233 case AMDGPU_INFO_FW_SOS: 234 fw_info->ver = adev->psp.sos_fw_version; 235 fw_info->feature = adev->psp.sos_feature_version; 236 break; 237 case AMDGPU_INFO_FW_ASD: 238 fw_info->ver = adev->psp.asd_fw_version; 239 fw_info->feature = adev->psp.asd_feature_version; 240 break; 241 default: 242 return -EINVAL; 243 } 244 return 0; 245 } 246 247 /* 248 * Userspace get information ioctl 249 */ 250 /** 251 * amdgpu_info_ioctl - answer a device specific request. 252 * 253 * @adev: amdgpu device pointer 254 * @data: request object 255 * @filp: drm filp 256 * 257 * This function is used to pass device specific parameters to the userspace 258 * drivers. Examples include: pci device id, pipeline parms, tiling params, 259 * etc. (all asics). 260 * Returns 0 on success, -EINVAL on failure. 261 */ 262 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 263 { 264 struct amdgpu_device *adev = dev->dev_private; 265 struct drm_amdgpu_info *info = data; 266 struct amdgpu_mode_info *minfo = &adev->mode_info; 267 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 268 uint32_t size = info->return_size; 269 struct drm_crtc *crtc; 270 uint32_t ui32 = 0; 271 uint64_t ui64 = 0; 272 int i, found; 273 int ui32_size = sizeof(ui32); 274 275 if (!info->return_size || !info->return_pointer) 276 return -EINVAL; 277 278 switch (info->query) { 279 case AMDGPU_INFO_ACCEL_WORKING: 280 ui32 = adev->accel_working; 281 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 282 case AMDGPU_INFO_CRTC_FROM_ID: 283 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 284 crtc = (struct drm_crtc *)minfo->crtcs[i]; 285 if (crtc && crtc->base.id == info->mode_crtc.id) { 286 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 287 ui32 = amdgpu_crtc->crtc_id; 288 found = 1; 289 break; 290 } 291 } 292 if (!found) { 293 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 294 return -EINVAL; 295 } 296 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 297 case AMDGPU_INFO_HW_IP_INFO: { 298 struct drm_amdgpu_info_hw_ip ip = {}; 299 enum amd_ip_block_type type; 300 uint32_t ring_mask = 0; 301 uint32_t ib_start_alignment = 0; 302 uint32_t ib_size_alignment = 0; 303 304 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 305 return -EINVAL; 306 307 switch (info->query_hw_ip.type) { 308 case AMDGPU_HW_IP_GFX: 309 type = AMD_IP_BLOCK_TYPE_GFX; 310 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 311 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i); 312 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 313 ib_size_alignment = 8; 314 break; 315 case AMDGPU_HW_IP_COMPUTE: 316 type = AMD_IP_BLOCK_TYPE_GFX; 317 for (i = 0; i < adev->gfx.num_compute_rings; i++) 318 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i); 319 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 320 ib_size_alignment = 8; 321 break; 322 case AMDGPU_HW_IP_DMA: 323 type = AMD_IP_BLOCK_TYPE_SDMA; 324 for (i = 0; i < adev->sdma.num_instances; i++) 325 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i); 326 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 327 ib_size_alignment = 1; 328 break; 329 case AMDGPU_HW_IP_UVD: 330 type = AMD_IP_BLOCK_TYPE_UVD; 331 ring_mask = adev->uvd.ring.ready ? 1 : 0; 332 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 333 ib_size_alignment = 16; 334 break; 335 case AMDGPU_HW_IP_VCE: 336 type = AMD_IP_BLOCK_TYPE_VCE; 337 for (i = 0; i < adev->vce.num_rings; i++) 338 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i); 339 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 340 ib_size_alignment = 1; 341 break; 342 case AMDGPU_HW_IP_UVD_ENC: 343 type = AMD_IP_BLOCK_TYPE_UVD; 344 for (i = 0; i < adev->uvd.num_enc_rings; i++) 345 ring_mask |= ((adev->uvd.ring_enc[i].ready ? 1 : 0) << i); 346 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 347 ib_size_alignment = 1; 348 break; 349 case AMDGPU_HW_IP_VCN_DEC: 350 type = AMD_IP_BLOCK_TYPE_VCN; 351 ring_mask = adev->vcn.ring_dec.ready ? 1 : 0; 352 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 353 ib_size_alignment = 16; 354 break; 355 case AMDGPU_HW_IP_VCN_ENC: 356 type = AMD_IP_BLOCK_TYPE_VCN; 357 for (i = 0; i < adev->vcn.num_enc_rings; i++) 358 ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0) << i); 359 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 360 ib_size_alignment = 1; 361 break; 362 default: 363 return -EINVAL; 364 } 365 366 for (i = 0; i < adev->num_ip_blocks; i++) { 367 if (adev->ip_blocks[i].version->type == type && 368 adev->ip_blocks[i].status.valid) { 369 ip.hw_ip_version_major = adev->ip_blocks[i].version->major; 370 ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor; 371 ip.capabilities_flags = 0; 372 ip.available_rings = ring_mask; 373 ip.ib_start_alignment = ib_start_alignment; 374 ip.ib_size_alignment = ib_size_alignment; 375 break; 376 } 377 } 378 return copy_to_user(out, &ip, 379 min((size_t)size, sizeof(ip))) ? -EFAULT : 0; 380 } 381 case AMDGPU_INFO_HW_IP_COUNT: { 382 enum amd_ip_block_type type; 383 uint32_t count = 0; 384 385 switch (info->query_hw_ip.type) { 386 case AMDGPU_HW_IP_GFX: 387 type = AMD_IP_BLOCK_TYPE_GFX; 388 break; 389 case AMDGPU_HW_IP_COMPUTE: 390 type = AMD_IP_BLOCK_TYPE_GFX; 391 break; 392 case AMDGPU_HW_IP_DMA: 393 type = AMD_IP_BLOCK_TYPE_SDMA; 394 break; 395 case AMDGPU_HW_IP_UVD: 396 type = AMD_IP_BLOCK_TYPE_UVD; 397 break; 398 case AMDGPU_HW_IP_VCE: 399 type = AMD_IP_BLOCK_TYPE_VCE; 400 break; 401 case AMDGPU_HW_IP_UVD_ENC: 402 type = AMD_IP_BLOCK_TYPE_UVD; 403 break; 404 case AMDGPU_HW_IP_VCN_DEC: 405 case AMDGPU_HW_IP_VCN_ENC: 406 type = AMD_IP_BLOCK_TYPE_VCN; 407 break; 408 default: 409 return -EINVAL; 410 } 411 412 for (i = 0; i < adev->num_ip_blocks; i++) 413 if (adev->ip_blocks[i].version->type == type && 414 adev->ip_blocks[i].status.valid && 415 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 416 count++; 417 418 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 419 } 420 case AMDGPU_INFO_TIMESTAMP: 421 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 422 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 423 case AMDGPU_INFO_FW_VERSION: { 424 struct drm_amdgpu_info_firmware fw_info; 425 int ret; 426 427 /* We only support one instance of each IP block right now. */ 428 if (info->query_fw.ip_instance != 0) 429 return -EINVAL; 430 431 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 432 if (ret) 433 return ret; 434 435 return copy_to_user(out, &fw_info, 436 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 437 } 438 case AMDGPU_INFO_NUM_BYTES_MOVED: 439 ui64 = atomic64_read(&adev->num_bytes_moved); 440 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 441 case AMDGPU_INFO_NUM_EVICTIONS: 442 ui64 = atomic64_read(&adev->num_evictions); 443 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 444 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 445 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 446 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 447 case AMDGPU_INFO_VRAM_USAGE: 448 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 449 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 450 case AMDGPU_INFO_VIS_VRAM_USAGE: 451 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 452 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 453 case AMDGPU_INFO_GTT_USAGE: 454 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 455 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 456 case AMDGPU_INFO_GDS_CONFIG: { 457 struct drm_amdgpu_info_gds gds_info; 458 459 memset(&gds_info, 0, sizeof(gds_info)); 460 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT; 461 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT; 462 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT; 463 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT; 464 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT; 465 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT; 466 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT; 467 return copy_to_user(out, &gds_info, 468 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 469 } 470 case AMDGPU_INFO_VRAM_GTT: { 471 struct drm_amdgpu_info_vram_gtt vram_gtt; 472 473 vram_gtt.vram_size = adev->gmc.real_vram_size; 474 vram_gtt.vram_size -= adev->vram_pin_size; 475 vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size; 476 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size); 477 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size; 478 vram_gtt.gtt_size *= PAGE_SIZE; 479 vram_gtt.gtt_size -= adev->gart_pin_size; 480 return copy_to_user(out, &vram_gtt, 481 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 482 } 483 case AMDGPU_INFO_MEMORY: { 484 struct drm_amdgpu_memory_info mem; 485 486 memset(&mem, 0, sizeof(mem)); 487 mem.vram.total_heap_size = adev->gmc.real_vram_size; 488 mem.vram.usable_heap_size = 489 adev->gmc.real_vram_size - adev->vram_pin_size; 490 mem.vram.heap_usage = 491 amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 492 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 493 494 mem.cpu_accessible_vram.total_heap_size = 495 adev->gmc.visible_vram_size; 496 mem.cpu_accessible_vram.usable_heap_size = 497 adev->gmc.visible_vram_size - 498 (adev->vram_pin_size - adev->invisible_pin_size); 499 mem.cpu_accessible_vram.heap_usage = 500 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 501 mem.cpu_accessible_vram.max_allocation = 502 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 503 504 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size; 505 mem.gtt.total_heap_size *= PAGE_SIZE; 506 mem.gtt.usable_heap_size = mem.gtt.total_heap_size 507 - adev->gart_pin_size; 508 mem.gtt.heap_usage = 509 amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 510 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 511 512 return copy_to_user(out, &mem, 513 min((size_t)size, sizeof(mem))) 514 ? -EFAULT : 0; 515 } 516 case AMDGPU_INFO_READ_MMR_REG: { 517 unsigned n, alloc_size; 518 uint32_t *regs; 519 unsigned se_num = (info->read_mmr_reg.instance >> 520 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 521 AMDGPU_INFO_MMR_SE_INDEX_MASK; 522 unsigned sh_num = (info->read_mmr_reg.instance >> 523 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 524 AMDGPU_INFO_MMR_SH_INDEX_MASK; 525 526 /* set full masks if the userspace set all bits 527 * in the bitfields */ 528 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 529 se_num = 0xffffffff; 530 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 531 sh_num = 0xffffffff; 532 533 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 534 if (!regs) 535 return -ENOMEM; 536 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 537 538 for (i = 0; i < info->read_mmr_reg.count; i++) 539 if (amdgpu_asic_read_register(adev, se_num, sh_num, 540 info->read_mmr_reg.dword_offset + i, 541 ®s[i])) { 542 DRM_DEBUG_KMS("unallowed offset %#x\n", 543 info->read_mmr_reg.dword_offset + i); 544 kfree(regs); 545 return -EFAULT; 546 } 547 n = copy_to_user(out, regs, min(size, alloc_size)); 548 kfree(regs); 549 return n ? -EFAULT : 0; 550 } 551 case AMDGPU_INFO_DEV_INFO: { 552 struct drm_amdgpu_info_device dev_info = {}; 553 uint64_t vm_size; 554 555 dev_info.device_id = dev->pdev->device; 556 dev_info.chip_rev = adev->rev_id; 557 dev_info.external_rev = adev->external_rev_id; 558 dev_info.pci_rev = dev->pdev->revision; 559 dev_info.family = adev->family; 560 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; 561 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 562 /* return all clocks in KHz */ 563 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 564 if (adev->pm.dpm_enabled) { 565 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 566 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 567 } else { 568 dev_info.max_engine_clock = adev->clock.default_sclk * 10; 569 dev_info.max_memory_clock = adev->clock.default_mclk * 10; 570 } 571 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 572 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 573 adev->gfx.config.max_shader_engines; 574 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 575 dev_info._pad = 0; 576 dev_info.ids_flags = 0; 577 if (adev->flags & AMD_IS_APU) 578 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 579 if (amdgpu_sriov_vf(adev)) 580 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 581 582 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 583 vm_size -= AMDGPU_VA_RESERVED_SIZE; 584 585 /* Older VCE FW versions are buggy and can handle only 40bits */ 586 if (adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 587 vm_size = min(vm_size, 1ULL << 40); 588 589 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 590 dev_info.virtual_address_max = 591 min(vm_size, AMDGPU_VA_HOLE_START); 592 593 if (vm_size > AMDGPU_VA_HOLE_START) { 594 dev_info.high_va_offset = AMDGPU_VA_HOLE_END; 595 dev_info.high_va_max = AMDGPU_VA_HOLE_END | vm_size; 596 } 597 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 598 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 599 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; 600 dev_info.cu_active_number = adev->gfx.cu_info.number; 601 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 602 dev_info.ce_ram_size = adev->gfx.ce_ram_size; 603 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 604 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 605 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 606 sizeof(adev->gfx.cu_info.bitmap)); 607 dev_info.vram_type = adev->gmc.vram_type; 608 dev_info.vram_bit_width = adev->gmc.vram_width; 609 dev_info.vce_harvest_config = adev->vce.harvest_config; 610 dev_info.gc_double_offchip_lds_buf = 611 adev->gfx.config.double_offchip_lds_buf; 612 613 if (amdgpu_ngg) { 614 dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr; 615 dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size; 616 dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr; 617 dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size; 618 dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr; 619 dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size; 620 dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr; 621 dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size; 622 } 623 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size; 624 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs; 625 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 626 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 627 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 628 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 629 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 630 631 return copy_to_user(out, &dev_info, 632 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 633 } 634 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 635 unsigned i; 636 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 637 struct amd_vce_state *vce_state; 638 639 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 640 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 641 if (vce_state) { 642 vce_clk_table.entries[i].sclk = vce_state->sclk; 643 vce_clk_table.entries[i].mclk = vce_state->mclk; 644 vce_clk_table.entries[i].eclk = vce_state->evclk; 645 vce_clk_table.num_valid_entries++; 646 } 647 } 648 649 return copy_to_user(out, &vce_clk_table, 650 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 651 } 652 case AMDGPU_INFO_VBIOS: { 653 uint32_t bios_size = adev->bios_size; 654 655 switch (info->vbios_info.type) { 656 case AMDGPU_INFO_VBIOS_SIZE: 657 return copy_to_user(out, &bios_size, 658 min((size_t)size, sizeof(bios_size))) 659 ? -EFAULT : 0; 660 case AMDGPU_INFO_VBIOS_IMAGE: { 661 uint8_t *bios; 662 uint32_t bios_offset = info->vbios_info.offset; 663 664 if (bios_offset >= bios_size) 665 return -EINVAL; 666 667 bios = adev->bios + bios_offset; 668 return copy_to_user(out, bios, 669 min((size_t)size, (size_t)(bios_size - bios_offset))) 670 ? -EFAULT : 0; 671 } 672 default: 673 DRM_DEBUG_KMS("Invalid request %d\n", 674 info->vbios_info.type); 675 return -EINVAL; 676 } 677 } 678 case AMDGPU_INFO_NUM_HANDLES: { 679 struct drm_amdgpu_info_num_handles handle; 680 681 switch (info->query_hw_ip.type) { 682 case AMDGPU_HW_IP_UVD: 683 /* Starting Polaris, we support unlimited UVD handles */ 684 if (adev->asic_type < CHIP_POLARIS10) { 685 handle.uvd_max_handles = adev->uvd.max_handles; 686 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 687 688 return copy_to_user(out, &handle, 689 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 690 } else { 691 return -ENODATA; 692 } 693 694 break; 695 default: 696 return -EINVAL; 697 } 698 } 699 case AMDGPU_INFO_SENSOR: { 700 struct pp_gpu_power query = {0}; 701 int query_size = sizeof(query); 702 703 if (amdgpu_dpm == 0) 704 return -ENOENT; 705 706 switch (info->sensor_info.type) { 707 case AMDGPU_INFO_SENSOR_GFX_SCLK: 708 /* get sclk in Mhz */ 709 if (amdgpu_dpm_read_sensor(adev, 710 AMDGPU_PP_SENSOR_GFX_SCLK, 711 (void *)&ui32, &ui32_size)) { 712 return -EINVAL; 713 } 714 ui32 /= 100; 715 break; 716 case AMDGPU_INFO_SENSOR_GFX_MCLK: 717 /* get mclk in Mhz */ 718 if (amdgpu_dpm_read_sensor(adev, 719 AMDGPU_PP_SENSOR_GFX_MCLK, 720 (void *)&ui32, &ui32_size)) { 721 return -EINVAL; 722 } 723 ui32 /= 100; 724 break; 725 case AMDGPU_INFO_SENSOR_GPU_TEMP: 726 /* get temperature in millidegrees C */ 727 if (amdgpu_dpm_read_sensor(adev, 728 AMDGPU_PP_SENSOR_GPU_TEMP, 729 (void *)&ui32, &ui32_size)) { 730 return -EINVAL; 731 } 732 break; 733 case AMDGPU_INFO_SENSOR_GPU_LOAD: 734 /* get GPU load */ 735 if (amdgpu_dpm_read_sensor(adev, 736 AMDGPU_PP_SENSOR_GPU_LOAD, 737 (void *)&ui32, &ui32_size)) { 738 return -EINVAL; 739 } 740 break; 741 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 742 /* get average GPU power */ 743 if (amdgpu_dpm_read_sensor(adev, 744 AMDGPU_PP_SENSOR_GPU_POWER, 745 (void *)&query, &query_size)) { 746 return -EINVAL; 747 } 748 ui32 = query.average_gpu_power >> 8; 749 break; 750 case AMDGPU_INFO_SENSOR_VDDNB: 751 /* get VDDNB in millivolts */ 752 if (amdgpu_dpm_read_sensor(adev, 753 AMDGPU_PP_SENSOR_VDDNB, 754 (void *)&ui32, &ui32_size)) { 755 return -EINVAL; 756 } 757 break; 758 case AMDGPU_INFO_SENSOR_VDDGFX: 759 /* get VDDGFX in millivolts */ 760 if (amdgpu_dpm_read_sensor(adev, 761 AMDGPU_PP_SENSOR_VDDGFX, 762 (void *)&ui32, &ui32_size)) { 763 return -EINVAL; 764 } 765 break; 766 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 767 /* get stable pstate sclk in Mhz */ 768 if (amdgpu_dpm_read_sensor(adev, 769 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 770 (void *)&ui32, &ui32_size)) { 771 return -EINVAL; 772 } 773 ui32 /= 100; 774 break; 775 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 776 /* get stable pstate mclk in Mhz */ 777 if (amdgpu_dpm_read_sensor(adev, 778 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 779 (void *)&ui32, &ui32_size)) { 780 return -EINVAL; 781 } 782 ui32 /= 100; 783 break; 784 default: 785 DRM_DEBUG_KMS("Invalid request %d\n", 786 info->sensor_info.type); 787 return -EINVAL; 788 } 789 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 790 } 791 case AMDGPU_INFO_VRAM_LOST_COUNTER: 792 ui32 = atomic_read(&adev->vram_lost_counter); 793 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 794 default: 795 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 796 return -EINVAL; 797 } 798 return 0; 799 } 800 801 802 /* 803 * Outdated mess for old drm with Xorg being in charge (void function now). 804 */ 805 /** 806 * amdgpu_driver_lastclose_kms - drm callback for last close 807 * 808 * @dev: drm dev pointer 809 * 810 * Switch vga_switcheroo state after last close (all asics). 811 */ 812 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 813 { 814 drm_fb_helper_lastclose(dev); 815 vga_switcheroo_process_delayed_switch(); 816 } 817 818 /** 819 * amdgpu_driver_open_kms - drm callback for open 820 * 821 * @dev: drm dev pointer 822 * @file_priv: drm file 823 * 824 * On device open, init vm on cayman+ (all asics). 825 * Returns 0 on success, error on failure. 826 */ 827 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 828 { 829 struct amdgpu_device *adev = dev->dev_private; 830 struct amdgpu_fpriv *fpriv; 831 int r, pasid; 832 833 file_priv->driver_priv = NULL; 834 835 r = pm_runtime_get_sync(dev->dev); 836 if (r < 0) 837 return r; 838 839 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 840 if (unlikely(!fpriv)) { 841 r = -ENOMEM; 842 goto out_suspend; 843 } 844 845 pasid = amdgpu_pasid_alloc(16); 846 if (pasid < 0) { 847 dev_warn(adev->dev, "No more PASIDs available!"); 848 pasid = 0; 849 } 850 r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid); 851 if (r) 852 goto error_pasid; 853 854 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 855 if (!fpriv->prt_va) { 856 r = -ENOMEM; 857 goto error_vm; 858 } 859 860 if (amdgpu_sriov_vf(adev)) { 861 r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va); 862 if (r) 863 goto error_vm; 864 } 865 866 mutex_init(&fpriv->bo_list_lock); 867 idr_init(&fpriv->bo_list_handles); 868 869 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 870 871 file_priv->driver_priv = fpriv; 872 goto out_suspend; 873 874 error_vm: 875 amdgpu_vm_fini(adev, &fpriv->vm); 876 877 error_pasid: 878 if (pasid) 879 amdgpu_pasid_free(pasid); 880 881 kfree(fpriv); 882 883 out_suspend: 884 pm_runtime_mark_last_busy(dev->dev); 885 pm_runtime_put_autosuspend(dev->dev); 886 887 return r; 888 } 889 890 /** 891 * amdgpu_driver_postclose_kms - drm callback for post close 892 * 893 * @dev: drm dev pointer 894 * @file_priv: drm file 895 * 896 * On device post close, tear down vm on cayman+ (all asics). 897 */ 898 void amdgpu_driver_postclose_kms(struct drm_device *dev, 899 struct drm_file *file_priv) 900 { 901 struct amdgpu_device *adev = dev->dev_private; 902 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 903 struct amdgpu_bo_list *list; 904 struct amdgpu_bo *pd; 905 unsigned int pasid; 906 int handle; 907 908 if (!fpriv) 909 return; 910 911 pm_runtime_get_sync(dev->dev); 912 913 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 914 915 if (adev->asic_type != CHIP_RAVEN) { 916 amdgpu_uvd_free_handles(adev, file_priv); 917 amdgpu_vce_free_handles(adev, file_priv); 918 } 919 920 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 921 922 if (amdgpu_sriov_vf(adev)) { 923 /* TODO: how to handle reserve failure */ 924 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 925 amdgpu_vm_bo_rmv(adev, fpriv->csa_va); 926 fpriv->csa_va = NULL; 927 amdgpu_bo_unreserve(adev->virt.csa_obj); 928 } 929 930 pasid = fpriv->vm.pasid; 931 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo); 932 933 amdgpu_vm_fini(adev, &fpriv->vm); 934 if (pasid) 935 amdgpu_pasid_free_delayed(pd->tbo.resv, pasid); 936 amdgpu_bo_unref(&pd); 937 938 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 939 amdgpu_bo_list_free(list); 940 941 idr_destroy(&fpriv->bo_list_handles); 942 mutex_destroy(&fpriv->bo_list_lock); 943 944 kfree(fpriv); 945 file_priv->driver_priv = NULL; 946 947 pm_runtime_mark_last_busy(dev->dev); 948 pm_runtime_put_autosuspend(dev->dev); 949 } 950 951 /* 952 * VBlank related functions. 953 */ 954 /** 955 * amdgpu_get_vblank_counter_kms - get frame count 956 * 957 * @dev: drm dev pointer 958 * @pipe: crtc to get the frame count from 959 * 960 * Gets the frame count on the requested crtc (all asics). 961 * Returns frame count on success, -EINVAL on failure. 962 */ 963 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) 964 { 965 struct amdgpu_device *adev = dev->dev_private; 966 int vpos, hpos, stat; 967 u32 count; 968 969 if (pipe >= adev->mode_info.num_crtc) { 970 DRM_ERROR("Invalid crtc %u\n", pipe); 971 return -EINVAL; 972 } 973 974 /* The hw increments its frame counter at start of vsync, not at start 975 * of vblank, as is required by DRM core vblank counter handling. 976 * Cook the hw count here to make it appear to the caller as if it 977 * incremented at start of vblank. We measure distance to start of 978 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 979 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 980 * result by 1 to give the proper appearance to caller. 981 */ 982 if (adev->mode_info.crtcs[pipe]) { 983 /* Repeat readout if needed to provide stable result if 984 * we cross start of vsync during the queries. 985 */ 986 do { 987 count = amdgpu_display_vblank_get_counter(adev, pipe); 988 /* Ask amdgpu_display_get_crtc_scanoutpos to return 989 * vpos as distance to start of vblank, instead of 990 * regular vertical scanout pos. 991 */ 992 stat = amdgpu_display_get_crtc_scanoutpos( 993 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 994 &vpos, &hpos, NULL, NULL, 995 &adev->mode_info.crtcs[pipe]->base.hwmode); 996 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 997 998 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 999 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1000 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1001 } else { 1002 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1003 pipe, vpos); 1004 1005 /* Bump counter if we are at >= leading edge of vblank, 1006 * but before vsync where vpos would turn negative and 1007 * the hw counter really increments. 1008 */ 1009 if (vpos >= 0) 1010 count++; 1011 } 1012 } else { 1013 /* Fallback to use value as is. */ 1014 count = amdgpu_display_vblank_get_counter(adev, pipe); 1015 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1016 } 1017 1018 return count; 1019 } 1020 1021 /** 1022 * amdgpu_enable_vblank_kms - enable vblank interrupt 1023 * 1024 * @dev: drm dev pointer 1025 * @pipe: crtc to enable vblank interrupt for 1026 * 1027 * Enable the interrupt on the requested crtc (all asics). 1028 * Returns 0 on success, -EINVAL on failure. 1029 */ 1030 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe) 1031 { 1032 struct amdgpu_device *adev = dev->dev_private; 1033 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1034 1035 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1036 } 1037 1038 /** 1039 * amdgpu_disable_vblank_kms - disable vblank interrupt 1040 * 1041 * @dev: drm dev pointer 1042 * @pipe: crtc to disable vblank interrupt for 1043 * 1044 * Disable the interrupt on the requested crtc (all asics). 1045 */ 1046 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe) 1047 { 1048 struct amdgpu_device *adev = dev->dev_private; 1049 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1050 1051 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1052 } 1053 1054 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1055 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1056 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1057 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1058 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 1059 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1060 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1061 /* KMS */ 1062 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1063 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1064 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1065 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1066 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1067 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1068 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1069 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1070 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1071 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW) 1072 }; 1073 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); 1074 1075 /* 1076 * Debugfs info 1077 */ 1078 #if defined(CONFIG_DEBUG_FS) 1079 1080 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) 1081 { 1082 struct drm_info_node *node = (struct drm_info_node *) m->private; 1083 struct drm_device *dev = node->minor->dev; 1084 struct amdgpu_device *adev = dev->dev_private; 1085 struct drm_amdgpu_info_firmware fw_info; 1086 struct drm_amdgpu_query_fw query_fw; 1087 int ret, i; 1088 1089 /* VCE */ 1090 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1091 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1092 if (ret) 1093 return ret; 1094 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1095 fw_info.feature, fw_info.ver); 1096 1097 /* UVD */ 1098 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1099 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1100 if (ret) 1101 return ret; 1102 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1103 fw_info.feature, fw_info.ver); 1104 1105 /* GMC */ 1106 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1107 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1108 if (ret) 1109 return ret; 1110 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1111 fw_info.feature, fw_info.ver); 1112 1113 /* ME */ 1114 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1115 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1116 if (ret) 1117 return ret; 1118 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1119 fw_info.feature, fw_info.ver); 1120 1121 /* PFP */ 1122 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1123 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1124 if (ret) 1125 return ret; 1126 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1127 fw_info.feature, fw_info.ver); 1128 1129 /* CE */ 1130 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1131 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1132 if (ret) 1133 return ret; 1134 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1135 fw_info.feature, fw_info.ver); 1136 1137 /* RLC */ 1138 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1139 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1140 if (ret) 1141 return ret; 1142 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1143 fw_info.feature, fw_info.ver); 1144 1145 /* MEC */ 1146 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1147 query_fw.index = 0; 1148 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1149 if (ret) 1150 return ret; 1151 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1152 fw_info.feature, fw_info.ver); 1153 1154 /* MEC2 */ 1155 if (adev->asic_type == CHIP_KAVERI || 1156 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) { 1157 query_fw.index = 1; 1158 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1159 if (ret) 1160 return ret; 1161 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1162 fw_info.feature, fw_info.ver); 1163 } 1164 1165 /* PSP SOS */ 1166 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1167 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1168 if (ret) 1169 return ret; 1170 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1171 fw_info.feature, fw_info.ver); 1172 1173 1174 /* PSP ASD */ 1175 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1176 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1177 if (ret) 1178 return ret; 1179 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1180 fw_info.feature, fw_info.ver); 1181 1182 /* SMC */ 1183 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1184 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1185 if (ret) 1186 return ret; 1187 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 1188 fw_info.feature, fw_info.ver); 1189 1190 /* SDMA */ 1191 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1192 for (i = 0; i < adev->sdma.num_instances; i++) { 1193 query_fw.index = i; 1194 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1195 if (ret) 1196 return ret; 1197 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1198 i, fw_info.feature, fw_info.ver); 1199 } 1200 1201 return 0; 1202 } 1203 1204 static const struct drm_info_list amdgpu_firmware_info_list[] = { 1205 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, 1206 }; 1207 #endif 1208 1209 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1210 { 1211 #if defined(CONFIG_DEBUG_FS) 1212 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, 1213 ARRAY_SIZE(amdgpu_firmware_info_list)); 1214 #else 1215 return 0; 1216 #endif 1217 } 1218