1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 34 #include <linux/vga_switcheroo.h> 35 #include <linux/slab.h> 36 #include <linux/pm_runtime.h> 37 #include "amdgpu_amdkfd.h" 38 39 #if defined(CONFIG_VGA_SWITCHEROO) 40 bool amdgpu_has_atpx(void); 41 #else 42 static inline bool amdgpu_has_atpx(void) { return false; } 43 #endif 44 45 /** 46 * amdgpu_driver_unload_kms - Main unload function for KMS. 47 * 48 * @dev: drm dev pointer 49 * 50 * This is the main unload function for KMS (all asics). 51 * Returns 0 on success. 52 */ 53 int amdgpu_driver_unload_kms(struct drm_device *dev) 54 { 55 struct amdgpu_device *adev = dev->dev_private; 56 57 if (adev == NULL) 58 return 0; 59 60 if (adev->rmmio == NULL) 61 goto done_free; 62 63 pm_runtime_get_sync(dev->dev); 64 65 amdgpu_amdkfd_device_fini(adev); 66 67 amdgpu_acpi_fini(adev); 68 69 amdgpu_device_fini(adev); 70 71 done_free: 72 kfree(adev); 73 dev->dev_private = NULL; 74 return 0; 75 } 76 77 /** 78 * amdgpu_driver_load_kms - Main load function for KMS. 79 * 80 * @dev: drm dev pointer 81 * @flags: device flags 82 * 83 * This is the main load function for KMS (all asics). 84 * Returns 0 on success, error on failure. 85 */ 86 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) 87 { 88 struct amdgpu_device *adev; 89 int r, acpi_status; 90 91 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); 92 if (adev == NULL) { 93 return -ENOMEM; 94 } 95 dev->dev_private = (void *)adev; 96 97 if ((amdgpu_runtime_pm != 0) && 98 amdgpu_has_atpx() && 99 ((flags & AMD_IS_APU) == 0)) 100 flags |= AMD_IS_PX; 101 102 /* amdgpu_device_init should report only fatal error 103 * like memory allocation failure or iomapping failure, 104 * or memory manager initialization failure, it must 105 * properly initialize the GPU MC controller and permit 106 * VRAM allocation 107 */ 108 r = amdgpu_device_init(adev, dev, dev->pdev, flags); 109 if (r) { 110 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 111 goto out; 112 } 113 114 /* Call ACPI methods: require modeset init 115 * but failure is not fatal 116 */ 117 if (!r) { 118 acpi_status = amdgpu_acpi_init(adev); 119 if (acpi_status) 120 dev_dbg(&dev->pdev->dev, 121 "Error during ACPI methods call\n"); 122 } 123 124 amdgpu_amdkfd_load_interface(adev); 125 amdgpu_amdkfd_device_probe(adev); 126 amdgpu_amdkfd_device_init(adev); 127 128 if (amdgpu_device_is_px(dev)) { 129 pm_runtime_use_autosuspend(dev->dev); 130 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 131 pm_runtime_set_active(dev->dev); 132 pm_runtime_allow(dev->dev); 133 pm_runtime_mark_last_busy(dev->dev); 134 pm_runtime_put_autosuspend(dev->dev); 135 } 136 137 out: 138 if (r) 139 amdgpu_driver_unload_kms(dev); 140 141 142 return r; 143 } 144 145 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 146 struct drm_amdgpu_query_fw *query_fw, 147 struct amdgpu_device *adev) 148 { 149 switch (query_fw->fw_type) { 150 case AMDGPU_INFO_FW_VCE: 151 fw_info->ver = adev->vce.fw_version; 152 fw_info->feature = adev->vce.fb_version; 153 break; 154 case AMDGPU_INFO_FW_UVD: 155 fw_info->ver = adev->uvd.fw_version; 156 fw_info->feature = 0; 157 break; 158 case AMDGPU_INFO_FW_GMC: 159 fw_info->ver = adev->mc.fw_version; 160 fw_info->feature = 0; 161 break; 162 case AMDGPU_INFO_FW_GFX_ME: 163 fw_info->ver = adev->gfx.me_fw_version; 164 fw_info->feature = adev->gfx.me_feature_version; 165 break; 166 case AMDGPU_INFO_FW_GFX_PFP: 167 fw_info->ver = adev->gfx.pfp_fw_version; 168 fw_info->feature = adev->gfx.pfp_feature_version; 169 break; 170 case AMDGPU_INFO_FW_GFX_CE: 171 fw_info->ver = adev->gfx.ce_fw_version; 172 fw_info->feature = adev->gfx.ce_feature_version; 173 break; 174 case AMDGPU_INFO_FW_GFX_RLC: 175 fw_info->ver = adev->gfx.rlc_fw_version; 176 fw_info->feature = adev->gfx.rlc_feature_version; 177 break; 178 case AMDGPU_INFO_FW_GFX_MEC: 179 if (query_fw->index == 0) { 180 fw_info->ver = adev->gfx.mec_fw_version; 181 fw_info->feature = adev->gfx.mec_feature_version; 182 } else if (query_fw->index == 1) { 183 fw_info->ver = adev->gfx.mec2_fw_version; 184 fw_info->feature = adev->gfx.mec2_feature_version; 185 } else 186 return -EINVAL; 187 break; 188 case AMDGPU_INFO_FW_SMC: 189 fw_info->ver = adev->pm.fw_version; 190 fw_info->feature = 0; 191 break; 192 case AMDGPU_INFO_FW_SDMA: 193 if (query_fw->index >= adev->sdma.num_instances) 194 return -EINVAL; 195 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 196 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 197 break; 198 default: 199 return -EINVAL; 200 } 201 return 0; 202 } 203 204 /* 205 * Userspace get information ioctl 206 */ 207 /** 208 * amdgpu_info_ioctl - answer a device specific request. 209 * 210 * @adev: amdgpu device pointer 211 * @data: request object 212 * @filp: drm filp 213 * 214 * This function is used to pass device specific parameters to the userspace 215 * drivers. Examples include: pci device id, pipeline parms, tiling params, 216 * etc. (all asics). 217 * Returns 0 on success, -EINVAL on failure. 218 */ 219 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 220 { 221 struct amdgpu_device *adev = dev->dev_private; 222 struct drm_amdgpu_info *info = data; 223 struct amdgpu_mode_info *minfo = &adev->mode_info; 224 void __user *out = (void __user *)(long)info->return_pointer; 225 uint32_t size = info->return_size; 226 struct drm_crtc *crtc; 227 uint32_t ui32 = 0; 228 uint64_t ui64 = 0; 229 int i, found; 230 231 if (!info->return_size || !info->return_pointer) 232 return -EINVAL; 233 234 switch (info->query) { 235 case AMDGPU_INFO_ACCEL_WORKING: 236 ui32 = adev->accel_working; 237 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 238 case AMDGPU_INFO_CRTC_FROM_ID: 239 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 240 crtc = (struct drm_crtc *)minfo->crtcs[i]; 241 if (crtc && crtc->base.id == info->mode_crtc.id) { 242 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 243 ui32 = amdgpu_crtc->crtc_id; 244 found = 1; 245 break; 246 } 247 } 248 if (!found) { 249 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 250 return -EINVAL; 251 } 252 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 253 case AMDGPU_INFO_HW_IP_INFO: { 254 struct drm_amdgpu_info_hw_ip ip = {}; 255 enum amd_ip_block_type type; 256 uint32_t ring_mask = 0; 257 uint32_t ib_start_alignment = 0; 258 uint32_t ib_size_alignment = 0; 259 260 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 261 return -EINVAL; 262 263 switch (info->query_hw_ip.type) { 264 case AMDGPU_HW_IP_GFX: 265 type = AMD_IP_BLOCK_TYPE_GFX; 266 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 267 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i); 268 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 269 ib_size_alignment = 8; 270 break; 271 case AMDGPU_HW_IP_COMPUTE: 272 type = AMD_IP_BLOCK_TYPE_GFX; 273 for (i = 0; i < adev->gfx.num_compute_rings; i++) 274 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i); 275 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 276 ib_size_alignment = 8; 277 break; 278 case AMDGPU_HW_IP_DMA: 279 type = AMD_IP_BLOCK_TYPE_SDMA; 280 for (i = 0; i < adev->sdma.num_instances; i++) 281 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i); 282 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 283 ib_size_alignment = 1; 284 break; 285 case AMDGPU_HW_IP_UVD: 286 type = AMD_IP_BLOCK_TYPE_UVD; 287 ring_mask = adev->uvd.ring.ready ? 1 : 0; 288 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 289 ib_size_alignment = 8; 290 break; 291 case AMDGPU_HW_IP_VCE: 292 type = AMD_IP_BLOCK_TYPE_VCE; 293 for (i = 0; i < AMDGPU_MAX_VCE_RINGS; i++) 294 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i); 295 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 296 ib_size_alignment = 8; 297 break; 298 default: 299 return -EINVAL; 300 } 301 302 for (i = 0; i < adev->num_ip_blocks; i++) { 303 if (adev->ip_blocks[i].type == type && 304 adev->ip_block_status[i].valid) { 305 ip.hw_ip_version_major = adev->ip_blocks[i].major; 306 ip.hw_ip_version_minor = adev->ip_blocks[i].minor; 307 ip.capabilities_flags = 0; 308 ip.available_rings = ring_mask; 309 ip.ib_start_alignment = ib_start_alignment; 310 ip.ib_size_alignment = ib_size_alignment; 311 break; 312 } 313 } 314 return copy_to_user(out, &ip, 315 min((size_t)size, sizeof(ip))) ? -EFAULT : 0; 316 } 317 case AMDGPU_INFO_HW_IP_COUNT: { 318 enum amd_ip_block_type type; 319 uint32_t count = 0; 320 321 switch (info->query_hw_ip.type) { 322 case AMDGPU_HW_IP_GFX: 323 type = AMD_IP_BLOCK_TYPE_GFX; 324 break; 325 case AMDGPU_HW_IP_COMPUTE: 326 type = AMD_IP_BLOCK_TYPE_GFX; 327 break; 328 case AMDGPU_HW_IP_DMA: 329 type = AMD_IP_BLOCK_TYPE_SDMA; 330 break; 331 case AMDGPU_HW_IP_UVD: 332 type = AMD_IP_BLOCK_TYPE_UVD; 333 break; 334 case AMDGPU_HW_IP_VCE: 335 type = AMD_IP_BLOCK_TYPE_VCE; 336 break; 337 default: 338 return -EINVAL; 339 } 340 341 for (i = 0; i < adev->num_ip_blocks; i++) 342 if (adev->ip_blocks[i].type == type && 343 adev->ip_block_status[i].valid && 344 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 345 count++; 346 347 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 348 } 349 case AMDGPU_INFO_TIMESTAMP: 350 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 351 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 352 case AMDGPU_INFO_FW_VERSION: { 353 struct drm_amdgpu_info_firmware fw_info; 354 int ret; 355 356 /* We only support one instance of each IP block right now. */ 357 if (info->query_fw.ip_instance != 0) 358 return -EINVAL; 359 360 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 361 if (ret) 362 return ret; 363 364 return copy_to_user(out, &fw_info, 365 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 366 } 367 case AMDGPU_INFO_NUM_BYTES_MOVED: 368 ui64 = atomic64_read(&adev->num_bytes_moved); 369 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 370 case AMDGPU_INFO_VRAM_USAGE: 371 ui64 = atomic64_read(&adev->vram_usage); 372 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 373 case AMDGPU_INFO_VIS_VRAM_USAGE: 374 ui64 = atomic64_read(&adev->vram_vis_usage); 375 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 376 case AMDGPU_INFO_GTT_USAGE: 377 ui64 = atomic64_read(&adev->gtt_usage); 378 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 379 case AMDGPU_INFO_GDS_CONFIG: { 380 struct drm_amdgpu_info_gds gds_info; 381 382 memset(&gds_info, 0, sizeof(gds_info)); 383 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT; 384 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT; 385 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT; 386 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT; 387 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT; 388 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT; 389 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT; 390 return copy_to_user(out, &gds_info, 391 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 392 } 393 case AMDGPU_INFO_VRAM_GTT: { 394 struct drm_amdgpu_info_vram_gtt vram_gtt; 395 396 vram_gtt.vram_size = adev->mc.real_vram_size; 397 vram_gtt.vram_size -= adev->vram_pin_size; 398 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size; 399 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size); 400 vram_gtt.gtt_size = adev->mc.gtt_size; 401 vram_gtt.gtt_size -= adev->gart_pin_size; 402 return copy_to_user(out, &vram_gtt, 403 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 404 } 405 case AMDGPU_INFO_READ_MMR_REG: { 406 unsigned n, alloc_size; 407 uint32_t *regs; 408 unsigned se_num = (info->read_mmr_reg.instance >> 409 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 410 AMDGPU_INFO_MMR_SE_INDEX_MASK; 411 unsigned sh_num = (info->read_mmr_reg.instance >> 412 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 413 AMDGPU_INFO_MMR_SH_INDEX_MASK; 414 415 /* set full masks if the userspace set all bits 416 * in the bitfields */ 417 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 418 se_num = 0xffffffff; 419 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 420 sh_num = 0xffffffff; 421 422 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 423 if (!regs) 424 return -ENOMEM; 425 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 426 427 for (i = 0; i < info->read_mmr_reg.count; i++) 428 if (amdgpu_asic_read_register(adev, se_num, sh_num, 429 info->read_mmr_reg.dword_offset + i, 430 ®s[i])) { 431 DRM_DEBUG_KMS("unallowed offset %#x\n", 432 info->read_mmr_reg.dword_offset + i); 433 kfree(regs); 434 return -EFAULT; 435 } 436 n = copy_to_user(out, regs, min(size, alloc_size)); 437 kfree(regs); 438 return n ? -EFAULT : 0; 439 } 440 case AMDGPU_INFO_DEV_INFO: { 441 struct drm_amdgpu_info_device dev_info = {}; 442 443 dev_info.device_id = dev->pdev->device; 444 dev_info.chip_rev = adev->rev_id; 445 dev_info.external_rev = adev->external_rev_id; 446 dev_info.pci_rev = dev->pdev->revision; 447 dev_info.family = adev->family; 448 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; 449 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 450 /* return all clocks in KHz */ 451 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 452 if (adev->pm.dpm_enabled) { 453 dev_info.max_engine_clock = 454 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; 455 dev_info.max_memory_clock = 456 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk * 10; 457 } else { 458 dev_info.max_engine_clock = adev->pm.default_sclk * 10; 459 dev_info.max_memory_clock = adev->pm.default_mclk * 10; 460 } 461 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 462 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 463 adev->gfx.config.max_shader_engines; 464 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 465 dev_info._pad = 0; 466 dev_info.ids_flags = 0; 467 if (adev->flags & AMD_IS_APU) 468 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 469 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 470 dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 471 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 472 dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) * 473 AMDGPU_GPU_PAGE_SIZE; 474 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; 475 476 dev_info.cu_active_number = adev->gfx.cu_info.number; 477 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 478 dev_info.ce_ram_size = adev->gfx.ce_ram_size; 479 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 480 sizeof(adev->gfx.cu_info.bitmap)); 481 dev_info.vram_type = adev->mc.vram_type; 482 dev_info.vram_bit_width = adev->mc.vram_width; 483 dev_info.vce_harvest_config = adev->vce.harvest_config; 484 485 return copy_to_user(out, &dev_info, 486 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 487 } 488 default: 489 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 490 return -EINVAL; 491 } 492 return 0; 493 } 494 495 496 /* 497 * Outdated mess for old drm with Xorg being in charge (void function now). 498 */ 499 /** 500 * amdgpu_driver_lastclose_kms - drm callback for last close 501 * 502 * @dev: drm dev pointer 503 * 504 * Switch vga_switcheroo state after last close (all asics). 505 */ 506 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 507 { 508 struct amdgpu_device *adev = dev->dev_private; 509 510 amdgpu_fbdev_restore_mode(adev); 511 vga_switcheroo_process_delayed_switch(); 512 } 513 514 /** 515 * amdgpu_driver_open_kms - drm callback for open 516 * 517 * @dev: drm dev pointer 518 * @file_priv: drm file 519 * 520 * On device open, init vm on cayman+ (all asics). 521 * Returns 0 on success, error on failure. 522 */ 523 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 524 { 525 struct amdgpu_device *adev = dev->dev_private; 526 struct amdgpu_fpriv *fpriv; 527 int r; 528 529 file_priv->driver_priv = NULL; 530 531 r = pm_runtime_get_sync(dev->dev); 532 if (r < 0) 533 return r; 534 535 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 536 if (unlikely(!fpriv)) 537 return -ENOMEM; 538 539 r = amdgpu_vm_init(adev, &fpriv->vm); 540 if (r) 541 goto error_free; 542 543 mutex_init(&fpriv->bo_list_lock); 544 idr_init(&fpriv->bo_list_handles); 545 546 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 547 548 file_priv->driver_priv = fpriv; 549 550 pm_runtime_mark_last_busy(dev->dev); 551 pm_runtime_put_autosuspend(dev->dev); 552 return 0; 553 554 error_free: 555 kfree(fpriv); 556 557 return r; 558 } 559 560 /** 561 * amdgpu_driver_postclose_kms - drm callback for post close 562 * 563 * @dev: drm dev pointer 564 * @file_priv: drm file 565 * 566 * On device post close, tear down vm on cayman+ (all asics). 567 */ 568 void amdgpu_driver_postclose_kms(struct drm_device *dev, 569 struct drm_file *file_priv) 570 { 571 struct amdgpu_device *adev = dev->dev_private; 572 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 573 struct amdgpu_bo_list *list; 574 int handle; 575 576 if (!fpriv) 577 return; 578 579 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 580 581 amdgpu_vm_fini(adev, &fpriv->vm); 582 583 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 584 amdgpu_bo_list_free(list); 585 586 idr_destroy(&fpriv->bo_list_handles); 587 mutex_destroy(&fpriv->bo_list_lock); 588 589 kfree(fpriv); 590 file_priv->driver_priv = NULL; 591 } 592 593 /** 594 * amdgpu_driver_preclose_kms - drm callback for pre close 595 * 596 * @dev: drm dev pointer 597 * @file_priv: drm file 598 * 599 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx 600 * (all asics). 601 */ 602 void amdgpu_driver_preclose_kms(struct drm_device *dev, 603 struct drm_file *file_priv) 604 { 605 struct amdgpu_device *adev = dev->dev_private; 606 607 amdgpu_uvd_free_handles(adev, file_priv); 608 amdgpu_vce_free_handles(adev, file_priv); 609 } 610 611 /* 612 * VBlank related functions. 613 */ 614 /** 615 * amdgpu_get_vblank_counter_kms - get frame count 616 * 617 * @dev: drm dev pointer 618 * @pipe: crtc to get the frame count from 619 * 620 * Gets the frame count on the requested crtc (all asics). 621 * Returns frame count on success, -EINVAL on failure. 622 */ 623 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) 624 { 625 struct amdgpu_device *adev = dev->dev_private; 626 int vpos, hpos, stat; 627 u32 count; 628 629 if (pipe >= adev->mode_info.num_crtc) { 630 DRM_ERROR("Invalid crtc %u\n", pipe); 631 return -EINVAL; 632 } 633 634 /* The hw increments its frame counter at start of vsync, not at start 635 * of vblank, as is required by DRM core vblank counter handling. 636 * Cook the hw count here to make it appear to the caller as if it 637 * incremented at start of vblank. We measure distance to start of 638 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 639 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 640 * result by 1 to give the proper appearance to caller. 641 */ 642 if (adev->mode_info.crtcs[pipe]) { 643 /* Repeat readout if needed to provide stable result if 644 * we cross start of vsync during the queries. 645 */ 646 do { 647 count = amdgpu_display_vblank_get_counter(adev, pipe); 648 /* Ask amdgpu_get_crtc_scanoutpos to return vpos as 649 * distance to start of vblank, instead of regular 650 * vertical scanout pos. 651 */ 652 stat = amdgpu_get_crtc_scanoutpos( 653 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 654 &vpos, &hpos, NULL, NULL, 655 &adev->mode_info.crtcs[pipe]->base.hwmode); 656 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 657 658 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 659 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 660 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 661 } else { 662 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 663 pipe, vpos); 664 665 /* Bump counter if we are at >= leading edge of vblank, 666 * but before vsync where vpos would turn negative and 667 * the hw counter really increments. 668 */ 669 if (vpos >= 0) 670 count++; 671 } 672 } else { 673 /* Fallback to use value as is. */ 674 count = amdgpu_display_vblank_get_counter(adev, pipe); 675 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 676 } 677 678 return count; 679 } 680 681 /** 682 * amdgpu_enable_vblank_kms - enable vblank interrupt 683 * 684 * @dev: drm dev pointer 685 * @pipe: crtc to enable vblank interrupt for 686 * 687 * Enable the interrupt on the requested crtc (all asics). 688 * Returns 0 on success, -EINVAL on failure. 689 */ 690 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe) 691 { 692 struct amdgpu_device *adev = dev->dev_private; 693 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe); 694 695 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 696 } 697 698 /** 699 * amdgpu_disable_vblank_kms - disable vblank interrupt 700 * 701 * @dev: drm dev pointer 702 * @pipe: crtc to disable vblank interrupt for 703 * 704 * Disable the interrupt on the requested crtc (all asics). 705 */ 706 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe) 707 { 708 struct amdgpu_device *adev = dev->dev_private; 709 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe); 710 711 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 712 } 713 714 /** 715 * amdgpu_get_vblank_timestamp_kms - get vblank timestamp 716 * 717 * @dev: drm dev pointer 718 * @crtc: crtc to get the timestamp for 719 * @max_error: max error 720 * @vblank_time: time value 721 * @flags: flags passed to the driver 722 * 723 * Gets the timestamp on the requested crtc based on the 724 * scanout position. (all asics). 725 * Returns postive status flags on success, negative error on failure. 726 */ 727 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 728 int *max_error, 729 struct timeval *vblank_time, 730 unsigned flags) 731 { 732 struct drm_crtc *crtc; 733 struct amdgpu_device *adev = dev->dev_private; 734 735 if (pipe >= dev->num_crtcs) { 736 DRM_ERROR("Invalid crtc %u\n", pipe); 737 return -EINVAL; 738 } 739 740 /* Get associated drm_crtc: */ 741 crtc = &adev->mode_info.crtcs[pipe]->base; 742 if (!crtc) { 743 /* This can occur on driver load if some component fails to 744 * initialize completely and driver is unloaded */ 745 DRM_ERROR("Uninitialized crtc %d\n", pipe); 746 return -EINVAL; 747 } 748 749 /* Helper routine in DRM core does all the work: */ 750 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, 751 vblank_time, flags, 752 &crtc->hwmode); 753 } 754 755 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 756 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 757 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 758 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 759 /* KMS */ 760 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 761 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 762 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 763 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 764 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 765 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 766 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 767 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 768 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 769 }; 770 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); 771 772 /* 773 * Debugfs info 774 */ 775 #if defined(CONFIG_DEBUG_FS) 776 777 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) 778 { 779 struct drm_info_node *node = (struct drm_info_node *) m->private; 780 struct drm_device *dev = node->minor->dev; 781 struct amdgpu_device *adev = dev->dev_private; 782 struct drm_amdgpu_info_firmware fw_info; 783 struct drm_amdgpu_query_fw query_fw; 784 int ret, i; 785 786 /* VCE */ 787 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 788 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 789 if (ret) 790 return ret; 791 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 792 fw_info.feature, fw_info.ver); 793 794 /* UVD */ 795 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 796 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 797 if (ret) 798 return ret; 799 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 800 fw_info.feature, fw_info.ver); 801 802 /* GMC */ 803 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 804 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 805 if (ret) 806 return ret; 807 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 808 fw_info.feature, fw_info.ver); 809 810 /* ME */ 811 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 812 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 813 if (ret) 814 return ret; 815 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 816 fw_info.feature, fw_info.ver); 817 818 /* PFP */ 819 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 820 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 821 if (ret) 822 return ret; 823 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 824 fw_info.feature, fw_info.ver); 825 826 /* CE */ 827 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 828 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 829 if (ret) 830 return ret; 831 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 832 fw_info.feature, fw_info.ver); 833 834 /* RLC */ 835 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 836 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 837 if (ret) 838 return ret; 839 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 840 fw_info.feature, fw_info.ver); 841 842 /* MEC */ 843 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 844 query_fw.index = 0; 845 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 846 if (ret) 847 return ret; 848 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 849 fw_info.feature, fw_info.ver); 850 851 /* MEC2 */ 852 if (adev->asic_type == CHIP_KAVERI || 853 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) { 854 query_fw.index = 1; 855 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 856 if (ret) 857 return ret; 858 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 859 fw_info.feature, fw_info.ver); 860 } 861 862 /* SMC */ 863 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 864 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 865 if (ret) 866 return ret; 867 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 868 fw_info.feature, fw_info.ver); 869 870 /* SDMA */ 871 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 872 for (i = 0; i < adev->sdma.num_instances; i++) { 873 query_fw.index = i; 874 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 875 if (ret) 876 return ret; 877 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 878 i, fw_info.feature, fw_info.ver); 879 } 880 881 return 0; 882 } 883 884 static const struct drm_info_list amdgpu_firmware_info_list[] = { 885 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, 886 }; 887 #endif 888 889 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 890 { 891 #if defined(CONFIG_DEBUG_FS) 892 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, 893 ARRAY_SIZE(amdgpu_firmware_info_list)); 894 #else 895 return 0; 896 #endif 897 } 898