1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include <drm/drm_drv.h> 32 #include <drm/drm_fb_helper.h> 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "atom.h" 36 37 #include <linux/vga_switcheroo.h> 38 #include <linux/slab.h> 39 #include <linux/uaccess.h> 40 #include <linux/pci.h> 41 #include <linux/pm_runtime.h> 42 #include "amdgpu_amdkfd.h" 43 #include "amdgpu_gem.h" 44 #include "amdgpu_display.h" 45 #include "amdgpu_ras.h" 46 #include "amd_pcie.h" 47 48 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 49 { 50 struct amdgpu_gpu_instance *gpu_instance; 51 int i; 52 53 mutex_lock(&mgpu_info.mutex); 54 55 for (i = 0; i < mgpu_info.num_gpu; i++) { 56 gpu_instance = &(mgpu_info.gpu_ins[i]); 57 if (gpu_instance->adev == adev) { 58 mgpu_info.gpu_ins[i] = 59 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 60 mgpu_info.num_gpu--; 61 if (adev->flags & AMD_IS_APU) 62 mgpu_info.num_apu--; 63 else 64 mgpu_info.num_dgpu--; 65 break; 66 } 67 } 68 69 mutex_unlock(&mgpu_info.mutex); 70 } 71 72 /** 73 * amdgpu_driver_unload_kms - Main unload function for KMS. 74 * 75 * @dev: drm dev pointer 76 * 77 * This is the main unload function for KMS (all asics). 78 * Returns 0 on success. 79 */ 80 void amdgpu_driver_unload_kms(struct drm_device *dev) 81 { 82 struct amdgpu_device *adev = drm_to_adev(dev); 83 84 if (adev == NULL) 85 return; 86 87 amdgpu_unregister_gpu_instance(adev); 88 89 if (adev->rmmio == NULL) 90 return; 91 92 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD)) 93 DRM_WARN("smart shift update failed\n"); 94 95 amdgpu_acpi_fini(adev); 96 amdgpu_device_fini_hw(adev); 97 } 98 99 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 100 { 101 struct amdgpu_gpu_instance *gpu_instance; 102 103 mutex_lock(&mgpu_info.mutex); 104 105 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 106 DRM_ERROR("Cannot register more gpu instance\n"); 107 mutex_unlock(&mgpu_info.mutex); 108 return; 109 } 110 111 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 112 gpu_instance->adev = adev; 113 gpu_instance->mgpu_fan_enabled = 0; 114 115 mgpu_info.num_gpu++; 116 if (adev->flags & AMD_IS_APU) 117 mgpu_info.num_apu++; 118 else 119 mgpu_info.num_dgpu++; 120 121 mutex_unlock(&mgpu_info.mutex); 122 } 123 124 /** 125 * amdgpu_driver_load_kms - Main load function for KMS. 126 * 127 * @adev: pointer to struct amdgpu_device 128 * @flags: device flags 129 * 130 * This is the main load function for KMS (all asics). 131 * Returns 0 on success, error on failure. 132 */ 133 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 134 { 135 struct drm_device *dev; 136 int r, acpi_status; 137 138 dev = adev_to_drm(adev); 139 140 /* amdgpu_device_init should report only fatal error 141 * like memory allocation failure or iomapping failure, 142 * or memory manager initialization failure, it must 143 * properly initialize the GPU MC controller and permit 144 * VRAM allocation 145 */ 146 r = amdgpu_device_init(adev, flags); 147 if (r) { 148 dev_err(dev->dev, "Fatal error during GPU init\n"); 149 goto out; 150 } 151 152 adev->pm.rpm_mode = AMDGPU_RUNPM_NONE; 153 if (amdgpu_device_supports_px(dev) && 154 (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */ 155 adev->pm.rpm_mode = AMDGPU_RUNPM_PX; 156 dev_info(adev->dev, "Using ATPX for runtime pm\n"); 157 } else if (amdgpu_device_supports_boco(dev) && 158 (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */ 159 adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO; 160 dev_info(adev->dev, "Using BOCO for runtime pm\n"); 161 } else if (amdgpu_device_supports_baco(dev) && 162 (amdgpu_runtime_pm != 0)) { 163 switch (adev->asic_type) { 164 case CHIP_VEGA20: 165 case CHIP_ARCTURUS: 166 /* enable BACO as runpm mode if runpm=1 */ 167 if (amdgpu_runtime_pm > 0) 168 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 169 break; 170 case CHIP_VEGA10: 171 /* enable BACO as runpm mode if noretry=0 */ 172 if (!adev->gmc.noretry) 173 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 174 break; 175 default: 176 /* enable BACO as runpm mode on CI+ */ 177 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 178 break; 179 } 180 181 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) 182 dev_info(adev->dev, "Using BACO for runtime pm\n"); 183 } 184 185 /* Call ACPI methods: require modeset init 186 * but failure is not fatal 187 */ 188 189 acpi_status = amdgpu_acpi_init(adev); 190 if (acpi_status) 191 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 192 193 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD)) 194 DRM_WARN("smart shift update failed\n"); 195 196 out: 197 if (r) 198 amdgpu_driver_unload_kms(dev); 199 200 return r; 201 } 202 203 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 204 struct drm_amdgpu_query_fw *query_fw, 205 struct amdgpu_device *adev) 206 { 207 switch (query_fw->fw_type) { 208 case AMDGPU_INFO_FW_VCE: 209 fw_info->ver = adev->vce.fw_version; 210 fw_info->feature = adev->vce.fb_version; 211 break; 212 case AMDGPU_INFO_FW_UVD: 213 fw_info->ver = adev->uvd.fw_version; 214 fw_info->feature = 0; 215 break; 216 case AMDGPU_INFO_FW_VCN: 217 fw_info->ver = adev->vcn.fw_version; 218 fw_info->feature = 0; 219 break; 220 case AMDGPU_INFO_FW_GMC: 221 fw_info->ver = adev->gmc.fw_version; 222 fw_info->feature = 0; 223 break; 224 case AMDGPU_INFO_FW_GFX_ME: 225 fw_info->ver = adev->gfx.me_fw_version; 226 fw_info->feature = adev->gfx.me_feature_version; 227 break; 228 case AMDGPU_INFO_FW_GFX_PFP: 229 fw_info->ver = adev->gfx.pfp_fw_version; 230 fw_info->feature = adev->gfx.pfp_feature_version; 231 break; 232 case AMDGPU_INFO_FW_GFX_CE: 233 fw_info->ver = adev->gfx.ce_fw_version; 234 fw_info->feature = adev->gfx.ce_feature_version; 235 break; 236 case AMDGPU_INFO_FW_GFX_RLC: 237 fw_info->ver = adev->gfx.rlc_fw_version; 238 fw_info->feature = adev->gfx.rlc_feature_version; 239 break; 240 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 241 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 242 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 243 break; 244 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 245 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 246 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 247 break; 248 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 249 fw_info->ver = adev->gfx.rlc_srls_fw_version; 250 fw_info->feature = adev->gfx.rlc_srls_feature_version; 251 break; 252 case AMDGPU_INFO_FW_GFX_RLCP: 253 fw_info->ver = adev->gfx.rlcp_ucode_version; 254 fw_info->feature = adev->gfx.rlcp_ucode_feature_version; 255 break; 256 case AMDGPU_INFO_FW_GFX_RLCV: 257 fw_info->ver = adev->gfx.rlcv_ucode_version; 258 fw_info->feature = adev->gfx.rlcv_ucode_feature_version; 259 break; 260 case AMDGPU_INFO_FW_GFX_MEC: 261 if (query_fw->index == 0) { 262 fw_info->ver = adev->gfx.mec_fw_version; 263 fw_info->feature = adev->gfx.mec_feature_version; 264 } else if (query_fw->index == 1) { 265 fw_info->ver = adev->gfx.mec2_fw_version; 266 fw_info->feature = adev->gfx.mec2_feature_version; 267 } else 268 return -EINVAL; 269 break; 270 case AMDGPU_INFO_FW_SMC: 271 fw_info->ver = adev->pm.fw_version; 272 fw_info->feature = 0; 273 break; 274 case AMDGPU_INFO_FW_TA: 275 switch (query_fw->index) { 276 case TA_FW_TYPE_PSP_XGMI: 277 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; 278 fw_info->feature = adev->psp.xgmi_context.context 279 .bin_desc.feature_version; 280 break; 281 case TA_FW_TYPE_PSP_RAS: 282 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; 283 fw_info->feature = adev->psp.ras_context.context 284 .bin_desc.feature_version; 285 break; 286 case TA_FW_TYPE_PSP_HDCP: 287 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; 288 fw_info->feature = adev->psp.hdcp_context.context 289 .bin_desc.feature_version; 290 break; 291 case TA_FW_TYPE_PSP_DTM: 292 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; 293 fw_info->feature = adev->psp.dtm_context.context 294 .bin_desc.feature_version; 295 break; 296 case TA_FW_TYPE_PSP_RAP: 297 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; 298 fw_info->feature = adev->psp.rap_context.context 299 .bin_desc.feature_version; 300 break; 301 case TA_FW_TYPE_PSP_SECUREDISPLAY: 302 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; 303 fw_info->feature = 304 adev->psp.securedisplay_context.context.bin_desc 305 .feature_version; 306 break; 307 default: 308 return -EINVAL; 309 } 310 break; 311 case AMDGPU_INFO_FW_SDMA: 312 if (query_fw->index >= adev->sdma.num_instances) 313 return -EINVAL; 314 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 315 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 316 break; 317 case AMDGPU_INFO_FW_SOS: 318 fw_info->ver = adev->psp.sos.fw_version; 319 fw_info->feature = adev->psp.sos.feature_version; 320 break; 321 case AMDGPU_INFO_FW_ASD: 322 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; 323 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; 324 break; 325 case AMDGPU_INFO_FW_DMCU: 326 fw_info->ver = adev->dm.dmcu_fw_version; 327 fw_info->feature = 0; 328 break; 329 case AMDGPU_INFO_FW_DMCUB: 330 fw_info->ver = adev->dm.dmcub_fw_version; 331 fw_info->feature = 0; 332 break; 333 case AMDGPU_INFO_FW_TOC: 334 fw_info->ver = adev->psp.toc.fw_version; 335 fw_info->feature = adev->psp.toc.feature_version; 336 break; 337 case AMDGPU_INFO_FW_CAP: 338 fw_info->ver = adev->psp.cap_fw_version; 339 fw_info->feature = adev->psp.cap_feature_version; 340 break; 341 case AMDGPU_INFO_FW_MES_KIQ: 342 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK; 343 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK) 344 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 345 break; 346 case AMDGPU_INFO_FW_MES: 347 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 348 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK) 349 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 350 break; 351 case AMDGPU_INFO_FW_IMU: 352 fw_info->ver = adev->gfx.imu_fw_version; 353 fw_info->feature = 0; 354 break; 355 case AMDGPU_INFO_FW_VPE: 356 fw_info->ver = adev->vpe.fw_version; 357 fw_info->feature = adev->vpe.feature_version; 358 break; 359 default: 360 return -EINVAL; 361 } 362 return 0; 363 } 364 365 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 366 struct drm_amdgpu_info *info, 367 struct drm_amdgpu_info_hw_ip *result) 368 { 369 uint32_t ib_start_alignment = 0; 370 uint32_t ib_size_alignment = 0; 371 enum amd_ip_block_type type; 372 unsigned int num_rings = 0; 373 unsigned int i, j; 374 375 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 376 return -EINVAL; 377 378 switch (info->query_hw_ip.type) { 379 case AMDGPU_HW_IP_GFX: 380 type = AMD_IP_BLOCK_TYPE_GFX; 381 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 382 if (adev->gfx.gfx_ring[i].sched.ready) 383 ++num_rings; 384 ib_start_alignment = 32; 385 ib_size_alignment = 32; 386 break; 387 case AMDGPU_HW_IP_COMPUTE: 388 type = AMD_IP_BLOCK_TYPE_GFX; 389 for (i = 0; i < adev->gfx.num_compute_rings; i++) 390 if (adev->gfx.compute_ring[i].sched.ready) 391 ++num_rings; 392 ib_start_alignment = 32; 393 ib_size_alignment = 32; 394 break; 395 case AMDGPU_HW_IP_DMA: 396 type = AMD_IP_BLOCK_TYPE_SDMA; 397 for (i = 0; i < adev->sdma.num_instances; i++) 398 if (adev->sdma.instance[i].ring.sched.ready) 399 ++num_rings; 400 ib_start_alignment = 256; 401 ib_size_alignment = 4; 402 break; 403 case AMDGPU_HW_IP_UVD: 404 type = AMD_IP_BLOCK_TYPE_UVD; 405 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 406 if (adev->uvd.harvest_config & (1 << i)) 407 continue; 408 409 if (adev->uvd.inst[i].ring.sched.ready) 410 ++num_rings; 411 } 412 ib_start_alignment = 64; 413 ib_size_alignment = 64; 414 break; 415 case AMDGPU_HW_IP_VCE: 416 type = AMD_IP_BLOCK_TYPE_VCE; 417 for (i = 0; i < adev->vce.num_rings; i++) 418 if (adev->vce.ring[i].sched.ready) 419 ++num_rings; 420 ib_start_alignment = 4; 421 ib_size_alignment = 1; 422 break; 423 case AMDGPU_HW_IP_UVD_ENC: 424 type = AMD_IP_BLOCK_TYPE_UVD; 425 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 426 if (adev->uvd.harvest_config & (1 << i)) 427 continue; 428 429 for (j = 0; j < adev->uvd.num_enc_rings; j++) 430 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 431 ++num_rings; 432 } 433 ib_start_alignment = 64; 434 ib_size_alignment = 64; 435 break; 436 case AMDGPU_HW_IP_VCN_DEC: 437 type = AMD_IP_BLOCK_TYPE_VCN; 438 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 439 if (adev->vcn.harvest_config & (1 << i)) 440 continue; 441 442 if (adev->vcn.inst[i].ring_dec.sched.ready) 443 ++num_rings; 444 } 445 ib_start_alignment = 16; 446 ib_size_alignment = 16; 447 break; 448 case AMDGPU_HW_IP_VCN_ENC: 449 type = AMD_IP_BLOCK_TYPE_VCN; 450 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 451 if (adev->vcn.harvest_config & (1 << i)) 452 continue; 453 454 for (j = 0; j < adev->vcn.num_enc_rings; j++) 455 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 456 ++num_rings; 457 } 458 ib_start_alignment = 64; 459 ib_size_alignment = 1; 460 break; 461 case AMDGPU_HW_IP_VCN_JPEG: 462 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 463 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 464 465 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 466 if (adev->jpeg.harvest_config & (1 << i)) 467 continue; 468 469 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) 470 if (adev->jpeg.inst[i].ring_dec[j].sched.ready) 471 ++num_rings; 472 } 473 ib_start_alignment = 16; 474 ib_size_alignment = 16; 475 break; 476 case AMDGPU_HW_IP_VPE: 477 type = AMD_IP_BLOCK_TYPE_VPE; 478 if (adev->vpe.ring.sched.ready) 479 ++num_rings; 480 ib_start_alignment = 256; 481 ib_size_alignment = 4; 482 break; 483 default: 484 return -EINVAL; 485 } 486 487 for (i = 0; i < adev->num_ip_blocks; i++) 488 if (adev->ip_blocks[i].version->type == type && 489 adev->ip_blocks[i].status.valid) 490 break; 491 492 if (i == adev->num_ip_blocks) 493 return 0; 494 495 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 496 num_rings); 497 498 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 499 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 500 501 if (adev->asic_type >= CHIP_VEGA10) { 502 switch (type) { 503 case AMD_IP_BLOCK_TYPE_GFX: 504 result->ip_discovery_version = 505 amdgpu_ip_version(adev, GC_HWIP, 0); 506 break; 507 case AMD_IP_BLOCK_TYPE_SDMA: 508 result->ip_discovery_version = 509 amdgpu_ip_version(adev, SDMA0_HWIP, 0); 510 break; 511 case AMD_IP_BLOCK_TYPE_UVD: 512 case AMD_IP_BLOCK_TYPE_VCN: 513 case AMD_IP_BLOCK_TYPE_JPEG: 514 result->ip_discovery_version = 515 amdgpu_ip_version(adev, UVD_HWIP, 0); 516 break; 517 case AMD_IP_BLOCK_TYPE_VCE: 518 result->ip_discovery_version = 519 amdgpu_ip_version(adev, VCE_HWIP, 0); 520 break; 521 default: 522 result->ip_discovery_version = 0; 523 break; 524 } 525 } else { 526 result->ip_discovery_version = 0; 527 } 528 result->capabilities_flags = 0; 529 result->available_rings = (1 << num_rings) - 1; 530 result->ib_start_alignment = ib_start_alignment; 531 result->ib_size_alignment = ib_size_alignment; 532 return 0; 533 } 534 535 /* 536 * Userspace get information ioctl 537 */ 538 /** 539 * amdgpu_info_ioctl - answer a device specific request. 540 * 541 * @dev: drm device pointer 542 * @data: request object 543 * @filp: drm filp 544 * 545 * This function is used to pass device specific parameters to the userspace 546 * drivers. Examples include: pci device id, pipeline parms, tiling params, 547 * etc. (all asics). 548 * Returns 0 on success, -EINVAL on failure. 549 */ 550 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 551 { 552 struct amdgpu_device *adev = drm_to_adev(dev); 553 struct drm_amdgpu_info *info = data; 554 struct amdgpu_mode_info *minfo = &adev->mode_info; 555 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 556 uint32_t size = info->return_size; 557 struct drm_crtc *crtc; 558 uint32_t ui32 = 0; 559 uint64_t ui64 = 0; 560 int i, found; 561 int ui32_size = sizeof(ui32); 562 563 if (!info->return_size || !info->return_pointer) 564 return -EINVAL; 565 566 switch (info->query) { 567 case AMDGPU_INFO_ACCEL_WORKING: 568 ui32 = adev->accel_working; 569 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 570 case AMDGPU_INFO_CRTC_FROM_ID: 571 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 572 crtc = (struct drm_crtc *)minfo->crtcs[i]; 573 if (crtc && crtc->base.id == info->mode_crtc.id) { 574 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 575 576 ui32 = amdgpu_crtc->crtc_id; 577 found = 1; 578 break; 579 } 580 } 581 if (!found) { 582 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 583 return -EINVAL; 584 } 585 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 586 case AMDGPU_INFO_HW_IP_INFO: { 587 struct drm_amdgpu_info_hw_ip ip = {}; 588 int ret; 589 590 ret = amdgpu_hw_ip_info(adev, info, &ip); 591 if (ret) 592 return ret; 593 594 ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip))); 595 return ret ? -EFAULT : 0; 596 } 597 case AMDGPU_INFO_HW_IP_COUNT: { 598 enum amd_ip_block_type type; 599 uint32_t count = 0; 600 601 switch (info->query_hw_ip.type) { 602 case AMDGPU_HW_IP_GFX: 603 type = AMD_IP_BLOCK_TYPE_GFX; 604 break; 605 case AMDGPU_HW_IP_COMPUTE: 606 type = AMD_IP_BLOCK_TYPE_GFX; 607 break; 608 case AMDGPU_HW_IP_DMA: 609 type = AMD_IP_BLOCK_TYPE_SDMA; 610 break; 611 case AMDGPU_HW_IP_UVD: 612 type = AMD_IP_BLOCK_TYPE_UVD; 613 break; 614 case AMDGPU_HW_IP_VCE: 615 type = AMD_IP_BLOCK_TYPE_VCE; 616 break; 617 case AMDGPU_HW_IP_UVD_ENC: 618 type = AMD_IP_BLOCK_TYPE_UVD; 619 break; 620 case AMDGPU_HW_IP_VCN_DEC: 621 case AMDGPU_HW_IP_VCN_ENC: 622 type = AMD_IP_BLOCK_TYPE_VCN; 623 break; 624 case AMDGPU_HW_IP_VCN_JPEG: 625 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 626 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 627 break; 628 default: 629 return -EINVAL; 630 } 631 632 for (i = 0; i < adev->num_ip_blocks; i++) 633 if (adev->ip_blocks[i].version->type == type && 634 adev->ip_blocks[i].status.valid && 635 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 636 count++; 637 638 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 639 } 640 case AMDGPU_INFO_TIMESTAMP: 641 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 642 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 643 case AMDGPU_INFO_FW_VERSION: { 644 struct drm_amdgpu_info_firmware fw_info; 645 int ret; 646 647 /* We only support one instance of each IP block right now. */ 648 if (info->query_fw.ip_instance != 0) 649 return -EINVAL; 650 651 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 652 if (ret) 653 return ret; 654 655 return copy_to_user(out, &fw_info, 656 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 657 } 658 case AMDGPU_INFO_NUM_BYTES_MOVED: 659 ui64 = atomic64_read(&adev->num_bytes_moved); 660 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 661 case AMDGPU_INFO_NUM_EVICTIONS: 662 ui64 = atomic64_read(&adev->num_evictions); 663 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 664 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 665 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 666 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 667 case AMDGPU_INFO_VRAM_USAGE: 668 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager); 669 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 670 case AMDGPU_INFO_VIS_VRAM_USAGE: 671 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 672 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 673 case AMDGPU_INFO_GTT_USAGE: 674 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager); 675 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 676 case AMDGPU_INFO_GDS_CONFIG: { 677 struct drm_amdgpu_info_gds gds_info; 678 679 memset(&gds_info, 0, sizeof(gds_info)); 680 gds_info.compute_partition_size = adev->gds.gds_size; 681 gds_info.gds_total_size = adev->gds.gds_size; 682 gds_info.gws_per_compute_partition = adev->gds.gws_size; 683 gds_info.oa_per_compute_partition = adev->gds.oa_size; 684 return copy_to_user(out, &gds_info, 685 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 686 } 687 case AMDGPU_INFO_VRAM_GTT: { 688 struct drm_amdgpu_info_vram_gtt vram_gtt; 689 690 vram_gtt.vram_size = adev->gmc.real_vram_size - 691 atomic64_read(&adev->vram_pin_size) - 692 AMDGPU_VM_RESERVED_VRAM; 693 vram_gtt.vram_cpu_accessible_size = 694 min(adev->gmc.visible_vram_size - 695 atomic64_read(&adev->visible_pin_size), 696 vram_gtt.vram_size); 697 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 698 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 699 return copy_to_user(out, &vram_gtt, 700 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 701 } 702 case AMDGPU_INFO_MEMORY: { 703 struct drm_amdgpu_memory_info mem; 704 struct ttm_resource_manager *gtt_man = 705 &adev->mman.gtt_mgr.manager; 706 struct ttm_resource_manager *vram_man = 707 &adev->mman.vram_mgr.manager; 708 709 memset(&mem, 0, sizeof(mem)); 710 mem.vram.total_heap_size = adev->gmc.real_vram_size; 711 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 712 atomic64_read(&adev->vram_pin_size) - 713 AMDGPU_VM_RESERVED_VRAM; 714 mem.vram.heap_usage = 715 ttm_resource_manager_usage(vram_man); 716 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 717 718 mem.cpu_accessible_vram.total_heap_size = 719 adev->gmc.visible_vram_size; 720 mem.cpu_accessible_vram.usable_heap_size = 721 min(adev->gmc.visible_vram_size - 722 atomic64_read(&adev->visible_pin_size), 723 mem.vram.usable_heap_size); 724 mem.cpu_accessible_vram.heap_usage = 725 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 726 mem.cpu_accessible_vram.max_allocation = 727 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 728 729 mem.gtt.total_heap_size = gtt_man->size; 730 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 731 atomic64_read(&adev->gart_pin_size); 732 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man); 733 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 734 735 return copy_to_user(out, &mem, 736 min((size_t)size, sizeof(mem))) 737 ? -EFAULT : 0; 738 } 739 case AMDGPU_INFO_READ_MMR_REG: { 740 unsigned int n, alloc_size; 741 uint32_t *regs; 742 unsigned int se_num = (info->read_mmr_reg.instance >> 743 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 744 AMDGPU_INFO_MMR_SE_INDEX_MASK; 745 unsigned int sh_num = (info->read_mmr_reg.instance >> 746 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 747 AMDGPU_INFO_MMR_SH_INDEX_MASK; 748 749 /* set full masks if the userspace set all bits 750 * in the bitfields 751 */ 752 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 753 se_num = 0xffffffff; 754 else if (se_num >= AMDGPU_GFX_MAX_SE) 755 return -EINVAL; 756 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 757 sh_num = 0xffffffff; 758 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 759 return -EINVAL; 760 761 if (info->read_mmr_reg.count > 128) 762 return -EINVAL; 763 764 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 765 if (!regs) 766 return -ENOMEM; 767 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 768 769 amdgpu_gfx_off_ctrl(adev, false); 770 for (i = 0; i < info->read_mmr_reg.count; i++) { 771 if (amdgpu_asic_read_register(adev, se_num, sh_num, 772 info->read_mmr_reg.dword_offset + i, 773 ®s[i])) { 774 DRM_DEBUG_KMS("unallowed offset %#x\n", 775 info->read_mmr_reg.dword_offset + i); 776 kfree(regs); 777 amdgpu_gfx_off_ctrl(adev, true); 778 return -EFAULT; 779 } 780 } 781 amdgpu_gfx_off_ctrl(adev, true); 782 n = copy_to_user(out, regs, min(size, alloc_size)); 783 kfree(regs); 784 return n ? -EFAULT : 0; 785 } 786 case AMDGPU_INFO_DEV_INFO: { 787 struct drm_amdgpu_info_device *dev_info; 788 uint64_t vm_size; 789 uint32_t pcie_gen_mask; 790 int ret; 791 792 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); 793 if (!dev_info) 794 return -ENOMEM; 795 796 dev_info->device_id = adev->pdev->device; 797 dev_info->chip_rev = adev->rev_id; 798 dev_info->external_rev = adev->external_rev_id; 799 dev_info->pci_rev = adev->pdev->revision; 800 dev_info->family = adev->family; 801 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 802 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 803 /* return all clocks in KHz */ 804 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 805 if (adev->pm.dpm_enabled) { 806 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 807 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 808 dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10; 809 dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10; 810 } else { 811 dev_info->max_engine_clock = 812 dev_info->min_engine_clock = 813 adev->clock.default_sclk * 10; 814 dev_info->max_memory_clock = 815 dev_info->min_memory_clock = 816 adev->clock.default_mclk * 10; 817 } 818 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 819 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 820 adev->gfx.config.max_shader_engines; 821 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 822 dev_info->ids_flags = 0; 823 if (adev->flags & AMD_IS_APU) 824 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 825 if (adev->gfx.mcbp) 826 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 827 if (amdgpu_is_tmz(adev)) 828 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 829 if (adev->gfx.config.ta_cntl2_truncate_coord_mode) 830 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD; 831 832 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 833 vm_size -= AMDGPU_VA_RESERVED_SIZE; 834 835 /* Older VCE FW versions are buggy and can handle only 40bits */ 836 if (adev->vce.fw_version && 837 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 838 vm_size = min(vm_size, 1ULL << 40); 839 840 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 841 dev_info->virtual_address_max = 842 min(vm_size, AMDGPU_GMC_HOLE_START); 843 844 if (vm_size > AMDGPU_GMC_HOLE_START) { 845 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 846 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 847 } 848 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 849 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 850 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 851 dev_info->cu_active_number = adev->gfx.cu_info.number; 852 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 853 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 854 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 855 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 856 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 857 sizeof(dev_info->cu_bitmap)); 858 dev_info->vram_type = adev->gmc.vram_type; 859 dev_info->vram_bit_width = adev->gmc.vram_width; 860 dev_info->vce_harvest_config = adev->vce.harvest_config; 861 dev_info->gc_double_offchip_lds_buf = 862 adev->gfx.config.double_offchip_lds_buf; 863 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 864 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 865 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 866 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 867 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 868 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 869 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 870 871 if (adev->family >= AMDGPU_FAMILY_NV) 872 dev_info->pa_sc_tile_steering_override = 873 adev->gfx.config.pa_sc_tile_steering_override; 874 875 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 876 877 /* Combine the chip gen mask with the platform (CPU/mobo) mask. */ 878 pcie_gen_mask = adev->pm.pcie_gen_mask & (adev->pm.pcie_gen_mask >> 16); 879 dev_info->pcie_gen = fls(pcie_gen_mask); 880 dev_info->pcie_num_lanes = 881 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 : 882 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 : 883 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 : 884 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 : 885 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 : 886 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1; 887 888 dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size; 889 dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp; 890 dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc; 891 dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc; 892 dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance * 893 adev->gfx.config.gc_gl1c_per_sa; 894 dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu; 895 dev_info->mall_size = adev->gmc.mall_size; 896 897 898 if (adev->gfx.funcs->get_gfx_shadow_info) { 899 struct amdgpu_gfx_shadow_info shadow_info; 900 901 ret = amdgpu_gfx_get_gfx_shadow_info(adev, &shadow_info); 902 if (!ret) { 903 dev_info->shadow_size = shadow_info.shadow_size; 904 dev_info->shadow_alignment = shadow_info.shadow_alignment; 905 dev_info->csa_size = shadow_info.csa_size; 906 dev_info->csa_alignment = shadow_info.csa_alignment; 907 } 908 } 909 910 ret = copy_to_user(out, dev_info, 911 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 912 kfree(dev_info); 913 return ret; 914 } 915 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 916 unsigned int i; 917 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 918 struct amd_vce_state *vce_state; 919 920 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 921 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 922 if (vce_state) { 923 vce_clk_table.entries[i].sclk = vce_state->sclk; 924 vce_clk_table.entries[i].mclk = vce_state->mclk; 925 vce_clk_table.entries[i].eclk = vce_state->evclk; 926 vce_clk_table.num_valid_entries++; 927 } 928 } 929 930 return copy_to_user(out, &vce_clk_table, 931 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 932 } 933 case AMDGPU_INFO_VBIOS: { 934 uint32_t bios_size = adev->bios_size; 935 936 switch (info->vbios_info.type) { 937 case AMDGPU_INFO_VBIOS_SIZE: 938 return copy_to_user(out, &bios_size, 939 min((size_t)size, sizeof(bios_size))) 940 ? -EFAULT : 0; 941 case AMDGPU_INFO_VBIOS_IMAGE: { 942 uint8_t *bios; 943 uint32_t bios_offset = info->vbios_info.offset; 944 945 if (bios_offset >= bios_size) 946 return -EINVAL; 947 948 bios = adev->bios + bios_offset; 949 return copy_to_user(out, bios, 950 min((size_t)size, (size_t)(bios_size - bios_offset))) 951 ? -EFAULT : 0; 952 } 953 case AMDGPU_INFO_VBIOS_INFO: { 954 struct drm_amdgpu_info_vbios vbios_info = {}; 955 struct atom_context *atom_context; 956 957 atom_context = adev->mode_info.atom_context; 958 if (atom_context) { 959 memcpy(vbios_info.name, atom_context->name, 960 sizeof(atom_context->name)); 961 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, 962 sizeof(atom_context->vbios_pn)); 963 vbios_info.version = atom_context->version; 964 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, 965 sizeof(atom_context->vbios_ver_str)); 966 memcpy(vbios_info.date, atom_context->date, 967 sizeof(atom_context->date)); 968 } 969 970 return copy_to_user(out, &vbios_info, 971 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; 972 } 973 default: 974 DRM_DEBUG_KMS("Invalid request %d\n", 975 info->vbios_info.type); 976 return -EINVAL; 977 } 978 } 979 case AMDGPU_INFO_NUM_HANDLES: { 980 struct drm_amdgpu_info_num_handles handle; 981 982 switch (info->query_hw_ip.type) { 983 case AMDGPU_HW_IP_UVD: 984 /* Starting Polaris, we support unlimited UVD handles */ 985 if (adev->asic_type < CHIP_POLARIS10) { 986 handle.uvd_max_handles = adev->uvd.max_handles; 987 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 988 989 return copy_to_user(out, &handle, 990 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 991 } else { 992 return -ENODATA; 993 } 994 995 break; 996 default: 997 return -EINVAL; 998 } 999 } 1000 case AMDGPU_INFO_SENSOR: { 1001 if (!adev->pm.dpm_enabled) 1002 return -ENOENT; 1003 1004 switch (info->sensor_info.type) { 1005 case AMDGPU_INFO_SENSOR_GFX_SCLK: 1006 /* get sclk in Mhz */ 1007 if (amdgpu_dpm_read_sensor(adev, 1008 AMDGPU_PP_SENSOR_GFX_SCLK, 1009 (void *)&ui32, &ui32_size)) { 1010 return -EINVAL; 1011 } 1012 ui32 /= 100; 1013 break; 1014 case AMDGPU_INFO_SENSOR_GFX_MCLK: 1015 /* get mclk in Mhz */ 1016 if (amdgpu_dpm_read_sensor(adev, 1017 AMDGPU_PP_SENSOR_GFX_MCLK, 1018 (void *)&ui32, &ui32_size)) { 1019 return -EINVAL; 1020 } 1021 ui32 /= 100; 1022 break; 1023 case AMDGPU_INFO_SENSOR_GPU_TEMP: 1024 /* get temperature in millidegrees C */ 1025 if (amdgpu_dpm_read_sensor(adev, 1026 AMDGPU_PP_SENSOR_GPU_TEMP, 1027 (void *)&ui32, &ui32_size)) { 1028 return -EINVAL; 1029 } 1030 break; 1031 case AMDGPU_INFO_SENSOR_GPU_LOAD: 1032 /* get GPU load */ 1033 if (amdgpu_dpm_read_sensor(adev, 1034 AMDGPU_PP_SENSOR_GPU_LOAD, 1035 (void *)&ui32, &ui32_size)) { 1036 return -EINVAL; 1037 } 1038 break; 1039 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 1040 /* get average GPU power */ 1041 if (amdgpu_dpm_read_sensor(adev, 1042 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 1043 (void *)&ui32, &ui32_size)) { 1044 return -EINVAL; 1045 } 1046 ui32 >>= 8; 1047 break; 1048 case AMDGPU_INFO_SENSOR_VDDNB: 1049 /* get VDDNB in millivolts */ 1050 if (amdgpu_dpm_read_sensor(adev, 1051 AMDGPU_PP_SENSOR_VDDNB, 1052 (void *)&ui32, &ui32_size)) { 1053 return -EINVAL; 1054 } 1055 break; 1056 case AMDGPU_INFO_SENSOR_VDDGFX: 1057 /* get VDDGFX in millivolts */ 1058 if (amdgpu_dpm_read_sensor(adev, 1059 AMDGPU_PP_SENSOR_VDDGFX, 1060 (void *)&ui32, &ui32_size)) { 1061 return -EINVAL; 1062 } 1063 break; 1064 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 1065 /* get stable pstate sclk in Mhz */ 1066 if (amdgpu_dpm_read_sensor(adev, 1067 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 1068 (void *)&ui32, &ui32_size)) { 1069 return -EINVAL; 1070 } 1071 ui32 /= 100; 1072 break; 1073 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 1074 /* get stable pstate mclk in Mhz */ 1075 if (amdgpu_dpm_read_sensor(adev, 1076 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 1077 (void *)&ui32, &ui32_size)) { 1078 return -EINVAL; 1079 } 1080 ui32 /= 100; 1081 break; 1082 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK: 1083 /* get peak pstate sclk in Mhz */ 1084 if (amdgpu_dpm_read_sensor(adev, 1085 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 1086 (void *)&ui32, &ui32_size)) { 1087 return -EINVAL; 1088 } 1089 ui32 /= 100; 1090 break; 1091 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK: 1092 /* get peak pstate mclk in Mhz */ 1093 if (amdgpu_dpm_read_sensor(adev, 1094 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 1095 (void *)&ui32, &ui32_size)) { 1096 return -EINVAL; 1097 } 1098 ui32 /= 100; 1099 break; 1100 default: 1101 DRM_DEBUG_KMS("Invalid request %d\n", 1102 info->sensor_info.type); 1103 return -EINVAL; 1104 } 1105 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1106 } 1107 case AMDGPU_INFO_VRAM_LOST_COUNTER: 1108 ui32 = atomic_read(&adev->vram_lost_counter); 1109 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1110 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 1111 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1112 uint64_t ras_mask; 1113 1114 if (!ras) 1115 return -EINVAL; 1116 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; 1117 1118 return copy_to_user(out, &ras_mask, 1119 min_t(u64, size, sizeof(ras_mask))) ? 1120 -EFAULT : 0; 1121 } 1122 case AMDGPU_INFO_VIDEO_CAPS: { 1123 const struct amdgpu_video_codecs *codecs; 1124 struct drm_amdgpu_info_video_caps *caps; 1125 int r; 1126 1127 if (!adev->asic_funcs->query_video_codecs) 1128 return -EINVAL; 1129 1130 switch (info->video_cap.type) { 1131 case AMDGPU_INFO_VIDEO_CAPS_DECODE: 1132 r = amdgpu_asic_query_video_codecs(adev, false, &codecs); 1133 if (r) 1134 return -EINVAL; 1135 break; 1136 case AMDGPU_INFO_VIDEO_CAPS_ENCODE: 1137 r = amdgpu_asic_query_video_codecs(adev, true, &codecs); 1138 if (r) 1139 return -EINVAL; 1140 break; 1141 default: 1142 DRM_DEBUG_KMS("Invalid request %d\n", 1143 info->video_cap.type); 1144 return -EINVAL; 1145 } 1146 1147 caps = kzalloc(sizeof(*caps), GFP_KERNEL); 1148 if (!caps) 1149 return -ENOMEM; 1150 1151 for (i = 0; i < codecs->codec_count; i++) { 1152 int idx = codecs->codec_array[i].codec_type; 1153 1154 switch (idx) { 1155 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: 1156 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: 1157 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: 1158 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: 1159 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: 1160 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: 1161 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: 1162 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: 1163 caps->codec_info[idx].valid = 1; 1164 caps->codec_info[idx].max_width = 1165 codecs->codec_array[i].max_width; 1166 caps->codec_info[idx].max_height = 1167 codecs->codec_array[i].max_height; 1168 caps->codec_info[idx].max_pixels_per_frame = 1169 codecs->codec_array[i].max_pixels_per_frame; 1170 caps->codec_info[idx].max_level = 1171 codecs->codec_array[i].max_level; 1172 break; 1173 default: 1174 break; 1175 } 1176 } 1177 r = copy_to_user(out, caps, 1178 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; 1179 kfree(caps); 1180 return r; 1181 } 1182 case AMDGPU_INFO_MAX_IBS: { 1183 uint32_t max_ibs[AMDGPU_HW_IP_NUM]; 1184 1185 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) 1186 max_ibs[i] = amdgpu_ring_max_ibs(i); 1187 1188 return copy_to_user(out, max_ibs, 1189 min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0; 1190 } 1191 default: 1192 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 1193 return -EINVAL; 1194 } 1195 return 0; 1196 } 1197 1198 1199 /* 1200 * Outdated mess for old drm with Xorg being in charge (void function now). 1201 */ 1202 /** 1203 * amdgpu_driver_lastclose_kms - drm callback for last close 1204 * 1205 * @dev: drm dev pointer 1206 * 1207 * Switch vga_switcheroo state after last close (all asics). 1208 */ 1209 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 1210 { 1211 drm_fb_helper_lastclose(dev); 1212 vga_switcheroo_process_delayed_switch(); 1213 } 1214 1215 /** 1216 * amdgpu_driver_open_kms - drm callback for open 1217 * 1218 * @dev: drm dev pointer 1219 * @file_priv: drm file 1220 * 1221 * On device open, init vm on cayman+ (all asics). 1222 * Returns 0 on success, error on failure. 1223 */ 1224 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1225 { 1226 struct amdgpu_device *adev = drm_to_adev(dev); 1227 struct amdgpu_fpriv *fpriv; 1228 int r, pasid; 1229 1230 /* Ensure IB tests are run on ring */ 1231 flush_delayed_work(&adev->delayed_init_work); 1232 1233 1234 if (amdgpu_ras_intr_triggered()) { 1235 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1236 return -EHWPOISON; 1237 } 1238 1239 file_priv->driver_priv = NULL; 1240 1241 r = pm_runtime_get_sync(dev->dev); 1242 if (r < 0) 1243 goto pm_put; 1244 1245 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1246 if (unlikely(!fpriv)) { 1247 r = -ENOMEM; 1248 goto out_suspend; 1249 } 1250 1251 pasid = amdgpu_pasid_alloc(16); 1252 if (pasid < 0) { 1253 dev_warn(adev->dev, "No more PASIDs available!"); 1254 pasid = 0; 1255 } 1256 1257 r = amdgpu_xcp_open_device(adev, fpriv, file_priv); 1258 if (r) 1259 goto error_pasid; 1260 1261 r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id); 1262 if (r) 1263 goto error_pasid; 1264 1265 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid); 1266 if (r) 1267 goto error_vm; 1268 1269 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1270 if (!fpriv->prt_va) { 1271 r = -ENOMEM; 1272 goto error_vm; 1273 } 1274 1275 if (adev->gfx.mcbp) { 1276 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1277 1278 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1279 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1280 if (r) 1281 goto error_vm; 1282 } 1283 1284 mutex_init(&fpriv->bo_list_lock); 1285 idr_init_base(&fpriv->bo_list_handles, 1); 1286 1287 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); 1288 1289 file_priv->driver_priv = fpriv; 1290 goto out_suspend; 1291 1292 error_vm: 1293 amdgpu_vm_fini(adev, &fpriv->vm); 1294 1295 error_pasid: 1296 if (pasid) { 1297 amdgpu_pasid_free(pasid); 1298 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0); 1299 } 1300 1301 kfree(fpriv); 1302 1303 out_suspend: 1304 pm_runtime_mark_last_busy(dev->dev); 1305 pm_put: 1306 pm_runtime_put_autosuspend(dev->dev); 1307 1308 return r; 1309 } 1310 1311 /** 1312 * amdgpu_driver_postclose_kms - drm callback for post close 1313 * 1314 * @dev: drm dev pointer 1315 * @file_priv: drm file 1316 * 1317 * On device post close, tear down vm on cayman+ (all asics). 1318 */ 1319 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1320 struct drm_file *file_priv) 1321 { 1322 struct amdgpu_device *adev = drm_to_adev(dev); 1323 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1324 struct amdgpu_bo_list *list; 1325 struct amdgpu_bo *pd; 1326 u32 pasid; 1327 int handle; 1328 1329 if (!fpriv) 1330 return; 1331 1332 pm_runtime_get_sync(dev->dev); 1333 1334 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1335 amdgpu_uvd_free_handles(adev, file_priv); 1336 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1337 amdgpu_vce_free_handles(adev, file_priv); 1338 1339 if (fpriv->csa_va) { 1340 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1341 1342 WARN_ON(amdgpu_unmap_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1343 fpriv->csa_va, csa_addr)); 1344 fpriv->csa_va = NULL; 1345 } 1346 1347 pasid = fpriv->vm.pasid; 1348 pd = amdgpu_bo_ref(fpriv->vm.root.bo); 1349 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) { 1350 amdgpu_vm_bo_del(adev, fpriv->prt_va); 1351 amdgpu_bo_unreserve(pd); 1352 } 1353 1354 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1355 amdgpu_vm_fini(adev, &fpriv->vm); 1356 1357 if (pasid) 1358 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1359 amdgpu_bo_unref(&pd); 1360 1361 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1362 amdgpu_bo_list_put(list); 1363 1364 idr_destroy(&fpriv->bo_list_handles); 1365 mutex_destroy(&fpriv->bo_list_lock); 1366 1367 kfree(fpriv); 1368 file_priv->driver_priv = NULL; 1369 1370 pm_runtime_mark_last_busy(dev->dev); 1371 pm_runtime_put_autosuspend(dev->dev); 1372 } 1373 1374 1375 void amdgpu_driver_release_kms(struct drm_device *dev) 1376 { 1377 struct amdgpu_device *adev = drm_to_adev(dev); 1378 1379 amdgpu_device_fini_sw(adev); 1380 pci_set_drvdata(adev->pdev, NULL); 1381 } 1382 1383 /* 1384 * VBlank related functions. 1385 */ 1386 /** 1387 * amdgpu_get_vblank_counter_kms - get frame count 1388 * 1389 * @crtc: crtc to get the frame count from 1390 * 1391 * Gets the frame count on the requested crtc (all asics). 1392 * Returns frame count on success, -EINVAL on failure. 1393 */ 1394 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1395 { 1396 struct drm_device *dev = crtc->dev; 1397 unsigned int pipe = crtc->index; 1398 struct amdgpu_device *adev = drm_to_adev(dev); 1399 int vpos, hpos, stat; 1400 u32 count; 1401 1402 if (pipe >= adev->mode_info.num_crtc) { 1403 DRM_ERROR("Invalid crtc %u\n", pipe); 1404 return -EINVAL; 1405 } 1406 1407 /* The hw increments its frame counter at start of vsync, not at start 1408 * of vblank, as is required by DRM core vblank counter handling. 1409 * Cook the hw count here to make it appear to the caller as if it 1410 * incremented at start of vblank. We measure distance to start of 1411 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1412 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1413 * result by 1 to give the proper appearance to caller. 1414 */ 1415 if (adev->mode_info.crtcs[pipe]) { 1416 /* Repeat readout if needed to provide stable result if 1417 * we cross start of vsync during the queries. 1418 */ 1419 do { 1420 count = amdgpu_display_vblank_get_counter(adev, pipe); 1421 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1422 * vpos as distance to start of vblank, instead of 1423 * regular vertical scanout pos. 1424 */ 1425 stat = amdgpu_display_get_crtc_scanoutpos( 1426 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1427 &vpos, &hpos, NULL, NULL, 1428 &adev->mode_info.crtcs[pipe]->base.hwmode); 1429 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1430 1431 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1432 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1433 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1434 } else { 1435 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1436 pipe, vpos); 1437 1438 /* Bump counter if we are at >= leading edge of vblank, 1439 * but before vsync where vpos would turn negative and 1440 * the hw counter really increments. 1441 */ 1442 if (vpos >= 0) 1443 count++; 1444 } 1445 } else { 1446 /* Fallback to use value as is. */ 1447 count = amdgpu_display_vblank_get_counter(adev, pipe); 1448 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1449 } 1450 1451 return count; 1452 } 1453 1454 /** 1455 * amdgpu_enable_vblank_kms - enable vblank interrupt 1456 * 1457 * @crtc: crtc to enable vblank interrupt for 1458 * 1459 * Enable the interrupt on the requested crtc (all asics). 1460 * Returns 0 on success, -EINVAL on failure. 1461 */ 1462 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1463 { 1464 struct drm_device *dev = crtc->dev; 1465 unsigned int pipe = crtc->index; 1466 struct amdgpu_device *adev = drm_to_adev(dev); 1467 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1468 1469 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1470 } 1471 1472 /** 1473 * amdgpu_disable_vblank_kms - disable vblank interrupt 1474 * 1475 * @crtc: crtc to disable vblank interrupt for 1476 * 1477 * Disable the interrupt on the requested crtc (all asics). 1478 */ 1479 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1480 { 1481 struct drm_device *dev = crtc->dev; 1482 unsigned int pipe = crtc->index; 1483 struct amdgpu_device *adev = drm_to_adev(dev); 1484 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1485 1486 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1487 } 1488 1489 /* 1490 * Debugfs info 1491 */ 1492 #if defined(CONFIG_DEBUG_FS) 1493 1494 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 1495 { 1496 struct amdgpu_device *adev = m->private; 1497 struct drm_amdgpu_info_firmware fw_info; 1498 struct drm_amdgpu_query_fw query_fw; 1499 struct atom_context *ctx = adev->mode_info.atom_context; 1500 uint8_t smu_program, smu_major, smu_minor, smu_debug; 1501 int ret, i; 1502 1503 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { 1504 #define TA_FW_NAME(type)[TA_FW_TYPE_PSP_##type] = #type 1505 TA_FW_NAME(XGMI), 1506 TA_FW_NAME(RAS), 1507 TA_FW_NAME(HDCP), 1508 TA_FW_NAME(DTM), 1509 TA_FW_NAME(RAP), 1510 TA_FW_NAME(SECUREDISPLAY), 1511 #undef TA_FW_NAME 1512 }; 1513 1514 /* VCE */ 1515 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1516 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1517 if (ret) 1518 return ret; 1519 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1520 fw_info.feature, fw_info.ver); 1521 1522 /* UVD */ 1523 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1524 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1525 if (ret) 1526 return ret; 1527 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1528 fw_info.feature, fw_info.ver); 1529 1530 /* GMC */ 1531 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1532 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1533 if (ret) 1534 return ret; 1535 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1536 fw_info.feature, fw_info.ver); 1537 1538 /* ME */ 1539 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1540 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1541 if (ret) 1542 return ret; 1543 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1544 fw_info.feature, fw_info.ver); 1545 1546 /* PFP */ 1547 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1548 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1549 if (ret) 1550 return ret; 1551 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1552 fw_info.feature, fw_info.ver); 1553 1554 /* CE */ 1555 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1556 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1557 if (ret) 1558 return ret; 1559 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1560 fw_info.feature, fw_info.ver); 1561 1562 /* RLC */ 1563 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1564 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1565 if (ret) 1566 return ret; 1567 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1568 fw_info.feature, fw_info.ver); 1569 1570 /* RLC SAVE RESTORE LIST CNTL */ 1571 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1572 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1573 if (ret) 1574 return ret; 1575 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1576 fw_info.feature, fw_info.ver); 1577 1578 /* RLC SAVE RESTORE LIST GPM MEM */ 1579 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1580 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1581 if (ret) 1582 return ret; 1583 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1584 fw_info.feature, fw_info.ver); 1585 1586 /* RLC SAVE RESTORE LIST SRM MEM */ 1587 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1588 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1589 if (ret) 1590 return ret; 1591 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1592 fw_info.feature, fw_info.ver); 1593 1594 /* RLCP */ 1595 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP; 1596 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1597 if (ret) 1598 return ret; 1599 seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n", 1600 fw_info.feature, fw_info.ver); 1601 1602 /* RLCV */ 1603 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV; 1604 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1605 if (ret) 1606 return ret; 1607 seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n", 1608 fw_info.feature, fw_info.ver); 1609 1610 /* MEC */ 1611 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1612 query_fw.index = 0; 1613 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1614 if (ret) 1615 return ret; 1616 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1617 fw_info.feature, fw_info.ver); 1618 1619 /* MEC2 */ 1620 if (adev->gfx.mec2_fw) { 1621 query_fw.index = 1; 1622 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1623 if (ret) 1624 return ret; 1625 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1626 fw_info.feature, fw_info.ver); 1627 } 1628 1629 /* IMU */ 1630 query_fw.fw_type = AMDGPU_INFO_FW_IMU; 1631 query_fw.index = 0; 1632 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1633 if (ret) 1634 return ret; 1635 seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n", 1636 fw_info.feature, fw_info.ver); 1637 1638 /* PSP SOS */ 1639 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1640 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1641 if (ret) 1642 return ret; 1643 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1644 fw_info.feature, fw_info.ver); 1645 1646 1647 /* PSP ASD */ 1648 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1649 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1650 if (ret) 1651 return ret; 1652 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1653 fw_info.feature, fw_info.ver); 1654 1655 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1656 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { 1657 query_fw.index = i; 1658 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1659 if (ret) 1660 continue; 1661 1662 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1663 ta_fw_name[i], fw_info.feature, fw_info.ver); 1664 } 1665 1666 /* SMC */ 1667 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1668 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1669 if (ret) 1670 return ret; 1671 smu_program = (fw_info.ver >> 24) & 0xff; 1672 smu_major = (fw_info.ver >> 16) & 0xff; 1673 smu_minor = (fw_info.ver >> 8) & 0xff; 1674 smu_debug = (fw_info.ver >> 0) & 0xff; 1675 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n", 1676 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug); 1677 1678 /* SDMA */ 1679 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1680 for (i = 0; i < adev->sdma.num_instances; i++) { 1681 query_fw.index = i; 1682 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1683 if (ret) 1684 return ret; 1685 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1686 i, fw_info.feature, fw_info.ver); 1687 } 1688 1689 /* VCN */ 1690 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1691 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1692 if (ret) 1693 return ret; 1694 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1695 fw_info.feature, fw_info.ver); 1696 1697 /* DMCU */ 1698 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1699 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1700 if (ret) 1701 return ret; 1702 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1703 fw_info.feature, fw_info.ver); 1704 1705 /* DMCUB */ 1706 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1707 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1708 if (ret) 1709 return ret; 1710 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1711 fw_info.feature, fw_info.ver); 1712 1713 /* TOC */ 1714 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1715 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1716 if (ret) 1717 return ret; 1718 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1719 fw_info.feature, fw_info.ver); 1720 1721 /* CAP */ 1722 if (adev->psp.cap_fw) { 1723 query_fw.fw_type = AMDGPU_INFO_FW_CAP; 1724 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1725 if (ret) 1726 return ret; 1727 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n", 1728 fw_info.feature, fw_info.ver); 1729 } 1730 1731 /* MES_KIQ */ 1732 query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ; 1733 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1734 if (ret) 1735 return ret; 1736 seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n", 1737 fw_info.feature, fw_info.ver); 1738 1739 /* MES */ 1740 query_fw.fw_type = AMDGPU_INFO_FW_MES; 1741 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1742 if (ret) 1743 return ret; 1744 seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n", 1745 fw_info.feature, fw_info.ver); 1746 1747 /* VPE */ 1748 query_fw.fw_type = AMDGPU_INFO_FW_VPE; 1749 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1750 if (ret) 1751 return ret; 1752 seq_printf(m, "VPE feature version: %u, firmware version: 0x%08x\n", 1753 fw_info.feature, fw_info.ver); 1754 1755 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_pn); 1756 1757 return 0; 1758 } 1759 1760 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); 1761 1762 #endif 1763 1764 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1765 { 1766 #if defined(CONFIG_DEBUG_FS) 1767 struct drm_minor *minor = adev_to_drm(adev)->primary; 1768 struct dentry *root = minor->debugfs_root; 1769 1770 debugfs_create_file("amdgpu_firmware_info", 0444, root, 1771 adev, &amdgpu_debugfs_firmware_info_fops); 1772 1773 #endif 1774 } 1775