1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 34 #include <linux/vga_switcheroo.h> 35 #include <linux/slab.h> 36 #include <linux/pm_runtime.h> 37 #include "amdgpu_amdkfd.h" 38 39 #if defined(CONFIG_VGA_SWITCHEROO) 40 bool amdgpu_has_atpx(void); 41 #else 42 static inline bool amdgpu_has_atpx(void) { return false; } 43 #endif 44 45 /** 46 * amdgpu_driver_unload_kms - Main unload function for KMS. 47 * 48 * @dev: drm dev pointer 49 * 50 * This is the main unload function for KMS (all asics). 51 * Returns 0 on success. 52 */ 53 void amdgpu_driver_unload_kms(struct drm_device *dev) 54 { 55 struct amdgpu_device *adev = dev->dev_private; 56 57 if (adev == NULL) 58 return; 59 60 if (adev->rmmio == NULL) 61 goto done_free; 62 63 if (amdgpu_device_is_px(dev)) { 64 pm_runtime_get_sync(dev->dev); 65 pm_runtime_forbid(dev->dev); 66 } 67 68 amdgpu_amdkfd_device_fini(adev); 69 70 amdgpu_acpi_fini(adev); 71 72 amdgpu_device_fini(adev); 73 74 done_free: 75 kfree(adev); 76 dev->dev_private = NULL; 77 } 78 79 /** 80 * amdgpu_driver_load_kms - Main load function for KMS. 81 * 82 * @dev: drm dev pointer 83 * @flags: device flags 84 * 85 * This is the main load function for KMS (all asics). 86 * Returns 0 on success, error on failure. 87 */ 88 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) 89 { 90 struct amdgpu_device *adev; 91 int r, acpi_status; 92 93 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); 94 if (adev == NULL) { 95 return -ENOMEM; 96 } 97 dev->dev_private = (void *)adev; 98 99 if ((amdgpu_runtime_pm != 0) && 100 amdgpu_has_atpx() && 101 (amdgpu_is_atpx_hybrid() || 102 amdgpu_has_atpx_dgpu_power_cntl()) && 103 ((flags & AMD_IS_APU) == 0)) 104 flags |= AMD_IS_PX; 105 106 /* amdgpu_device_init should report only fatal error 107 * like memory allocation failure or iomapping failure, 108 * or memory manager initialization failure, it must 109 * properly initialize the GPU MC controller and permit 110 * VRAM allocation 111 */ 112 r = amdgpu_device_init(adev, dev, dev->pdev, flags); 113 if (r) { 114 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 115 goto out; 116 } 117 118 /* Call ACPI methods: require modeset init 119 * but failure is not fatal 120 */ 121 if (!r) { 122 acpi_status = amdgpu_acpi_init(adev); 123 if (acpi_status) 124 dev_dbg(&dev->pdev->dev, 125 "Error during ACPI methods call\n"); 126 } 127 128 amdgpu_amdkfd_load_interface(adev); 129 amdgpu_amdkfd_device_probe(adev); 130 amdgpu_amdkfd_device_init(adev); 131 132 if (amdgpu_device_is_px(dev)) { 133 pm_runtime_use_autosuspend(dev->dev); 134 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 135 pm_runtime_set_active(dev->dev); 136 pm_runtime_allow(dev->dev); 137 pm_runtime_mark_last_busy(dev->dev); 138 pm_runtime_put_autosuspend(dev->dev); 139 } 140 141 out: 142 if (r) { 143 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 144 if (adev->rmmio && amdgpu_device_is_px(dev)) 145 pm_runtime_put_noidle(dev->dev); 146 amdgpu_driver_unload_kms(dev); 147 } 148 149 return r; 150 } 151 152 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 153 struct drm_amdgpu_query_fw *query_fw, 154 struct amdgpu_device *adev) 155 { 156 switch (query_fw->fw_type) { 157 case AMDGPU_INFO_FW_VCE: 158 fw_info->ver = adev->vce.fw_version; 159 fw_info->feature = adev->vce.fb_version; 160 break; 161 case AMDGPU_INFO_FW_UVD: 162 fw_info->ver = adev->uvd.fw_version; 163 fw_info->feature = 0; 164 break; 165 case AMDGPU_INFO_FW_GMC: 166 fw_info->ver = adev->mc.fw_version; 167 fw_info->feature = 0; 168 break; 169 case AMDGPU_INFO_FW_GFX_ME: 170 fw_info->ver = adev->gfx.me_fw_version; 171 fw_info->feature = adev->gfx.me_feature_version; 172 break; 173 case AMDGPU_INFO_FW_GFX_PFP: 174 fw_info->ver = adev->gfx.pfp_fw_version; 175 fw_info->feature = adev->gfx.pfp_feature_version; 176 break; 177 case AMDGPU_INFO_FW_GFX_CE: 178 fw_info->ver = adev->gfx.ce_fw_version; 179 fw_info->feature = adev->gfx.ce_feature_version; 180 break; 181 case AMDGPU_INFO_FW_GFX_RLC: 182 fw_info->ver = adev->gfx.rlc_fw_version; 183 fw_info->feature = adev->gfx.rlc_feature_version; 184 break; 185 case AMDGPU_INFO_FW_GFX_MEC: 186 if (query_fw->index == 0) { 187 fw_info->ver = adev->gfx.mec_fw_version; 188 fw_info->feature = adev->gfx.mec_feature_version; 189 } else if (query_fw->index == 1) { 190 fw_info->ver = adev->gfx.mec2_fw_version; 191 fw_info->feature = adev->gfx.mec2_feature_version; 192 } else 193 return -EINVAL; 194 break; 195 case AMDGPU_INFO_FW_SMC: 196 fw_info->ver = adev->pm.fw_version; 197 fw_info->feature = 0; 198 break; 199 case AMDGPU_INFO_FW_SDMA: 200 if (query_fw->index >= adev->sdma.num_instances) 201 return -EINVAL; 202 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 203 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 204 break; 205 default: 206 return -EINVAL; 207 } 208 return 0; 209 } 210 211 /* 212 * Userspace get information ioctl 213 */ 214 /** 215 * amdgpu_info_ioctl - answer a device specific request. 216 * 217 * @adev: amdgpu device pointer 218 * @data: request object 219 * @filp: drm filp 220 * 221 * This function is used to pass device specific parameters to the userspace 222 * drivers. Examples include: pci device id, pipeline parms, tiling params, 223 * etc. (all asics). 224 * Returns 0 on success, -EINVAL on failure. 225 */ 226 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 227 { 228 struct amdgpu_device *adev = dev->dev_private; 229 struct drm_amdgpu_info *info = data; 230 struct amdgpu_mode_info *minfo = &adev->mode_info; 231 void __user *out = (void __user *)(long)info->return_pointer; 232 uint32_t size = info->return_size; 233 struct drm_crtc *crtc; 234 uint32_t ui32 = 0; 235 uint64_t ui64 = 0; 236 int i, found; 237 238 if (!info->return_size || !info->return_pointer) 239 return -EINVAL; 240 241 switch (info->query) { 242 case AMDGPU_INFO_ACCEL_WORKING: 243 ui32 = adev->accel_working; 244 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 245 case AMDGPU_INFO_CRTC_FROM_ID: 246 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 247 crtc = (struct drm_crtc *)minfo->crtcs[i]; 248 if (crtc && crtc->base.id == info->mode_crtc.id) { 249 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 250 ui32 = amdgpu_crtc->crtc_id; 251 found = 1; 252 break; 253 } 254 } 255 if (!found) { 256 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 257 return -EINVAL; 258 } 259 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 260 case AMDGPU_INFO_HW_IP_INFO: { 261 struct drm_amdgpu_info_hw_ip ip = {}; 262 enum amd_ip_block_type type; 263 uint32_t ring_mask = 0; 264 uint32_t ib_start_alignment = 0; 265 uint32_t ib_size_alignment = 0; 266 267 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 268 return -EINVAL; 269 270 switch (info->query_hw_ip.type) { 271 case AMDGPU_HW_IP_GFX: 272 type = AMD_IP_BLOCK_TYPE_GFX; 273 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 274 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i); 275 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 276 ib_size_alignment = 8; 277 break; 278 case AMDGPU_HW_IP_COMPUTE: 279 type = AMD_IP_BLOCK_TYPE_GFX; 280 for (i = 0; i < adev->gfx.num_compute_rings; i++) 281 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i); 282 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 283 ib_size_alignment = 8; 284 break; 285 case AMDGPU_HW_IP_DMA: 286 type = AMD_IP_BLOCK_TYPE_SDMA; 287 for (i = 0; i < adev->sdma.num_instances; i++) 288 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i); 289 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 290 ib_size_alignment = 1; 291 break; 292 case AMDGPU_HW_IP_UVD: 293 type = AMD_IP_BLOCK_TYPE_UVD; 294 ring_mask = adev->uvd.ring.ready ? 1 : 0; 295 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 296 ib_size_alignment = 16; 297 break; 298 case AMDGPU_HW_IP_VCE: 299 type = AMD_IP_BLOCK_TYPE_VCE; 300 for (i = 0; i < adev->vce.num_rings; i++) 301 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i); 302 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 303 ib_size_alignment = 1; 304 break; 305 default: 306 return -EINVAL; 307 } 308 309 for (i = 0; i < adev->num_ip_blocks; i++) { 310 if (adev->ip_blocks[i].version->type == type && 311 adev->ip_blocks[i].status.valid) { 312 ip.hw_ip_version_major = adev->ip_blocks[i].version->major; 313 ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor; 314 ip.capabilities_flags = 0; 315 ip.available_rings = ring_mask; 316 ip.ib_start_alignment = ib_start_alignment; 317 ip.ib_size_alignment = ib_size_alignment; 318 break; 319 } 320 } 321 return copy_to_user(out, &ip, 322 min((size_t)size, sizeof(ip))) ? -EFAULT : 0; 323 } 324 case AMDGPU_INFO_HW_IP_COUNT: { 325 enum amd_ip_block_type type; 326 uint32_t count = 0; 327 328 switch (info->query_hw_ip.type) { 329 case AMDGPU_HW_IP_GFX: 330 type = AMD_IP_BLOCK_TYPE_GFX; 331 break; 332 case AMDGPU_HW_IP_COMPUTE: 333 type = AMD_IP_BLOCK_TYPE_GFX; 334 break; 335 case AMDGPU_HW_IP_DMA: 336 type = AMD_IP_BLOCK_TYPE_SDMA; 337 break; 338 case AMDGPU_HW_IP_UVD: 339 type = AMD_IP_BLOCK_TYPE_UVD; 340 break; 341 case AMDGPU_HW_IP_VCE: 342 type = AMD_IP_BLOCK_TYPE_VCE; 343 break; 344 default: 345 return -EINVAL; 346 } 347 348 for (i = 0; i < adev->num_ip_blocks; i++) 349 if (adev->ip_blocks[i].version->type == type && 350 adev->ip_blocks[i].status.valid && 351 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 352 count++; 353 354 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 355 } 356 case AMDGPU_INFO_TIMESTAMP: 357 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 358 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 359 case AMDGPU_INFO_FW_VERSION: { 360 struct drm_amdgpu_info_firmware fw_info; 361 int ret; 362 363 /* We only support one instance of each IP block right now. */ 364 if (info->query_fw.ip_instance != 0) 365 return -EINVAL; 366 367 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 368 if (ret) 369 return ret; 370 371 return copy_to_user(out, &fw_info, 372 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 373 } 374 case AMDGPU_INFO_NUM_BYTES_MOVED: 375 ui64 = atomic64_read(&adev->num_bytes_moved); 376 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 377 case AMDGPU_INFO_NUM_EVICTIONS: 378 ui64 = atomic64_read(&adev->num_evictions); 379 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 380 case AMDGPU_INFO_VRAM_USAGE: 381 ui64 = atomic64_read(&adev->vram_usage); 382 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 383 case AMDGPU_INFO_VIS_VRAM_USAGE: 384 ui64 = atomic64_read(&adev->vram_vis_usage); 385 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 386 case AMDGPU_INFO_GTT_USAGE: 387 ui64 = atomic64_read(&adev->gtt_usage); 388 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 389 case AMDGPU_INFO_GDS_CONFIG: { 390 struct drm_amdgpu_info_gds gds_info; 391 392 memset(&gds_info, 0, sizeof(gds_info)); 393 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT; 394 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT; 395 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT; 396 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT; 397 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT; 398 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT; 399 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT; 400 return copy_to_user(out, &gds_info, 401 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 402 } 403 case AMDGPU_INFO_VRAM_GTT: { 404 struct drm_amdgpu_info_vram_gtt vram_gtt; 405 406 vram_gtt.vram_size = adev->mc.real_vram_size; 407 vram_gtt.vram_size -= adev->vram_pin_size; 408 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size; 409 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size); 410 vram_gtt.gtt_size = adev->mc.gtt_size; 411 vram_gtt.gtt_size -= adev->gart_pin_size; 412 return copy_to_user(out, &vram_gtt, 413 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 414 } 415 case AMDGPU_INFO_MEMORY: { 416 struct drm_amdgpu_memory_info mem; 417 418 memset(&mem, 0, sizeof(mem)); 419 mem.vram.total_heap_size = adev->mc.real_vram_size; 420 mem.vram.usable_heap_size = 421 adev->mc.real_vram_size - adev->vram_pin_size; 422 mem.vram.heap_usage = atomic64_read(&adev->vram_usage); 423 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 424 425 mem.cpu_accessible_vram.total_heap_size = 426 adev->mc.visible_vram_size; 427 mem.cpu_accessible_vram.usable_heap_size = 428 adev->mc.visible_vram_size - 429 (adev->vram_pin_size - adev->invisible_pin_size); 430 mem.cpu_accessible_vram.heap_usage = 431 atomic64_read(&adev->vram_vis_usage); 432 mem.cpu_accessible_vram.max_allocation = 433 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 434 435 mem.gtt.total_heap_size = adev->mc.gtt_size; 436 mem.gtt.usable_heap_size = 437 adev->mc.gtt_size - adev->gart_pin_size; 438 mem.gtt.heap_usage = atomic64_read(&adev->gtt_usage); 439 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 440 441 return copy_to_user(out, &mem, 442 min((size_t)size, sizeof(mem))) 443 ? -EFAULT : 0; 444 } 445 case AMDGPU_INFO_READ_MMR_REG: { 446 unsigned n, alloc_size; 447 uint32_t *regs; 448 unsigned se_num = (info->read_mmr_reg.instance >> 449 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 450 AMDGPU_INFO_MMR_SE_INDEX_MASK; 451 unsigned sh_num = (info->read_mmr_reg.instance >> 452 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 453 AMDGPU_INFO_MMR_SH_INDEX_MASK; 454 455 /* set full masks if the userspace set all bits 456 * in the bitfields */ 457 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 458 se_num = 0xffffffff; 459 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 460 sh_num = 0xffffffff; 461 462 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 463 if (!regs) 464 return -ENOMEM; 465 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 466 467 for (i = 0; i < info->read_mmr_reg.count; i++) 468 if (amdgpu_asic_read_register(adev, se_num, sh_num, 469 info->read_mmr_reg.dword_offset + i, 470 ®s[i])) { 471 DRM_DEBUG_KMS("unallowed offset %#x\n", 472 info->read_mmr_reg.dword_offset + i); 473 kfree(regs); 474 return -EFAULT; 475 } 476 n = copy_to_user(out, regs, min(size, alloc_size)); 477 kfree(regs); 478 return n ? -EFAULT : 0; 479 } 480 case AMDGPU_INFO_DEV_INFO: { 481 struct drm_amdgpu_info_device dev_info = {}; 482 483 dev_info.device_id = dev->pdev->device; 484 dev_info.chip_rev = adev->rev_id; 485 dev_info.external_rev = adev->external_rev_id; 486 dev_info.pci_rev = dev->pdev->revision; 487 dev_info.family = adev->family; 488 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; 489 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 490 /* return all clocks in KHz */ 491 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 492 if (adev->pm.dpm_enabled) { 493 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 494 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 495 } else { 496 dev_info.max_engine_clock = adev->pm.default_sclk * 10; 497 dev_info.max_memory_clock = adev->pm.default_mclk * 10; 498 } 499 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 500 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 501 adev->gfx.config.max_shader_engines; 502 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 503 dev_info._pad = 0; 504 dev_info.ids_flags = 0; 505 if (adev->flags & AMD_IS_APU) 506 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 507 if (amdgpu_sriov_vf(adev)) 508 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 509 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 510 dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 511 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 512 dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) * 513 AMDGPU_GPU_PAGE_SIZE; 514 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; 515 516 dev_info.cu_active_number = adev->gfx.cu_info.number; 517 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 518 dev_info.ce_ram_size = adev->gfx.ce_ram_size; 519 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 520 sizeof(adev->gfx.cu_info.bitmap)); 521 dev_info.vram_type = adev->mc.vram_type; 522 dev_info.vram_bit_width = adev->mc.vram_width; 523 dev_info.vce_harvest_config = adev->vce.harvest_config; 524 525 return copy_to_user(out, &dev_info, 526 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 527 } 528 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 529 unsigned i; 530 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 531 struct amd_vce_state *vce_state; 532 533 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 534 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 535 if (vce_state) { 536 vce_clk_table.entries[i].sclk = vce_state->sclk; 537 vce_clk_table.entries[i].mclk = vce_state->mclk; 538 vce_clk_table.entries[i].eclk = vce_state->evclk; 539 vce_clk_table.num_valid_entries++; 540 } 541 } 542 543 return copy_to_user(out, &vce_clk_table, 544 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 545 } 546 case AMDGPU_INFO_VBIOS: { 547 uint32_t bios_size = adev->bios_size; 548 549 switch (info->vbios_info.type) { 550 case AMDGPU_INFO_VBIOS_SIZE: 551 return copy_to_user(out, &bios_size, 552 min((size_t)size, sizeof(bios_size))) 553 ? -EFAULT : 0; 554 case AMDGPU_INFO_VBIOS_IMAGE: { 555 uint8_t *bios; 556 uint32_t bios_offset = info->vbios_info.offset; 557 558 if (bios_offset >= bios_size) 559 return -EINVAL; 560 561 bios = adev->bios + bios_offset; 562 return copy_to_user(out, bios, 563 min((size_t)size, (size_t)(bios_size - bios_offset))) 564 ? -EFAULT : 0; 565 } 566 default: 567 DRM_DEBUG_KMS("Invalid request %d\n", 568 info->vbios_info.type); 569 return -EINVAL; 570 } 571 } 572 default: 573 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 574 return -EINVAL; 575 } 576 return 0; 577 } 578 579 580 /* 581 * Outdated mess for old drm with Xorg being in charge (void function now). 582 */ 583 /** 584 * amdgpu_driver_lastclose_kms - drm callback for last close 585 * 586 * @dev: drm dev pointer 587 * 588 * Switch vga_switcheroo state after last close (all asics). 589 */ 590 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 591 { 592 struct amdgpu_device *adev = dev->dev_private; 593 594 amdgpu_fbdev_restore_mode(adev); 595 vga_switcheroo_process_delayed_switch(); 596 } 597 598 /** 599 * amdgpu_driver_open_kms - drm callback for open 600 * 601 * @dev: drm dev pointer 602 * @file_priv: drm file 603 * 604 * On device open, init vm on cayman+ (all asics). 605 * Returns 0 on success, error on failure. 606 */ 607 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 608 { 609 struct amdgpu_device *adev = dev->dev_private; 610 struct amdgpu_fpriv *fpriv; 611 int r; 612 613 file_priv->driver_priv = NULL; 614 615 r = pm_runtime_get_sync(dev->dev); 616 if (r < 0) 617 return r; 618 619 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 620 if (unlikely(!fpriv)) { 621 r = -ENOMEM; 622 goto out_suspend; 623 } 624 625 r = amdgpu_vm_init(adev, &fpriv->vm); 626 if (r) { 627 kfree(fpriv); 628 goto out_suspend; 629 } 630 631 mutex_init(&fpriv->bo_list_lock); 632 idr_init(&fpriv->bo_list_handles); 633 634 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 635 636 file_priv->driver_priv = fpriv; 637 638 out_suspend: 639 pm_runtime_mark_last_busy(dev->dev); 640 pm_runtime_put_autosuspend(dev->dev); 641 642 return r; 643 } 644 645 /** 646 * amdgpu_driver_postclose_kms - drm callback for post close 647 * 648 * @dev: drm dev pointer 649 * @file_priv: drm file 650 * 651 * On device post close, tear down vm on cayman+ (all asics). 652 */ 653 void amdgpu_driver_postclose_kms(struct drm_device *dev, 654 struct drm_file *file_priv) 655 { 656 struct amdgpu_device *adev = dev->dev_private; 657 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 658 struct amdgpu_bo_list *list; 659 int handle; 660 661 if (!fpriv) 662 return; 663 664 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 665 666 amdgpu_uvd_free_handles(adev, file_priv); 667 amdgpu_vce_free_handles(adev, file_priv); 668 669 amdgpu_vm_fini(adev, &fpriv->vm); 670 671 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 672 amdgpu_bo_list_free(list); 673 674 idr_destroy(&fpriv->bo_list_handles); 675 mutex_destroy(&fpriv->bo_list_lock); 676 677 kfree(fpriv); 678 file_priv->driver_priv = NULL; 679 680 pm_runtime_mark_last_busy(dev->dev); 681 pm_runtime_put_autosuspend(dev->dev); 682 } 683 684 /** 685 * amdgpu_driver_preclose_kms - drm callback for pre close 686 * 687 * @dev: drm dev pointer 688 * @file_priv: drm file 689 * 690 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx 691 * (all asics). 692 */ 693 void amdgpu_driver_preclose_kms(struct drm_device *dev, 694 struct drm_file *file_priv) 695 { 696 pm_runtime_get_sync(dev->dev); 697 } 698 699 /* 700 * VBlank related functions. 701 */ 702 /** 703 * amdgpu_get_vblank_counter_kms - get frame count 704 * 705 * @dev: drm dev pointer 706 * @pipe: crtc to get the frame count from 707 * 708 * Gets the frame count on the requested crtc (all asics). 709 * Returns frame count on success, -EINVAL on failure. 710 */ 711 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) 712 { 713 struct amdgpu_device *adev = dev->dev_private; 714 int vpos, hpos, stat; 715 u32 count; 716 717 if (pipe >= adev->mode_info.num_crtc) { 718 DRM_ERROR("Invalid crtc %u\n", pipe); 719 return -EINVAL; 720 } 721 722 /* The hw increments its frame counter at start of vsync, not at start 723 * of vblank, as is required by DRM core vblank counter handling. 724 * Cook the hw count here to make it appear to the caller as if it 725 * incremented at start of vblank. We measure distance to start of 726 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 727 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 728 * result by 1 to give the proper appearance to caller. 729 */ 730 if (adev->mode_info.crtcs[pipe]) { 731 /* Repeat readout if needed to provide stable result if 732 * we cross start of vsync during the queries. 733 */ 734 do { 735 count = amdgpu_display_vblank_get_counter(adev, pipe); 736 /* Ask amdgpu_get_crtc_scanoutpos to return vpos as 737 * distance to start of vblank, instead of regular 738 * vertical scanout pos. 739 */ 740 stat = amdgpu_get_crtc_scanoutpos( 741 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 742 &vpos, &hpos, NULL, NULL, 743 &adev->mode_info.crtcs[pipe]->base.hwmode); 744 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 745 746 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 747 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 748 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 749 } else { 750 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 751 pipe, vpos); 752 753 /* Bump counter if we are at >= leading edge of vblank, 754 * but before vsync where vpos would turn negative and 755 * the hw counter really increments. 756 */ 757 if (vpos >= 0) 758 count++; 759 } 760 } else { 761 /* Fallback to use value as is. */ 762 count = amdgpu_display_vblank_get_counter(adev, pipe); 763 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 764 } 765 766 return count; 767 } 768 769 /** 770 * amdgpu_enable_vblank_kms - enable vblank interrupt 771 * 772 * @dev: drm dev pointer 773 * @pipe: crtc to enable vblank interrupt for 774 * 775 * Enable the interrupt on the requested crtc (all asics). 776 * Returns 0 on success, -EINVAL on failure. 777 */ 778 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe) 779 { 780 struct amdgpu_device *adev = dev->dev_private; 781 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe); 782 783 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 784 } 785 786 /** 787 * amdgpu_disable_vblank_kms - disable vblank interrupt 788 * 789 * @dev: drm dev pointer 790 * @pipe: crtc to disable vblank interrupt for 791 * 792 * Disable the interrupt on the requested crtc (all asics). 793 */ 794 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe) 795 { 796 struct amdgpu_device *adev = dev->dev_private; 797 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe); 798 799 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 800 } 801 802 /** 803 * amdgpu_get_vblank_timestamp_kms - get vblank timestamp 804 * 805 * @dev: drm dev pointer 806 * @crtc: crtc to get the timestamp for 807 * @max_error: max error 808 * @vblank_time: time value 809 * @flags: flags passed to the driver 810 * 811 * Gets the timestamp on the requested crtc based on the 812 * scanout position. (all asics). 813 * Returns postive status flags on success, negative error on failure. 814 */ 815 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 816 int *max_error, 817 struct timeval *vblank_time, 818 unsigned flags) 819 { 820 struct drm_crtc *crtc; 821 struct amdgpu_device *adev = dev->dev_private; 822 823 if (pipe >= dev->num_crtcs) { 824 DRM_ERROR("Invalid crtc %u\n", pipe); 825 return -EINVAL; 826 } 827 828 /* Get associated drm_crtc: */ 829 crtc = &adev->mode_info.crtcs[pipe]->base; 830 if (!crtc) { 831 /* This can occur on driver load if some component fails to 832 * initialize completely and driver is unloaded */ 833 DRM_ERROR("Uninitialized crtc %d\n", pipe); 834 return -EINVAL; 835 } 836 837 /* Helper routine in DRM core does all the work: */ 838 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, 839 vblank_time, flags, 840 &crtc->hwmode); 841 } 842 843 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 844 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 845 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 846 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 847 /* KMS */ 848 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 849 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 850 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 851 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 852 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 853 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 854 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 855 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 856 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 857 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 858 }; 859 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); 860 861 /* 862 * Debugfs info 863 */ 864 #if defined(CONFIG_DEBUG_FS) 865 866 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) 867 { 868 struct drm_info_node *node = (struct drm_info_node *) m->private; 869 struct drm_device *dev = node->minor->dev; 870 struct amdgpu_device *adev = dev->dev_private; 871 struct drm_amdgpu_info_firmware fw_info; 872 struct drm_amdgpu_query_fw query_fw; 873 int ret, i; 874 875 /* VCE */ 876 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 877 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 878 if (ret) 879 return ret; 880 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 881 fw_info.feature, fw_info.ver); 882 883 /* UVD */ 884 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 885 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 886 if (ret) 887 return ret; 888 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 889 fw_info.feature, fw_info.ver); 890 891 /* GMC */ 892 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 893 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 894 if (ret) 895 return ret; 896 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 897 fw_info.feature, fw_info.ver); 898 899 /* ME */ 900 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 901 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 902 if (ret) 903 return ret; 904 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 905 fw_info.feature, fw_info.ver); 906 907 /* PFP */ 908 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 909 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 910 if (ret) 911 return ret; 912 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 913 fw_info.feature, fw_info.ver); 914 915 /* CE */ 916 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 917 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 918 if (ret) 919 return ret; 920 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 921 fw_info.feature, fw_info.ver); 922 923 /* RLC */ 924 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 925 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 926 if (ret) 927 return ret; 928 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 929 fw_info.feature, fw_info.ver); 930 931 /* MEC */ 932 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 933 query_fw.index = 0; 934 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 935 if (ret) 936 return ret; 937 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 938 fw_info.feature, fw_info.ver); 939 940 /* MEC2 */ 941 if (adev->asic_type == CHIP_KAVERI || 942 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) { 943 query_fw.index = 1; 944 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 945 if (ret) 946 return ret; 947 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 948 fw_info.feature, fw_info.ver); 949 } 950 951 /* SMC */ 952 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 953 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 954 if (ret) 955 return ret; 956 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 957 fw_info.feature, fw_info.ver); 958 959 /* SDMA */ 960 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 961 for (i = 0; i < adev->sdma.num_instances; i++) { 962 query_fw.index = i; 963 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 964 if (ret) 965 return ret; 966 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 967 i, fw_info.feature, fw_info.ver); 968 } 969 970 return 0; 971 } 972 973 static const struct drm_info_list amdgpu_firmware_info_list[] = { 974 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, 975 }; 976 #endif 977 978 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 979 { 980 #if defined(CONFIG_DEBUG_FS) 981 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, 982 ARRAY_SIZE(amdgpu_firmware_info_list)); 983 #else 984 return 0; 985 #endif 986 } 987